Light emitting element and method for manufacturing the same

Abstract

A light emitting element and a manufacturing method thereof are disclosed. The light emitting element includes a first edge and a second edge opposite to the first edge; a substrate including an upper surface; a plurality of light emitting units arranged in N rows on the upper surface, wherein the N rows include a first row of light emitting units located at the first edge and an Nth row of light emitting units located at the second edge; and a plurality of conductive structures located on the light emitting units and electrically connected to the light emitting units; wherein the first row of light emitting units includes a first light emitting unit, and the first light emitting unit includes a notch located at the first edge and having a bottom portion exposed to the upper surface.

Description

Technical Field

[0001] The present invention relates to a light-emitting element, and more specifically, to a light-emitting element comprising a plurality of light-emitting units. Background Technology

[0002] Solid-state light-emitting diodes (LEDs) possess characteristics such as low power consumption, low heat generation, long lifespan, small size, fast response speed, and excellent photoelectric properties, including a stable emission wavelength. Therefore, they have been widely used in household appliances, lighting devices, indicator lights, and optoelectronic products. With the development of optoelectronic technology, solid-state light-emitting elements have made significant progress in luminous efficiency, operating life, and brightness.

[0003] Existing light-emitting diode (LED) chips include a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer formed on the substrate, as well as p and n electrodes formed on the p-type and n-type semiconductor layers, respectively. When the LED chip is energized through the electrodes and subjected to a specific forward bias voltage, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer recombine in the active layer to emit light.

[0004] High-voltage light-emitting diode (LED) chips are formed by dividing the LED chip area into multiple light-emitting units connected in series on a single substrate. Compared to traditional single LED chips, high-voltage LED chips can operate at low current and high voltage with the same chip size and have higher output power. The number and size of the light-emitting units in a high-voltage LED chip can be determined according to different input voltage requirements, and each light-emitting unit can be optimized. It has advantages such as high voltage operation, small size, and excellent flexibility in packaging and optical design. Summary of the Invention

[0005] A light-emitting element includes: a first edge and a second edge opposite to the first edge; a substrate including an upper surface; a plurality of light-emitting units arranged in N rows on the upper surface, wherein the N rows include a first row of light-emitting units located at the first edge and an Nth row of light-emitting units located at the second edge; and a plurality of conductive structures located on the light-emitting units and electrically connected to the light-emitting units; wherein the first row of light-emitting units includes a first light-emitting unit, and the first light-emitting unit includes a notch located at the first edge and has a bottom exposed on the upper surface.

[0006] A light-emitting element includes: a first edge and a second edge opposite to the first edge; a substrate including an upper surface; a plurality of light-emitting units arranged in N rows on the upper surface, wherein the N rows of light-emitting units include a first row of light-emitting units located at the first edge and an Nth row of light-emitting units located at the second edge; and a plurality of conductive structures located on the light-emitting units and electrically connected to the light-emitting units; wherein the first row of light-emitting units includes a first light-emitting unit, and the first light-emitting unit includes a notch; the Nth row of light-emitting units includes a second light-emitting unit, a third light-emitting unit, and a trench located between the second light-emitting unit and the third light-emitting unit; and the notch is located on an extension line of the trench. Attached Figure Description

[0007] Figures 1A to 1E This is a top view of each step in a method for manufacturing a light-emitting element 1 according to an embodiment of the present invention;

[0008] Figures 2A to 2F This is a cross-sectional view of each step in a method for manufacturing a light-emitting element 1 according to an embodiment of the present invention;

[0009] Figure 3 This is a top view of a light-emitting element 1 according to an embodiment of the present invention;

[0010] Figure 4A for Figure 1E A magnified view of a portion of the image;

[0011] Figure 4B This is a partially enlarged top view of a method for manufacturing a light-emitting element in a comparative example;

[0012] Figure 5 This is a scanning electron microscope (SEM) image of the light-emitting element 1 according to an embodiment of the present invention;

[0013] Figure 6A This is a top view of the light-emitting element 2 according to another embodiment of the present invention;

[0014] Figure 6B This is a top view of a method for manufacturing the light-emitting element 2 according to another embodiment of the present invention;

[0015] Figure 6C for Figure 6B A magnified view of a portion of the image.

[0016] Symbol Explanation

[0017] 1, 2 Light-emitting elements

[0018] 10 substrate

[0019] 10a Substrate Top Surface

[0020] 12 Semiconductor stack

[0021] 121 First Semiconductor Layer

[0022] 121a First semiconductor layer upper surface

[0023] 122 Second Semiconductor Layer

[0024] 123 Active layer

[0025] 17 Lasers

[0026] 18 Transparent conductive layer

[0027] 180 opening

[0028] 20 First Electrode

[0029] 201 First pad electrode

[0030] 202 First Extension Electrode

[0031] 22, 22a-22e Light-emitting units

[0032] 23 Current blocking layer

[0033] 23a Middle section

[0034] 23c extension

[0035] 230a First Current Blocking Section

[0036] 230b Second Current Blocking Section

[0037] 30 Second electrode

[0038] 301 Second Pad Electrode

[0039] 302 Second Extension Electrode

[0040] 36. Grooves

[0041] 50, 50' notch

[0042] 60 Connecting electrodes

[0043] CL separator line

[0044] E1 First Edge

[0045] E2 Second Edge

[0046] MS Gaotai District

[0047] P Patterned structure

[0048] Rows R1, R2, R3

[0049] S1, S2, S3 sidewalls

[0050] Angle between θ1 and θ2

[0051] WF Semiconductor Wafer

[0052] W, Z local regions

[0053] IML extension cable Detailed Implementation

[0054] Figure 3 Showing a top view of a light-emitting element 1 according to an embodiment of the present invention; Figures 1A to 1E This shows a partial top view of each step in a method for manufacturing a light-emitting element 1 according to an embodiment of the present invention. Figures 2A to 2F This shows cross-sectional views of each step in a method for manufacturing a light-emitting element 1 according to an embodiment of the present invention. For example... Figure 3 As shown, the light-emitting element 1 includes a plurality of light-emitting units 22 (22a-22e) spaced apart by trenches 36 on a substrate 10, and electrically connected to each other by connecting electrodes 60 to form a series of light-emitting units. The light-emitting element 1 includes a first edge E1 and a second edge E2 opposite to the first edge E1. In one embodiment, the first edge E1 and the second edge E2 are two opposite edges of the substrate 10. In this embodiment, the light-emitting units 22a-22e are arranged in two rows R1 and R2 (hereinafter referred to as the first row and the second row), with the starting light-emitting unit 22a and the ending light-emitting unit 22e spanning the first row R1 and the second row R2, light-emitting unit 22c located in the first row R1, and light-emitting units 22b and 22d located in the second row R2. Three light-emitting units 22a, 22c, and 22e are provided on the first edge E1, and four light-emitting units 22a, 22b, 22d, and 22e are provided on the second edge E2. The light-emitting units 22 arranged at the first edge E1 and the second edge E2 in the light-emitting element 1 are asymmetrical. The light-emitting units 22a-22e respectively include a transparent conductive layer 18, a first electrode 20 (201, 202), a second electrode 30 (301, 302), and a current blocking layer 23. The light-emitting unit 22c includes a notch 50 located at the first edge E1.

[0055] In one embodiment, the manufacturing method of the light-emitting element 1 is described in detail below. Figure 2A for Figure 1A Cross-sectional view along line segment A-A'. (Refer to...) Figure 1A and Figure 2A The process involves forming a semiconductor stack and a mesa. First, a semiconductor stack 12 is formed on a substrate 10. In this embodiment, for ease of illustration, the substrate in the manufacturing process and the substrate of the final light-emitting element are both represented by the same symbol. The substrate 10 and the semiconductor stack 12 formed thereon constitute a semiconductor wafer (WF). Figure 1A Displays a semiconductor wafer WF and a magnified view of a portion thereof.

[0056] The substrate 10 can be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for growing gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate 10 includes an upper surface 10a. The substrate 10 can be a patterned substrate, that is, the substrate 10 has a patterned structure P on its upper surface 10a. In one embodiment, light emitted from the semiconductor stack 12 can be refracted by the patterned structure P of the substrate 10, thereby improving the brightness of the light-emitting element. Furthermore, the patterned structure P mitigates or suppresses misalignment between the substrate 10 and the semiconductor stack 12 caused by lattice mismatch, thereby improving the epitaxial quality of the semiconductor stack 12.

[0057] In one embodiment of the present invention, the method for forming a semiconductor stack 12 on a substrate 10 includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation.

[0058] A buffer structure (not shown), a first semiconductor layer 121, an active layer 123, and a second semiconductor layer 122 are sequentially formed on a substrate 10. The buffer structure, the first semiconductor layer 121, the active layer 123, and the second semiconductor layer 122 constitute a semiconductor stack 12. The buffer structure can reduce the aforementioned lattice mismatch and suppress dislocations, thereby improving epitaxial quality. The material of the buffer layer includes GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes multiple sublayers (not shown). The sublayers may be made of the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the first sublayer is grown by sputtering and the second sublayer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The third sublayer is grown by MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second, and third sublayers include the same material, such as AlN. In one embodiment of the present invention, the first semiconductor layer 121 and the second semiconductor layer 122, for example, cladding layers or confinement layers, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 121 is an n-type semiconductor, and the second semiconductor layer 122 is a p-type semiconductor. An active layer 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. Electrons and holes combine in the active layer 123 under the drive of an electric current, converting electrical energy into light energy to emit light. The wavelength of the light emitted by the light-emitting element 1 or the semiconductor stack 12 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 12.

[0059] The material of semiconductor stack 12 includes Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P is a group III-V semiconductor material, where 0≤x, y≤1; x+y≤1. Depending on the material of the active layer, when the semiconductor stack 12 is made of the AlInGaP series, it can emit red light with wavelengths between 610nm and 650nm or yellow light with wavelengths between 550nm and 570nm. When the semiconductor stack 12 is made of the InGaN series, it can emit blue or deep blue light with wavelengths between 400nm and 490nm or green light with wavelengths between 490nm and 550nm. When the semiconductor stack 12 is made of the AlGaN series, it can emit UV light with wavelengths between 400nm and 250nm. The active layer 123 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The active layer 123 can be an i-type, p-type, or n-type semiconductor.

[0060] Next, a sill formation step is performed, removing a portion of the semiconductor stack 12 until the upper surface 121a of the first semiconductor layer 121 is exposed, forming multiple sill regions MS. The upper surface of each sill region MS is the upper surface of the second semiconductor layer 122. Viewed from above, the upper surface 121a surrounds each sill region MS. In this embodiment, one sill region MS corresponds to one light-emitting unit 22. The method for removing a portion of the semiconductor stack 12 includes etching.

[0061] Next, refer to Figure 1B and Figure 2B Implement a trench formation step. Figure 2B for Figure 1B A cross-sectional view along line segment A-A'. In this step, the first semiconductor layer 121 is removed downwards from the upper surface 121a of the first semiconductor layer to form a trench 36. The trench 36 separates the semiconductor stack 12 of a single light-emitting element 1 and defines multiple light-emitting units 22 (22a~22e). The sidewalls of the trench 36 are the sidewalls of the semiconductor stack 12 of two adjacent light-emitting units 22, and the bottom of the trench 36 is the exposed upper surface 10a of the substrate 10. The included angle between the sidewall of the trench 36 and the upper surface 10a of the substrate 10 is θ1, which is less than 90 degrees. In one embodiment, θ1 is between 20 and 80 degrees. The first semiconductor layers 121 between adjacent light-emitting elements 1 are connected. That is, adjacent light-emitting elements 1 are not separated by the trench 36, but the boundary between adjacent light-emitting elements 1 is defined from the upper surface 121a of the first semiconductor layer 121, serving as the location of the pre-defined dividing line (not shown) in the subsequent cutting process.

[0062] Next, refer to Figure 1C and Figure 2C The steps of forming a current blocking layer and a transparent conductive layer are implemented. Figure 2C for Figure 1C Cross-sectional view along line segment B-B'.

[0063] First, an insulating material layer (not shown) is formed on each light-emitting unit 22 and within the trench 36, covering the trench 36. Then, the insulating material layer is patterned using processes such as developing and etching to form a current blocking layer 23. In this embodiment, the current blocking layer 23 includes a first current blocking portion 230a, a second current blocking portion 230b, a middle portion 23a, and an extension portion 23c; wherein, the first current blocking portion 230a is located on the first semiconductor layer 121 of the end light-emitting unit 22e in the light-emitting unit series, the second current blocking portion 230b is located on the second semiconductor layer 122 of the starting light-emitting unit 22a, and the middle portion 23a is located on the trench 36. In one embodiment, as... Figure 2C As shown, the middle portion 23a covers the bottom of the trench 36 and the sidewalls of the semiconductor stack 12. The extension portion 23c extends from the middle portion 23a and is formed on the upper surface of the second semiconductor layer 122 in the light-emitting unit 22b. In another embodiment, the current blocking layer 23 does not include the first current blocking portion 230a.

[0064] The material of the current blocking layer 23 includes a transparent insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, aluminum oxide, or a combination or stack of the above materials. The current blocking layer 23 can be a single layer or a stack of multiple layers; in one embodiment, the current blocking layer 23 comprises a stack of one or more insulating layer pairs, each insulating layer pair comprising two sublayers, the insulating materials constituting the two sublayers having different refractive indices, and the current blocking layer 23 is a distributed Bragg reflector (DBR).

[0065] In one embodiment, the second current blocking portion 230b includes an opening that exposes the upper surface of the second semiconductor layer 122 of the light-emitting unit 22a. In another embodiment, the first semiconductor layer 121 of the end light-emitting unit 22e does not have the first current blocking portion 230a.

[0066] Next, a transparent conductive layer 18 is formed to cover the upper surface of the second semiconductor layer 122 of each light-emitting unit 22 and to make electrical contact with the second semiconductor layer 122. In this embodiment, the transparent conductive layer 18 simultaneously covers the extension 23c of the current blocking layer 23 and the second current blocking portion 230b. The transparent conductive layer 18 can be a metal or a transparent conductive material. The metal can be selected from a thin metal layer with light transmittance, and the transparent conductive material is transparent to the light emitted by the active layer 123, including materials such as indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), or indium zinc oxide (IZO). In one embodiment, the transparent conductive layer 18 has an opening 180 corresponding to the opening of the second current blocking portion 230b.

[0067] Next, refer to Figure 1D and Figure 2D A conductive structure formation step is implemented. Figure 2D for Figure 1D Cross-sectional view along line segment B-B'.

[0068] A conductive structure is formed on the light-emitting unit 22 and the trench 36. The conductive structure includes a first electrode 20 and a second electrode 30 on the light-emitting unit 22, and a connecting electrode 60 formed between two adjacent light-emitting units 22. The material of the conductive structure includes metals such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), rhodium (Rh), or platinum (Pt), or alloys or stacks of the above materials.

[0069] On the light-emitting unit 22e, a first electrode 20 is formed on its first semiconductor layer 121, including a first pad electrode 201. In other embodiments, the first electrode 20 further includes a first extension electrode 202 extending from the first pad electrode 201. The first electrode 20 is electrically connected to the first semiconductor layer 121 and is located above the first current blocking portion 230a. In a top view, the area of ​​the first pad electrode 201 is larger than the area of ​​the first current blocking portion 230a, and the first pad electrode 201 covers the upper surface and sidewalls of the first current blocking portion 230a. In other embodiments, the area of ​​the first pad electrode 201 is smaller than the area of ​​the first current blocking portion 230a. On each of the other light-emitting units, a first extension electrode 202 is provided and electrically connected to its first semiconductor layer 121. On the light-emitting unit 22a, a second electrode 30 is formed on the transparent conductive layer 18, electrically connected to the transparent conductive layer 18 and the second semiconductor layer 122, including a second pad electrode 301 and a second extension electrode 302 extending from the second pad electrode 301. On each of the other light-emitting units, a second extended electrode 302 is also provided, electrically connected to its second semiconductor layer 122. In this embodiment, the second pad electrode 301 is located corresponding to the opening of the second current blocking portion 230b and the opening 180 of the transparent conductive layer 18, and contacts the second semiconductor layer 122 through these openings. In one embodiment, the second pad electrode 301 is located inside the opening 180 of the transparent conductive layer 18, does not contact the transparent conductive layer 18, and is located on the second current blocking portion 230b, extending into the opening of the second current blocking portion 230b to contact the second semiconductor layer 122. A connecting electrode 60 is formed on the middle portion 23a of the current blocking layer 23, connecting the first extended electrode 202 on one light-emitting unit and the second extended electrode 302 on an adjacent light-emitting unit, so that the light-emitting units 22 form a series light-emitting unit array.

[0070] In another embodiment, the connecting electrode 60 is connected to the first extended electrode 202 on two adjacent light-emitting units 22, and / or the connecting electrode 60 is connected to the second extended electrode 302 on two adjacent light-emitting units 22, so that the light-emitting units 22 form different light-emitting unit arrays such as parallel, series, or series-parallel connection.

[0071] The second pad electrode 301 on the light-emitting unit 22a and the first pad electrode 201 on the light-emitting unit 22e will be used for wire bonding in subsequent manufacturing processes to form an electrical connection between the light-emitting element 1 and external electronic components or power supplies. In another embodiment, a first external electrode pad and a second external electrode pad (not shown) can be formed on the light-emitting element 1, which are electrically connected to the first pad electrode 201 and the second pad electrode 301, respectively, and then flip-chip bonded to a carrier (not shown), or directly connected to external electronic components or power supplies. The aforementioned first current blocking portion 230a and second current blocking portion 230b serve to prevent current from flowing directly into the semiconductor stack 12 through the pad electrodes, and instead allow the current to diffuse through the first electrode 20, the second electrode 30, and the transparent conductive layer 18 above it. Similarly, the extension 23c of the current blocking layer 23 is disposed along the second extended electrode 302 and located below the second extended electrode 302, preventing the current conducted through the second extended electrode 302 from flowing directly into the semiconductor stack 12, but instead diffusing through the transparent conductive layer 18 above the current blocking layer 23. The current blocking layer 23 can make the current uniformly distributed.

[0072] Figures 1A-1E , Figures 2A-2F ,and Figure 3 Although not all the components on the light-emitting unit 22 are labeled, those skilled in the art can understand the structure of each light-emitting unit 22 and the components above it through the accompanying drawings and the above description.

[0073] Next, refer to Figure 1E and Figure 2E Then, a cutting step is performed. Figure 2E for Figure 1E Cross-sectional view along line segment A-A'. Figure 4A for Figure 1E A partial enlarged view of region Z in the middle. In one embodiment, a laser 17 is used to irradiate the back side of the substrate 10 at the position corresponding to the pre-defined dividing line, forming a modified region (not shown) inside the substrate 10. Cracks are then formed along the crystal plane of the substrate from the modified region, and each light-emitting element 1 is separated along the dividing line CL to form an independent light-emitting element 1. Each light-emitting element 1 includes a plurality of electrically connected light-emitting units 22 (22a-22e). Figure 2F show Figure 2E After cutting, multiple independent light-emitting elements 1 are formed. Each light-emitting element 1 has a first semiconductor layer sidewall S1 surrounding it connected to a substrate sidewall S2 below it. In one embodiment, the first semiconductor layer sidewall S1 surrounding the light-emitting element 1 is connected to the substrate sidewall S2 below it and is coplanar. In one embodiment, the inner angle between the first semiconductor layer sidewall S1 and the upper surface 10a of the substrate is greater than 80 degrees. In one embodiment, the first semiconductor layer sidewall S1 is substantially perpendicular to the upper surface 10a of the substrate.

[0074] In a comparative method for manufacturing a light-emitting element with a series of light-emitting units, trenches are formed to define the light-emitting units, and each light-emitting element is also separated from the others by trenches; that is, the trenches around each light-emitting unit serve as the location of the pre-dividing line. However, in the method for manufacturing the light-emitting element 1 of the present invention, trenches 36 are not used as the location of the pre-dividing line between adjacent light-emitting elements 1. Instead, the first semiconductor layer 121 between adjacent light-emitting units 22 is retained to maintain their connection. This connected first semiconductor layer 121 is then separated during a subsequent dicing process to form multiple independent light-emitting elements 1. As a result, in the semiconductor wafer WF, a trench does not need to be formed between the light-emitting elements 1 as the location of the pre-dividing line. Therefore, the arrangement of the light-emitting elements 1 can be more compact, and a greater number of light-emitting elements 1 can be produced per unit area of ​​semiconductor wafer WF. Furthermore, by retaining the first semiconductor layer 121 between adjacent light-emitting units 22 as the location of the pre-dividing line, the amount of semiconductor stacking lost due to errors in the preceding and following manufacturing processes is reduced, thus preserving a larger light-emitting area. Therefore, after forming an independent light-emitting element 1, under the same substrate area, the light-emitting element 1 formed according to the manufacturing method of this embodiment can have a larger semiconductor layer area and thus higher brightness. In one embodiment, in Figure 1D and Figure 1E During the manufacturing process, light-emitting units 22b and 22d of one light-emitting element 1 are simultaneously adjacent to and connected to light-emitting unit 22c of another light-emitting element 1. If the width and position of the groove 36 and / or the dividing line CL are not precisely controlled during manufacturing, it may result in... Figure 4B In a comparative example, the trench 36 between light-emitting units 22b and 22d does not intersect with the dividing line CL, leaving a portion of the first semiconductor layer 121 connected between light-emitting units 22b and 22d. After the independent light-emitting element 1 is completed, a short circuit will occur between light-emitting units 22b and 22d due to the partial connection of the first semiconductor layer 121, causing the light-emitting element 1 to malfunction. Therefore, referring to... Figure 1E and Figure 4A In this embodiment, when forming the trench 36, the trench 36 between the light-emitting units 22b and 22d is extended into the first semiconductor layer 121 of the light-emitting unit 22c of the adjacent light-emitting element 1. This ensures that in the subsequent cutting and fabrication process, the light-emitting units 22b and 22d can be reliably separated and disposed on the substrate 10 by the extension of the trench 36 and the dividing line CL.

[0075] Because the groove 36 between light-emitting units 22b and 22d extends into the light-emitting unit 22c of the adjacent light-emitting element 1 during the manufacturing process, in one embodiment, after the independent light-emitting element 1 is completed, as Figure 3As shown, the first semiconductor layer 121 of the light-emitting unit 22c includes a notch 50 located at the first edge E1, situated on an extension line IML of the trench 36 between light-emitting units 22b and 22d. The notch 50 is recessed inward from the first edge E1. The bottom of the notch 50 is the upper surface 10a of the substrate. The difference between the maximum bottom width of the notch 50 and the minimum bottom width of the trench 36 is less than 20%. In one embodiment, the difference between the maximum bottom width of the notch 50 and the minimum bottom width of the trench 36 is less than 10%. In one embodiment, the difference between the maximum bottom width of the notch 50 and the minimum bottom width of the trench 36 between light-emitting units 22b and 22d is less than 20%. In one embodiment, the difference between the maximum bottom width of the notch 50 and the minimum bottom width of the trench 36 between light-emitting units 22b and 22d is less than 10%.

[0076] Figure 5 Display by Figure 3 A scanning electron microscope (SEM) image of the sidewalls of the semiconductor stack 12 and the substrate 10 observed in the X-direction. The sidewall S3 of the notch 50 is connected to the sidewall S1 of the first semiconductor layer of the light-emitting unit 22c. In one embodiment, the notch 50 is wider at the top and narrower at the bottom, and the inner angle θ2 between the notch sidewall S3 and the upper surface 10a of the substrate is between 20 degrees and 80 degrees. In one embodiment, the difference between the inner angle θ2 between the notch sidewall S3 and the upper surface 10a of the substrate and the inner angle θ1 between the trench 36 sidewall and the upper surface 10a of the substrate is less than 20%. In another embodiment, the difference between the inner angle θ2 between the notch sidewall S3 and the upper surface 10a of the substrate and the inner angle θ1 between the trench 36 sidewall and the upper surface 10a of the substrate is less than 10%.

[0077] Figure 6A This shows a top view of the light-emitting element 2 according to another embodiment of the present invention. Figure 6B A partial top view showing a manufacturing method of an embodiment of the light-emitting element 2. Figure 6C for Figure 6B A magnified view of a portion of region W. Light-emitting element 2 is similar to light-emitting element 1, also having multiple light-emitting units 22 spaced apart by trenches 36 on the substrate 10, electrically connected to each other by connecting electrodes 60, forming a series of light-emitting units. The difference is that light-emitting element 2 contains 12 light-emitting units arranged in a 3×4 array. To clearly show light-emitting element 2, in... Figures 6A to 6C The current blocking layer and the transparent conductive layer are not shown in the illustration. However, those skilled in the art can still be taught through the description of the foregoing embodiments and understand the structure and relative relationship of each light-emitting unit 22 in the light-emitting element 2.

[0078] like Figure 6AAs shown, the areas of the light-emitting units 22 in the first row R1 and the third row R3 of the light-emitting element 2 are designed to be unequal. Therefore, the light-emitting units 22 arranged at the first edge E1 and the second edge E2 in the light-emitting element 2 are asymmetrical. In other words, the groove positions between the light-emitting elements 2 in the first row R1 and the groove positions of the light-emitting units 22 in the third row R3 are not aligned. The light-emitting unit 22 in the first row R1 includes a notch 50' located at the first edge E1, and the light-emitting unit 22 in the third row R3 includes another notch 50' located at the second edge E2. In one embodiment, the manufacturing method of the light-emitting element 2 is similar to the manufacturing method of the light-emitting element 1, such as... Figure 6B As shown, instead of using trenches 36 as pre-dividing areas between adjacent light-emitting elements 2, the first semiconductor layer 121 between adjacent light-emitting elements 2 is retained to maintain their connection. This connected first semiconductor layer 121 is then separated during the subsequent dicing process to form multiple independent light-emitting elements 2. In this embodiment, when forming the trenches 36, the trenches 36 between the light-emitting units 22 are extended to the light-emitting units 22 of the adjacent light-emitting elements 2. For example, the trenches 36 between the light-emitting units 22 in the third row R3 of the light-emitting elements 2 in the semiconductor wafer are extended to the first semiconductor layer 121 of the light-emitting units 22 in the first row R1 of the adjacent light-emitting elements 2. This ensures that, during the subsequent dicing process, all light-emitting units 22 can be reliably separated and formed on the substrate 10 through the trenches 36, their extensions, and the dividing line CL.

[0079] In one embodiment, after the light-emitting element 2 is formed, as follows: Figure 6A As shown, the first semiconductor layer 121 of the light-emitting unit 22 in the first row R1 includes a notch 50' located at the first edge E1, which is situated on an extension line IML of the trench 36 between the light-emitting units 22 in the third row R3. In one embodiment, the notch 50' is formed as described above. In the uncut semiconductor wafer, the trench 36 between the light-emitting units 22 in the third row R3 of the light-emitting element adjacent to the left side of the light-emitting element 2 extends into the first semiconductor layer 121 of the light-emitting unit 22 in the first row R1 of the light-emitting element 2, forming the notch 50' at the first edge E1 of the cut light-emitting element 2.

[0080] In one embodiment, such as Figure 6AAs shown, the first semiconductor layer 121 of the light-emitting unit 22 in the third row R3 may include another notch 50' located at the second edge E2. The notch 50' is located on an extension line IML of the trench 36 between the light-emitting units 22 in the first row R1. In one embodiment, the notch 50' is formed as described above. In the uncut semiconductor wafer, the trench 36 between the light-emitting units 22 in the first row R1 of the light-emitting element adjacent to the right side of the light-emitting element 2 extends into the first semiconductor layer 121 of the light-emitting unit 22 in the third row R3 of the light-emitting element 2, forming the notch 50' at the second edge E2 of the cut light-emitting element 2. The notch 50' has a similar structure to the notch 50 of the light-emitting unit 22 in the aforementioned embodiment. The notches 50' located at the first edge E1 and the second edge E2 are recessed inward from the first edge E1 and the second edge E2, respectively. The bottom of the notch 50' is the upper surface 10a of the substrate. The difference between the maximum bottom width of the notch 50' and the minimum bottom width of the trench 36 is less than 20%. In one embodiment, the difference between the maximum bottom width of the notch 50' and the minimum bottom width of the groove 36 is less than 10%.

[0081] In one embodiment, the difference between the maximum bottom width of the notch 50' located at the first edge E1 and the minimum bottom width of the groove 36 between the third row of R3 light-emitting units 22 is less than 20%. In another embodiment, the difference between the maximum bottom width of the notch 50' located at the first edge E1 and the minimum bottom width of the groove 36 between the third row of R3 light-emitting units 22 is less than 10%. In one embodiment, the difference between the maximum bottom width of the notch 50' located at the second edge E2 and the minimum bottom width of the groove 36 between the first row of R1 light-emitting units 22 is less than 20%. In another embodiment, the difference between the maximum bottom width of the notch 50' located at the second edge E2 and the minimum bottom width of the groove 36 between the first row of R1 light-emitting units 22 is less than 10%.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Anyone skilled in the art can make modifications and variations to the above embodiments without departing from the technical principles and spirit of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

Claims

1. A light-emitting element, characterized in that, Include: The first edge and the second edge relative to the first edge; Substrate, including the upper surface; Multiple light-emitting units are arranged in N rows on the upper surface, wherein the N rows include a first row of light-emitting units located at the first edge and an Nth row of light-emitting units located at the second edge; as well as Multiple conductive structures are located on and electrically connected to the light-emitting units; The first row of light-emitting units contains a first light-emitting unit, and the Nth row of light-emitting units contains a second light-emitting unit and a third light-emitting unit; The groove is located between the second light-emitting unit and the third light-emitting unit; The first light-emitting unit includes a notch located at the first edge and recessed inward from the first edge, the notch being located on the extension line of the groove and having a bottom exposed on the upper surface.

2. The light-emitting element as described in claim 1, wherein, The first light-emitting unit includes a first sidewall located at the first edge, and the substrate includes a second sidewall located at the first edge. The first sidewall and the second sidewall are connected and are coplanar.

3. The light-emitting element as described in claim 2, wherein, The first sidewall is connected to the notch.

4. The light-emitting element as described in claim 2, wherein, The notch includes a third sidewall, the inner angle between the third sidewall and the upper surface being smaller than the inner angle between the first sidewall and the upper surface.

5. The light-emitting element as claimed in claim 1, wherein, The difference between the maximum bottom width of the notch and the minimum bottom width of the groove is less than 20%.

6. The light-emitting element as claimed in claim 1, wherein, The notch includes a third sidewall, the groove includes a fourth sidewall, and the angle difference between the inner angle of the third sidewall and the upper surface and the inner angle of the fourth sidewall and the upper surface is less than 10%.

7. The light-emitting element as claimed in claim 1, wherein, The second light-emitting unit includes a fourth sidewall located at the second edge, and the substrate includes a fifth sidewall located at the second edge. The fourth sidewall and the fifth sidewall are connected and coplanar.

8. The light-emitting element as claimed in claim 1, wherein, The first light-emitting unit comprises a first semiconductor layer, an active layer, and a second semiconductor layer sequentially formed on the upper surface; and The notch is located in the first semiconductor layer.

9. A method for manufacturing a plurality of light-emitting elements, characterized in that, Include: A semiconductor stack is formed on the upper surface of the substrate; A trench is formed in the semiconductor stack, and a plurality of light-emitting units are defined in the semiconductor stack, each light-emitting element comprising a portion of the light-emitting units; in: The adjacent light-emitting elements include a first light-emitting element and a second light-emitting element, and the light-emitting units include a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit; The first light-emitting element includes the first light-emitting unit, and the second light-emitting element includes the second light-emitting unit and the third light-emitting unit; The second and third light-emitting units are adjacent to the first light-emitting unit; The semiconductor stack between the second light-emitting unit, the third light-emitting unit and the first light-emitting unit is partially connected to each other; as well as The groove located between the second light-emitting unit and the third light-emitting unit extends into the first light-emitting unit; as well as Perform a cutting step to separate the connected portion of the semiconductor stack; The groove extending into the first light-emitting unit forms a notch in the first light-emitting unit.

10. The method of claim 9, wherein, Forming the trench involves removing a portion of the semiconductor stack to expose the upper surface.

11. The method of claim 9, wherein, The notch is located at the edge of the first light-emitting element and has a bottom that exposes the upper surface.

12. The method of claim 9, wherein performing the cutting step further comprises dividing the substrate into multiple portions corresponding to the light-emitting elements; The first light-emitting unit includes a first sidewall; One of the plurality of portions corresponding to the first light-emitting unit includes a second sidewall; and The first sidewall and the second sidewall are connected.

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