Memory device, integrated chip and method for forming the same

Abstract

Various embodiments of the present disclosure relate to a memory cell including a co-doped data storage structure. A bottom electrode overlies a substrate, and a top electrode overlies the bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a dielectric material doped with a first dopant and a second dopant.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to memory devices, integrated chips, and methods of forming the same. Background Art

[0002] Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data when powered, while non-volatile memory can retain data when power is removed. Resistive random access memory (RRAM) is a potential candidate for the next generation of non-volatile memory technology due to its simple structure and compatibility with complementary metal oxide semiconductor (CMOS) logic processes. RRAM cells include a dielectric data storage structure with a variable resistance, which is placed between two electrodes disposed within an interconnect metallization layer. Summary of the invention

[0003] The present disclosure discloses a storage device, characterized in that it includes: a substrate; a bottom electrode overlying the substrate; a top electrode overlying the bottom electrode; and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure includes a dielectric material doped with a first dopant and a second dopant.

[0004] The disclosed embodiment proposes an integrated chip, characterized in that it includes: a substrate; a bottom electrode through hole overlying the substrate; a top electrode through hole overlying the bottom electrode through hole; and a resistive random access memory unit arranged between the bottom electrode through hole and the top electrode through hole, wherein the resistive random access memory unit includes a top electrode, a bottom electrode and a data storage structure arranged between the top electrode and the bottom electrode, wherein the data storage structure includes a co-doped high dielectric constant dielectric material.

[0005] The disclosed embodiment proposes a method for forming a memory device, characterized in that the method includes: forming a lower conductive wiring on a substrate; depositing a bottom electrode layer on the lower conductive wiring; forming a data storage structure on the bottom electrode layer, so that the data storage structure includes a dielectric material, a first dopant and a second dopant; forming a top electrode on the data storage structure; and patterning the bottom electrode layer, the data storage structure and the top electrode to define a memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Schematic diagrams illustrating some embodiments of a memory device including a memory cell having a low formation voltage.

[0008] Figure 2 Cross-sectional views of some embodiments of a memory device including a memory cell having a co-doped data storage structure are shown.

[0009] Figure 3 and Figure 4 Show Figure 1 Cross-sectional views of some alternative embodiments of memory devices are shown.

[0010] Figure 5 Cross-sectional views of some embodiments of an integrated chip including memory cells each having a low formation voltage and disposed within an embedded memory region laterally adjacent to a logic region are shown.

[0011] Figure 6 Show Figure 5 Some alternative embodiments of the integrated chip shown are based on Figure 5 Top view of the line shown in .

[0012] Figure 7 and Figure 8 Cross-sectional views of some embodiments of an integrated chip including a memory cell having a low formation voltage and disposed within an interconnect structure are shown.

[0013] Figures 9 to 14 Cross-sectional views illustrating some embodiments of methods of forming a memory cell having a low formation voltage.

[0014] Fig.15 A flow chart is shown according to some embodiments of a method of forming a memory cell having a low formation voltage. DETAILED DESCRIPTION

[0015] The present invention provides many different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements are described below to make the present invention concise. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature cannot be directly contacted. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not essentially specify the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] A resistive random access memory (RRAM) cell includes a data storage structure (e.g., one or more oxide layers) arranged between a top electrode and a bottom electrode. The RRAM cell is disposed on a semiconductor substrate. The variable resistance of the data storage structure represents a data unit, such as a data bit. Depending on the voltage applied between the top electrode and the bottom electrode, the variable resistance undergoes a reversible change between a high resistance state and a low resistance state corresponding to the data state of the data unit. The "high" of the high resistance state is that the variable resistance exceeds a threshold value, and the "low" of the low resistance state is that the variable resistance is below a threshold value.

[0018] Before the RRAM cell can be used to store data, an initial conductive path (i.e., conductive filament) is typically formed in the data storage structure. The formation of the initial conductive path makes subsequent write operations (forming the conductive path) easier to perform. To form the initial conductive path, a forming voltage is applied to the top electrode and the bottom electrode at the end of the RRAM manufacturing process. In some types of RRAM cells, the conductive path may include vacancies (e.g., oxygen vacancies). In these devices, the forming voltage can knock oxygen atoms out of the lattice of the data storage structure, thereby forming local oxygen vacancies. These local oxygen vacancies tend to align to form a conductive path extending through the data storage structure. Thereafter, a set voltage or a reset voltage may be applied across the top electrode and the bottom electrode to change the resistivity of the data storage structure between a high resistance state and a low resistance state. Typically, the forming voltage is greater than the set voltage. Typically, one or more transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) disposed on / above a semiconductor substrate provide voltages for the RRAM cell so that a forming voltage, a set voltage, and a reset voltage may be applied across the top electrode and the bottom electrode.

[0019] In some embodiments where the conductive filament is formed before the RRAM cell is used to store data, the data storage structure may be or include an undoped metal oxide structure (e.g., undoped aluminum oxide (AlO x)). In these embodiments, the formation voltage may be relatively high. In an effort to increase device density and device efficiency, the feature size of the one or more transistors and / or the feature size of the RRAM cell continues to shrink. However, as the feature size of the one or more transistors shrinks, the relatively high formation voltage becomes a problem (e.g., because the reduction in the feature size of the one or more transistors reduces the breakdown voltage). The relatively high formation voltage may be greater than the safe output voltage of the one or more transistors. Therefore, if the one or more transistors are operated to output the relatively high formation voltage, the one or more transistors may be damaged and / or destroyed.

[0020] In some embodiments, the present application relates to a RRAM cell with a low formation voltage. The RRAM cell includes a bottom electrode disposed in an inter-level dielectric (ILD) structure disposed on a substrate. A top electrode is disposed in the ILD structure and overlies the bottom electrode. A data storage structure is disposed in the ILD structure and is located between the top electrode and the bottom electrode. The data storage structure includes a dielectric material (e.g., aluminum oxide (AlO)) co-doped with a first dopant (e.g., nitrogen) and a second dopant (e.g., tantalum). x )). Since the data storage structure is co-doped with the first dopant and the second dopant, the formation voltage of the RRAM cell can be improved (e.g., reduced) while maintaining good reliability of the RRAM cell. For example, doping the data storage structure with the first dopant can reduce or eliminate the formation voltage of the RRAM cell, and doping the data storage structure with the second dopant can ensure that the RRAM cell is maintained with good reliability (e.g., good retention performance). Therefore, an integrated chip including an RRAM cell can have one or more transistors with reduced feature sizes that can safely provide a low formation voltage for the RRAM cell. This in turn promotes the reduction of the feature size of the RRAM cell and the feature size of the one or more transistors while reducing and / or eliminating damage to the RRAM cell and / or the one or more transistors.

[0021] Figure 1 Schematic diagram illustrating some embodiments of a memory device 100 including a memory cell 104 having a low formation voltage.

[0022] In some embodiments, the memory device 100 includes a memory cell 104 electrically coupled to a transistor 102, such that the memory device 100 is a single transistor single resistor memory cell (1T1R) configuration. In other embodiments, the transistor 102 may be, for example, a metal oxide semiconductor field effect transistor (MOSFET). The memory cell 104 includes a bottom electrode 106, a top electrode 110, and a data storage structure 108 disposed between the bottom electrode 106 and the top electrode 110. The bit line (BL) is electrically coupled to one end of the data storage structure 108 through the top electrode 110, and the source line (SL) is electrically coupled to the opposite end of the data storage structure 108 through the transistor 102. The word line (WL) is electrically coupled to the gate electrode of the transistor 102. Therefore, applying a suitable WL voltage to the gate electrode of the transistor 102 couples the memory cell 104 between BL and SL. Therefore, in some embodiments, by providing suitable bias conditions, the memory cell 104 can be switched between two resistance states, a low resistance state and a high resistance state, to store data.

[0023] In some embodiments, the data storage structure 108 includes a dielectric material (eg, aluminum oxide (AlO)) co-doped with a first dopant (eg, nitrogen) and a second dopant (eg, tantalum). x )). Thus, in various embodiments, the data storage structure 108 may include aluminum oxide, nitrogen, and tantalum and / or may have a thickness in the range of about 20 angstroms to 80 angstroms. In other embodiments, the first dopant (e.g., nitrogen) comprises between about 1 percent and 15 percent of the chemical composition of the data storage structure 108. In further embodiments, the second dopant (e.g., tantalum) comprises between about 2 percent and 20 percent of the chemical composition of the data storage structure 108. In some embodiments, the memory cell 104 may be configured as a resistive random access memory (RRAM) cell such that the data storage structure 108 comprises a material having a variable resistance that is configured to undergo a reversible phase change between a high resistance state and a low resistance state.

[0024] In some embodiments, before the memory cell 104 can be used to store data, an initial conductive path (i.e., a conductive filament) is typically formed across the data storage structure 108 through the region 112. The formation of the initial conductive path makes subsequent write operations (forming the conductive path) easier to perform. In other embodiments, to form the initial conductive path, a forming voltage is applied between the top electrode 110 and the bottom electrode 106 through the transistor 102 and the BL. The initial conductive path may include vacancies (e.g., oxygen vacancies). In these embodiments, the forming voltage may knock oxygen atoms out of the lattice of the data storage structure 108, thereby forming local oxygen vacancies. These local vacancies tend to align within the region 112 to form an initial conductive path extending from the bottom electrode 106 to the top electrode 110 within the data storage structure 108. Thereafter, a set voltage or a reset voltage may be applied between the bottom electrode 106 and the top electrode 110 via the transistor 102 and the BL to change the resistivity of the data storage structure 108 between a high resistance state and a low resistance state.

[0025] In various embodiments, since the data storage structure 108 includes the first dopant (e.g., nitrogen), the formation voltage can be reduced and / or eliminated. For example, in some embodiments, the formation of the initial conductive path cannot be performed before the set operation is performed on the memory cell 104, so that the formation voltage is not applied between the data storage structure 108 and / or the transistor 102. This in turn helps to reduce the feature size of the memory cell 104 and / or the feature size of the transistor 102 while reducing and / or eliminating damage to the memory cell 104 and / or the transistor 102. In some embodiments, the formation voltage can be equal to the set voltage. In other embodiments, the formation voltage can be approximately equal to the set voltage and / or the formation voltage can be in the range of approximately 0 to 25 percent greater than the set voltage. In some embodiments, if the set voltage is approximately 2 volts (V), the formation voltage is less than approximately 2.5V. In some embodiments, for example, the first dopant can reduce the energy required to form a vacancy in the data storage structure 108, thereby increasing the ability to form a local oxygen vacancy in the region 112. In other embodiments, data retention of the memory cell 104 may be improved because the data storage structure 108 includes a second dopant, such as tantalum. In these embodiments, the second dopant has a strong bond with the oxygen atoms within the data storage structure 108, so the strong bond may not be broken by the baking process performed on the memory cell 104. In some embodiments, the strong bond between the second dopant and the oxygen atoms may be greater than about 600 kilojoules per mole (kJ / mol). For example, if the second dopant is tantalum, the strong bond between tantalum and oxygen may be in the range of about 805 kJ / mol to 839 kJ / mol. In other embodiments, the strong bond between the second dopant and oxygen is greater than the bond between the first dopant and oxygen, and the bond between the first dopant and oxygen is greater than the bond between aluminum and oxygen. In further embodiments, the bond between the first dopant and oxygen may be about 630 kJ / mol, and / or the bond between aluminum and oxygen may be in the range of about 490 kJ / mol to 515 kJ / mol. In some embodiments, a bake process may be performed on the memory cell 104 to determine whether the data storage structure 108 can retain its data state, and / or whether the bake process may reach a temperature in a range of approximately 125 degrees C. to 250 degrees C. Therefore, since the data storage structure 108 is co-doped with the first dopant and the second dopant, the formation voltage of the memory cell 104 may be improved (e.g., reduced or eliminated) while maintaining good data retention of the memory cell 104.

[0026] Figure 2 A cross-sectional view of some embodiments of a memory device 200 is shown including a memory cell 104 having a data storage structure 108 including a first dopant and a second dopant.

[0027] The memory device 200 includes an interconnect dielectric structure 216 and a substrate 202. In some embodiments, for example, the substrate 202 may be or include a semiconductor body such as a single crystal silicon / CMOS substrate, silicon germanium (SiGe), silicon on insulator (SOI), or another suitable semiconductor substrate material, and / or the substrate 202 may include a first doping type (e.g., p-type). The transistor 102 is disposed on / in the substrate 202. In some embodiments, for example, the transistor 102 may be or include a metal oxide semiconductor field effect transistor (MOSFET), a high voltage transistor, a bipolar junction transistor (BJT), an n-channel metal oxide semiconductor (nMOS) transistor, a p-channel metal oxide semiconductor (pMOS) transistor, or another suitable transistor. In other embodiments, the transistor 102 may include a source / drain region 204, a gate dielectric layer 206, a gate electrode 208, and / or a sidewall spacer structure 210. The source / drain region 204 may be disposed in the substrate 202 and / or may include a second doping type (e.g., n-type) opposite to the first doping type.

[0028] The lower inner connecting via 212 is disposed in the inner connecting dielectric structure 216 and overlies the source / drain region 204 of the transistor 102. In some embodiments, for example, the inner connecting dielectric structure 216 may be or include one or more interlayer dielectric (ILD) layers. For example, the one or more ILD layers may be or include silicon oxide, a low-κ dielectric material, an extremely low-κ dielectric material, another suitable dielectric material, or a combination of the foregoing materials. As used herein, for example, a low-κ dielectric material may be or include a dielectric material having a dielectric constant κ less than approximately 3.9, 3, 2, or 1. The lower inner connecting wire 214 overlies the lower inner connecting via 212. In some embodiments, for example, the lower inner connecting via 212 and the lower inner connecting wire 214 may each be or include copper, aluminum, tungsten, another suitable conductive material, or a combination of the foregoing materials. The bottom electrode via 218 is disposed in the inner connecting dielectric structure 216 and overlies the lower inner connecting wire 214. The top electrode via 220 overlies the bottom electrode via 218. The memory cell 104 is disposed in the interconnect dielectric structure 216 and between the bottom electrode via 218 and the top electrode via 220. The upper interconnect via 222 is disposed in the interconnect dielectric structure 216 and overlies the top electrode via 220. The upper interconnect wiring 224 overlies the upper interconnect via 222.

[0029] In some embodiments, the memory cell 104 includes a bottom electrode 106, a top electrode 110, and a data storage structure 108 disposed between the bottom electrode 106 and the top electrode 110. During operation, the memory cell 104 forms and eliminates a conductive path 228 in a region 112 of the data storage structure 108 between the bottom electrode 106 and the top electrode 110 by a redox reaction. The presence of the conductive path 228 in the region 112 between the bottom electrode 106 and the top electrode 110 results in a low resistance state, while the absence of the conductive path 228 in the region 112 results in a high resistance state. Thus, the memory cell 104 can be switched between a high resistance state and a low resistance state by applying an appropriate bias to the memory cell 104 to create or eliminate the conductive path 228 in the region 112. In other embodiments, for example, the conductive path 228 may include an oxygen vacancy 226 disposed within the region 112 and extending between the bottom electrode 106 and the top electrode 110.

[0030] In some embodiments, the data storage structure 108 may include a co-doped dielectric material, so that the data storage structure 108 includes a dielectric material, a first dopant, and a second dopant. In some embodiments, the first dopant may be a cation and the second dopant may be an anion. In some embodiments, for example, the dielectric material may be or include a high-κ dielectric material, aluminum oxide (e.g., Al2O3), tantalum oxide, hafnium oxide, another suitable dielectric material, or a combination of the foregoing materials. As used herein, for example, a high-κ dielectric material may be or include a dielectric material having a dielectric constant κ greater than approximately 3.9, 9.34, 9.9, or 11.54. In some embodiments, for example, the first dopant may be or include nitrogen, carbon, fluorine, etc. In other embodiments, for example, the second dopant may be or include tantalum, cerium, hafnium, zirconium, etc. Therefore, in some embodiments, for example, the data storage structure 108 may be or include aluminum oxide doped with a first dopant and a second dopant, wherein the first dopant is different from the second dopant. In other embodiments, the first dopant may be configured to reduce the formation voltage of the data storage structure 108 , while the second dopant may be configured to prolong data retention of the data storage structure 108 .

[0031] In various embodiments, the first dopant (e.g., nitrogen, carbon, fluorine, etc.) comprises between about 1 percent and 15 percent of the chemical composition of the data storage structure 108. In some embodiments, if the first dopant is less than 1 percent of the chemical composition of the data storage structure 108, the formation voltage of the memory cell 104 cannot be reduced. In other embodiments, if the first dopant is greater than 15 percent of the chemical composition of the data storage structure 108, the durability of the memory cell 104 is reduced, thereby reducing the number of set operations and / or reset operations that can be performed on the data storage structure 108. In some embodiments, the second dopant (e.g., tantalum, cerium, hafnium, zirconium, etc.) comprises between about 2 percent and 20 percent of the chemical composition of the data storage structure 108. In some embodiments, if the second dopant is less than about 2 percent of the chemical composition of the data storage structure 108, the data retention of the memory cell 104 cannot be extended. In other embodiments, if the second dopant is greater than about 20 percent of the chemical composition of the data storage structure 108, the number of set operations and / or reset operations that can be performed on the data storage structure 108 is reduced. In some embodiments, the data storage structure 108 includes a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. In some embodiments, the first atomic percentage is less than the second atomic percentage. In other embodiments, the first atomic percentage may be in a range of about 1 percent to 15 percent, and / or the second atomic percentage may be in a range of about 2 percent to 20 percent. In some embodiments, the thickness of the data storage structure 108 is in a range of about 20 angstroms to 80 angstroms. In other embodiments, if the thickness of the data storage structure 108 is less than about 20 angstroms, high leakage current may occur between the bottom electrode 106 and the top electrode 110. In other embodiments, if the thickness of the data storage structure 108 is greater than about 80 angstroms, the formation voltage of the memory cell 104 is increased.

[0032] In some embodiments, for example, the bottom electrode via 218 and / or the top electrode via 220 may each be or include copper, aluminum, tungsten, combinations of the foregoing materials, etc. In some embodiments, for example, the bottom electrode 106 may be or include tantalum, tantalum nitride, titanium nitride, tungsten, ruthenium, iridium, platinum, etc. In other embodiments, for example, the top electrode 110 may be or include hafnium, hafnium nitride, titanium, titanium nitride, tantalum, tantalum nitride, etc. In further embodiments, aluminum comprises between about 20 and 50 percent of the chemical composition of the data storage structure 108, and / or oxygen comprises between about 50 and 70 percent of the chemical composition of the data storage structure 108. In some embodiments, the bottom electrode 106 may include a first dopant (e.g., nitrogen) and / or the top electrode 110 may include a first dopant (e.g., nitrogen). In further embodiments, the bottom electrode 106 and the top electrode 110 may include the same material. In other embodiments, the top electrode 110 may include a first dopant (eg, nitrogen) and / or a second dopant (eg, tantalum). For example, the top electrode 110 may include tantalum nitride.

[0033] Figure 3 A cross-sectional view of some embodiments of a memory device 300 is shown, and the memory device 300 corresponds to Figure 2 Some alternative embodiments of the memory device 200 are shown.

[0034] The interconnect dielectric structure 216 may be or include a plurality of ILD layers 302a to 302d. In some embodiments, for example, the ILD layers 302a to 302d may be or include an oxide (e.g., silicon dioxide), a low-κ dielectric material, an ultra-low-κ dielectric material, or another suitable dielectric material, respectively. In some embodiments, the memory cell 104 includes a bottom electrode 106, a data storage structure 108, a top electrode 110, and a cap layer 304. The cap layer 304 is disposed between the top electrode 110 and the top electrode via 220. In some embodiments, for example, the cap layer 304 may be or include hafnium, titanium, tantalum, aluminum, zirconium, another suitable material, or a combination of the foregoing materials. In some embodiments, a sidewall spacer structure 306 is disposed around the sidewalls of the data storage structure 108, the sidewalls of the top electrode 110, and the sidewalls of the cap layer 304. In some embodiments, for example, the sidewall spacer structure 306 may be or include silicon carbide, silicon nitride, etc.

[0035] In some embodiments, the data storage structure 108 may include a co-doped dielectric material such that the data storage structure 108 includes a dielectric material (e.g., aluminum oxide (Al2O3)), a first dopant (e.g., nitrogen, carbon, fluorine, etc.), and a second dopant (e.g., tantalum, cerium, hafnium, zirconium, etc.). In other embodiments, the cap layer 304 includes the second dopant (e.g., tantalum). In further embodiments, the sidewall spacer structure 306 includes the first dopant (e.g., nitrogen), for example, the sidewall spacer structure 306 may include silicon nitride.

[0036] Figure 4 A cross-sectional view of some embodiments of a memory device 400 is shown, and the memory device 400 corresponds to Figure 2 Some alternative embodiments of the memory device 200 are shown.

[0037] In some embodiments, the memory cell 104 includes a film stack 402, which includes: a bottom electrode via 218, a bottom electrode 106, a data storage structure 108, a top electrode 110, and a cap layer 304. The film stack 402 includes a middle region located above the lower interconnect wiring 214 and a peripheral region located below a pair of sidewalls of the sidewall spacer structure 306. The bottom surface of the middle region of the film stack 402 is disposed to be lower than the bottom surface of the peripheral region of the film stack 402.

[0038] Figure 5 A cross-sectional view of some embodiments of an integrated chip 500 is shown, which includes a first memory cell 104 a and a second memory cell 104 b laterally disposed within an embedded memory region 502 , wherein the embedded memory region 502 is laterally adjacent to a logic region 504 .

[0039] In some embodiments, the first storage unit 104a and / or the second storage unit 104b are respectively configured as Figure 3 The first memory cell 104a and the second memory cell 104b are laterally offset from the logic region 504. In some embodiments, the logic region 504 includes a lower inner connection line 214 disposed in the lower ILD layer 302a. In addition, an upper inner connection via 222 is disposed in the logic region 504 and vertically extends from the upper inner connection line 224 to the lower inner connection line 214.

[0040] Figure 6 Show Figure 5 Some embodiments of the integrated chip 500 are shown along Figure 5 A top view 600 taken along the line in FIG.

[0041] In some embodiments, Figure 6As shown in , when viewed from above, the first memory cell 104a and / or the second memory cell 104b each have a square shape. In some embodiments, when viewed from above, the first memory cell 104a and / or the second memory cell 104b may each have a rectangular shape, a circular shape, an elliptical shape, or another suitable shape. In addition, the sidewall spacer structure 306 surrounds the top cover layer 304 in the lateral direction. In other embodiments, when viewed from above, the upper inner communication hole 222 in the logic area 504 may have an elliptical shape or a circular shape, for example.

[0042] Figure 7 A cross-sectional view of some embodiments of an integrated chip 700 including a memory cell 104 disposed within an interconnect structure 714 and configured as a one-transistor one-resistor memory cell (1T1R) arrangement is shown.

[0043] In some embodiments, the integrated chip 700 includes an interconnect structure 714 overlying the substrate 202. In some embodiments, for example, the substrate 202 may be or include a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The transistor 706 is disposed in / on the substrate 202. In some embodiments, for example, the transistor 706 may be configured as a MOSFET. The transistor 706 includes a pair of source / drain regions 708 disposed in the substrate 202 and spaced apart laterally. The gate dielectric 710 is between the source / drain regions 708 and overlies the substrate 202, and the gate electrode 712 overlies the gate dielectric 710. In some embodiments, for example, the gate electrode 712 may be or include polysilicon or another suitable conductive material. The substrate 202 includes a first doping type (e.g., p-type), and the source / drain region 708 includes a second doping type (e.g., n-type) opposite to the first doping type. In some embodiments, the source / drain regions 708 include a doping concentration greater than that of the substrate 202. The well region 704 is disposed between the source / drain regions 708 and includes a first doping type (eg, p-type) having a doping concentration greater than that of the substrate 202.

[0044] The interconnect structure 714 includes an interconnect dielectric structure 216, a plurality of conductive vias 716, and a plurality of conductive wires 718. The plurality of conductive vias 716 and the plurality of conductive wires 718 are disposed within the interconnect dielectric structure 216 and are configured to provide electrical connections between various devices (e.g., transistors 706 and / or memory cells 104) disposed throughout the integrated chip 700. In some embodiments, for example, the conductive vias 716 and the conductive wires 718 may each be or include copper, aluminum, tungsten, a combination of the foregoing materials, or some other suitable conductive material. In some embodiments, the memory cell 104 is configured as Figure 3The memory cell 104 is shown and can be disposed between a lower conductive wiring 718 and an upper conductive wiring 718. In some embodiments, the bottom electrode 106 of the memory cell 104 is electrically coupled to the first source / drain region 708 of the transistor 706 via the interconnect structure 714. In other embodiments, the top electrode 110 of the memory cell 104 is electrically coupled to a bit line (BL) via the interconnect structure 714.

[0045] In some embodiments, the gate electrode 712 of the transistor 706 is electrically coupled to a word line (WL) so that an appropriate WL signal (e.g., voltage and / or current) can be applied to the gate electrode 712 to electrically couple the memory cell 104 to the BL and the source line (SL). The SL is electrically coupled to the second source / drain region 708 of the transistor 706, and the BL is electrically coupled to the first source / drain region 708 via the interconnect structure 714 and the memory cell 104. Thus, in some embodiments, the output of the BL and / or the output of the memory cell 104 can be accessed at the SL after applying an appropriate WL signal. In other embodiments, appropriate bias conditions can be applied to the transistor 706 and the memory cell 104 via the WL, SL, and BL so that a forming operation, a setting operation, a reset operation, or a reading operation can be performed on the memory cell 104. In further embodiments, a voltage can be applied at the transistor body node 702 (i.e., the body of the transistor 706) electrically coupled to the well region 704 disposed below the gate electrode 712. The voltage applied at transistor body node 702 can be configured to assist in controlling a conductive channel formed in well region 704. In other embodiments, since memory cell 104 has data storage structure 108 including first and second dopants, the feature size of transistor 706 can be reduced.

[0046] Figure 8 A cross-sectional view of some embodiments of an integrated chip 800 is shown, and the integrated chip 800 corresponds to Figure 7 Some alternative embodiments of the integrated chip 700 are shown. In some embodiments, the integrated chip 800 includes a memory cell 104 disposed within the interconnect structure 714 and configured as a two-transistor single-resistance memory cell (2T1R) arrangement.

[0047] In some embodiments, the integrated chip 800 includes a first transistor 706a and a second transistor 706b, wherein the first transistor 706a and the second transistor 706b are respectively configured as Figure 7The first transistor 706a and the second transistor 706b share a common source / drain region 708 disposed laterally between the first transistor 706a and the second transistor 706b. The common source / drain region 708 can be electrically coupled to the bottom electrode 106 of the memory cell 104 via an interconnect structure 714. In some embodiments, since the memory cell 104 has the data storage structure 108 including the first dopant and the second dopant, the feature size of the first transistor 706a and the feature size of the second transistor 706b can be reduced.

[0048] Figures 9 to 14 Cross-sectional views 900 to 1400 of some embodiments of a method of forming a memory device according to the present invention include a memory cell having a data storage structure including a first dopant and a second dopant. Figures 9 to 14 900 to 1400, but it should be understood that Figures 9 to 14 The structure shown in is not limited to the method but can exist independently of the method. Figures 9 to 14 It is described as a series of actions, but it should be understood that these actions are not restrictive, but the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions described and / or described can be omitted completely or in part.

[0049] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , a lower interconnect 214 is formed in the lower ILD layer 302a. A lower dielectric layer 302b is formed on the lower ILD layer 302a. A bottom electrode via layer 902 is formed on the lower interconnect 214 and the lower dielectric layer 302b. A memory cell layer stack 904 is formed on the bottom electrode via layer 902. The memory cell layer stack 904 includes a bottom electrode layer 906, a data storage layer 908, a top electrode layer 910, and a cap film 912. In some embodiments, each layer in the memory cell layer stack 904 may be formed by the following processes: for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, co-sputtering, electroless plating, electroplating, or another suitable growth process or deposition process.

[0050] In some embodiments, forming the memory cell layer stack 904 may include performing a deposition process to obtain each layer within the memory cell layer stack 904. For example, a first deposition process (e.g., CVD, PVD, etc.) may be performed to form a bottom electrode layer 906 on the bottom electrode via layer 902. In addition, a second deposition process (e.g., CVD, PVD, sputtering, co-sputtering, etc.) may be performed to form a data storage layer 908 on the bottom electrode layer 906. In some embodiments, the data storage layer 908 is formed in a manner such that the data storage layer 908 includes a dielectric material (e.g., aluminum oxide (Al2O3)) co-doped with a first dopant (e.g., nitrogen) and a second dopant (e.g., tantalum). In some embodiments, for example, the dielectric material may be or include a high-κ dielectric material, aluminum oxide (e.g., Al2O3), tantalum oxide, hafnium oxide, another suitable dielectric material, or a combination of the foregoing materials. In other embodiments, for example, the first dopant may be or include nitrogen, carbon, fluorine, etc. In other embodiments, for example, the second dopant may be or include tantalum, cerium, hafnium, zirconium, etc. Further, for example, the data storage layer 908 may be formed such that the data storage layer 908 includes a first atomic percentage of the first dopant and a second atomic percentage of the second dopant. In some embodiments, the first atomic percentage may be in a range of approximately 1 percent to 15 percent, and / or the second atomic percentage may be in a range of approximately 2 percent to 20 percent. In addition, the process of forming the data storage layer 908 may include depositing a composite (e.g., a dielectric material (e.g., a composite of aluminum oxide (Al2O3) and a second dopant (e.g., tantalum)) by a deposition process (e.g., CVD, PVD, sputtering, co-sputtering, etc.), while exposing the composite to an enhancement substance (e.g., nitrogen (N)) so that the data storage layer 908 includes a co-doped dielectric material (e.g., aluminum oxide co-doped with a first dopant and a second dopant). In further embodiments, an annealing process may be performed on the data storage layer 908 during the deposition process to cause the data storage layer 908 to include the first dopant and / or the second dopant. In some embodiments, the enhancement substance is a gas form of the first dopant. In further embodiments, the data storage layer 908 is formed to a thickness in a range of approximately 20 angstroms to 80 angstroms.

[0051] In some embodiments, the process of forming the data storage layer 908 may include performing a co-sputtering process in a plasma environment to deposit a composite comprising aluminum oxide and a second dopant (e.g., co-sputtering aluminum oxide (e.g., Al2O3) and tantalum oxide (e.g., Ta2O5)), wherein the plasma includes, for example, nitrogen (e.g., N2). In other embodiments, the process of forming the data storage layer 908 may include performing a CVD process or an ALD process in a plasma environment to deposit a composite (e.g., the composite comprises aluminum oxide (e.g., Al2O3) and tantalum oxide (e.g., Ta2O5)), wherein the plasma includes N2 or NH3. In further embodiments, the process of forming the data storage layer 908 may include performing a CVD process or an ALD process in a chamber using a first precursor and / or a second precursor to form a material (e.g., aluminum oxide), wherein the first precursor ensures that the material is doped with the first dopant and the second precursor ensures that the material is doped with the second dopant. In some embodiments, for example, the first precursor may be or include (NH4)OH or another suitable precursor. In other embodiments, the second precursor may be or include TaCl 5 , Ta(OC 2 H 5 ) 5 , or another suitable precursor, for example.

[0052] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a first mask layer 1002 is formed over the memory cell layer stack 904. In some embodiments, the first mask layer 1002 covers a middle region of the memory cell layer stack 904 and exposes a peripheral region of the memory cell layer stack 904.

[0053] like Fig.11 As shown in the cross-sectional view 1100, according to the first mask layer ( Fig.10 1002) for stacking the memory cell layers ( Fig.10 904) is patterned to define the data storage structure 108, the top electrode 110 and the cap layer 304. In some embodiments, the patterning process may include: Fig.10 1002) is exposed to one or more etchants; and a removal process (not shown) is performed to remove the first mask layer ( Fig.10 In some embodiments, the patterning process may etch through a portion of the data storage structure 108 so that the data storage structure 108 extends continuously along the upper surface of the bottom electrode layer 906 after the patterning process is performed.

[0054] In addition Fig.11, a passivation layer 1102 is formed on the cap layer 304 and the data storage structure 108. In some embodiments, for example, the passivation layer 1102 may be or include silicon carbide, silicon nitride, silicon oxynitride, etc. In other embodiments, the passivation layer 1102 may be deposited by, for example, CVD, PVD, ALD, or another suitable deposition process. In addition, after the passivation layer 1102 is formed, a second mask layer 1104 is formed on the passivation layer 1102, wherein the second mask layer 1104 overlies the cap layer 304.

[0055] like Fig.12 As shown in the cross-sectional view 1200, according to the second mask layer ( Fig.11 1104) Fig.11 The data storage structure 108 is formed by a top cap layer 304, a top electrode 110, a bottom electrode 106, a sidewall spacer structure 306, and a memory cell 104. In some embodiments, the patterning process completely etches through the data storage structure 108. In other embodiments, after the patterning process, the data storage structure 108, the bottom electrode 106, and the bottom electrode through hole 218 each have inclined relative outer sidewalls. In some embodiments, the memory cell 104 includes a cap layer 304, a top electrode 110, a bottom electrode 106, and a data storage structure 108 disposed between the bottom electrode 106 and the top electrode 110.

[0056] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a first upper ILD layer 302c is formed over and around the memory cell 104. In some embodiments, the first upper ILD layer 302c may be deposited by, for example, PVD, CVD, ALD, or another suitable deposition process. In addition, a top electrode via 220 is formed over the memory cell 104, wherein the top electrode via 220 extends through the first upper ILD layer 302c and the sidewall spacer structure 306 to contact the cap layer 304. In some embodiments, the top electrode via 220 may be formed by, for example, CVD, PVD, electroless plating, electroplating, or another suitable growth process or deposition process.

[0057] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14 , a second upper ILD layer 302d is formed on the first upper ILD layer 302c. In some embodiments, the second upper ILD layer 302d may be deposited by, for example, CVD, PVD, ALD, or another suitable deposition process. In addition, an upper inner communication via 222 and an upper inner connection wiring 224 are formed on the top electrode via 220. In some embodiments, the upper inner communication via 222 and / or the upper inner connection wiring 224 may be formed by a single damascene process or may be formed by a dual damascene process.

[0058] Fig.15 A method 1500 of forming a memory device including a memory cell according to the present invention is shown, the memory cell having a data storage structure including a first dopant and a second dopant. Although method 1500 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be implemented in an order different from the order shown and / or may be implemented simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be implemented at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0059] At act 1502, lower interconnect wiring is formed over a substrate. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1502 is shown.

[0060] At action 1504, a memory cell layer stack is formed above the lower interconnect wiring. The memory cell layer stack includes a bottom electrode layer, a top electrode layer, and a data storage layer disposed between the top electrode layer and the bottom electrode layer. The data storage layer includes a co-doped dielectric material. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1504 is shown.

[0061] At act 1506, a first patterning process is performed on the memory cell layer stack to define a data storage structure and a top electrode. Fig.10 and Fig.11 Cross-sectional views 1000 and 1100 corresponding to some embodiments of act 1506 are shown.

[0062] At act 1508, a passivation layer is formed over the top electrode and along an upper surface of the data storage structure. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 1508 is shown.

[0063] At action 1510, a second patterning process is performed on the passivation layer, the data storage structure, and the bottom electrode layer to define the sidewall spacer structure, the bottom electrode, and the memory cell. Fig.12 Cross-sectional view 1200 corresponding to some embodiments of act 1510 is shown.

[0064] At act 1512, a top electrode via is formed over the memory cell. Fig.13 Cross-sectional view 1300 corresponding to some embodiments of act 1512 is shown.

[0065] At action 1514, an upper interconnect via and an upper interconnect wiring are formed over the top electrode via. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 1514 is shown.

[0066] Thus, in some embodiments, the present invention is directed to a memory cell comprising a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a co-doped dielectric material.

[0067] In some embodiments, the present application provides a memory device, comprising: a substrate; a bottom electrode overlying the substrate; a top electrode overlying the bottom electrode; and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a dielectric material doped with a first dopant and a second dopant.

[0068] In some embodiments, the first dopant is different from the second dopant.

[0069] In some embodiments, the dielectric material is a high-k dielectric material.

[0070] In some embodiments, the dielectric material is aluminum oxide, the first dopant is nitrogen, and the second dopant is tantalum.

[0071] In some embodiments, the dielectric material includes a first atomic percentage of the first dopant and a second atomic percentage of the second dopant, wherein the second atomic percentage is greater than the first atomic percentage.

[0072] In some embodiments, the first atomic percentage is in a range of about 1 percent to about 15 percent and the second atomic percentage is in a range of about 2 percent to about 20 percent.

[0073] In some embodiments, the memory device further includes: a sidewall spacer structure overlying the substrate, wherein the sidewall spacer structure laterally surrounds the sidewall of the data storage structure and the sidewall of the top electrode.

[0074] In some embodiments, the sidewall spacer structure includes the first dopant.

[0075] In some embodiments, the top electrode and / or the bottom electrode comprises the second dopant. In some embodiments, the present application provides an integrated chip, the integrated chip comprising: a substrate; a bottom electrode via overlying the substrate; a top electrode via overlying the bottom electrode via; and a resistive random access memory (RRAM) cell disposed between the bottom electrode via and the top electrode via, wherein the RRAM cell comprises a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a co-doped high-κ dielectric material.

[0076] In some embodiments, the co-doped high-k dielectric material includes a first dopant and a second dopant different from the first dopant.

[0077] In some embodiments, the top electrode includes a first conductive material and the top electrode via includes a second conductive material different from the first conductive material.

[0078] In some embodiments, the first conductive material includes the first dopant or the second dopant.

[0079] In some embodiments, the integrated chip further includes: a sidewall spacer structure overlying the bottom electrode through hole, wherein the sidewall spacer structure laterally surrounds the sidewall of the data storage structure; and a top cover layer disposed between the top electrode and the top electrode through hole.

[0080] In some embodiments, the sidewall spacer structure extends continuously from a sidewall of the data storage structure to an upper surface of the data storage structure.

[0081] In some embodiments, the data storage structure includes a first pair of opposing sidewalls and a second pair of opposing sidewalls, wherein the first pair of opposing sidewalls are laterally spaced apart between the second pair of opposing sidewalls. In some embodiments, the present application provides a method of forming a memory device, the method comprising: forming a lower conductive wiring on a substrate; depositing a bottom electrode layer on the lower conductive wiring; forming a data storage structure on the bottom electrode layer, so that the data storage structure includes a dielectric material, a first dopant, and a second dopant; forming a top electrode on the data storage structure; and patterning the bottom electrode layer, the data storage structure, and the top electrode to define a memory cell.

[0082] In some embodiments, the data storage structure includes a first atomic percentage of the first dopant and a second atomic percentage of the second dopant, wherein the second atomic percentage is greater than the first atomic percentage.

[0083] In some embodiments, forming the data storage structure includes depositing a composite of the dielectric material and the second dopant while exposing the composite to an enhancement substance, wherein depositing the composite includes performing a physical vapor deposition process and the enhancement substance includes the first dopant.

[0084] In some embodiments, the dielectric material is aluminum oxide, the first dopant is nitrogen, and the second dopant is tantalum. The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

[0085] [Explanation of Symbols]

[0086] 100, 200, 300, 400: Storage devices

[0087] 102, 706: Transistor

[0088] 104: Storage unit

[0089] 104a: First storage unit

[0090] 104b: Second storage unit

[0091] 106: Bottom electrode

[0092] 108: Data storage structure

[0093] 110: Top electrode

[0094] 112: District

[0095] 202: Substrate

[0096] 204: Source / drain region

[0097] 206: Gate dielectric layer

[0098] 208, 712: Gate electrode

[0099] 210, 306: Sidewall spacer structure

[0100] 212: Lower internal connecting hole

[0101] 214: Lower internal wiring

[0102] 216: Interconnect dielectric structure

[0103] 218: Bottom electrode through hole

[0104] 220: Top electrode through hole

[0105] 222: Upper internal connecting hole

[0106] 224: Upper internal wiring

[0107] 226: Oxygen vacancy

[0108] 228: Conductive Path

[0109] 302a: Interlayer dielectric layer / lower interlayer dielectric layer

[0110] 302b: Interlayer dielectric layer / lower dielectric layer

[0111] 302c: interlayer dielectric layer / first upper interlayer dielectric layer

[0112] 302d: interlayer dielectric layer / second upper interlayer dielectric layer

[0113] 304: Top cover layer

[0114] 402: Membrane stack

[0115] 500, 700, 800: integrated chip

[0116] 502: Embedded storage area

[0117] 504: Logical area

[0118] 600: Top view

[0119] 702: Transistor body node

[0120] 704: Well Area

[0121] 706a: First transistor

[0122] 706b: Second transistor

[0123] 708: Source / drain region / first source / drain region / second source / drain region / common source / drain region

[0124] 710: Gate Dielectric

[0125] 714: Inner Link Structure

[0126] 716: Conductive vias

[0127] 718: Conductive wiring / lower conductive wiring / upper conductive wiring

[0128] 900, 1000, 1100, 1200, 1300, 1400: Section view

[0129] 902: Bottom electrode via layer

[0130] 904: Storage unit layer stacking

[0131] 906: Bottom electrode layer

[0132] 908: Data storage layer

[0133] 910: Top electrode layer

[0134] 912: Top cover film

[0135] 1002: first mask layer

[0136] 1102: Passivation layer

[0137] 1104: Second mask layer

[0138] 1500: Methods

[0139] 1502, 1504, 1506, 1508, 1510, 1512, 1514: Action

Claims

1. A storage device, characterized in that include: substrate; a bottom electrode overlying the substrate; a top electrode overlying the bottom electrode; as well as A data storage structure is disposed between the top electrode and the bottom electrode, wherein the data storage structure includes a dielectric material doped with a first dopant and a second dopant, wherein the dielectric material includes a first atomic percentage of the first dopant and a second atomic percentage of the second dopant, the second atomic percentage is different from the first atomic percentage, and wherein the first atomic percentage is in the range of 1 percent to 15 percent and the second atomic percentage is in the range of 2 percent to 20 percent. 2 . The memory device of claim 1 , wherein the first dopant is different from the second dopant.

3. The memory device of claim 1, wherein the dielectric material is a high-k dielectric material.

4. The memory device of claim 1, wherein the dielectric material is aluminum oxide, the first dopant is nitrogen, and the second dopant is tantalum. The memory device of claim 1 , wherein the second atomic percentage is greater than the first atomic percentage. 6 . The memory device according to claim 1 , further comprising a metal cap layer disposed on the top electrode.

7. The memory device according to claim 1, further comprising: A sidewall spacer structure overlies the substrate, wherein the sidewall spacer structure laterally surrounds a sidewall of the data storage structure and a sidewall of the top electrode. 8 . The memory device of claim 7 , the sidewall spacer structure comprising the first dopant. 9 . The memory device of claim 1 , wherein the top electrode and / or the bottom electrode comprises the second dopant.

10. An integrated chip, characterized in that include: substrate; a bottom electrode through hole overlying the substrate; a top electrode through hole overlying the bottom electrode through hole; a resistance random access memory cell disposed between the bottom electrode via and the top electrode via, wherein the resistance random access memory cell comprises a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode, wherein the data storage structure comprises a co-doped high-k dielectric material; a sidewall spacer structure overlying the bottom electrode through hole, wherein the sidewall spacer structure laterally surrounds a sidewall of the data storage structure; as well as A metal cap layer is disposed between the top electrode and the top electrode through hole, The sidewall spacer structure extends along a top surface of the metal cap layer. 11 . The integrated chip of claim 10 , wherein the co-doped high-k dielectric material comprises a first dopant and a second dopant different from the first dopant.

12. The integrated chip of claim 11, wherein the top electrode comprises a first conductive material and the top electrode via comprises a second conductive material different from the first conductive material. 13 . The integrated chip according to claim 12 , wherein the first conductive material comprises the first dopant or the second dopant.

14. The integrated chip of claim 10, wherein the metal cap layer comprises hafnium, titanium, tantalum, aluminum, zirconium, or a combination thereof. 15 . The integrated chip according to claim 10 , wherein the sidewall spacer structure continuously extends from a sidewall of the data storage structure to an upper surface of the data storage structure.

16. The integrated chip of claim 10, wherein the data storage structure comprises a first pair of opposing sidewalls and a second pair of opposing sidewalls, wherein the first pair of opposing sidewalls are laterally spaced apart between the second pair of opposing sidewalls.

17. A method for forming a memory device, characterized in that The method comprises: forming a lower conductive wiring on the substrate; depositing a bottom electrode layer over the lower conductive wiring; forming a data storage structure above the bottom electrode layer, such that the data storage structure comprises a dielectric material, a first dopant, and a second dopant; forming a top electrode over the data storage structure; and patterning the bottom electrode layer, the data storage structure and the top electrode to define a memory cell, The data storage structure is formed as follows: A composite of the dielectric material and the second dopant is deposited while exposing the composite to an enhancement substance, wherein depositing the composite includes performing a physical vapor deposition process and the enhancement substance includes the first dopant.

18. The method of forming a memory device of claim 17, wherein the data storage structure comprises a first atomic percentage of the first dopant and a second atomic percentage of the second dopant, wherein the second atomic percentage is greater than the first atomic percentage.

19. The method of forming a memory device according to claim 17, wherein the first dopant is different from the second dopant.

20. The method of forming a memory device of claim 17, wherein the dielectric material is aluminum oxide, the first dopant is nitrogen, and the second dopant is tantalum.

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