Boost DC-DC converter circuit with intelligent anti-ringing circuit actuation

Abstract

Embodiments of the present disclosure relate to a boost DC-DC converter circuit with intelligent anti-ringing circuit actuation. An inductor and a shunt switch circuit are connected in parallel between an input node and an intermediate node. A first power transistor is connected between the intermediate node and a ground node. A second power transistor is connected between the intermediate node and an output node. The first power transistor and the second power transistor are driven in response to a pulse width modulation (PWM) drive cycle having an on-time and an off-time. The input node receives a DC input voltage, and a DC output voltage is generated at the output node. A control circuit senses the input node and the output node and determines whether the DC input voltage is within a threshold voltage of the DC output voltage. In response to this determination, the shunt switch circuit conducts only during the off-time of the PWM drive cycle.

Description

Technical Field

[0001] Embodiments and implementations relate to boost DC-DC converter circuits. Background Art

[0002] Reference Figure 1 , which shows a circuit diagram of a conventional boost DC-DC converter circuit 10. A DC input voltage Vin is applied to an input node 12, and the circuit 10 generates a DC output voltage Vout at an output node 14. An inductor 16 is connected between the input node 12 and an intermediate node 18. A first transistor switch 20 (also referred to as a low-side switch) is connected between the intermediate node 18 and ground. The first transistor switch 20 may include, for example, an n-channel power transistor device having a drain terminal connected to the intermediate node 18 and a source terminal connected to ground. The control terminal of the first transistor switch 20 is driven by a pulse-width modulation (PWM) drive signal 24. A second transistor switch 26 (also referred to as a high-side switch) is connected between the intermediate node 18 and the output node 14. The second transistor switch 26 may include, for example, an n-channel power transistor device having a drain terminal connected to the intermediate node 18 and a source terminal connected to the output node 14. The control terminal of the second transistor switch 20 is driven by a signal 30 that is 180° out of phase (e.g., its logical inverse) with the pulse-width modulation (PWM) drive signal 24. A resistive voltage divider 34 is connected between the output node 14 and ground. The voltage divider 34 is formed by a series connection of a first resistor 36 and a second resistor 38. A feedback voltage Vfb is generated at a tap node between the resistors 36 and 38 of the voltage divider 34, and the feedback voltage Vfb is a scaled version of the output voltage Vout. An output capacitor 40 is connected between the output node 14 and ground. The PWM control circuit 44 generates the PWM drive signals 24 and 30 in response to a comparison of the feedback voltage Vfb with a reference voltage Vref.

[0003] In operation, the drive signal 24 is asserted to turn on the low-side transistor 20. This connects the inductor 16 between the input node 12 and ground, and the current through the inductor increases. Then, the drive signal 24 is de-asserted to turn off the low-side transistor 20, and the drive signal 30 is asserted to turn on the high-side transistor 26. Then, the inductor current discharges into the output capacitor 40, and the output voltage Vout rises. The output voltage Vout is sensed by the resistive voltage divider 34 to generate a feedback voltage Vfb, which is compared with a reference voltage Vref. The difference between Vfb and Vref (referred to as the error voltage) is used by the PWM control circuit 44 to set the length of the time that the drive signal 24 is asserted to turn on the low-side transistor 20. One period of the PWM control signal used to drive the transistors 20 and 26 is formed by the on-time (Ton) of the low-side transistor 20 and the subsequent off-time (Toff) of the low-side transistor 20 (where the duty cycle of the PWM control signal is equal to Ton / (Ton + Toff)).

[0004] Even when the magnitude of the input voltage Vin is at a level very close to the desired magnitude of the output voltage Vout, the DC-DC converter should be able to maintain a given performance. This operation is crucial for boost DC-DC converters; in fact, the closer Vin is to Vout, the more difficult it is for the converter to achieve a small duty cycle for the PWM control signal and the worse it performs. In these adverse situations, the duty cycle required for the PWM control signal should be close to zero in order to maintain output regulation. More specifically, for a boost DC-DC converter with a fixed frequency, this means that the on-time (Ton) of the drive signal 24 that is asserted to turn on the low-side transistor 20 should be reduced to zero. Unfortunately, this is problematic because the on-time Ton is bottom-limited and cannot be reduced to zero. This is due to the fact that propagation delays, the on / off times of the power transistors, and dead times are inevitable and limit the minimum viable value of the on-time Ton.

[0005] The bottom - limited on - time \(T_{on}\) is converted to a bottom - limited minimum current. During each cycle of the converter operation, this bottom - limited minimum current accumulates inside the inductor 16 during the on - time \(T_{on}\) and is transferred to the output during the off - time \(T_{off}\). This limitation results in an inevitable natural skip behavior. In fact, when the voltage level of the input voltage \(V_{in}\) is very close to the output voltage \(V_{out}\), the skip mode occurs when the boost DC - DC converter can no longer operate at the theoretically required small duty cycle. In other words, since the converter cannot reduce its on - time \(T_{on}\), the minimum current accumulates and then transfers an excessive minimum current on the output 14, and \(V_{out}\) increases. As a result, the converter is out of regulation. In these cases, the converter operation is usually inhibited by skipping one or more switching cycles in order to regain the ability to maintain regulated operation. As a result, when switching cycles are skipped during the skip mode, no charge is transferred to the output.

[0006] However, skip - mode operation inherently generates an undesirable output ripple that is greater than the ripple that occurs in the normal operating mode of the boost converter (i.e., continuous conduction mode (CCM)). In some applications that use boost converters, this behavior is not allowed. For example, in AMOLED applications, the positive regulated power supply for the display panel is provided by a boost DC - DC converter, and the output ripple on this rail is directly converted into display flicker. Therefore, the output ripple must be minimized. Thus, the DC - DC boost converter must remain in the continuous conduction mode and the skip mode must be avoided.

[0007] The first possible solution to this problem is to use a buck - boost topology for the DC - DC converter instead. This would solve the problems associated with the skip mode and would keep the converter in the CCM mode all the time when \(V_{in}\) is close to \(V_{out}\). However, using a buck - boost topology in many applications comes at an unacceptable cost: the circuit topology requires more power transistor devices, is more complex, requires a larger silicon area to achieve comparable efficiency, and will experience higher current leakage through the power transistor devices.

[0008] The second possible solution is to utilize a different control scheme. For example, the DC - DC frequency can be changed and reduced in order to achieve a smaller duty cycle (e.g., constant on - time (COT) control, pulse - frequency modulation (PFM), etc.). Due to customer requirements, this alternative solution is not always feasible. In fact, in some applications, customers explicitly require the use of a boost DC - DC converter with a fixed frequency (with a strictly specified operating frequency), and in those cases, the alternative control scheme is not an option. Summary of the Invention

[0009] In one embodiment, a circuit includes: an inductor; a first power transistor; wherein the inductor and the first power transistor are connected in series between a DC power supply node and a ground node; a shunt switch circuit connected in parallel with the inductor; a pulse width modulation (PWM) drive circuit configured to drive a control terminal of the first power transistor with a PWM drive signal having an on-time and an off-time; and a control circuit configured to sense an input voltage at the DC power supply node and configured to turn on the shunt switch circuit in response to a level of the sensed input voltage and only during the off-time of the PWM drive signal.

[0010] In one embodiment, the control circuit is configured to receive the PWM drive signal, sense a difference between the input voltage at the DC power supply node and the output voltage generated at a DC output node, and turn on the shunt switch circuit in response to a level of the sensed difference and when the received PWM drive signal is in the off-time so as to transfer a portion of the inductor current output by the inductor during the off-time device back to the DC power supply node through the shunt switch circuit.

[0011] In one embodiment, a circuit includes: an inductor connected between an input node and an intermediate node; a first power transistor connected between the intermediate node and a ground node, the first power transistor being turned on during an on-time of a pulse width modulation (PWM) drive cycle; a second power transistor connected between the intermediate node and an output node, the second power transistor being turned on during an off-time of the PWM drive cycle; a shunt switch circuit connected in parallel with the inductor between the input node and the intermediate node; wherein the input node receives a DC input voltage and a DC output voltage is generated at the output node; and a control circuit configured to sense the input node and the output node and determine whether the DC input voltage is within a threshold voltage of the DC output voltage and, in response to the determination, turn on the shunt switch circuit only during the off-time of the PWM drive cycle. Description of the Drawings

[0012] Other advantages and features of the present invention will become apparent by examining the detailed description of the fully non-limiting embodiments and implementations and the drawings, wherein:

[0013] Figure 1 is a circuit diagram of a conventional boost DC-DC converter circuit;

[0014] Figure 2 is a circuit diagram of a boost DC-DC converter circuit according to an embodiment of the present invention;

[0015] Figures 3A to 3B is a circuit diagram of an example shunt switch; and

[0016] Figure 4 is a circuit diagram of a boost DC-DC converter circuit according to another embodiment of the present invention. Detailed Description

[0017] Now referring to Figure 2 , which shows a circuit diagram of a DC-DC converter circuit 100 according to an embodiment of the present invention. A DC input voltage Vin is applied to an input node 12, and the circuit 10 generates a DC output voltage Vout at an output node 14. An inductor 16 is connected between the input node 12 and an intermediate node 18. A shunt switch 15 is also connected between the input node 12 and the intermediate node 18 and is in parallel with the inductor 16. The shunt switch 15 may include, for example, an n-channel power transistor device having a drain terminal connected to the intermediate node 18 and a source terminal connected to the input node 12 (e.g., see Figure 3A ). Alternatively, the shunt switch 15 may include a plurality of power transistor devices connected in series between the input node 12 and the intermediate node 18 (e.g., see Figure 3B , which shows the use of a series connection of two n-channel power transistor devices).

[0018] A first transistor switch 20 (also referred to as a low-side switch) is connected between the intermediate node 18 and ground. The first transistor switch 20 may include, for example, an n-channel power transistor device having a drain terminal connected to the intermediate node 18 and a source terminal connected to ground. The control terminal of the first transistor switch 20 is driven by a pulse-width modulation (PWM) drive signal 24. A second transistor switch 26 (also referred to as a high-side switch) is connected between the intermediate node 18 and the output node 14. The second transistor switch 26 may include, for example, an n-channel power transistor device having a drain terminal connected to the intermediate node 18 and a source terminal connected to the output node 14. The control terminal of the second transistor switch 20 is driven by a signal 30 that is 180° out of phase (e.g., its logical inverse) with the pulse-width modulation (PWM) drive signal 24.

[0019] A resistive voltage divider 34 is connected between the output node 14 and ground. The voltage divider 34 is formed by a series connection of a first resistor 36 and a second resistor 38. A feedback voltage Vfb is generated at a tap node between the resistors 36 and 38 of the voltage divider 34, and the feedback voltage Vfb is a scaled version of the output voltage Vout.

[0020] The PWM control circuit 44 generates the PWM drive signals 24 and 30 in response to a comparison of the feedback voltage Vfb with a reference voltage Vref.

[0021] An output capacitor 40 is connected between the output node 14 and ground.

[0022] A resistive voltage divider 17 is connected between the input node 12 and ground. The voltage divider 17 is formed by a series connection of a first resistor 19 and a second resistor 21. A voltage Vinsc is generated at the tap node between the resistors 19 and 21 of the voltage divider 17, and the voltage Vinsc is a scaled version of the input voltage Vin.

[0023] A resistive voltage divider 23 is connected between the output node 14 and ground. The voltage divider 23 is formed by a series connection of a first resistor 25 and a second resistor 27. A voltage Voutsc is generated at the tap node between the resistors 25 and 27 of the voltage divider 23, and the voltage Voutsc is a scaled version of the output voltage Vout. In one embodiment, the same resistive voltage divider can be used to generate Vfb and Voutsc, and in this case, Vfb = Voutsc. Alternatively, a single resistive voltage divider having multiple tap nodes can be used to generate Vfb and Voutsc.

[0024] A voltage comparator circuit 31 (having a hysteresis voltage Vhyst) has a first (non-inverting) input that receives the scaled input voltage Vinsc, and has a second (inverting) input that receives the scaled output voltage Voutsc. The voltage comparator circuit 31 is configured to compare the scaled input voltage Vinsc with the scaled output voltage Voutsc, and to determine based on this comparison whether the difference between the scaled input voltage Vinsc and the scaled output voltage Voutsc is less than the hysteresis voltage Vhyst (i.e., when Vinsc - Voutsc < Vhyst). In other words, the voltage comparator circuit 31 detects the time when the difference between the input voltage Vin and the output voltage Vout is less than a comparison threshold voltage Vth set by the hysteresis voltage Vhyst (i.e., when Vin - Vout < Vth, where Vth can be equal to 200 mV, for example). In response to Vinsc - Voutsc < Vhyst (i.e., Vin - Vout < Vth), the output 35 of the voltage comparator circuit 31 is asserted to logic high. A logic circuit in the form of a logical AND gate 33 has a first input that receives the output 35 of the voltage comparator circuit 31, and has a second input that receives a signal 30, where the signal 30 is the logical inversion of a pulse width modulation (PWM) drive signal 24. When the pulse width modulation (PWM) drive signal 24 is logic low (in other words, logic low during the on-time Ton and logic high during the off-time Toff), the signal 30 is logic high. When both the output 35 and the signal 30 are logic high, the output 39 of the AND gate 33 is logic high, and the shunt switch 15 is actuated (i.e., turned on) to couple the intermediate node 18 to the input node 12 through a resistive circuit connection having a resistance Ron (e.g., the source-drain path of an actuated transistor).

[0025] In operation, the drive signal 24 is asserted to turn on the low-side transistor 20 for a duration of time Ton. This connects the inductor 16 between the input node 12 and ground, and the current IL through the inductor increases. Then, the drive signal 24 is de-asserted to turn off the low-side transistor 20, and the drive signal 30 is asserted to turn on the high-side transistor 26 for a duration of time Toff. Then, the inductor current discharges along with the current Iout delivered to the output capacitor 40, and the output voltage Vout rises. The output voltage Vout is sensed by the resistive voltage divider 34 to generate a feedback voltage Vfb, which is compared with a reference voltage Vref. The difference between Vfb and Vref (referred to as the error voltage) is used by the PWM control circuit 44 to set the length of the time (i.e., time (Ton)) during which the drive signal 24 is asserted to turn on the low-side transistor 20 relative to the period of the PWM control signal (given by the sum of Ton and Toff).

[0026] The voltage comparator circuit 31 compares the input voltage Vin with the output voltage Vout (by comparing the scaled input voltage Vinsc and the scaled output voltage Voutsc generated by the voltage dividers 17 and 23). If the input voltage Vin is at a level within the threshold voltage Vth of the output voltage Vout, the output 35 of the voltage comparator circuit 31 is asserted to logic high (since the difference between the scaled input voltage Vinsc and the scaled output voltage Voutsc is less than the hysteresis voltage Vhyst). When the signal 30 (which is the logical inverse of the pulse-width modulation (PWM) drive signal 24) is simultaneously asserted to logic high at the end of the on-time Ton (this time period corresponds to the off-time (Toff) of the converter), the logic AND gate 33 drives the signal 39 to logic high to turn on the shunt switch 15 and allow the shunt current Ish to flow from the intermediate node 18 to the input node 12. This current Ish subtracts from the current Iout delivered to the load capacitor 40 (Iout = IL - Ish). The operation of the actuated shunt switch 15 effectively diverts a portion of the current accumulated in the inductor 16 back to the input node 12. The magnitude of the shunt current Ish is given by Ish = (Vout - Vin) / Ron, where Ron is the on-resistance of the resistive circuit connection between the intermediate node 18 and the input node 12 (e.g., the source-drain path of the actuated transistor).

[0027] In continuous conduction mode (CCM), the normal operation is: during the on-time Ton, the inductor 16 is charged at Vin by closing the low-side switch transistor 20, and then during the off-time Toff, the inductor 16 is discharged to Vout by opening the low-side switch transistor 20 and closing the high-side switch transistor 26 to deliver the current Iout to the load capacitor 40. In the case where Vin is at a level close to Vout, the duty cycle is adjusted and the on-time is reduced. For reasons discussed elsewhere in this document, it is not possible to drive the on-time Ton to 0. During the off-time Toff (i.e., during the inductor 16 discharge phase), the actuation of the shunt switch 15 allows the current IL accumulated inside the inductor 16 to be discharged to the output node 14 (as usual) as the current Iout through the switch 26, and to be discharged back to the input node 12 as the current Ish through the switch 15. As a result, the boost DC-DC converter 100 is forced to maintain a larger on-time Ton (i.e., during the inductor 16 charge phase) in order to accumulate the additional current required to maintain Vout in regulation.

[0028] The actuation of the shunt switch 15 in response to the input voltage Vin within the threshold voltage Vth of the output voltage Vout enables the boost DC-DC converter 100 to operate continuously over a much wider voltage range in CCM. As a result, the undesired skip-mode behavior is mitigated and delayed (and may even be completely avoided). The design and scaling of the shunt switch 15 sets the on-resistance (Ron) of the device to ensure CCM operation for the desired difference between the output voltage Vout and the input voltage Vin.

[0029] When the shunt switch 15 is actuated, the siphoning of the current Ish from the intermediate node 18 effectively amounts to adding an additional load to the converter 100. Advantageously, the additional load is on the input node 12 rather than on the output node 14, and for this reason, the efficiency of the converter 100 is minimally affected by the actuation of the shunt switch 15. In fact, during the off-time Toff, the accumulated additional inductor current IL is recovered back to the input node 12 at the input voltage Vin through the shunt current Ish, and thus is not wasted but is effectively recycled.

[0030] Typically, since for a given input voltage Vin and output voltage Vout, the converter 100 is not pushed to operate at its lower limit or at the minimum value of the on-time (Ton) for inductor charging, the dynamic performance of the converter 100 is improved.

[0031] If the on-resistance (Ron) of the shunt switch 15 is relatively low (such as when the switch 15 is implemented as a single high-power transistor device), actuation of the shunt switch 15 by the signal 39 may interfere with the operation of the DC-DC converter 100 and cause an undesired transient in the output voltage Vout. This is especially true if the shunt switch 15 is scaled such that the shunt current Ish is a large magnitude compared to the load current IL. To address this issue, Figure 4 A circuit diagram of an alternative embodiment for the converter 100’ is shown. Figure 4 The converter 100’ of Figure 2 differs from the converter 100 in Figure 3A that Figure 3B it has a variable on-resistance (Ron_var) in the implementation of the shunt switch 15’. The shunt switch 15’ is formed by a plurality (in this case, n) of switch circuits 15-1 to 15-n connected in parallel with each other between the input node 12 and the intermediate node 18, and the shunt switch 15’ is also connected in parallel with the inductor 16. For example, each switch circuit 15-1, 15-n of the shunt switch 15’ may include a circuit such as shown by

[0032] Figure 4 and also has an on-resistance (Ron) when actuated. Figure 2 The converter 100’ of

[0033] also differs from the converter 100 in the implementation of the logic circuit, which is configured as a digital control circuit 33’ that operates to generate a plurality (in this case, n) of control signals 39’ for individually controlling the actuation of the switch circuits 15-1 to 15-n of the variable-resistance shunt switch 15’. Control of the individual actuation of the switch circuits 15-1 to 15-n allows setting of the variable on-resistance (Ron_var) of the shunt switch 15’. As a non-limiting example, consider a circuit architecture where the switch circuits 15-1 to 15-n are matching transistors with substantially the same on-resistance: if only a single switch circuit 15 is actuated, the on-resistance Ron_var is equal to the on-resistance Ron of the actuated switch circuit 15; conversely, if two switch circuits 15 are actuated, the on-resistance Ron_var is equal to half of the on-resistance Ron; conversely, if three switch circuits 15 are actuated, the on-resistance Ron_var is equal to one-third of the on-resistance Ron. However, more generally, the designer of the circuit architecture can utilize switch circuits 15-1 to 15-n with different on-resistances. Thus, it will be understood that for each additional switch circuit 15-1 to 15-n actuated by the digital control circuit 33’, the variable on-resistance Ron_var of the shunt switch 15’ decreases in a known and controllable manner.

[0033] In response to the assertion of a logic high at the output 35 of the voltage comparator circuit 31 (when the difference between the scaled input voltage Vinsc and the scaled output voltage Voutsc is less than the hysteresis voltage Vhyst), the digital control circuit 33’ is enabled to operate. In response to being enabled by signal 35, the digital control circuit 33’ generates a control signal 39’ (during the off-time Toff after the end of the on-time Ton) in response to a signal 30 output from the PWM drive controller 44. The control signal 39’ is generated in a manner that sequentially actuates (i.e., turns on) the n switch circuits 15-1 to 15-n. As a result, the variable on-resistance Ron_var of the shunt switch 15’ gradually decreases from an infinite resistance (or open-circuit condition) to the on-resistance of a single switch circuit 15 (e.g., Ron), and further terminates in the on-resistance of the n switch circuits 15 in parallel (e.g., Ron / n) through one or more steps.

[0034] In response to a logic low at the output 35 of the voltage comparator circuit 31 (when the difference between the scaled input voltage Vinsc and the scaled output voltage Voutsc is greater than the hysteresis voltage Vhyst), the operation of the digital control circuit 33’ is disabled. In response to being disabled by signal 35, the digital control circuit 33’ generates a control signal 39’ (during the off-time Toff after the end of the on-time Ton) in response to a signal 30 output from the PWM drive controller 44. The control signal 39’ is generated in a manner that sequentially de-actuates (i.e., turns off) the n switch circuits 15-1 to 15-n. As a result, the variable on-resistance Ron_var of the shunt switch 15’ gradually increases from the on-resistance of the n switch circuits 15 in parallel (e.g., Ron / n), and further reaches the on-resistance of a single switch circuit 15 (i.e., Ron) through one or more steps, and then reaches an infinite resistance (or open-circuit condition).

[0035] One or more switching cycles of the PWM control signal generated by the PWM drive controller 44 can occur between successive steps of the gradual decrease / increase of the variable on-resistance Ron_var, which is effected by the selective actuation / de-actuation of each of the n switch circuits 15-1 to 15-n. As an example of this: one switch 15 can be actuated / de-actuated by the control signal 39’ in the first cycle of the PWM drive signal, the second, third, and fourth subsequent cycles occur while the control signal 39’ remains unchanged, and then the next switch 15 can be actuated / de-actuated in the fifth subsequent cycle of the PWM drive signal.

[0036] It will be noted that due to the operation of the digital control circuit 33’, the gradual decrease / increase of the variable on-resistance Ron_var of the shunt switch 15’ will advantageously result in a more abrupt behavior and the avoidance of an undesired transient on the output voltage Vout.

[0037] Compared with the prior art solutions, Figure 2 and Figure 4 the use of the shunt switch 15, 15’ solutions presents the following advantages: a) the performance of the converters 100, 100’ is enhanced in a minimum-effort implementation manner, and without using the skip mode, the boost DC-DC can guarantee high performance at a higher input voltage Vin; b) the actuation of the shunt switch 15, 15’ in the proposed manner has a negligible impact on the overall efficiency of the converters 100, 100’; specifically, the impact on efficiency is very low, negligible, and limited to the joule losses and switching losses for driving the shunt switch 15, 15’; c) in terms of circuit area consumption, the difference is negligible compared to an equivalent general / common / standard architecture (e.g., see Figure 1 ); d) in some circuit implementations, the shunt switch 15, 15’ has already been deployed in the DC-DC converter for different purposes, as an anti-ringing (i.e., ringing eliminator) switch, which suppresses ringing at node 18 in other functional modes (e.g., in discontinuous conduction mode (DCM), see, for example, FIG. 7 of U.S. Patent No. 8169198 (incorporated by reference)), so for additionally using the shunt switch driven by different circuits (reference numerals 17, 23, 31, 33, 33’) to solve the problem when Vin is at a level close to Vout, the added system complexity is minimal; and e) the circuit implementation does not require trimming actions (i.e., does not require implementing final calibration or tuning, e.g., when the chip comes out of the manufacturing plant, through a calibration or tuning procedure to be followed).

[0038] Although the invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A DC-DC converter circuit, comprising: An inductor; A first power transistor; Wherein the inductor and the first power transistor are connected in series between a DC power supply node and a ground node; A shunt switch circuit, connected in parallel with the inductor; A pulse width modulation (PWM) drive circuit, configured to drive a control terminal of the first power transistor with a PWM drive signal having an on-time and an off-time; And A control circuit, configured to receive the PWM drive signal, sense a difference between an input voltage at the DC power supply node and an output voltage generated at a DC output node, and in response to a level of the sensed difference and when the received PWM drive signal is in the off-time, turn on the shunt switch circuit so as to transfer a portion of an inductor current output by the inductor during the off-time back to the DC power supply node through the shunt switch circuit.

2. The DC-DC converter circuit according to claim 1, wherein the PWM drive circuit generates the PWM drive signal for operating the inductor of the DC-DC converter circuit in a continuous conduction mode (CCM).

3. The DC-DC converter circuit according to claim 1, wherein the level of the sensed difference is satisfied when the input voltage is within a threshold voltage of the output voltage.

4. The DC-DC converter circuit according to claim 3, further comprising a conduction circuit connected between the output node and an intermediate node of the inductor and the first power transistor connected in series.

5. The DC-DC converter circuit according to claim 4, wherein the conduction circuit is a second power transistor.

6. The DC-DC converter circuit according to claim 4, wherein the conduction circuit transfers an output current to the DC output node during the off-time of the PWM drive signal.

7. The DC-DC converter circuit according to claim 3, wherein the control circuit comprises: A first voltage sensing circuit, configured to sense the input voltage at the DC power supply node and generate a first signal; A second voltage sensing circuit, configured to sense the output voltage at the DC output node and generate a second signal; A comparator circuit with hysteresis, configured to compare the first signal and the second signal and generate an enable signal; And A logic circuit, enabled in response to the enable signal and configured to turn on the shunt switch circuit in response to the received PWM drive signal being in the off-time.

8. The DC-DC converter circuit according to claim 7, wherein the logic circuit is a logic AND gate having a first input receiving the enable signal, a second input receiving a logical inversion of the PWM drive signal, and an output generating a third signal to turn on the shunt switch circuit.

9. The DC-DC converter circuit according to claim 8, wherein the shunt switch circuit is a transistor switch, and the transistor switch has a control terminal driven by the third signal.

10. The DC-DC converter circuit according to claim 8, wherein the shunt switch circuit is a pair of transistor switches connected in series, and the transistor switches in the pair of transistor switches have control terminals driven in response to the third signal.

11. The DC-DC converter circuit according to claim 7, wherein the shunt switch circuit has a controllable variable resistor, and wherein the logic circuit is a digital control circuit configured to generate a plurality of control signals, and the plurality of control signals are applied to the shunt switch circuit to set a level of the controllable variable resistor of the shunt switch circuit.

12. The DC-DC converter circuit according to claim 11, wherein the shunt switch circuit includes a plurality of transistor switches connected in parallel with each other, and wherein a control terminal of each transistor switch receives one of the plurality of control signals.

13. The DC-DC converter circuit according to claim 12, wherein the digital control circuit generates the plurality of control signals to sequentially turn on the transistor switches in the plurality of transistor switches connected in parallel to reduce the level of the controllable variable resistor over a period of time.

14. The DC-DC converter circuit according to claim 13, wherein the period of time extends over a plurality of cycles of the PWM drive signal.

15. The DC-DC converter circuit according to claim 14, wherein at least one cycle of the PWM drive signal occurs between two consecutive steps in the sequential turn-on of the transistor switches in the plurality of transistor switches.

16. The DC-DC converter circuit according to claim 1 further includes: A second power transistor coupled between the DC output node and an intermediate node of the inductor and the first power transistor connected in series.

17. The DC-DC converter circuit according to claim 16, wherein when the input voltage is within a threshold voltage of the output voltage, the level of the sensed difference is satisfied.

18. The DC-DC converter circuit according to claim 16, wherein during the off-time of the PWM drive signal, the PWM drive circuit turns on the second power transistor.

19. The DC-DC converter circuit according to claim 1, wherein the shunt switch circuit is a transistor switch, and the transistor switch has a control terminal driven in response to an output signal from the control circuit.

20. The DC-DC converter circuit according to claim 1, wherein the shunt switch circuit is a pair of transistor switches connected in series, and the transistor switches have control terminals driven in response to an output signal from the control circuit.

21. The DC-DC converter circuit according to claim 1, wherein the shunt switch circuit has a controllable variable resistance, and wherein the control circuit is configured to set a level of the controllable variable resistance of the shunt switch circuit.

22. The DC-DC converter circuit according to claim 21, wherein the shunt switch circuit includes a plurality of transistor switches connected in parallel with each other, and wherein the control circuit is configured to generate a plurality of control signals, the plurality of control signals being applied to control terminals of the transistor switches.

23. The DC-DC converter circuit according to claim 22, wherein the control circuit generates the plurality of control signals to sequentially turn on transistor switches among the plurality of transistor switches connected in parallel to reduce the level of the controllable variable resistance over a period of time.

24. The DC-DC converter circuit according to claim 23, wherein the period of time extends over a plurality of cycles of the PWM drive signal.

25. The DC-DC converter circuit according to claim 24, wherein at least one cycle of the PWM drive signal occurs between two consecutive steps in the sequential turn-on of the transistor switches among the plurality of transistor switches.

26. A DC-DC converter circuit, comprising: An inductor connected between an input node and an intermediate node; A first power transistor connected between the intermediate node and a ground node, the first power transistor being turned on during a conduction time of a pulse width modulation (PWM) drive cycle; A second power transistor connected between the intermediate node and an output node, the second power transistor being turned on during an off time of the PWM drive cycle; A shunt switch circuit connected in parallel with the inductor between the input node and the intermediate node; Wherein the input node receives a DC input voltage and a DC output voltage is generated at the output node; And A control circuit configured to sense the input node and the output node and determine whether the DC input voltage is within a threshold voltage of the DC output voltage, and in response to the determination and the PWM drive cycle being in the off time, turn on the shunt switch circuit to pass a portion of an inductor current output by the inductor during the off time back to the input node through the shunt switch circuit.

27. The DC-DC converter circuit according to claim 26 further comprises: A PWM drive circuit configured to drive a control terminal of the first power transistor and drive a control terminal of the second power transistor according to the PWM drive cycle.

28. The DC-DC converter circuit according to claim 26, wherein the shunt switch circuit is a transistor switch having a control terminal that is driven in response to an output signal from the control circuit.

29. The DC-DC converter circuit according to claim 26, wherein the shunt switch circuit is a pair of transistor switches connected in series, and the transistor switches in the pair of transistor switches have control terminals that are driven in response to an output signal from the control circuit.

30. The DC-DC converter circuit according to claim 26, wherein the shunt switch circuit has a controllable variable resistance, and wherein the control circuit is configured to set a level of the controllable variable resistance of the shunt switch circuit.

31. The DC-DC converter circuit according to claim 30, wherein the shunt switch circuit includes a plurality of transistor switches connected in parallel with each other, and wherein the control circuit is configured to generate a plurality of control signals that are applied to control terminals of the transistor switches.

32. The DC-DC converter circuit according to claim 31, wherein the control circuit generates the plurality of control signals to sequentially turn on the transistor switches in the plurality of transistor switches connected in parallel to reduce the level of the controllable variable resistance over a period of time.

33. The DC-DC converter circuit according to claim 32, wherein the period of time extends over a plurality of cycles of the PWM drive cycle.

34. The DC-DC converter circuit according to claim 33, wherein at least one cycle of the PWM drive cycle occurs between two consecutive steps in the sequential turn-on of the transistor switches in the plurality of transistor switches.

35. The DC-DC converter circuit according to claim 26, wherein the on-time and off-time of the PWM drive cycle configure the DC-DC converter circuit in a continuous conduction mode CCM of operation.

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