Method and circuit for partitioning combinational logic

Abstract

The present disclosure relates to a method and circuit for partitioning combinatorial logic. A method for partitioning combinatorial logic is provided. The method includes receiving input parameters of an algorithm. The method also includes cyclically and sequentially performing a first operation, a second operation, and a third operation included in the algorithm based on the input parameters. Here, the first operation in the Nth cycle and the third operation in the N-1th cycle are divided into a first combinatorial logic and N is an integer greater than 1, and the second operation is divided into at least one second combinatorial logic.

Description

Technical Field

[0001] The present disclosure relates generally to the field of circuits, and more particularly to methods and circuits for partitioning combinational logic. Background Art

[0002] Hash algorithm, also known as hash algorithm, is a very basic and important technology in the field of information technology. It can map binary values ​​(plain text) of arbitrary length to shorter binary values ​​(Hash values) of fixed length, and different plain texts are difficult to map to the same Hash value.

[0003] Algorithms such as SHA256 and MD5 were originally designed to be computationally sensitive, which means that computing resources are the bottleneck, and the higher the CPU frequency, the faster the hashing speed.

[0004] In order to limit the dependence on computing power, people began to seek new algorithms and turned their attention to storage dependence, that is, memory dependence. The Scrypt algorithm was proposed by programmer and cryptographer Colin Percival in his 2009 paper "STRONGER KEY DERIVATION VIA SEQUENTIAL MEMORY-HARD FUNCTIONS".

[0005] Scrypt is a key derivation function algorithm, namely KDF algorithm, which is mainly used to generate keys. The purpose is to prevent hackers from generating a large number of keys at low cost to test passwords.

[0006] The Scrypt algorithm takes up a lot of memory during operation, and the hardware cost of memory is high.

[0007] Therefore, there is a need for circuits and methods to improve the operational efficiency of KDF algorithms such as the Scrypt algorithm. Summary of the invention

[0008] According to a first aspect of the present disclosure, a method for dividing a combinational logic is provided. The method includes receiving an input parameter of an algorithm. The method also includes cyclically and sequentially executing a first operation, a second operation, and a third operation included in the algorithm based on the input parameter. Here, the first operation in the Nth cycle and the third operation in the N-1th cycle are divided into a first combinational logic and N is an integer greater than 1, and the second operation is divided into at least one second combinational logic.

[0009] According to a second aspect of the present disclosure, a circuit for dividing a combinational logic is provided. The circuit includes an input module, which is configured to receive input parameters of an algorithm. The circuit also includes an operation module, which is configured to cyclically and sequentially perform a first operation, a second operation, and a third operation included in the algorithm based on the input parameters. The circuit also includes a control module, which is configured to divide the first operation in the Nth cycle and the third operation in the N-1th cycle into a first combinational logic and divide the second operation into at least one second combinational logic, where N is an integer greater than 1.

[0010] According to a third aspect of the present disclosure, a computing chip is provided, wherein the computing chip comprises one or more circuits as described above.

[0011] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0014] Figure 1 An illustrative diagram showing the steps of the Scrypt algorithm;

[0015] Figure 2 Shows Figure 1 An illustration of the steps of the scryptROMix algorithm used in the Scrypt algorithm;

[0016] Figure 3 Shows Figure 2 An illustration of the steps of the scryptBlockMix algorithm used in the scryptROMix algorithm;

[0017] Figure 4 Shows Figure 3 Detailed description of the Salsa algorithm used in the scryptBlockMix algorithm;

[0018] Figure 5 A flow chart of a method for partitioning combinatorial logic according to an embodiment of the present invention is shown;

[0019] Figure 6 FIG. 6 is a functional block diagram of a circuit 600 for partitioning combinatorial logic according to an embodiment of the present invention.

[0020] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0021] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0022] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0023] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure and its application or use. That is, the circuits and methods for implementing the hash algorithm herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in the present disclosure, and are not intended to be limiting. Those skilled in the art will appreciate that they merely illustrate exemplary ways that can be used to implement the present invention, rather than an exhaustive way.

[0024] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0025] The Scrypt algorithm includes the following input parameters: P, S, N, r, p and dkLen. Here, P is the passphrase, which is a byte string; S is the salt, which is a byte string; N is the CPU / memory consumption parameter, which must be greater than 1, is a power of 2 and less than 2^(128*r / 8); r is the block size parameter; p is the parallelization parameter, which is a positive integer less than or equal to ((2^32-1)*hLen) / MFLen, where hLen is 32 and MFlen is 128*r; dkLen is the byte length of the desired output derived key, which is a positive integer less than or equal to (2^32-1)*hLen, where hLen is 32.

[0026] The Scrypt algorithm includes an output DK. DK is a derived key, which is dkLen bytes long.

[0027] In the context of this disclosure, a byte is simply an 8-bit byte, which has the same meaning as an octet.

[0028] Figure 1 An explanatory diagram showing the steps of the Scrypt algorithm.

[0029] exist Figure 1 In step 1, an array B is initialized, the array B consists of p blocks, each block is 128*r bytes in size. For example, B[0] represents the first block, B[1] represents the second block, and B[p-1] represents the pth block. In step 1, the PBKDF2-HMAC-SHA256 algorithm is called. This algorithm is a known algorithm, for example, see "Password-Based Cryptography Specification Version 2.0" (B. Kaliski, Network Working Group, IETF, Informational, RFC 2898, Section 5.2, September 2000) for details.

[0030] exist Figure 1 In step 2, for each block of array B, the scryptROMix algorithm is called to perform the calculation.

[0031] exist Figure 1 In step 3, the array B calculated in step 2 is used as a salt and the PBKDF2-HMAC-SHA256 algorithm is called again to obtain the derived key DK as an output.

[0032] In short, the Scrypt algorithm is used to transform a human-readable passphrase P into a derived key of length dkLen bytes.

[0033] The scryptROMix algorithm called in the Scrypt algorithm includes the following input parameters: r, B and N. Here, r is the block size parameter; B is the input block length of 128*r bytes; N is the CPU / memory consumption parameter, which must be greater than 1, a power of 2 and less than 2^(128*r / 8).

[0034] The scryptROMix algorithm includes an output B'. B' is an output block of length 128*r bytes.

[0035] Figure 2 Shows Figure 1 An illustration of the steps of the scryptROMix algorithm used in the Scrypt algorithm.

[0036] exist Figure 2In step 1, create a variable X and assign it the value of the input block B.

[0037] exist Figure 2 In step 2, the scryptBlockMix algorithm (ie, block mixing algorithm) is called N times in a loop, and X returned by each call to the scryptBlockMix algorithm is backed up in elements V[0] to V[N-1] of the array V.

[0038] exist Figure 2 In step 3, in a loop, X is XORed with a random element V[j] in the backup array V, and the result is used as the input parameter to call the scryptBlockMix algorithm. This process is performed N times. Here, Integerify(B[0]...B[2*r-1]) is defined as converting B[2*r-1] to a little-endian integer. In other words, the function of the Integerify function is to take the last 64 bytes of the input block X and convert them into a little-endian integer. j is equal to the remainder obtained by dividing the little-endian integer by N. Thus, the jth element in the array V is taken out and XORed with X.

[0039] The scryptBlockMix algorithm called in the scryptROMix algorithm includes as input a byte string B whose length is 128*r bytes, corresponding to the block B in the scryptROMix algorithm, but is treated as 2*r 64-byte blocks in the scryptBlockMix algorithm, denoted as B[0]||B[1]||...||B[2*r-1], where each element is a 64-byte block.

[0040] The scryptBlockMix algorithm consists of outputting B'[0]||B'[1]||...||B'[2*r-1], where the concatenation of these 2*r 64-byte blocks forms a byte string of length 128*r bytes.

[0041] Figure 3 Shows Figure 2 An illustration of the steps of the scryptBlockMix algorithm used in the scryptROMix algorithm.

[0042] exist Figure 3 In step 1, a temporary variable X is defined, and the last block B[2*r-1] in the input byte string B is taken out and assigned to X.

[0043] exist Figure 3In step 2, all blocks are XORed with the result of the previous Salsa in a loop, and the first block B[0] is XORed with the last block B[2*r-1]. Then, the Salsa algorithm is called using the result of the XOR operation as input. Finally, the result of the Salsa algorithm is saved in array Y. The above loop is executed 2*r times, that is, once for each 64-byte block.

[0044] exist Figure 3 In step 3, Figure 3 The elements of the array Y are cross-combined as shown to output a byte string B'.

[0045] Figure 4 Shows Figure 3 A detailed description of the Salsa algorithm used in the scryptBlockMix algorithm in Figure 1.

[0046] exist Figure 4 In the Salsa algorithm, the input 64-byte block is divided into 16 words in[0]…in

[15] , where each word is a 32-bit unsigned integer. The output 64-byte block is also formed by 16 words out[0]…out

[15] which are unsigned integers. Figure 4 The function R(a,b) in is to shift a (a 32-bit word) left by b bits and right by (32-b) bits, and then OR the results of the two shifts.

[0047] exist Figure 4 In the first for loop, the 16 input words are assigned to temporary variables x[0]…x

[15] .

[0048] exist Figure 4 In the second for loop in , the loop is executed 4 times in total, and each loop calculates the four formulas in each of the blocks 401 to 408 once.

[0049] exist Figure 4 In the third for loop, the input word in[i] is added to the corresponding word x[i] in the intermediate variable to obtain the word out[i] to be output.

[0050] The above is a brief introduction to the Scrypt algorithm.

[0051] At present, in addition to general-purpose computers, dedicated chips are also widely used to execute the Scrypt algorithm, such as ASIC chips or FPGA chips. In addition, in one operation level of the chip, the combinational logic obtains operands from a set of registers, performs operations, and then outputs the operation results to another set of registers. The maximum operating frequency of the chip is determined by the longest combinational logic path from register to register in the chip. The longer this longest combinational logic path, the lower the maximum operating frequency of the chip. According to the Scrypt algorithm, its longest combinational logic is determined by, for example, the formula x[4]^=R(x[0]+x

[12] ,7) in box 401, because this formula forms the longest combinational logic. The formula includes: an addition operation, a circular shift operation, and an XOR operation. And Figure 4 The remaining 31 formulas in blocks 401-408 include the same three operations. Therefore, usually the chip will take the execution time of the combinational logic (addition+rotation shift+XOR) as an execution cycle to determine its operating frequency.

[0052] The present invention is described by taking the Scrypt algorithm described above as an example. To simplify the description, assume that the parameters N=1024, r=1 and p=1 in the algorithm. Figures 1 to 4 It can be seen that the core of the Scrypt algorithm is the scryptBlockMix algorithm, which is mainly reflected in Figure 3 and Figure 4 middle.

[0053] The inventors of the present invention have found that the time required for one execution of the scryptBlockMix algorithm is:

[0054] (1 cycle( Figure 3 The time consumed by X xor B[i] in line 3) + the execution time of the Salsa algorithm) * 2r.

[0055] In the case of r=1, the scryptBlockMix algorithm will only execute two cycles (see Figure 3 It should be noted that the assignment operation in the algorithm only involves read and write operations and does not involve calculation operations, so the time consumed by the assignment operation can be ignored.

[0056] The inventor of the present invention has found that the calculation in the Salsa algorithm stores the following dependency. That is, the four formulas in each of the boxes 401-408 need to be executed sequentially, that is, each formula depends on the calculation result of the previous formula in the same box. At the same time, the calculation of the boxes 405-408 as the lower half of the cycle depends on the calculation result of the boxes 401-404 as the upper half, and it is necessary to wait for the calculation in the boxes 401-404 to be fully completed. In addition, there is no dependency between the calculations of the boxes 401-404 in the upper half of the cycle, and there is no dependency between the calculations of the boxes 405-408 in the lower half of the cycle.

[0057] Taking the formula in block 401 as an example, the calculation of x[8] can only start after the calculation of x[4] is completed, the calculation of x

[12] can only start after the calculation of x[8] is completed, and the calculation of x[0] can only start after the calculation of x

[12] is completed. On the other hand, for example, the calculation of x[9] in block 402, the calculation of x

[14] in block 403, and the calculation of x[3] in block 404 do not depend on the calculation of the formulas in other blocks, and thus can start immediately.

[0058] As mentioned above, since the chip cycle is determined by the longest combinational logic (i.e., the most complex formula) in the algorithm, Figure 4 Each of the formulas in can be executed in one cycle. Therefore, the four formulas in block 401 can be completed in 4 cycles, and the formulas in blocks 402-404 can be completed in parallel with the formula in block 401, so that the execution of the formulas in blocks 401-404 takes a total of 4 cycles. Similarly, the execution of the formulas in blocks 405-408 in the lower half of the loop will also take 4 cycles.

[0059] because Figure 4 The second for loop in will execute four times, so it will take a total of 4*(4+4)=32 cycles. Finally, there is an addition calculation at the end of the Salsa algorithm, which will consume one cycle.

[0060] In summary, when N=1024, r=1 and p=1, a complete execution of the scryptBlockMix algorithm will require (1+((4+4)*4)+1)*2=68 cycles.

[0061] Figure 5 FIG. 1 is a flow chart of a method for partitioning combinatorial logic according to an embodiment of the present invention. The method may be executed by a circuit or a chip, for example. Figure 5As shown, the method includes step 510, in which input parameters of the algorithm are received. For example, in the example of the Scrypt algorithm, step 510 includes receiving parameters such as P, S, N, r, p, dkLen, etc.

[0062] In step 520, based on the input parameters, the first operation, the second operation and the third operation included in the algorithm are cyclically and sequentially executed. According to an embodiment of the present invention, the algorithm includes a part of the Scrypt algorithm, such as the scryptBlockMix algorithm.

[0063] According to one embodiment of the present invention, the first operation in the Nth cycle of the algorithm and the third operation in the N-1th cycle are divided into a first combination logic and N is an integer greater than 1, and the second operation is divided into at least one second combination logic. In the example of the scryptBlockMix algorithm, the first operation corresponds to Figure 3 The XOR operation in line 3 of the code corresponds to the second operation Figure 4 The operation in the second for loop of the Salsa algorithm corresponds to Figure 4 That is, the present disclosure proposes dividing the first operation in the Nth cycle and the last operation in the N-1th cycle of an algorithm into a combinational logic.

[0064] According to an embodiment of the present invention, the first operation and the third operation in the first combinatorial logic may be configured to be executed in one clock cycle.

[0065] In the example of the scryptBlockMix algorithm, according to the present invention, (x[i]+in[i]) will be configured to complete execution in the same cycle as (X xor B[i]) at the beginning of the next loop. By doing so, the time required for the execution of the scryptBlockMix algorithm will be reduced from

[0066] 1+((4+4)*4)+1+1+((4+4)*4)+1=68

[0067] become

[0068] 1+((4+4)*4)+1+((4+4)*4)+1=67

[0069] Therefore, the operation efficiency is improved by 68 / 67-1=1.493%.

[0070] In another example, when p=1 and r=2, since four cycles need to be executed, three cycles can be saved, thereby improving the operation efficiency by (34*4) / (34*4-3)-1=2.256%. The inventor of the present invention found that the operation efficiency is improved more when the number of cycles is greater.

[0071] According to one embodiment of the present invention, the execution time of the second combinatorial logic is greater than or equal to the execution time of the first combinatorial logic. In the example of the scryptBlockMix algorithm, because the execution time of the combinatorial logic of a single operation (addition + circular shift + XOR) in the Salsa algorithm, such as the formula x[4]^=R(x[0]+x

[12] ,7), is significantly greater than the execution time of the combinatorial logic (addition + XOR) merged into the same cycle, the cycle or frequency of the chip does not change, thereby adding no additional hardware overhead.

[0072] According to one embodiment of the present invention, the clock cycle depends on the execution time of the second combinatorial logic. For example, in the example of the scryptBlockMix algorithm, the clock cycle depends on the execution time of the combinatorial logic (addition+cyclic shift+XOR), for example, it can be equal to or slightly greater than the execution time of the combinatorial logic (addition+cyclic shift+XOR).

[0073] According to one embodiment of the present invention, each of the at least one second combinatorial logic can be configured to execute in one clock cycle. In the example of the scryptBlockMix algorithm, the second operation can include multiple operations (i.e., the formula in the second for loop), and each operation can form a combinatorial logic.

[0074] According to an embodiment of the present invention, the algorithm may further include a fourth operation, which is performed after the first operation and before the third operation. That is, in addition to the second operation for determining the cycle of the chip, the algorithm may further include other operations between the first operation and the third operation.

[0075] Figure 6A functional block diagram of a circuit 600 for dividing a combinational logic according to an embodiment of the present invention is shown. The circuit 600 includes an input module 610, an operation module 620, and a control module 630. According to an embodiment of the present invention, the input module 610 is configured to receive input parameters of an algorithm. According to an embodiment of the present invention, the operation module 620 is configured to cyclically and sequentially perform the first operation, the second operation, and the third operation included in the algorithm based on the input parameters. According to an embodiment of the present invention, the control module 630 is configured to divide the first operation in the Nth cycle and the third operation in the N-1th cycle into a first combinational logic and divide the second operation into at least one second combinational logic, where N is an integer greater than 1.

[0076] According to one embodiment of the present invention, the algorithm executed by the operation module includes a part of the Scrypt algorithm.

[0077] According to an embodiment of the present invention, the control module configures the first operation and the third operation in the first combinatorial logic to be executed in one clock cycle.

[0078] According to an embodiment of the present invention, the execution time of the second combinational logic is greater than or equal to the execution time of the first combinational logic.

[0079] According to an embodiment of the present invention, the clock cycle depends on the execution time of the second combinatorial logic.

[0080] According to an embodiment of the present invention, the control module configures each of the at least one second combinatorial logic to be executed in one clock cycle.

[0081] According to one embodiment of the present invention, the algorithm further comprises a fourth operation, which is performed after the first operation and before the third operation.

[0082] According to an embodiment of the present disclosure, the circuit for dividing the combinatorial logic as described above may be implemented as a computing chip.

[0083] Those skilled in the art will appreciate that the circuits and / or chips according to the present disclosure may be implemented using a hardware description language (HDL) such as Verilog or VHDL. The HDL description may be synthesized from a library of cells designed for a given integrated circuit manufacturing technology and may be modified for timing, power, and other reasons to obtain a final design database that may be transmitted to a factory to produce integrated circuits through a semiconductor manufacturing system. The semiconductor manufacturing system may produce integrated circuits by depositing semiconductor materials (e.g., on a wafer that may include a mask), removing materials, changing the shape of the deposited materials, modifying the materials (e.g., by doping the materials or modifying the dielectric constant using ultraviolet treatment), and the like. The integrated circuit may include transistors and may also include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between transistors and circuit elements.

[0084] Although the concept of the present invention is explained above using the Scrypt algorithm, the Scrypt algorithm is only an example for illustration, and the present invention is not limited to the Scrypt algorithm, but can also be applied to other algorithms as long as multiple operations in the algorithm can be divided into the same clock cycle to shorten the operation time.

[0085] By adopting the technical solution of the present invention, since the original cycle or frequency of the chip is not changed, the original performance of the chip is not reduced, and the hardware overhead is not increased, the operation efficiency can be improved.

[0086] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0087] The words "front", "rear", "top", "bottom", "above", "below", etc., if present, in the specification and claims are used for descriptive purposes and are not necessarily used to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances, such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0088] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not limited by any expressed or implied theory given in the above technical field, background technology, summary of the invention, or detailed description.

[0089] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0090] The above description may indicate an element or node or feature that is "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" means that one element / node / feature is directly connected (or directly communicates) to another element / node / feature electrically, mechanically, logically or otherwise. Similarly, unless otherwise expressly stated, "coupling" means that one element / node / feature can be mechanically, electrically, logically or otherwise connected to another element / node / feature in a direct or indirect manner to allow interaction, even if the two features may not be directly connected. In other words, "coupling" is intended to include direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0091] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0092] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0093] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method for partitioning combinational logic in a chip, the method comprising: Receive input parameters of the algorithm; as well as Based on the input parameters, the first operation, the second operation and the third operation included in the algorithm are cyclically and sequentially executed. The first operation in the Nth cycle and the third operation in the N-1th cycle are divided into a first combinational logic and N is an integer greater than 1, and the second operation is divided into at least one second combinational logic, and the first operation and the third operation in the first combinational logic are configured to be executed in one clock cycle of the chip.

2. The method according to claim 1, wherein: The algorithm includes a portion of the Scrypt algorithm.

3. The method according to claim 1, wherein: An execution time of the second combinational logic is greater than or equal to an execution time of the first combinational logic.

4. The method according to claim 1, wherein: The clock cycle depends on the execution time of the second combinatorial logic.

5. The method according to claim 4, wherein: Each of the at least one second combinatorial logic is configured to be executed in one of the clock cycles.

6. The method according to claim 1, wherein: The algorithm also includes a fourth operation that is performed after the first operation and before the third operation.

7. A circuit for partitioning combinational logic in a chip, the circuit comprising: An input module configured to receive input parameters of the algorithm; An operation module, configured to cyclically and sequentially execute a first operation, a second operation and a third operation included in the algorithm based on the input parameters; as well as A control module is configured to divide the first operation in the Nth cycle and the third operation in the N-1th cycle into a first combinational logic and divide the second operation into at least one second combinational logic, where N is an integer greater than 1, wherein the control module configures the first operation and the third operation in the first combinational logic to be executed in one clock cycle of the chip.

8. The circuit according to claim 7, wherein: The algorithm executed by the operation module includes a part of the Scrypt algorithm.

9. The circuit according to claim 7, wherein: An execution time of the second combinational logic is greater than or equal to an execution time of the first combinational logic.

10. The circuit according to claim 7, wherein: The clock cycle depends on the execution time of the second combinatorial logic.

11. The circuit according to claim 10, wherein: The control module configures each of the at least one second combinatorial logic to be executed in one of the clock cycles.

12. The circuit according to claim 7, wherein: The algorithm also includes a fourth operation that is performed after the first operation and before the third operation.

13. A computing chip comprising one or more circuits as claimed in any one of claims 7 to 12.

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