CMOS Image Sensor and Method of Forming an Image Sensor

Abstract

The present invention relates to a CMOS image sensor and an associated forming method, the CMOS image sensor having a doped isolation structure separating a photodiode from a pixel device. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode from a pixel device. The photodiode is disposed within the substrate on the front side away from the substrate. The pixel device is disposed at the front side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Compared to previous image sensor designs in which the upper portion of the photodiode is typically disposed at the top surface of the front side of the substrate, the photodiode is now disposed away from the top surface and more space is left for the pixel device. Accordingly, larger pixel devices can be disposed in the sensing pixels, and the short channel effect and the noise level can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to a CMOS image sensor and a method of forming an image sensor. Background Art

[0002] Digital cameras and optical imaging devices employ an image sensor. The image sensor converts an optical image into digital data that can be represented as digital images. The image sensor includes a pixel array (or grid) for detecting light and recording the intensity (brightness) of the detected light. The pixel array responds to light by accumulating charge. The accumulated charge is then used to provide color and brightness signals for suitable applications such as digital cameras. Summary of the Invention

[0003] Embodiments of the present invention provide a CMOS image sensor, including a substrate, a photodiode doping region, a vertical transfer gate electrode, a doped lateral isolation region, a pixel device well, and a pixel device. The substrate has a first doping type and has a front side and a back side opposite to the front side. The photodiode doping region has a second doping type opposite to the first doping type and is disposed within the substrate. The vertical transfer gate electrode extends vertically from the front side of the substrate to a first position within the substrate and is separated from the substrate by a gate dielectric. The doped lateral isolation region is disposed on the photodiode doping region. The pixel device well is disposed on the doped lateral isolation region. And the pixel device is disposed on the pixel device well at the front side of the substrate, and the pixel device includes a gate electrode disposed above the substrate and a pair of source / drain (S / D) regions disposed within the substrate.

[0004] Embodiments of the present invention provide a CMOS image sensor, including a p-type substrate, an n-type photodiode region, a vertical transfer gate electrode, a p-type lateral isolation region, and a p-type vertical isolation region. The p-type substrate has a front side and a back side opposite to the front side. The n-type photodiode region is disposed within the p-type substrate and is in direct contact with the p-type substrate. The vertical transfer gate electrode extends vertically from the front side of the p-type substrate to a first position within the p-type substrate and is separated from the p-type substrate by a gate dielectric. The p-type lateral isolation region is disposed on the n-type photodiode region. And the p-type vertical isolation region extends vertically from the front side of the p-type substrate and reaches the p-type lateral isolation region.

[0005] An embodiment of the present invention provides a method for an image sensor, including: forming a shallow trench isolation (STI) structure at the outer periphery of a pixel region from the front side of a substrate; forming a photodiode doping region of a photodiode in the pixel region from the front side of the substrate; forming a doped lateral isolation region and a doped vertical isolation region on the photodiode doping region and the substrate; forming a vertical transfer gate structure beside the doped vertical isolation region, and forming a floating diffusion well at one side of the vertical transfer gate structure opposite to the doped vertical isolation region; forming a pixel device on the front side of the substrate on one side of the doped vertical isolation region opposite to the vertical transfer gate structure; and forming a deep trench isolation (DTI) structure, the deep trench isolation structure extending from the back side of the substrate into the substrate, surrounding the photodiode doping region and separated from the photodiode doping region by the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 A cross-sectional view of a CMOS image sensor according to some embodiments is shown, the CMOS image sensor having a doped isolation structure separating a photodiode from a pixel device.

[0008] Figure 2 A layout diagram of a 2×2 pixel region of a CMOS image sensor according to some embodiments is shown.

[0009] Figure 3 A layout diagram of a sensing array made of an array of repeated 2×2 pixel regions according to some embodiments is shown.

[0010] Figure 4 A cross-sectional view of a CMOS image sensor according to some embodiments is shown, the CMOS image sensor having a doped isolation structure separating a photodiode from a pixel device.

[0011] Figure 5 A layout diagram of a 2×2 pixel region of a CMOS image sensor according to some embodiments is shown.

[0012] Figure 6 A layout diagram of a 2×2 pixel region of a CMOS image sensor according to some embodiments is shown.

[0013] Figure 7 A cross-sectional view of a CMOS image sensor according to some embodiments is shown, the CMOS image sensor having a pair of doped regions under a transfer gate electrode.

[0014] Figure 8Shows a layout diagram of a 2×2 pixel region of a CMOS image sensor according to some embodiments, where the CMOS image sensor can employ PMOS pixel devices and n-type pixel device wells to reduce pixel noise.

[0015] Figure 9 Shows a layout diagram of a 2×2 pixel region of a CMOS image sensor according to some embodiments, where the CMOS image sensor has dual pixel device wells.

[0016] Figure 10 Shows a graph depicting the effect of a biased photodiode doping well on the full well capacity of a CMOS image sensor according to some embodiments.

[0017] Figure 11 Shows a cross-sectional view of a CMOS image sensor according to some embodiments, where the CMOS image sensor has a doped isolation structure that separates the photodiode from the pixel device.

[0018] Figure 12 Shows a cross-sectional view of a CMOS image sensor according to some embodiments, where the CMOS image sensor has a doped isolation structure that separates the photodiode from the pixel device.

[0019] Figure 13 Shows according to some embodiments corresponding to the above Figure 11 or Figure 12 A circuit diagram of some embodiments of a 2×2 pixel of an image sensor.

[0020] Figure 14 Shows according to some embodiments corresponding to the following Figure 15 or Figure 16 A circuit diagram of some embodiments of a 2×2 pixel of an image sensor.

[0021] Figure 15 Shows a cross-sectional view of a CMOS image sensor according to some embodiments, where the CMOS image sensor has a doped isolation structure that separates the photodiode from the PMOS pixel device.

[0022] Figure 16 Shows a cross-sectional view of a CMOS image sensor according to some embodiments, where the CMOS image sensor has a doped isolation structure that separates the photodiode from the pixel device.

[0023] Figure 17 Shows a cross-sectional view of a CMOS image sensor according to some embodiments, where the CMOS image sensor has a dual STI structure for PMOS pixel devices.

[0024] Figure 18 Shows according to some embodiments corresponding toFigure 17 or Figure 20 The circuit diagrams of some embodiments of 2×2 pixels of the image sensor.

[0025] Figure 19 and Figure 20 show a layout diagram and a cross-sectional view of a CMOS image sensor according to some additional embodiments, the CMOS image sensor having a source follower transistor disposed in a first n-type pixel device well and a select transistor disposed separately in a second n-type pixel device well.

[0026] Figure 21 show a layout diagram of a 2×4 pixel region of a CMOS image sensor according to some additional embodiments, the CMOS image sensor having a PMOS pixel device disposed in a dual n-type pixel device well.

[0027] Figure 22 show corresponding to Figure 21 The circuit diagrams of some embodiments of 2×4 pixels of the image sensor.

[0028] Figure 23 show a layout diagram of a 2×4 pixel region of a CMOS image sensor according to some additional embodiments, the CMOS image sensor having a PMOS pixel device disposed in a dual n-type pixel device well.

[0029] Figure 24 show corresponding to Figure 23 The circuit diagrams of some embodiments of 2×4 pixels of the image sensor.

[0030] Figures 25 to 34 show some embodiments of a cross-sectional view depicting a method of forming a CMOS image sensor, the CMOS image sensor having pixel devices on a photodiode structure.

[0031] Figure 35 show a flowchart of some embodiments of a method of forming a CMOS image sensor, the CMOS image sensor having pixel devices on a photodiode structure.

[0032] Explanation of reference numerals

[0033] 100, 400, 700, 1100, 1200, 1500, 1600, 1700, 2000, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300: Cross-sectional views;

[0034] 102: Substrate;

[0035] 103, 103a, 103b, 103c, 103d, 103e, 103f, 103g, 103h: Sensing pixel / Unit pixel;

[0036] 104, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8: Photodiode;

[0037] 105, 107, 109: Sensing unit;

[0038] 106: Interlayer dielectric layer;

[0039] 108: Doped lateral isolation region;

[0040] 108b, 112s, 116b: Bottom surface;

[0041] 108t: Top surface;

[0042] 110: Photodiode doping region;

[0043] 111: Deep trench isolation structure;

[0044] 112, 112a: Shallow trench isolation structure / Dielectric isolation structure;

[0045] 112': Doped isolation structure;

[0046] 114: Gate dielectric;

[0047] 116, VTX1, VTX2, VTX3, VTX4, VTX5, VTX6, VTX7, VTX8: Vertical transfer gate;

[0048] 118: Microlens;

[0049] 120: Incident radiation / Incident light;

[0050] 122: Front side;

[0051] 124: Back side;

[0052] 128: High-dose N-type region;

[0053] 130, 130': Source / drain region;

[0054] 132: Doped vertical isolation region;

[0055] 134, SF: Source follower transistor;

[0056] 136, RST: Reset transistor;

[0057] 138: Sidewall spacer;

[0058] 140, SEL: Row selection transistor;

[0059] 142, FD: Floating diffusion well;

[0060] 143: Well node;

[0061] 144: Color filter;

[0062] 146: Floating diffusion contact;

[0063] 148, 148': Pixel device;

[0064] 150: Gate electrode;

[0065] 152, 152': Pixel device well;

[0066] 152a, 152b, NW1, NW2: n-type pixel device well;

[0067] 154: Photodiode well region;

[0068] 200, 300, 500, 600, 800, 900, 1900, 2100, 2300: Layout diagram;

[0069] 602: Anti-reflection layer;

[0070] 1000: Curve graph;

[0071] 1002: Point;

[0072] 1300, 1400, 1800, 2200, 2400: Circuit diagram;

[0073] 1520, 1520a, 1520b, PW: Contact region;

[0074] 1602: Conductive contact;

[0075] 1604: Metal wire layer;

[0076] 1606: BEOL metallization stack;

[0077] 1802: Deep trench;

[0078] 2802: Vertical gate trench;

[0079] 3500: Method;

[0080] 3502, 3504, 3506, 3508, 3510, 3512, 3514, 3516, 3518, 3520: Action;

[0081] d1, d2, d2a, d2b,: Width;

[0082] Vdd: DC voltage supply terminal;

[0083] Vout: Output. Detailed implementation manners

[0084] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0085] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatially relative descriptors used herein may be interpreted accordingly.

[0086] Integrated circuit (IC) technology is generally improved by shrinking device geometries to achieve lower manufacturing costs, higher device integration densities, higher speeds, and better performance. However, due to device shrinking, the sensing pixels of an image sensor have smaller sizes and are closer to each other, and thus result in the degradation of pixel performance characteristics such as pixel noise, charge transfer ability, and full well capacity. Due to limited available area, it becomes challenging to use traditional pixel layouts and structures and achieve good pixel performance.

[0087] The present invention relates to a CMOS image sensor including an improved sensing pixel structure, and a related forming method. The CMOS image sensor has a doped isolation structure that separates a photodiode from a pixel device. The photodiode is disposed within the substrate away from the front side of the substrate. The pixel device is disposed at the front side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Compared with previous image sensor designs in which the upper portion of the photodiode is typically disposed at the top surface of the front side of the substrate, the photodiode is now disposed away from the top surface, leaving more space for the pixel device. Therefore, a larger pixel device can be disposed in the sensing pixel, and the short channel effect and the noise level can be improved.

[0088] Figure 1 FIG. 100 shows a cross-sectional view of a CMOS image sensor according to some embodiments, the CMOS image sensor having a pixel device 148 overlying a photodiode 104. The doped vertical isolation region 132 and the doped lateral isolation region 108 together act as a doped isolation structure and separate the pixel device 148 from the photodiode 104. In some embodiments, as Figure 2 shown, the CMOS image sensor includes a substrate 102 having a front side 122 and a back side 124. In various embodiments, the substrate 102 may include any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, SOI, etc.), such as a semiconductor wafer or one or more die on a wafer, and any other type of semiconductor and / or an epitaxial layer formed thereon and / or otherwise associated therewith. As an example, the substrate 102 may have a depth in the range of about 2 micrometers (μm) to about 10 micrometers. The photodiode doping region 110 is disposed within the substrate 102 and is surrounded by a photodiode well region 154 of the substrate 102. The photodiode doping region 110 and the substrate 102 may be joined at the interface of the P-N junction and are configured to convert radiation into an electrical signal.

[0089] The vertical transfer gate electrode 116 is disposed from the front side 122 of the substrate 102 to the bottom surface 116b of the vertical transfer gate electrode 116 within the substrate 102. The vertical transfer gate electrode 116 is separated from the substrate 102 by a gate dielectric 114. In some embodiments, the gate dielectric 114 abuts the sidewalls of the doped vertical isolation region 132 and the sidewalls of the doped lateral isolation region 108. The bottom surface 116b may be positioned at a first position vertically between the top surface 108t and the bottom surface 108b of the doped lateral isolation region 108.

[0090] The floating diffusion well 142 is disposed within the substrate 102 on the other side of the vertical transfer gate electrode 116 opposite the doped vertical isolation region 132. In some embodiments, the doped vertical isolation region 132 surrounds the vertical transfer gate electrode 116 and its sidewalls directly abut the sidewalls of the floating diffusion well 142. Different contacts may be arranged on the corresponding device structures. For example, the floating diffusion contact 146 may be disposed on the upper surface of the floating diffusion well 142.

[0091] The pixel device well 152 is disposed on the doped lateral isolation region 108. The pixel device well 152 may be separated from the photodiode doping region 110 by the doped lateral isolation region 108. The shallow trench isolation (STI) structure 112 is disposed within the pixel device well 152 from the front side 122 of the substrate 102 to the bottom surface 112s within the pixel device well 152. The bottom surface 112s of the STI structure 112 may be positioned at a location vertically closer to the front side 122 of the substrate 102 compared to the top surface 108t of the doped lateral isolation region 108. As an example, the STI structure 112 may have a depth in the range of about 50 nanometers (nm) to about 500 nanometers. In some embodiments, the STI structure 112 includes a dielectric fill layer (such as an oxide layer). The pixel device 148 is disposed at the front side 122 of the substrate 102 within the pixel device well 152 and directly overlies the photodiode doping region 110. The pixel device 148 includes a gate electrode 150 disposed above the substrate 102 and a pair of source / drain (S / D) regions (not shown) disposed within the substrate 102.

[0092] A deep trench isolation (DTI) structure 111 is disposed in the substrate 102, extending from the back side 124 to a position within the substrate 102. In some embodiments, the DTI structure 111 has a top surface that shares a common plane with a top surface of the photodiode doped region 110 and a bottom surface 108b of the doped lateral isolation region 108. The DTI structure 111 and the photodiode doped region 110 may have depths that are substantially equal to each other. As an example, the DTI structure 111 and the photodiode doped region 110 may each have a depth in a range of about 2 microns to about 10 microns. In some embodiments, the DTI structure 111 includes a dielectric fill layer (e.g., an oxide layer).

[0093] In some embodiments, the doped lateral isolation region 108 abuts the top surface of the photodiode doped region 110 and can also serve as a pinned implant layer for the photodiode doped region and block dark current from the silicon surface. The doped lateral isolation region 108 can be heavily doped (e.g., with a resistivity drop in the milliohm / cm range).

[0094] Figure 2 A layout diagram 200 of a 2×2 pixel area of ​​a CMOS image sensor according to some embodiments is shown. The term “pixel” refers to a unit cell containing features (e.g., photodetectors and various circuits, which may include various semiconductor devices) for converting electromagnetic radiation into electrical signals. In the depicted embodiment, each pixel may include a photodetector (e.g., a photogate-type photodetector) for recording the intensity or brightness of light (radiation). Each pixel may also include various semiconductor devices, such as various transistors, including a transfer transistor, a reset transistor, a source-follower transistor, a select transistor, another suitable transistor, or a combination thereof. Additional circuits, inputs, and / or outputs may be coupled to the pixel array to provide an operating environment for the pixel and to support external communications with the pixel. For example, the pixel array may be coupled to a readout circuit and / or a control circuit. As an example, the sensing pixel 103 may have a size in the range of about 0.5 microns to about 10 microns. If not otherwise specified, the size examples below are all based on this pixel size. Figure 1 Can be described as Figure 2 The cross-sectional view of the line A-A', but it should be understood that Figure 1 Some of the features shown may also be independent and therefore not affected byFigure 2 The feature limitations shown in. As shown in FIG. 2, four sensing pixels 103a, sensing pixel 103b, sensing pixel 103c, and sensing pixel 103d can share a floating diffusion well 142 and a set of pixel devices (presented as Figure 1 the pixel devices 148 in). The pixel devices can be source follower transistors 134, reset transistors 136, or row selection transistors 140, and can respectively include a gate electrode 150 disposed on the pixel device well 152 and a pair of source / drain (S / D) regions 130 disposed within the pixel device well 152. According to the layout diagram, the vertical transfer gate electrode 116 can have a pentagonal shape. The vertical transfer gate electrode 116 can also be other polygonal shapes. Different contacts can be arranged on the corresponding device structures. Example contacts are shown by "X" placed in a box. The STI structure 112 is disposed at the outer peripheral regions of the sensing pixels 103a, sensing pixel 103b, sensing pixel 103c, and sensing pixel 103d.

[0095] Figure 3 FIG. 300 shows a layout diagram of a sensing array made of a repeating 2×2 pixel region array according to some embodiments. The sensing pixels 103a, sensing pixel 103b, sensing pixel 103c, and sensing pixel 103d and the corresponding circuits can form the sensing pixel 103. The sensing units can be repeated and enlarged row by row as examples of the sensing unit 105, sensing unit 107, and sensing unit 109, and can also be repeated and enlarged column by column.

[0096] Figure 4FIG. 400 shows a cross-sectional view of a sensing pixel 103a of a CMOS image sensor according to some embodiments, the CMOS image sensor having a doped isolation structure that separates a photodiode from a pixel device. The photodiode 104 may include a photodiode doping region 110 disposed within a photodiode well region 154 of a substrate 102. A floating diffusion well 142 is disposed within the substrate 102 adjacent to the photodiode 104. A vertical transfer gate electrode 116 is disposed into the substrate 102 between the floating diffusion well 142 and the photodiode doping region. The photodiode doping region 110 and the substrate 102 may be in contact with each other and form a P-N junction at the interface therebetween. The photodiode doping region 110 may be disposed under the vertical transfer gate electrode 116. The top surface of the photodiode doping region 110 may be further from the front side 122 of the substrate than the bottom surface of the vertical transfer gate electrode 116. At an outer peripheral region of the sensing pixel 103a away from the floating diffusion well 142, an STI structure 112 is disposed overlying the photodiode doping region 110 and the vertical transfer gate electrode 116. A doped vertical isolation region 132 is disposed between the STI structure 112 and the vertical transfer gate electrode 116. A pixel device 148 is disposed outside the STI structure 112 on a pixel device well 152. The doped vertical isolation region 132 separates the vertical transfer gate electrode 116 from the pixel device well 152. In some embodiments, the pixel device well 152 covers the entire bottom surface of the STI structure 112.

[0097] A plurality of color filters 144 are arranged on the back side 124 of the substrate 102. The plurality of color filters 144 are each configured to transmit incident radiation or incident light 120 of a specific wavelength. For example, a first color filter (e.g., a red color filter) may transmit light having a wavelength within a first range, while a second color filter may transmit light having a wavelength within a second range, the second range being different from the first range. In some embodiments, the plurality of color filters 144 may be arranged within a gate structure overlying the substrate 102. In some embodiments, the gate structure may include a dielectric material.

[0098] In some embodiments, an antireflection layer 602 is disposed between the color filter 144 and the substrate 102. In some embodiments, the antireflection layer 602 may include oxides, nitrides, high-k dielectric materials such as aluminum oxide (AlO), tantalum oxide (TaO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HfTaO), or a combination thereof. A plurality of microlenses 118 may be disposed on the plurality of color filters 144. The corresponding microlenses 118 are aligned with the color filters 144 and overlie the sensing pixels 103. In some embodiments, the plurality of microlenses 118 have a generally flat bottom surface adjacent to the plurality of color filters 144 and a curved upper surface. The curved upper surface is configured to focus incident radiation or incident light 120 (e.g., light directed toward the underlying sensing pixel 103). During operation of the CMOS image sensor, the incident radiation or incident light 120 is focused onto the underlying sensing pixel 103 by the microlenses 118. When incident radiation or incident light of sufficient energy irradiates the photodiode 104, it generates electron-hole pairs, and the electron-hole pairs generate a photocurrent. It should be noted that although Figure 4 the microlenses 118 are illustrated as being fixed to the image sensor, it should be understood that the image sensor may not include microlenses and the microlenses may be attached to the image sensor at a later separate manufacturing operation.

[0099] In some embodiments, a back-end-of-the-line (BEOL) metallization stack may be disposed on the front side 122 of the substrate 102. The BEOL metallization stack includes a plurality of metal interconnect layers disposed within one or more inter-level dielectric (ILD) layers 106. The ILD layers 106 may include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (such as silicon oxide). Conductive contacts 1602 are disposed within the ILD layers 106. The conductive contacts 1602 extend from the transfer gate electrode 116 and the floating diffusion well 142 to one or more metal wire layers 1604. In various embodiments, the conductive contacts 1602 may include a conductive metal such as copper or tungsten.

[0100] The doped lateral isolation region 108 may be disposed under the pixel device well 152 and may cover the entire bottom surface of the pixel device well 152. The photodiode doping region 110 and the DTI structure 111 are disposed directly under the doped lateral isolation region 108. The doped lateral isolation region 108 may cover the top surface of the photodiode doping region 110 and act as a pinning layer and be partially undepleted to obtain a larger P-N junction capacitance. The doped lateral isolation region 108 is also used to isolate the photodiode from the pixel device and, in addition, block the dark current from the silicon surface.

[0101] Figure 5 FIG. 500 shows a layout of a 2×2 pixel region of a CMOS image sensor according to some embodiments, which specifically depicts the lateral coverage region of the doped lateral isolation region 108. Figure 6 FIG. 600 shows a layout of a 2×2 pixel region of a CMOS image sensor according to some embodiments, which specifically depicts the lateral coverage region of the doped vertical isolation region 132. As Figure 5 shown, the doped lateral isolation region 108 surrounds the outer peripheral regions of the four sensing pixels 103a, sensing pixel 103b, sensing pixel 103c, sensing pixel 103d and extends to laterally overlap with pixel devices 148 such as source follower transistors 134, reset transistors 136, and row selection transistors 140. Examples of the CMOS image sensor described in more detail above are referenced Figure 1 and Figure 2 In some embodiments, the doped lateral isolation region 108 may be heavily doped with a p-type dopant. The p-type doping concentration may be in the range of about 1e17 to about 1e19 / cm 3 range. In some embodiments, the doped lateral isolation region 108 also acts as a pinning layer (partially undepleted to obtain a larger pn junction capacitance), and is used to isolate the photodiode doping region 110 (n-type) from the pixel device 148 (such as n-type), and in addition, to block the dark current from the silicon surface. The distance between the doped lateral isolation region 108 and the vertical transfer gate electrode 116 is in the range of about -50 nanometers (overlap) to about 250 nanometers.

[0102] As Figure 6 shown, the doped vertical isolation region 132 surrounds the sidewall of the vertical transfer gate electrode 116 and leaves one side of the floating diffusion well 142. The vertical transfer gate electrode 116 may have an upper portion above the front side 122 of the substrate, which is wider than the lower portion below the front side 122 of the substrate 102 (see the exemplary cross-sectional view in Figure 1 . The doped vertical isolation region 132 is adjacent to the sidewall of the lower portion and may thus be disposed under the upper portion and laterally overlap with the boundary portion of the top portion, as Figure 6As shown. The doped vertical isolation region 132 can be re-doped with a p-type dopant and can have a junction depth that is approximately equal to or greater than the depth of the vertical transfer gate. The p-type doping concentration is generally in the range of 1e17 to 1e19 / cm 3 within the range. The width can be at least about 50 nanometers.

[0103] Figure 7 FIG. 700 shows a cross-sectional view of a CMOS image sensor according to some embodiments, the CMOS image sensor having a pair of doped regions under a transfer gate electrode. As Figure 7 shown, a high-dose N-type region 128 can be generally disposed below the bottom of the vertical transfer gate electrode 116 to improve hysteresis and anti-blooming. The n-type peak doping concentration is generally in the range of about 5e16 to about 1e18 / cm 3 within the range. The distance between the high-dose N-type region 128 and the vertical transfer gate electrode 116 is in the range of 0 nanometers to 100 nanometers. Thus, the charge transfer ability of the vertical transfer gate electrode 116 is exchanged to increase the full well capacity.

[0104] Figure 8 FIG. 800 shows a layout diagram of a 2×2 pixel region of a CMOS image sensor according to some embodiments. As Figure 8 shown, PMOS pixel devices 148' having n-type wells (e.g., source follower transistors 134, row selection transistors 140, and reset transistors 136) can be employed to reduce pixel noise. The width of the S / D region 130 of the pixel device 148' can laterally overlap with the connected pixel device well 152 to maintain a small resistance from the S / D region 130 to the pixel device well 152. The overlap width d1 between the pixel device 148' and the connected pixel device well is greater than 50 nanometers. The pixel device well 152 is electrically separated from the S / D region 130 by an insulator film (e.g., STI structure 112). The width d2 of the isolation insulator film between the pixel device well 152 and the S / D region 130 is less than the width of other isolation regions, such as the width d2a between the row selection transistor 140 and the reset transistor 136 or the width d2b between the pixel device 148 and the doped vertical isolation region 132.

[0105] Figure 9 FIG. 900 shows a layout diagram of a 2×2 pixel region of a CMOS image sensor according to some embodiments, the CMOS image sensor having a dual pixel device well. As Figure 9As shown, a PMOS pixel device 148' (e.g., source follower transistor 134, row selection transistor 140, and reset transistor 136) having dual n-type pixel device wells 152a and 152b is employed to improve the conversion gain. The first n-well 152a for the source follower transistor 134 is different from the second n-type pixel device well 152b for the reset transistor 136. The first n-well 152a can be connected to the S / D region 130 of the source follower transistor 134 or the selection transistor device 140.

[0106] Figure 10 FIG. 1000 shows a graph depicting the effect of a biased photodiode doped well on the full well capacity of a CMOS image sensor according to some embodiments. In some embodiments, the photodiode p-type well (e.g., Figure 1 or Figure 4 the photodiode well region 154 in Figure 1 or Figure 4 is separated from the pixel device well (e.g., Figure 1 or Figure 4 the pixel device well 152 in Figure 10 The photodiode p-type well (e.g.,

[0107] Figure 11 FIG. 1100 shows a cross-sectional view of a CMOS image sensor according to some embodiments, the CMOS image sensor having a doped isolation structure that separates the photodiode from the pixel device. Figure 11 It can be a cross-sectional view taken along line A-A” of Figure 2 The description associated with Figure 1 and Figure 2 can be fully incorporated herein. The pixel devices (e.g., reset transistor 136, row selection transistor 140, and source follower transistor 134) can be NMOS devices embedded in a p-type pixel device well 152. The reset transistor 136 can be separated from the row selection transistor 140 and the source follower transistor 134 by the STI structure 112. The S / D regions 130 of the row selection transistor 140 and the source follower transistor 134 can be coupled to corresponding bias nodes or output nodes.

[0108] Figure 12 FIG. 1200 shows a cross-sectional view of a CMOS image sensor according to some embodiments, the CMOS image sensor having a doped isolation structure that separates the photodiode from the pixel device. Similarly,Figure 12 It may be a cross-sectional view taken along line A-A” Figure 2 As different from that shown in the above embodiments, in some alternative embodiments, the pixel devices may be separated by doping the isolation structure 112' when replacing the dielectric STI structure 112 described above. The doped isolation structure 112' may include doped silicon or other semiconductor materials and may have a depth deeper than that of the S / D regions 130 or other contact regions. Similar to the dielectric STI structure 112 described above, the doped isolation structure 112' may be disposed in the upper portion of the p-type pixel device well 152 from the front side 122 of the substrate 102. The doped isolation structure 112' may be disposed to cover the bottom surface and sidewall surfaces of the contact region PW of the pixel device well 152. The doped isolation structure 112' may be adjacent to the sidewalls of the doped vertical isolation region 132.

[0109] Figure 13 FIG. 1300 shows a circuit diagram of a 2×2 pixel of an image sensor corresponding to the above Figure 11 or Figure 12 in some embodiments. The photodiodes PD1 to PD4 of the pixel sensor may represent Figure 4 the photodiode 104 of the sensing pixel 103a or other embodiments of the image sensor described above. As shown in Figure 4 , when incident light (photons with sufficient energy) irradiates the photodiode 104, electron-hole pairs are formed. If absorption occurs in the depletion region of the junction or within a diffusion length away from it, the carriers of this electron-hole pair are cleared from the junction by the built-in electric field of the depletion region. Thus, the holes move towards the anode region of the photodiode 104 (as well as Figure 13 and One the photodiodes PD1 to PD4 in some of the following diagrams) and the electrons move towards the cathode region of the photodiode 104, and a photocurrent is generated. The total current passing through the photodiode 104 is the sum of the dark current (the current generated in the absence of light) and the photocurrent. The photodiode 104 is electrically connected to the floating diffusion well 142 (as well as Figure 13 and One the transfer gate electrodes VTX1 to VTX4 in some of the following diagrams) via the transfer gate electrode 116 (as well as Figure 13 and One the floating diffusion wells FD in some of the following diagrams). The other end of the photodiode 104 may be connected to the photodiode surrounding the well node 143. The transfer gate electrode 116 selectively transfers the charge from the photodiode 104 to the floating diffusion well 142. The reset transistor 136 (as well as Figure 13 and OneA reset transistor (RST) in some of the following diagrams is electrically connected between a DC voltage supply terminal Vdd and a floating diffusion well 142 to selectively clear the charge at the floating diffusion well 142. A source follower transistor (SF) in some of the following diagrams is electrically connected between Vdd and an output Vout and is gated through the floating diffusion well 142 to permit observation of the charge level at the floating diffusion well 142 without removing the charge. A row selection transistor (SEL) in some of the following diagrams is electrically connected between the source follower transistor 134 and the output Vout to selectively output a voltage proportional to the charge at the floating diffusion well 142. A current source may be connected between the row selection transistor 140 and the output Vout. Figure 13 and One A source follower transistor (SF) in some of the following diagrams is electrically connected between Vdd and an output Vout and is gated through the floating diffusion well 142 to permit observation of the charge level at the floating diffusion well 142 without removing the charge. A row selection transistor (SEL) in some of the following diagrams is electrically connected between the source follower transistor 134 and the output Vout to selectively output a voltage proportional to the charge at the floating diffusion well 142. A current source may be connected between the row selection transistor 140 and the output Vout. Figure 13 and One A row selection transistor (SEL) in some of the following diagrams is electrically connected between the source follower transistor 134 and the output Vout to selectively output a voltage proportional to the charge at the floating diffusion well 142. A current source may be connected between the row selection transistor 140 and the output Vout.

[0110] During use, the pixel sensor is exposed to an optical image for a predetermined integration time period. During this period, the pixel sensor records the intensity of light incident on the photodiode 104 by accumulating charge proportional to the light intensity. After the predetermined integration time period, the accumulated charge quantity is read. In some embodiments, the accumulated charge quantity of the photodiode 104 is read by briefly activating the reset transistor 136 to clear the charge stored at the floating diffusion well 142. Thereafter, the row selection transistor 140 is activated and the accumulated charge of the photodiode 104 is transferred to the floating diffusion well 142 by activating the transfer gate electrode 116 for a predetermined transfer time period. During the predetermined transfer time period, the voltage at the output Vout is monitored. As the charge is transferred, the voltage at the output Vout changes, decreasing. After the predetermined transfer time period, the observed voltage change at the output Vout is proportional to the intensity of the light recorded at the photodiode 104.

[0111] Figure 14 FIG. 1400 shows a circuit diagram of a 2×2 pixel corresponding to some embodiments of an image sensor according to some embodiments below Figure 15 or Figure 16 The photodiodes PD1 to PD4 of the pixel sensor may represent the photodiode 104 of the sensing pixel 103a or other embodiments of the image sensor described above. Compared with the circuit diagram shown in Figure 4 The pixel devices (such as the reset transistor 136, the row selection transistor 140, and the source follower transistor 134) may be PMOS devices having p-type S / D regions embedded in an n-type pixel device well NW. Figure 13 In the circuit diagram shown in

[0112] Figure 15FIG. 1500 shows a cross-sectional view of a CMOS image sensor according to some embodiments, the CMOS image sensor having a dielectric isolation structure 112 that separates a photodiode 104 from a PMOS pixel device 148'. Compared with Figure 11 the CMOS image sensor shown in, pixel devices (such as a reset transistor 136, a row selection transistor 140, and a source follower transistor 134) may be PMOS devices having p-type S / D regions 130' embedded in an n-type pixel device well 152'. The contact region 1520 of the pixel device well 152' may be heavily doped with an n-type dopant. The reset transistor 136 may be separated from the row selection transistor 140 and the source follower transistor 134 by the STI structure 112. The S / D regions 130' of the row selection transistor 140 and the source follower transistor 134 may be coupled to corresponding bias nodes or output nodes.

[0113] Figure 16 FIG. 1600 shows a cross-sectional view of a CMOS image sensor according to some embodiments, the CMOS image sensor having a dual n-type well structure for a PMOS pixel device 148'. The PMOS pixel device 148' may include a reset transistor 136, a row selection transistor 140, and a source follower transistor 134, where p-type S / D regions 130' are embedded in a plurality of n-type pixel device wells 152a, n-type pixel device wells 152b. As an example, the row selection transistor 140, the source follower transistor 134, and a first contact region 1520a may be disposed within a first n-type pixel device well 152a. The reset transistor 136 and a second contact region 1520b may be disposed within a second n-type pixel device well 152b. The S / D regions 130' of the PMOS pixel device 148' and the n-type pixel device wells 152a, n-type pixel device wells 152b may be coupled to corresponding bias nodes or output nodes as shown in the figure.

[0114] Figure 17FIG. 1700 shows a cross-sectional view of a CMOS image sensor according to some embodiments, the CMOS image sensor having a dual STI structure for PMOS pixel devices 148'. A first STI structure 112a is disposed at an outer peripheral region of the PMOS pixel device 148'. The first STI structure 112a may also be disposed between various pixel devices and isolate the various pixel devices. For example, the first STI structure 112a may isolate the reset transistor 136 from the row selection transistor 140. The first STI structure 112a has a first depth from the front side 122 of the substrate 102. The first depth may be substantially equal to the depths of the first n-type pixel device well 152a and the second n-type pixel device well 152b. The first STI structure 112a may reach the top surface of the doped lateral isolation region 108. A second STI structure 112b is disposed to isolate the PMOS pixel device 148' from the contact regions of the n-type pixel device well 152a and the n-type pixel device well 152b. For example, the second STI structure 112b may be disposed between the S / D region 130' of the row selection transistor 140 and the first contact region 1520a of the first n-type pixel device well 152a and isolate the S / D region 130' of the row selection transistor 140 from the first contact region 1520a of the first n-type pixel device well 152a. The second STI structure 112b may also be disposed between the S / D region 130' of the reset transistor 136 and the second contact region 1520b of the second n-type pixel device well 152b and isolate the S / D region 130' of the reset transistor 136 from the second contact region 1520b of the second n-type pixel device well 152b. The second STI structure 112b has a second depth from the front side 122 of the substrate 102. The second depth is less than the first depth.

[0115] Figure 18 FIG. shows some embodiments of a 2×2 pixel of an image sensor corresponding to the following Figure 19 or Figure 20 and the photodiodes PD1 to PD4 of the pixel sensor may represent Figure 4 the photodiode 104 of the sensing pixel 103a or other embodiments of the image sensor described above. Compared with the Figure 14 circuit diagram shown in, pixel devices such as the reset transistor 136, the row selection transistor 140, and the source follower transistor 134 may be PMOS devices, the PMOS devices having p-type S / D regions and being respectively embedded in the first n-type pixel device well NW1 ( Figure 19 or Figure 20 the n-type pixel device well 152a in) and the second n-type pixel device well NW2 ( Figure 19 or Figure 20 the n-type pixel device well 152b in).

[0116] Figure 19 and Figure 20 shows layout diagram 1900 and cross-sectional view 2000 of a CMOS image sensor according to some additional embodiments, the CMOS image sensor having a source follower transistor 134 disposed within a first n-type pixel device well 152a and a select transistor 140 separately disposed within a second n-type pixel device well 152b. The first n-type pixel device well 152a can be isolated from the second n-type pixel device well 152b by a STI structure 112. The reset transistor 136 and the select transistor 140 can be arranged on the same side of a 2×2 pixel of the image sensor, so that the source follower transistor 134 can be arranged only on the other side of the 2×2 pixel of the image sensor and has a larger size.

[0117] Figure 21 shows layout diagram 2100 of a 2×4 pixel region of a CMOS image sensor according to some additional embodiments, the CMOS image sensor having PMOS pixel devices 148' disposed within dual n-type pixel device wells 152a, n-type pixel device well 152b. Figure 22 shows corresponding to Figure 21 circuit diagram 2200 of some embodiments of a 2×4 pixel of an image sensor. As an example, eight unit pixels 103a to unit pixel 103h share a select transistor 140 and a source follower transistor 134 disposed within a first n-type pixel device well 152a and a reset transistor 136 disposed within a second n-type pixel device well 152b.

[0118] Figure 23 shows layout diagram 2300 of a 2×4 pixel region of a CMOS image sensor according to some additional embodiments, the CMOS image sensor having PMOS pixel devices 148' disposed within dual n-type pixel device wells 152a, n-type pixel device well 152b. Figure 24 shows corresponding to Figure 23 circuit diagram 2400 of some embodiments of a 2×4 pixel of an image sensor. The select transistor 140 and the reset transistor 136 are disposed within a first n-type pixel device well 152a. The first n-type pixel device well 152a can be disposed between a first set of 2×2 unit pixels 103a to unit pixel 103d and a second set of 2×2 unit pixels 103e to unit pixel 103h. The source follower transistor 134 is disposed within a second n-type pixel device well 152b. The second n-type pixel device well 152b can be disposed at one side of the second set of 2×2 unit pixels 103e to unit pixel 103h opposite to the first set of 2×2 unit pixels 103a to unit pixel 103d.

[0119] Figures 25 to 34Some embodiments showing a layout and / or cross-sectional view depicting a method of forming a CMOS image sensor having a doped isolation structure separating a photodiode from a pixel device are shown.

[0120] As Figure 25 shown in cross-sectional view 2500, a substrate 102 is provided. In various embodiments, the substrate 102 may include any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, SOI, etc.), such as a semiconductor wafer or one or more die on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated therewith. The substrate 102 may be fabricated to include forming an epitaxial layer having a first doping type (e.g., p-type) doping concentration in the range of about 10 13 / cm 3 to about 10 15 / cm 3 . Subsequently, a shallow trench isolation (STI) structure 112 is formed from a front side 122 of the substrate 102. The STI structure 112 may be formed by performing an etching process to form a shallow trench ring at a peripheral region of a sensing pixel of the CMOS image sensor. Subsequently, a dielectric layer is filled into the shallow trench ring and over the substrate 102, followed by an etching back process to etch and expose a top surface of the substrate 102.

[0121] As Figure 26 shown in cross-sectional view 2600, a first dopant is implanted into the substrate 102 to form a doped region having a second doping type (e.g., n-type), the doped region including a photodiode doping region 110 within the substrate 102 and a floating diffusion well 142 at the front side 122 of the substrate 102. The first dopant may include a second doping type (e.g., an n-type dopant, such as phosphorus), and the first dopant is implanted from the front side 122 of the substrate 102. The doping concentration of the floating diffusion well 142 is maximum at the silicon surface and gradually decreases with increasing depth. Although not shown in the figures in some alternative embodiments, a doped well having a first doping type (e.g., p-type) may be formed within the epitaxial layer as a first region of a photodiode to be formed, the first doping type having a doping concentration in the range of about 10 14 / cm 3 to about 10 18 / cm 3 . The photodiode doping region contacts the substrate 102 or the doped well to form a photodiode 104. The photodiode doping region 110 may be formed away from the front side 122 of the substrate 102. The photodiode doping region 110 may be formed to have a top surface at a deeper depth than a bottom surface of the STI structure 112.

[0122] As shown Figure 27 in the cross-sectional view 2700 of [[ID=]], different doped regions of a first doping type (e.g., p-type) are formed. The concentration of these doped regions can be in the range of about 1e15 to about 1e18 / cm 3 range. A doped lateral isolation region 108 is formed between the photodiode and the pixel device region, and the doping concentration is generally in the range of about 1e17 to about 1e19 / cm 3 range. A doped vertical isolation region 132 is formed from the front side 122 of the substrate 102. The doped lateral isolation region 108 can be formed undepleted and then biased by the pixel p-type well electrode. Thus, the p-n junction capacitance is increased. The doped vertical isolation region 132 can be formed to surround the sidewalls of the vertical transfer gate to be formed except for the floating diffusion side, and thus suppress the extension of the depletion region into the pixel device region during readout. The pixel device well doping concentration and the photodiode doping concentration are generally in the range of 1e16 to 1e18 / cm 3 range, and are lower than the doped lateral isolation region 108 and the doped vertical isolation region 132.

[0123] As shown Figure 28 in the cross-sectional view 2800 of [[ID=]], a vertical gate trench 2802 is formed extending from the front side of the substrate 102. A p-type region is formed generally below the vertical gate trench 2802 to protect the VTX interface and control the overflow potential. An n-type region is formed below the p-type region to improve hysteresis and obtain a potential gradient from the photodiode to the floating diffusion during readout.

[0124] As shown Figure 29 in the cross-sectional view 2900 of [[ID=]], the vertical transfer gate layer is patterned to form a transfer gate electrode 116 and a gate structure for a pixel device 148 (e.g., a source follower transistor 134, a reset transistor 136, and / or a row select transistor 140), and the pixel device is formed above the front side 122 of the substrate 102. The gate structure can be formed by depositing a gate dielectric film and a gate electrode film above the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric layer and a gate electrode. Sidewall spacers 138 can be formed on the outer sidewalls of the gate electrode. In some embodiments, the sidewall spacers 138 can be formed by depositing a nitride on the front side 122 of the substrate 102 and selectively etching the nitride to form the sidewall spacers 138.

[0125] As shown Figure 30As shown in the cross-sectional view 3000, multiple implantation processes are performed. An implantation process is performed within the front side 122 of the substrate 102 to form a floating diffusion well 142 along one side of the transfer gate electrode 116. S / D regions 130 are formed alongside the gate structures of pixel devices 148 (such as source follower transistors 134, reset transistors 136, and / or row select transistors 140). In some embodiments, a patterned mask may be used to implant a second dopant to form a doped lateral isolation region 108 extending from the front side 122 to a first depth within the substrate 102. The second dopant species may include a first doping type (e.g., a p-type dopant such as boron). The doped lateral isolation region 108 may have a higher doping concentration than the doped well. An example doping concentration of the doped lateral isolation region 108 may be in the range of about 10 16 / cm 3 to about 10 18 / cm 3 range. Example doping concentrations of the floating diffusion well 142 and the S / D regions 130 may be in the range of about 10 18 / cm 3 to about 10 21 / cm 3 range. In some embodiments, the substrate 102 may be selectively implanted according to a patterned mask layer (not shown) including photoresist.

[0126] As Figure 31 shown in the cross-sectional view 3100, a BEOL metallization stack 1606 may be formed over the front side 122 of the substrate 102, the BEOL metallization stack including multiple metal interconnect layers disposed within the ILD layer 106. In some embodiments, the BEOL metallization stack 1606 may be formed by forming the ILD layer 106 over the front side 122 of the substrate 102, the ILD layer including one or more ILD material layers. The ILD layer 106 is then etched to form vias and / or metal trenches. The vias and / or metal trenches are then filled with a conductive material to form multiple metal interconnect layers. In some embodiments, the ILD layer may be deposited by physical vapor deposition techniques (e.g., PVD, CVD, etc.). The multiple metal interconnect layers may be formed using deposition processes and / or plating processes (e.g., electroplating or electroless plating, etc.). In various embodiments, the multiple metal interconnect layers may include tungsten, copper, or aluminum copper. The ILD layer may then be bonded to a handling substrate (not shown) or any other functional substrate for the stacked structure. In some embodiments, the bonding process may use an intermediate bonding oxide layer disposed between the ILD layer and the handling substrate. In some embodiments, the bonding process may include a fusion bonding process.

[0127] As Figure 32As shown in cross-sectional view 3200, substrate 102 is flipped for further processing on the backside 124 opposite the front side 122. Substrate 102 is thinned and the backside of the photodiode doping region may be exposed. As an example, the thinned substrate 102 may have a thickness in the range of about 2 microns to about 10 microns. In some embodiments, substrate 102 may be thinned by etching the backside 124 of the semiconductor substrate. In other embodiments, substrate 102 may be thinned by mechanically polishing the backside 124 of the semiconductor substrate.

[0128] As Figure 33 As shown in cross-sectional view 3300, substrate 102 is selectively etched to form a deep trench isolation structure within the backside 124 of substrate 102. In some embodiments, substrate 102 may be etched by forming a mask layer on the backside 124 of substrate 102. Subsequently, substrate 102 is exposed to an etchant in regions not covered by the mask layer. The etchant etches substrate 102 to form deep trenches 1802 that extend to a location reaching and / or passing through the bottom surface of the STI structure 112. A dielectric fill layer is formed to fill the deep trenches.

[0129] As Figure 34 As shown in cross-sectional view 3400, a plurality of color filters 144 may subsequently be formed over the backside 124 of substrate 102. An anti-reflection layer 602 may be formed between the color filters 144 and substrate 102. In some embodiments, a plurality of color filters 144 may be formed by forming a color filter layer and patterning the color filter layer. The color filter layer is formed of a material that permits transmission of radiation (e.g., light) having a specific range of wavelengths while blocking light outside of a specific range of wavelengths. Additionally, in some embodiments, the color filter layer is planarized after formation. A plurality of microlenses 118 may be formed over the plurality of color filters. In some embodiments, a plurality of microlenses may be formed by depositing a microlens material over the plurality of color filters (e.g., by a spin coating method or a deposition process). A microlens template having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template may include a photoresist material that uses a distributed exposure light dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a circular shape. Then, a plurality of microlenses are formed by selectively etching the microlens material according to the microlens template.

[0130] Figure 35A flowchart showing some embodiments of a method 3500 of forming a CMOS image sensor having a doped isolation structure separating a photodiode from a pixel device. Although the disclosed method 3500 is shown and described herein as a series of acts or events, it should be understood that the shown ordering of such acts or events should not be construed in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events in addition to those shown and / or described herein. Additionally, not all of the shown acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and / or phases.

[0131] At act 3502, a substrate is provided. A doped well having a first doping type (e.g., p-type) may be formed within an epitaxial layer as a first region of a P-N junction photodiode to be formed. Subsequently, a first shallow trench isolation (STI) structure and a second STI structure are formed from a front side of the substrate. Figure 25 A cross-sectional view corresponding to some embodiments is shown, the some embodiments corresponding to act 3502.

[0132] At act 3504, a first dopant is implanted into the substrate to form a doped region including a photodiode doping column within the substrate and a floating diffusion well at a front side of the substrate. Figure 26 A cross-sectional view corresponding to some embodiments is shown, the some embodiments corresponding to act 3504.

[0133] At act 3506, a doped lateral isolation region is formed between the photodiode and a pixel device region, and a doped vertical isolation region is formed from the front side of the substrate. Figure 27 A cross-sectional view corresponding to some embodiments is shown, the some embodiments corresponding to act 3506.

[0134] At act 3508, a vertical gate trench is formed extending from the front side of the substrate. A pair of doped regions may be formed below the vertical gate trench. Figure 28 A cross-sectional view corresponding to some embodiments is shown, the some embodiments corresponding to act 3508.

[0135] At act 3510, a transfer gate electrode and gate structures for pixel devices (e.g., a source follower transistor, a reset transistor, and / or a row select transistor) are formed above the front side of the substrate. The gate structures for the pixel devices are formed between the STI structures. The gate structures may be formed by depositing a gate dielectric film and a gate electrode film over the substrate. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric layer and a gate electrode. Sidewall spacers may be formed on outer sidewalls of the gate electrode.Figure 29 A cross-sectional view corresponding to some embodiments is shown, and the some embodiments correspond to operation 3510.

[0136] At operation 3512, multiple implantation processes are performed. An implantation process is performed within the front side of the substrate to form a floating diffusion well along one side of the transfer gate electrode. S / D regions are formed beside the gate structure for the pixel device. Figure 30 A cross-sectional view corresponding to some embodiments is shown, and the some embodiments correspond to operation 3512.

[0137] At operation 3514, a BEOL metallization stack including a plurality of metal interconnect layers disposed within an ILD layer can be formed above the front side of the substrate. Figure 31 A cross-sectional view corresponding to some embodiments is shown, and the some embodiments correspond to operation 3514.

[0138] At operation 3516, the substrate is flipped for further processing on the back side opposite the front side. The substrate is thinned and the back side of the P-N junction photodiode doping column may be exposed. Figure 32 A cross-sectional view corresponding to some embodiments is shown, and the some embodiments correspond to operation 3516.

[0139] At operation 3518, the substrate is selectively etched to form a deep trench isolation structure within the back side of the substrate. Figure 33 A cross-sectional view corresponding to some embodiments is shown, and the some embodiments correspond to operation 3518.

[0140] At operation 3520, a color filter and a microlens are formed above the back side of the semiconductor substrate. Figure 34 A cross-sectional view corresponding to some embodiments is shown, and the some embodiments correspond to operation 3520.

[0141] Accordingly, the present invention relates to a CMOS image sensor and an associated forming method, the CMOS image sensor having a doped isolation structure that separates a photodiode from a pixel device. The DTI structure includes a doped layer that fills the sidewall surfaces of the deep trench and a dielectric layer that fills the remaining space of the deep trench. By forming the disclosed pixel device directly overlying the DTI structure, short channel effects are reduced, both because of the space for the pixel device and because of the insulating layer beneath the pixel device. Accordingly, higher device performance can be achieved, and blooming and crosstalk are reduced.

[0142] In some embodiments, the present invention relates to a CMOS image sensor. The image sensor includes a substrate having a first doping type and having a front side and a back side opposite the front side. A photodiode doping region has a second doping type opposite the first doping type and is disposed within the substrate. A vertical transfer gate electrode extends vertically from the front side of the substrate to a first position within the substrate and is separated from the substrate by a gate dielectric. A doped lateral isolation region is disposed over the photodiode doping region. A pixel device well is disposed over the doped lateral isolation region. A pixel device is disposed over the pixel device well at the front side of the substrate, the pixel device including a gate electrode disposed on the substrate and a pair of source / drain (S / D) regions disposed within the substrate.

[0143] In some embodiments, the CMOS image sensor further comprises: a doped vertical isolation region extending vertically from the front side of the substrate and reaching onto the doped lateral isolation region; wherein the doped vertical isolation region and the doped lateral isolation region separate the pixel device well from the photodiode doped region. In some embodiments, the doped vertical isolation region and the doped lateral isolation region separate the pixel device well from the photodiode doped region. In some embodiments, the CMOS image sensor further comprises: a floating diffusion well disposed in the substrate on the other side of the vertical transfer gate electrode opposite to the doped vertical isolation region. In some embodiments, the floating diffusion well has a doping concentration that decreases in a gradient from the top surface at the front side of the substrate to the bottom surface away from the front side of the substrate. In some embodiments, the CMOS image sensor further comprises: a shallow trench isolation (STI) structure located between the pixel device and the vertical transfer gate electrode, extending from the front side of the substrate to a position within the pixel device well. In some embodiments, the shallow trench isolation structure has a bottom surface positioned at a location in the substrate shallower than the location of the doped lateral isolation region. In some embodiments, the source / drain region of the pixel device has a bottom surface positioned at a location in the substrate above the bottom surface of the shallow trench isolation structure. In some embodiments, the CMOS image sensor further comprises: a first VTX doped region surrounding a lower portion of the vertical transfer gate electrode; and a second VTX doped region disposed below and adjacent to the first VTX doped region; wherein the second VTX doped region has a doping type opposite to that of the first VTX doped region. In some embodiments, the first VTX doped region and the second VTX doped region have sidewall surfaces that are vertically aligned with the sidewall surfaces of the photodiode doped region. In some embodiments, the doped lateral isolation region and the pixel device well have the first doping type. In some embodiments, the pixel device is a source follower transistor, a reset transistor, or a row selection transistor. In some embodiments, the photodiode doped region and the substrate are joined at the interface of the P-N junction and are configured to convert radiation into an electrical signal. In some embodiments, the radiation enters from the back side of the substrate. In some embodiments, the CMOS image sensor further comprises: a deep trench isolation (DTI) structure surrounding the photodiode doped region and separated from the photodiode doped region by the substrate; wherein the top surface of the photodiode doped region and the top surface of the deep trench isolation structure are coplanar, and the bottom surface of the photodiode doped region and the bottom surface of the deep trench isolation structure are coplanar.

[0144] In some alternative embodiments, the present invention relates to a CMOS image sensor. The image sensor includes a p-type substrate having a front side and a back side opposite the front side. An n-type photodiode region is disposed within the p-type substrate and is in direct contact with the p-type substrate. A vertical transfer gate electrode extends vertically from the front side of the p-type substrate into a first position within the p-type substrate and is spaced from the p-type substrate by a gate dielectric. A p-type lateral isolation region is disposed over the n-type photodiode region. A p-type vertical isolation region extends vertically from the front side of the p-type substrate and reaches over the p-type lateral isolation region.

[0145] In some embodiments, the CMOS image sensor further includes: a deep trench isolation (DTI) structure surrounding the n-type photodiode region but separated from the n-type photodiode region by the p-type substrate; wherein the p-type lateral isolation region is in direct contact with the n-type photodiode region, the p-type substrate, and the deep trench isolation structure and extends laterally along the n-type photodiode region, the p-type substrate, and the deep trench isolation structure. In some embodiments, the p-type lateral isolation region and the p-type vertical isolation region have substantially the same doping concentration, which is greater than 10 times the concentration of the p-type substrate. In some embodiments, the CMOS image sensor further includes: a p-type pixel device well disposed over the p-type lateral isolation region; and a pixel device disposed over the p-type pixel device well at the front side of the p-type substrate, the pixel device including a gate electrode disposed on the p-type substrate and a pair of source / drain (S / D) regions disposed within the p-type substrate.

[0146] In other embodiments, the present invention relates to a method of forming an image sensor. The method includes forming a shallow trench isolation (STI) structure at the periphery of a pixel region from the front side of a substrate and forming a photodiode doping region of a photodiode of the pixel region from the front side of the substrate. The method further includes forming a doped lateral isolation region and a doped vertical isolation region over the photodiode doping region and the substrate, forming a vertical transfer gate structure beside the doped vertical isolation region, and forming a floating diffusion well at a side of the vertical transfer gate structure opposite the doped vertical isolation region. The method further includes forming a pixel device on the front side of the substrate on a side of the doped vertical isolation region opposite the vertical transfer gate structure and forming a deep trench isolation (DTI) structure that extends from the back side of the substrate into the substrate, surrounds the photodiode doping region, and is separated from the photodiode doping region by the substrate.

[0147] The foregoing outlines features of several embodiments enabling those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should appreciate that they can readily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purposes and / or attaining the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A CMOS image sensor, characterized in that, Comprising: A substrate having a first doping type and having a front side and a back side opposite to the front side; A photodiode doping region having a second doping type opposite to the first doping type and disposed within the substrate; A vertical transfer gate electrode extending vertically from the front side of the substrate into a first position within the substrate and separated from the substrate by a gate dielectric; A doped vertical isolation region extending vertically along the vertical transfer gate electrode; A continuously doped doped lateral isolation region disposed on the photodiode doping region, in direct contact with the doped vertical isolation region, and extending in a direction laterally opposite to the vertical transfer gate electrode; A pixel device well disposed on the doped lateral isolation region, wherein the doping concentration of the pixel device well is less than the doping concentration of the doped vertical isolation region; And A pixel device disposed on the pixel device well at the front side of the substrate, the pixel device including a gate electrode disposed above the substrate and a pair of source / drain (S / D) regions disposed within the substrate.

2. The CMOS image sensor according to claim 1, characterized in that, The doped vertical isolation region and the doped lateral isolation region separate the pixel device well from the photodiode doping region.

3. The CMOS image sensor according to claim 2, characterized in that, The doped vertical isolation region abuts a sidewall of the gate dielectric.

4. The CMOS image sensor according to claim 2, characterized in that, Further comprising: A floating diffusion well disposed within the substrate on the other side of the vertical transfer gate electrode opposite to the doped vertical isolation region.

5. The CMOS image sensor according to claim 4, characterized in that, The floating diffusion well has a doping concentration that decreases in a gradient from a top surface at the front side of the substrate to a bottom surface away from the front side of the substrate.

6. The CMOS image sensor according to claim 1, wherein Further comprising: A shallow trench isolation (STI) structure located between the pixel device and the doped vertical isolation region, extending from the front side of the substrate to a position within the pixel device well.

7. The CMOS image sensor according to claim 6, wherein, The shallow trench isolation structure has a bottom surface positioned at a position within the substrate that is shallower than the position of the doped lateral isolation region.

8. The CMOS image sensor according to claim 6, characterized in that, The source / drain regions of the pixel device have a bottom surface positioned at a position within the substrate that is higher than the bottom surface of the shallow trench isolation structure.

9. The CMOS image sensor according to claim 1, wherein, Further comprising: A first doping region surrounding a lower portion of the vertical transfer gate electrode; And A second doping region disposed below the first doping region and adjacent to the first doping region; Wherein the second doping region has a doping type opposite to that of the first doping region.

10. The CMOS image sensor according to claim 9, wherein The first doping region and the second doping region each have a sidewall surface that is vertically aligned with a sidewall surface of the photodiode doping region.

11. The CMOS image sensor according to claim 1, wherein, The doped lateral isolation region and the pixel device well have the first doping type.

12. The CMOS image sensor according to claim 1, wherein The pixel device is a source follower transistor, a reset transistor, or a row selection transistor.

13. The CMOS image sensor according to claim 1, wherein, The photodiode doping region and the substrate are joined at an interface of a P-N junction and are configured to convert radiation into an electrical signal.

14. The CMOS image sensor according to claim 13, wherein, The radiation enters from the back side of the substrate.

15. The CMOS image sensor according to claim 1, characterized in that, Further comprising: A deep trench isolation (DTI) structure of a dielectric fill layer surrounding the photodiode doping region and separated from the photodiode doping region by the substrate.

16. A CMOS image sensor, characterized in that, Comprising: A p-type substrate having a front side and a back side opposite to the front side; An n-type photodiode region disposed within the p-type substrate and in direct contact with the p-type substrate; A vertical transfer gate electrode extending vertically from the front side of the p-type substrate into a first position within the p-type substrate and separated from the p-type substrate by a gate dielectric; A p-type lateral isolation region disposed over the n-type photodiode region; A p-type pixel device well disposed over the p-type lateral isolation region; A p-type vertical isolation region extending vertically from the front side of the p-type substrate and reaching over the p-type lateral isolation region, wherein the doping concentration of the p-type vertical isolation region is greater than the doping concentration of the p-type pixel device well; and A deep trench isolation (DTI) structure surrounding the n-type photodiode region; Wherein the p-type lateral isolation region is in direct contact with and covers the top surface of the deep trench isolation structure.

17. The CMOS image sensor according to claim 16, wherein, The deep trench isolation (DTI) structure is separated from the n-type photodiode region by the p-type substrate; Wherein the p-type lateral isolation region is in direct contact with the n-type photodiode region, the p-type substrate, and the deep trench isolation structure and extends laterally along the top surface of the n-type photodiode region, the p-type substrate, and the dielectric-filled deep trench isolation structure.

18. The CMOS image sensor according to claim 16, wherein The p-type lateral isolation region and the p-type vertical isolation region have substantially the same doping concentration, which is greater than 10 times the concentration of the p-type substrate.

19. The CMOS image sensor according to claim 16, wherein The p-type lateral isolation region is in direct contact with the p-type vertical isolation region and extends in a direction laterally opposite to the vertical transfer gate electrode.

20. A method of forming an image sensor, characterized in that, Comprising: Forming a shallow trench isolation (STI) structure from the front side of the substrate at the periphery of the pixel region; Forming a photodiode doping region of a photodiode of the pixel region from the front side of the substrate; Forming a doped lateral isolation region and a doped vertical isolation region on the photodiode doping region, along the shallow trench isolation structure, and within the substrate, wherein the doped lateral isolation region and the doped vertical isolation region separate the photodiode doping region from the pixel region above it; Forming a vertical transfer gate structure next to the doped vertical isolation region and forming a floating diffusion well at a side of the vertical transfer gate structure opposite to the doped vertical isolation region; Forming a pixel device on the front side of the substrate on a side of the doped vertical isolation region opposite to the vertical transfer gate structure; And Forming a deep trench isolation (DTI) structure of a dielectric fill layer, the deep trench isolation structure extending from the back side of the substrate into the substrate, surrounding the photodiode doping region and reaching the bottom surface of the doped lateral isolation region.

Images