Semiconductor memory device and memory system having the same

Abstract

A semiconductor memory device includes a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal, and a temperature code storage unit configured to receive the temperature signal in response to a temperature code write control signal generated when an operation corresponding to a specific command is performed, generate an operation temperature code corresponding to the temperature signal, compare the operation temperature code with a previously stored temperature code, store a greater one of the operation temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority from Korean Patent Application No. 10-2019-0113429 filed on September 16, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor memory device and a memory system having the same. Background Art

[0004] Semiconductor memory devices may be sensitive to temperature. Therefore, the semiconductor memory device may include a temperature sensor and may control internal operations according to the temperature sensed by the temperature sensor.

[0005] In some cases, an external device (eg, a controller or a test system) may control the operation of the semiconductor memory device based on the temperature sensed by the temperature sensor. Summary of the Invention

[0006] A semiconductor memory device according to an exemplary embodiment of the present invention includes: a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal; and a temperature code storage unit configured to receive the temperature signal in response to a temperature code write control signal generated when an operation corresponding to a specific command is performed, generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, store a larger temperature code between the operating temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal.

[0007] A semiconductor memory apparatus according to an exemplary embodiment of the inventive concept includes an internal clock signal generator configured to receive an external clock signal from an external source and to generate an internal clock signal; a command and address generator configured to receive a command and an address from the external source in response to the external clock signal, to decode a command signal included in the command and the address to generate an active command, a read command, a write command, or a mode setting command, to generate an address signal included in the command and the address applied with the active command as a row address, to generate the address signal included in the command and the address applied with the read command or the write command as a column signal, and to generate the address signal included in the command and the address applied with the mode setting command as a mode setting code; a mode setting register configured to receive the mode setting code in response to the mode setting command, and to set a read latency, a write latency, and a burst length; a latency controller configured to generate a read latency control signal, a temperature code write control signal, and a temperature code read control signal using the read latency, the internal clock signal, or the burst length when the specific command is the read command, or to generate a write latency control signal, the temperature code write control signal, and the temperature code read control signal using the write latency, the internal clock signal, or the burst length when the specific command is the write command; a temperature sensor configured to sense an internal temperature of the semiconductor memory apparatus and to generate a temperature signal; a temperature code storage unit configured to receive the temperature signal in response to the temperature code write control signal to generate an operating temperature code corresponding to the temperature signal, to compare the operating temperature code with a previously stored temperature code, and to store a greater one of the operating temperature code and the previously stored temperature code as a maximum temperature code, and to output the maximum temperature code or a temperature range code corresponding to the maximum temperature code to an external source in response to the temperature code read control signal; a row decoder configured to decode the row address to generate a plurality of word line selection signals; a column decoder configured to decode the column address to generate a plurality of column selection signals; a memory cell array including a plurality of memory cells, and configured to store input data in memory cells selected by the plurality of word line selection signals and the plurality of column selection signals, or to generate output data from the selected memory cells; a data read unit configured to receive output data output from the memory cell array in response to the read latency control signal to output the output data to the external source through a data terminal; and a data write unit configured to receive data from the external source through the data terminal in response to the write latency control signal to output the received data to the memory cell array.

[0008] A memory system according to an exemplary embodiment of the present inventive concept includes a control unit configured to transmit a command and an address in response to an external clock signal, transmit and receive data, and receive a maximum temperature code; and a memory configured to receive the command and the address in response to the external clock signal, transmit and receive the data, and transmit the maximum temperature code, wherein the memory includes a temperature sensor configured to sense an internal temperature of the memory and generate a temperature signal, and a temperature code storage unit configured to receive the temperature signal in response to a temperature code write control signal generated when an operation corresponding to a specific command is actually performed, generate an operation temperature code corresponding to the temperature signal, compare the operation temperature code with a previously stored temperature code, store a greater one of the operation temperature code and the previously stored temperature code as the maximum temperature code, and output the maximum temperature code to the external source in response to a temperature code read control signal. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

[0010] Figure 1 , Figure 2 , Figure 3 and Figure 4 each illustrate a block diagram of a configuration of a semiconductor memory device according to an exemplary embodiment of the present inventive concept;

[0011] Figure 5 , Figure 6 and Figure 7 each illustrate a block diagram of a configuration of a temperature storage unit according to an exemplary embodiment of the present inventive concept;

[0012] Figure 8 is a block diagram illustrating a configuration of a second comparator according to an exemplary embodiment of the present inventive concept;

[0013] Figure 9 is a block diagram illustrating a configuration of a programming unit according to an exemplary embodiment of the present inventive concept;

[0014] Figure 10 and Figure 11 each illustrate a block diagram of a memory system according to an exemplary embodiment of the present inventive concept;

[0015] Figure 12 is an operation timing chart for describing a read operation of a memory system according to an exemplary embodiment of the present inventive concept; and

[0016] Figure 13is an operation timing diagram for describing a write operation of a memory system according to exemplary embodiments of the inventive concept. DETAILED DESCRIPTION

[0017] Hereinafter, a semiconductor memory device according to exemplary embodiments of the inventive concept and a memory system having the same will be described with reference to the accompanying drawings.

[0018] Figure 1 is a block diagram illustrating a configuration of a semiconductor memory device according to exemplary embodiments of the inventive concept. The semiconductor memory device 100 includes an internal clock signal generator 10, a command and address generator 12, a mode setting register 14, a latency controller 16, a temperature sensor 18, a temperature code storage unit 20, a row decoder 22, a column decoder 24, a memory cell array 26, a data read path unit 28, a data write path unit 30, a data output buffer 32, and a data input buffer 34.

[0019] The functions of each of the blocks illustrated in Figure 1 will be described below.

[0020] The internal clock signal generator 10 can receive an external clock signal CK applied from an external source to generate an internal clock signal ICLK. The internal clock signal generator 10 can be a delay-locked loop circuit.

[0021] The command and address generator 12 can receive a command and address CA applied from an external source in response to the external clock signal CK to generate an internal command and address. The command and address generator 12 can decode a command signal included in the command and address CA to generate a mode setting command MRS, an active command ACT, a write command WR, or a read command RD as an internal command. In addition, the command and address generator 12 can generate an address signal included in the command and address CA as a row address RADD, a column address CADD, or a mode setting code OPC. For example, the command and address generator 12 can generate the mode setting code OPC applied together with the mode setting command MRS, generate the row address RADD applied together with the active command ACT, and generate the column address CADD applied together with the write command WR or the read command RD. In addition, the command and address generator 12 can decode the command signal included in the command and address CA to generate a temperature code read control signal TRD.

[0022] The mode setting register 14 can receive the mode setting code OPC in response to the mode setting command MRS to set a read latency RL, a write latency WL, and a burst length BL. The mode setting command MRS can be a test mode setting command applied during a test operation, or a mode setting command applied during a normal operation.

[0023] When the read command RD is applied, the latency controller 16 can generate the temperature code write control signal TWR, the read latency control signal RLA, and the write latency control WLA using the read latency RL, the write latency WL, and the burst length BL in response to the internal clock signal ICLK. When the read command RD is applied, the latency controller 16 can generate the read latency control signal RLA in response to the internal clock signal ICLK, which is activated by being delayed by the number of clock periods corresponding to the read latency RL and is deactivated by being delayed by the number of clock periods corresponding to the burst length BL. Also, when the write command WR is applied, the latency controller 16 can generate the write latency control signal WLA in response to the internal clock signal ICLK, which is activated by being delayed by the number of clock periods corresponding to the write latency WL and is deactivated by being delayed by the number of clock periods corresponding to the burst length BL. Also, the latency controller 16 can generate the temperature code write control signal TWR using the read latency RL or the write latency WL in response to the internal clock signal ICLK. For example, the latency controller 16 can generate the temperature code write control signal TWR based on the read latency control signal RLA or the write latency control signal WLA. The temperature code write control signal TWR can be a pulse signal generated at an activation point of time or during an activation period of the read latency control signal RLA or the write latency control signal WLA, in other words, when data is input or output through the data terminal. Also, the temperature code write control signal TWR can be a pulse signal generated before a predetermined number of clock periods from an activation point of time of the read latency control signal RLA or the write latency control signal WLA, in other words, when the memory cell array 26 performs a read operation or a write operation in response to the read command RD or the write command WR.

[0024] The temperature sensor 18 can detect an internal temperature and generate a temperature signal VTEMP corresponding to the internal temperature. For example, the temperature signal VTEMP can be a temperature voltage VTEMP that varies as the temperature increases (or decreases).

[0025] The temperature code storage unit 20 can receive the temperature signal VTEMP in response to the temperature code write control signal TWR, generate a temperature code corresponding to the temperature signal VTEMP, compare the temperature code with a previously stored temperature code, store a temperature code corresponding to a higher temperature as a maximum temperature code TCODE, and output the maximum temperature code TCODE to an external source in response to a temperature code read control signal TRD. As another example, the temperature code storage unit 20 outputs a temperature range code TCODE' indicating a temperature range to which the maximum temperature code TCODE belongs. The temperature range can be one of at least two temperature ranges set by at least one temperature range designation code. The previously stored temperature code can be a temperature code stored in response to the temperature code write control signal TWR in a previous operation. The previously stored temperature code and the at least one temperature range designation code can be a previously set or programmed temperature code. The previously stored temperature code and the at least one temperature range designation code can be preset by a mode setting code OPC applied to the mode setting register 14 in response to a mode setting command MRS. As an example, the maximum temperature code TCODE or the temperature range code TCODE' can be serially output through a separate temperature code output terminal (e.g., a pin or a ball) regardless of the temperature code read control signal TRD. As another example, the maximum temperature code TCODE or the temperature range code TCODE' can be parallelly output through the data output buffer 32 and the data terminal in response to the temperature code read control signal TRD.

[0026] The row decoder 22 can decode the row address RADD to generate a plurality of word line selection signals wl.

[0027] The column decoder 24 can decode the column address CADD to generate a plurality of column selection signals csl.

[0028] The memory cell array 26 can include a plurality of memory cells, and output output data do output from the memory cells selected by the plurality of word line selection signals wl and the plurality of column selection signals csl, or store input data di in the selected memory cells.

[0029] The data read path unit 28 can receive the output data do in response to the read latency control signal RLA to generate the data DO. The data read path unit 28 can receive the output data do in parallel and generate the data DO in series a number of times corresponding to the burst length BL during the activation period of the read latency control signal RLA. For example, when the burst length BL is 16, the data read path unit 28 can output 8-bit data DO in series a number of times corresponding to the burst length BL, 16, while receiving 128-bit output data do in parallel. The data output buffer 32 can buffer the data DO and output the data DQ to an external source through a data terminal. Although the data read path unit 28 and the data output buffer 32 are configured as separate blocks, they can be configured as one data read unit.

[0030] The data write path unit 30 can receive the data DI in response to the write latency control signal WLA to generate the input data di. The data write path unit 30 can receive the data DI in series a number of times corresponding to the burst length BL during the activation period of the write latency control signal WLA and generate the input data di in parallel. For example, when the burst length BL is 16, the data write path unit 30 can receive 8-bit data DI in series a number of times corresponding to the burst length BL, 16, and generate 128-bit input data di in parallel. The data input buffer 34 can buffer the data DQ received from an external source through a data terminal to generate the data DI. Although the data write path unit 30 and the data input buffer 34 are configured as separate blocks, they can be configured as one data write unit.

[0031] In an exemplary embodiment of the inventive concept, the temperature code read control signal TRD can not be generated by the command and address generator 12. For example, the temperature code read control signal TRD can be applied through a separate temperature code read control signal input terminal of the semiconductor memory device 100, or can be set and generated by a mode set code OPC applied to the mode set register 14 in response to a mode set command MRS.

[0032] Figure 2 is a block diagram illustrating a configuration of a semiconductor memory device according to an exemplary embodiment of the inventive concept. The semiconductor memory device 110 can have the same configuration as the semiconductor memory device 100 illustrated in Figure 1

[0033] In Figure 2 Figure 1 ​​The command and address generator 12' can not generate the temperature code read control signal TRD, unlike the command and address generator 12.

[0034] The latency controller 16' can generate the temperature code write control signal TWR, the read latency control signal RLA, and the write latency control signal WLA by performing the same operations as the latency controller 16 shown in FIG. 8. Figure 1 The latency controller 16' can additionally generate the temperature code read control signal TRD. The latency controller 16' can generate the temperature code read control signal TRD using the read latency RL or the write latency WL and the burst length BL in response to the internal clock signal ICLK. For example, the temperature code read control signal TRD can be a pulse signal generated after an activation period of the read latency control signal RLA or the write latency control signal WLA, in other words, after data is input and output through the data terminals.

[0035] The block having the same reference numeral as the block shown in FIG. 8 can perform the same function as the block shown in FIG. 8. Figure 1 The block having the same reference numeral as the block shown in FIG. 8 can perform the same function as the block shown in FIG. 8. Figure 2 The block having the same reference numeral as the block shown in FIG. 8 can perform the same function as the block shown in FIG. 8. Figure 1 The block having the same reference numeral as the block shown in FIG. 8 can perform the same function as the block shown in FIG. 8.

[0036] Figure 3 is a block diagram illustrating a configuration of a semiconductor memory device according to an exemplary embodiment of the inventive concept. Except that the maximum temperature code TCODE or the temperature range code TCODE' is output to the data terminals through the data output buffer 32', the semiconductor memory device 110' can have the same configuration as the semiconductor memory device 110 shown in FIG. 1. Figure 3 The semiconductor memory device 110' of FIG. 10 can have the same configuration as the semiconductor memory device 110 shown in FIG. 1. Figure 2 The semiconductor memory device 110' shown in FIG. 10 can have the same configuration as the semiconductor memory device 110 shown in FIG. 1.

[0037] In other words, the semiconductor memory device 110' shown in FIG. 10 can output the maximum temperature code TCODE (or the temperature range code TCODE') to the data terminals through the data output buffer 32' after data DQ is input or output through the data terminals in response to the temperature code read control signal TRD generated after an activation period of the read latency control signal RLA or the write latency control signal WLA. In this case, the maximum temperature code TCODE (or the temperature range code TCODE') can be output in parallel through the data terminals. For example, when the maximum temperature code TCODE (or the temperature range code TCODE') is 8-bit or less data, there can be 8 data terminals, and the 8-bit or less data can be output in parallel. Figure 3

[0038] Figure 4 is a block diagram illustrating a configuration of a semiconductor memory device according to an exemplary embodiment of the inventive concept. Except that the maximum temperature code TCODE or the temperature range code TCODE' is output to the data terminals through the data output buffer 32', the semiconductor memory device 110' can have the same configuration as the semiconductor memory device 110 shown in FIG. 1. Figure 3 ​Unlike the semiconductor memory device 110' shown in FIG. 1, the semiconductor memory device 110" can include a mode setting register 14' and a latency controller 16" instead of the mode setting register 14 and the latency controller 16', respectively, and can further include an enable signal generator 15.

[0039] In Figure 4 The mode setting register 14' can receive a mode setting code OPC in response to a mode setting command MRS to set a command code CCODE. The command code CCODE can be a code corresponding to a command signal included in the command and address CA. Further, the command code CCODE can be a code corresponding to a command signal requiring a maximum temperature code TCODE (or a temperature range code TCODE') when performing an actual operation. For example, the command code CCODE can be a code corresponding to a command signal for generating a read command RD and / or a code corresponding to a command signal for generating a write command WR. In other words, the command code CCODE can be one or more codes corresponding to one or more command signals.

[0040] The enable signal generator 15 can generate a first enable signal en1 or a second enable signal en2 when a code corresponding to a command signal included in the command and address CA matches the command code CCODE. For example, when the command code CCODE corresponds to a command signal for generating a read command RD, the enable signal generator 15 can activate the first enable signal en1. In other words, when a command signal included in the command and address signal CA corresponds to a read command RD, the enable signal generator 15 can activate the first enable signal en1. When the command code CCODE corresponds to a command signal for generating a write command WR, the enable signal generator 15 can activate the second enable signal en2. In other words, when a command signal included in the command and address signal CA corresponds to a write command WR, the enable signal generator 15 can activate the second enable signal en2.

[0041] The latency controller 16" can perform the same operation as Figure 3The delay controller 16 ′ shown in FIG1 has the same function as the delay controller 16 ′ shown in FIG2 to generate the read delay control signal RLA and the write delay control signal WLA. However, when the first enable signal en1 is activated, the delay controller 16 ″ can generate the temperature code write control signal TWR and the temperature code read control signal TRD using the read delay RL and / or the burst length BL in response to the internal clock signal ICLK. In addition, when the second enable signal en2 is activated, the delay controller 16 ″ can generate the temperature code write control signal TWR and the temperature code read control signal TRD using the write delay WL and / or the burst length BL in response to the internal clock signal ICLK. In other words, when the first enable signal en1 is activated and the second enable signal en2 is deactivated, the delay controller 16" may generate the temperature code write control signal TWR, the read delay control signal RLA, and the temperature code read control signal TRD in response to the read command RD, and generate the write delay control signal WLA in response to the write command WR. In addition, when the first enable signal en1 is deactivated and the second enable signal en2 is activated, the delay controller 16" may generate the read delay control signal RLA in response to the read command RD, and generate the temperature code write control signal TWR, the write delay control signal WLA, and the temperature code read control signal TRD in response to the write command WR. When both the first enable signal en1 and the second enable signal en2 are activated, the delay controller 16" may perform the same Figure 3 The delay controller 16' performs the same operation.

[0042] and Figure 3 The blocks shown in FIG. 1 have the same reference numerals as those in FIG. Figure 4 The blocks shown in FIG. 1 may be executed with Figure 3 Same functionality as shown in the box.

[0043] Figure 3 and Figure 4 The semiconductor memory device 110′ or 110″ shown in FIG may not apply a separate temperature code read control signal and may not have a separate temperature code output terminal for storing the maximum temperature code TCODE (or the temperature range code TCODE′) and outputting the maximum temperature code TCODE (or the temperature range code TCODE′) to an external source.

[0044] Figure 5 is a block diagram illustrating a configuration of a temperature storage unit according to an exemplary embodiment of the inventive concept. The temperature storage unit 20 may include an analog-to-digital converter 20-2, a pulse generator 20-4, a first comparator 20-6, and a register 20-8.

[0045] The following will describe Figure 5 The function of each box is shown in the box.

[0046] The analog-to-digital converter 20-2 can receive the temperature signal VTEMP in response to the temperature code write control signal TWR and perform an analog-to-digital conversion operation to generate an operating temperature code tcode. In other words, the analog-to-digital converter 20-2 can generate the operating temperature code tcode corresponding to the temperature signal VTEMP.

[0047] The pulse generator 20-4 can generate the first read pulse signal ren1 when the temperature code read control signal TRD is received. When the maximum temperature code TCODE (or the temperature range code TCODE') is serially output to the external source, the pulse generator 20-4 generates the first read pulse signal ren1 using the internal clock signal ICLK, the first read pulse signal ren1 including a number of pulses corresponding to the number of bits of the maximum temperature code TCODE. For example, when the maximum temperature code TCODE is 8-bit data, the pulse generator 20-4 can generate the first read pulse signal ren1 including eight pulses. On the other hand, when the maximum temperature code TCODE is parallelly output to the external source, the pulse generator 20-4 can generate the first read pulse signal ren1 including one pulse using the internal clock signal ICLK.

[0048] The first comparator 20-6 can receive the operating temperature code tcode in response to the temperature code write control signal TWR, compare the operating temperature code tcode with the previously stored temperature code Tc, and generate the operating temperature code tcode as the output temperature code Tm when the operating temperature code tcode is greater than (or less than) the previously stored temperature code Tc. On the other hand, when the operating temperature code tcode is less than (or greater than) the previously stored temperature code Tc, the first comparator 20-6 can not generate the output temperature code Tm.

[0049] The register 20-8 can output the previously stored temperature code Tc in response to the temperature code write control signal TWR, and when the output temperature code Tm is received at the register 20-8, the register 20-8 can store the output temperature code Tm instead of the previously stored temperature code Tc as the maximum temperature code TCODE. The previously stored temperature code Tc can be a temperature code stored in response to the temperature code write control signal TWR in a previous operation, or can be a preset or programmed temperature code. In addition, the register 20-8 can output the maximum temperature code TCODE in response to the first read pulse signal ren1. When the maximum temperature code TCODE is 8-bit data, the register 20-8 can output the maximum temperature code TCODE serially one bit at a time in response to the first read pulse signal ren1 including eight pulses, or can output the maximum temperature code TCODE in parallel in response to the first read pulse signal ren1 including one pulse.

[0050] Figure 6 The temperature storage unit 20' may include an analog-to-digital converter 20-2, a pulse generator 20-4', a first comparator 20-6, a register 20-8', a second comparator 20-10, and a programming unit 20-12.

[0051] Figure 6 The function of each of the blocks shown in FIG will be described below.

[0052] The analog-to-digital converter 20-2 can perform the same Figure 5 The same function as the analog-to-digital converter 20-2 shown in FIG.

[0053] Upon receiving the temperature read command TRD, the pulse generator 20-4' may generate a second read pulse signal ren2. When the temperature range code TCODE' is serially output to an external source, the pulse generator 20-4' may use the internal clock signal ICLK to generate the second read pulse signal ren2, which includes a number of pulses corresponding to the number of bits of the temperature range code TCODE'. For example, when the temperature range code TCODE' is 3-bit data, the pulse generator 20-4' may generate a second read pulse signal ren2 including three pulses. On the other hand, when the temperature range code TCODE' is output in parallel to an external source, the pulse generator 20-4' may use the internal clock signal ICLK to generate a second read pulse signal ren2 including one pulse.

[0054] The first comparator 20-6 can perform Figure 5In this case, when the operating temperature code tcode is greater than (or less than) the previously stored temperature code Tc, the first comparator 20-6 may output the output temperature code Tm.

[0055] Register 20-8' can be executed with Figure 5 The same operation as the register 20-8 shown in FIG is performed, and when the output temperature code Tm is received, the output temperature code Tm is stored as the maximum temperature code TCODE instead of the previously stored temperature code Tc. In addition, when the output temperature code Tm is not received, the register 20-8′ may maintain the previously stored temperature code Tc as the maximum temperature code TCODE. However, Figure 5 Unlike the register 20-8 that serially outputs the maximum temperature code TCODE shown in FIG, the register 20-8' can output the maximum temperature code TCODE in parallel. For example, when the temperature code TCODE is 8-bit data, the register 20-8' can output the 8-bit data in parallel.

[0056] The second comparator 20-10 can activate at least one programming signal by comparing the maximum temperature code TCODE with at least one previously stored temperature range designation code in response to the temperature code write control signal TWR. For example, the second comparator 20-10 can compare the maximum temperature code TCODE with two previously stored first temperature range designation codes tc1 and second temperature range designation codes tc2, where tc1 <tc2。当最大温度代码TCODE属于第一温度范围(换句话说,TCODE≤tc1)时,第二比较器20-10可以激活第一编程信号pgm1,当最大温度代码TCODE属于第二温度范围(换句话说,tc1<TCODE≤tc2)时,第二比较器20-10可以激活第二编程信号pgm2,并且当最大温度代码TCODE属于第三温度范围(换句话说,tc2<TCODE)时,第二比较器20-10可以激活第三编程信号pgm3。与 Figure 6 Unlike that shown in FIG. 1 , the second comparator 20 - 10 may compare the maximum temperature code TCODE with only one previously stored temperature range designation code tc1, activate the first programming signal pgm1 when the maximum temperature code TCODE belongs to the first temperature range (in other words, TCODE≤tc1), and activate the first programming signal pgm1 when the maximum temperature code TCODE belongs to the second temperature range (in other words, tc1 <TCODE)时,激活第二编程信号pgm2。

[0057] The programming unit 20-12 can program the temperature range code TCODE' in response to at least one of the programming signals pgm1, pgm2, and pgm3, and output the temperature range code TCODE' in response to the second read pulse signal ren2. For example, the programming unit 20-12 can generate a 3-bit temperature range code TCODE' in response to the first to third programming signals pgm1, pgm2, and pgm3. When the maximum temperature code TCODE belongs to the first temperature range, the programming unit 20-12 can generate the temperature range code TCODE' "100", when the maximum temperature code TCODE belongs to the second temperature range, the temperature range code TCODE' "010", and when the maximum temperature code TCODE belongs to the third temperature range, the temperature range code TCODE' "001". When the temperature range code TCODE' is "110", it can indicate that the semiconductor memory device operates within the first and second temperature ranges, and when the temperature range code TCODE' is "111", it can indicate that the semiconductor memory device operates within the first temperature range, the second temperature range and the third temperature range.

[0058] and Figure 5 The temperature storage unit 20 shown in FIG. 1 outputs a maximum temperature code TCODE corresponding to the internal temperature when the semiconductor memory device performs actual operation. Figure 6 The temperature storage unit 20' shown in FIG. 1 may output a temperature range code TCODE' corresponding to a temperature range when the semiconductor memory device performs an actual operation.

[0059] Figure 7 is a block diagram illustrating a configuration of a temperature storage unit according to an exemplary embodiment of the present inventive concept. The temperature storage unit 20 ″ may include Figure 6 The pulse generator 20 - 4 ′ and the register 20 - 8 ′ shown in FIG. 2 are the pulse generator 20 - 4 ″ and the register 20 - 8 ″, and further include a first switch SW1 and a second switch SW2 .

[0060] exist Figure 7 The register 20-8" can be executed in response to the temperature code write control signal TWR. Figure 6The register 20-8' shown in FIG. 10 performs the same operation as the register 20-8 shown in FIG. 1, stores the output temperature code Tm as the maximum temperature code TCODE instead of the previously stored temperature code Tc when the output temperature code Tm is received, and maintains the previously stored temperature code Tc as the maximum temperature code TCODE when the output temperature code Tm is not received. In addition, the register 20-8" can serially output the maximum temperature code TCODE in response to the first read pulse signal ren1 when the temperature code read selection signal trdm is activated, or can parallelly output the maximum temperature code TCODE when the temperature code read selection signal trdm is deactivated.

[0061] The pulse generator 20-4" can generate the first read pulse signal ren1 when the temperature code read selection signal trdm is activated and the temperature code read control signal TRD is received. In other words, the pulse generator 20-4" can perform the same operation as the pulse generator 20-4 shown in FIG. 1 to generate the first read pulse signal ren1. Figure 5 The pulse generator 20-4" shown in FIG. 10 performs the same operation as the pulse generator 20-4 shown in FIG. 1 to generate the first read pulse signal ren1. In addition, the pulse generator 20-4" can generate the second read pulse signal ren2 when the temperature code read selection signal trdm is deactivated and the temperature code read control signal TRD is received. In other words, the pulse generator 20-4" can perform the same operation as the pulse generator 20-4 shown in FIG. 1 to generate the second read pulse signal ren2. Figure 6 The pulse generator 20-4" shown in FIG. 10 performs the same operation as the pulse generator 20-4 shown in FIG. 1 to generate the first read pulse signal ren1. In addition, the pulse generator 20-4" can generate the second read pulse signal ren2 when the temperature code read selection signal trdm is deactivated and the temperature code read control signal TRD is received. In other words, the pulse generator 20-4" can perform the same operation as the pulse generator 20-4 shown in FIG. 1 to generate the second read pulse signal ren2.

[0062] The first switch SW1 can be turned on when the temperature code read selection signal trdm is activated, and can be turned off when the temperature code read selection signal trdm is deactivated. The maximum temperature code TCODE can be output when the first switch SW1 is turned on.

[0063] The second switch SW2 can be turned on when the temperature code read selection signal trdm is deactivated, and can be turned off when the temperature code read selection signal trdm is activated. The programmed temperature range code TCODE' is output when the second switch SW2 is closed by the deactivated temperature code read selection signal trdm.

[0064] The block shown in FIG. 10 having the same reference numeral as the block shown in FIG. 1 can perform the same function as the block shown in FIG. 1. Figure 6 The block shown in FIG. 10 having the same reference numeral as the block shown in FIG. 1 can perform the same function as the block shown in FIG. 1. Figure 7 The block shown in FIG. 10 having the same reference numeral as the block shown in FIG. 1 can perform the same function as the block shown in FIG. 1. Figure 6 The block shown in FIG. 10 having the same reference numeral as the block shown in FIG. 1 can perform the same function as the block shown in FIG. 1.

[0065] Figure 7 The temperature code read selection signal trdm shown in FIG. 10 can be activated by a mode setting code OPC generated in response to a mode setting command MRS in the same manner as the temperature code read selection signal trdm shown in FIG. 1. Figures 1 to 4set in the mode setting register 14 or 14' and output.

[0066] In other words, Figure 7 The temperature code storage unit 20" shown in FIG. 2 can output a maximum temperature code TCODE corresponding to an internal temperature or a temperature range code TCODE' corresponding to a temperature range of the maximum temperature code when the semiconductor memory device performs an actual operation in response to a temperature code read selection signal trdm.

[0067] Figure 8 is a block diagram illustrating a configuration of a second comparator according to an exemplary embodiment of the inventive concept. The second comparator 20-10 can include a first temperature range detector 20-22, a second temperature range detector 20-24, and a third temperature range detector 20-26.

[0068] The functions of each of the blocks shown in FIG. 2 will be described below. Figure 8

[0069] When the maximum temperature code TCODE is less than or equal to a first temperature range specification code tc1, the first temperature range detector 20-22 can activate a first programming signal pgm1. For example, the first temperature range specification code tc1 can be a temperature code corresponding to a temperature of 45℃.

[0070] When the maximum temperature code TCODE is greater than the first temperature range specification code tc1 and less than or equal to a second temperature range specification code tc2, the second temperature range detector 20-24 can activate a second programming signal pgm2. For example, the second temperature range specification code tc2 can be a temperature code corresponding to a temperature of 85℃.

[0071] When the maximum temperature code TCODE is greater than the second temperature range specification code tc2, the third temperature range detector 20-26 can activate a third programming signal pgm3. The output of the first temperature range detector 20-22 can be provided to the second temperature range detector 20-24, and the output of the second temperature range detector 20-24 can be provided to the third temperature range detector 20-26.

[0072] Figure 9 is a block diagram illustrating a configuration of a programming unit according to an exemplary embodiment of the inventive concept. The programming unit 20-12 can include first to third fuse circuits 20-32, 20-34, and 20-36, and a register 20-38. Each of the first to third fuse circuits 20-32, 20-34, and 20-36 can include a fuse F, an N-type metal oxide semiconductor (NMOS) transistor N, and a latch LA including a first inverter I1 and a second inverter I2. ​

[0073] The functions of each of the blocks shown in FIG. 20 will be described below. Figure 9 The functions of each of the blocks shown in FIG. 20 will be described below.

[0074] The NMOS transistor N of each of the first to third fuse circuits 20-32, 20-34, and 20-36 can be turned on in response to the corresponding programming signal pgm1, pgm2, or pgm3 having a "high" level. When the NMOS transistor N of each of the first to third fuse circuits 20-32, 20-34, and 20-36 is turned on, the fuse F of each of the first to third fuse circuits 20-32, 20-34, and 20-36 can be blown. Accordingly, a signal of a "low" level can be generated to the node n. The latch LA can invert and latch the signal of the "low" level to output a signal of a "high" level.

[0075] On the other hand, the NMOS transistor N of each of the first to third fuse circuits 20-32, 20-34, and 20-36 can be turned off in response to the corresponding programming signal pgm1, pgm2, or pgm3 having a "low" level. When the NMOS transistor N of each of the first to third fuse circuits 20-32, 20-34, and 20-36 is turned off, the fuse F of each of the first to third fuse circuits 20-32, 20-34, and 20-36 can remain connected. Accordingly, a signal of a "high" level can be generated to the node n. The latch LA can invert and latch the signal of the "high" level to output a signal of a "low" level.

[0076] The register 20-38 can store the signals output from the first to third fuse circuits 20-32, 20-34, and 20-36 and output a temperature range code TCODE' in response to the second read pulse signal ren2. In other words, the register 20-38 can output a 3-bit programmed temperature range code TCODE' in parallel or in a single bit string in response to the second read pulse signal ren2.

[0077] Figure 10 is a block diagram illustrating a configuration of a memory system according to an exemplary embodiment of the inventive concept. The memory system 1000 can include a controller 200 and a memory 300. The controller 200 can be a central processing unit or a test device, and the memory 300 can be a semiconductor memory device described with reference to FIGS. 1 to 19, or a memory module including a plurality of semiconductor memory devices. Figures 1 to 9 The semiconductor memory device described with reference to FIGS. 1 to 19, or a memory module including a plurality of semiconductor memory devices.

[0078] The functions of each of the blocks shown in FIG. 20 will be described below. Figure 10 The functions of each of the blocks shown in FIG. 20 will be described below.

[0079] The controller 200 can transmit an external clock signal CK, as well as a command and an address CA, transmit and receive data DQ, and receive a maximum temperature code TCODE (or a temperature range code TCODE') to the memory 300. For example, the controller 200 can receive the maximum temperature code TCODE (or the temperature range code TCODE') and adjust a period in which the command and the address CA are applied according to the maximum temperature code TCODE (or the temperature range code TCODE').

[0080] The memory 300 can receive an external clock signal CK, as well as a command and an address CA, transmit and receive data DQ, and transmit a maximum temperature code TCODE (or a temperature range code TCODE'). When a command signal included in the command and the address CA indicates a temperature code read control signal TRD, the memory 300 can output the maximum temperature code TCODE (or the temperature range code TCODE').

[0081] Figure 11 is a block diagram illustrating a configuration of a memory system according to an exemplary embodiment of the present inventive concept. The memory system 1100 can include a controller 210 and a memory 310. The controller 210 can be a central processing unit or a test device, and the memory 310 can be a semiconductor memory device or a memory module including a plurality of semiconductor memory devices, as described above with reference to FIGS. 1 to 9. Figures 1 to 9 The semiconductor memory device or the memory module including a plurality of semiconductor memory devices is described.

[0082] The functions of each of the blocks illustrated in Figure 11 will be described below.

[0083] The controller 210 can transmit an external clock signal CK, a command and an address CA, and data DQ to the memory 310, and receive data DQ and a maximum temperature code TCODE (or a temperature range code TCODE'). The controller 210 can receive the maximum temperature code TCODE (or the temperature range code TCODE') as the controller 200 illustrated in Figure 10

[0084] The memory 310 can receive an external clock signal CK, a command and an address CA, and data DQ, and transmit data DQ and a maximum temperature code TCODE (or a temperature range code TCODE'). When a command signal included in the command and the address CA indicates a read command and / or a write command, the memory 310 can output the maximum temperature code TCODE (or the temperature range code TCODE').

[0085] Figure 12 ​is an operation timing diagram illustrating a read operation of a memory system according to an exemplary embodiment of the inventive concept. Figure 12 is an operation timing diagram for describing an operation of a semiconductor memory device when a command signal included in a first command and address ca1 is a read command, a read latency RL is set to p, a burst length BL is set to k, and data DQ and a maximum temperature code TCODE (or a temperature range code TCODE’) are output at a double data rate (DDR) through i data terminals.

[0086] Referring to Figures 1 to 9 , Figure 11 and Figure 12 , when the controller 210 transmits the first command and address ca1 in response to a rising edge of an external clock signal CK, the memory 310 can generate a read latency control signal RLA, which can be activated p clock cycles after a corresponding rising edge of the external clock signal CK and deactivated p+r (=k / 2) clock cycles later (since the data DQ is output at a DDR). The memory 310 can transmit the data DQ during an activation period of the read latency control signal RLA. In addition, the memory 310 can generate a temperature code write control signal TWR, which is a pulse signal P11 activated at an activation point of the read latency control signal RLA. The memory 310 can store the maximum temperature code TCODE or the temperature range code TCODE’ in response to the temperature code write control signal TWR. In other words, the memory 310 can store the maximum temperature code TCODE or the temperature range code TCODE’ at a point in time at which the data DQ starts to be output. As another example, the temperature code write control signal TWR can be a pulse signal P12 activated when a read operation of a memory cell array 26 of the memory 310 is performed and illustrated by a dotted line. In addition, the memory 310 can generate a temperature code read control signal TRD, which is a pulse signal P13 activated at a deactivation point of the read latency control signal RLA. The memory 310 can output the maximum temperature code TCODE or the temperature range code TCODE’ after the data DQ is output through i data terminals in response to the temperature code read control signal TRD.

[0087] Figure 13 is an operation timing diagram illustrating a read operation of a memory system according to an exemplary embodiment of the inventive concept. Figure 13is an operation timing diagram for describing an operation of a semiconductor memory device when a command signal included in a second command and address ca2 is a write command, a write latency WL is set to q, a burst length BL is set to k, data DQ is input in DDR through i data terminals, and a maximum temperature code TCODE (or a temperature range code TCODE') is output through the i data terminals.

[0088] Referring to Figures 1 to 9 , Figure 11 and Figure 13 , when the controller 210 transmits the second command and address ca2 in response to a rising edge of an external clock signal CK, the memory 310 can generate a write latency control signal WLA that is activated after a latency q clock cycles from a corresponding rising edge of the external clock signal CK and is deactivated after a latency q+r (=k / 2) clock cycles (since the data DQ is input in DDR). The memory 310 can receive the data DQ transmitted from the controller 210 during an activation period of the write latency control signal WLA. Further, the memory 310 can generate a temperature code write control signal TWR that is a pulse signal P21 activated at an activation point in time of the write latency control signal WLA. The memory 310 can store the maximum temperature code TCODE or the temperature range code TCODE' in response to the temperature code write control signal TWR. In other words, the memory 310 can store the maximum temperature code TCODE or the temperature range code TCODE' at a point in time at which the data DQ starts to be input. As another example, the temperature code write control signal TWR can be a pulse signal P22 activated one clock cycle before a deactivation point in time of the write latency control signal WLA, as shown by a dotted line. Further, the memory 310 can generate a temperature code read control signal TRD that is a pulse signal P24 activated at a deactivation point in time of the write latency control signal WLA. The memory 310 can output the maximum temperature code TCODE or the temperature range code TCODE' after the data DQ is output through the i data terminals in response to the temperature code read control signal TRD. As another example, the temperature code write control signal TWR can be a pulse signal P23 activated when the write operation of the memory cell array 26 of the memory 310 is performed after the write latency control signal WLA is deactivated and is shown by a dotted line. In this case, the maximum temperature code TCODE or the temperature range code TCODE' stored in response to the pulse signal P23 can be output in response to the temperature code read control signal TRD generated during a next write operation or a read operation.

[0089] The semiconductor memory device according to an exemplary embodiment of the present inventive concept can output data related to an internal temperature (e.g., a maximum temperature code or a temperature range code) to an external source at a point (or during) in time corresponding to a specific operation (e.g., a read operation or a write operation, etc.) that is actually performed. Accordingly, the semiconductor memory device and the memory system having the same can accurately sense a temperature and output the sensed temperature at the time (at a specific point in time) when the actual operation is performed.

[0090] The memory system according to an exemplary embodiment of the present inventive concept can receive data related to an internal temperature from the semiconductor memory device to control a period in which a command and an address are applied to the semiconductor memory device.

[0091] Accordingly, the reliability of the operation of the semiconductor memory device and the memory system can be improved.

[0092] Although the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the present inventive concept as set forth in the appended claims.

Claims

1. A semiconductor memory device comprising: a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal; as well as A temperature code storage unit is configured to receive a temperature signal in response to a temperature code write control signal generated when an operation corresponding to a specific command is performed, generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, store a larger temperature code between the operating temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal.

2. The semiconductor memory device according to claim 1, wherein The temperature code storage unit includes: an analog-to-digital converter configured to receive the temperature signal in response to the temperature code write control signal and perform an analog-to-digital conversion operation to generate the operating temperature code; a first comparator configured to compare the operating temperature code with the previously stored temperature code in response to the temperature code write control signal to generate an output temperature code; a pulse generator configured to generate a first read pulse signal in response to the temperature code read control signal; and A register is configured to store the output temperature code as the maximum temperature code in response to the temperature code write control signal, and output the maximum temperature code to the external source in response to the first read pulse signal.

3. The semiconductor memory device according to claim 2, wherein The pulse generator is configured to generate a second read pulse signal instead of the first read pulse signal in response to the temperature code read control signal, and The temperature code storage unit further includes: a second comparator configured to receive the maximum temperature code output from the register in response to the temperature code write control signal, and compare the maximum temperature code with at least one temperature range specifying code specifying at least two temperature ranges to generate at least two programming signals, the at least two programming signals indicating to which of the at least two temperature ranges the maximum temperature code belongs; and A programming unit is configured to program a temperature range code indicating a temperature range to which the maximum temperature code belongs in response to the at least two programming signals and output the temperature range code.

4. The semiconductor memory device according to claim 3, wherein The pulse generator generates the first read pulse signal or the second read pulse signal in response to a temperature code read selection signal, and The temperature code storage unit outputs the maximum temperature code or the temperature range code to the external source in response to the temperature code read selection signal.

5. The semiconductor memory device according to claim 3, further comprising: an internal clock signal generator configured to receive an external clock signal from the external source and generate an internal clock signal; a command and address generator configured to receive a command and an address from the external source in response to the external clock signal, decode a command signal included in the command and address to generate an active command, a read command, a write command, or a mode setting command, generate an address signal included in the command and address and applied together with the active command as a row address, generate the address signal included in the command and address and applied together with the read command or the write command as a column address, and generate the address signal included in the command and address and applied together with the mode setting command as a mode setting code; a mode setting register configured to receive the mode setting code in response to the mode setting command to set a read latency, a write latency, and a burst length; a latency controller configured to, when the specific command is the read command, generate a read latency control signal and the temperature code write control signal using the read latency, the internal clock signal, or the burst length, or to, when the specific command is the write command, generate a write latency control signal and the temperature code write control signal using the write latency, the internal clock signal, or the burst length; a row decoder configured to decode the row address to generate a plurality of word line selection signals; a column decoder configured to decode the column address to generate a plurality of column selection signals; a memory cell array including a plurality of memory cells and configured to store input data in a memory cell selected by the plurality of word line selection signals and the plurality of column selection signals or to generate output data from the selected memory cell; a data reading unit configured to receive the output data output from the memory cell array in response to the read delay control signal and output the output data to the external source through a data terminal; as well as A data writing unit is configured to receive data applied from the external source through the data terminal in response to the write delay control signal and output the received data to the memory cell array.

6. The semiconductor memory device according to claim 5, wherein The latency controller is further configured to generate the temperature code read control signal by using the read latency and the burst length when the specific command is the read command, or to generate the temperature code read control signal by using the write latency and the burst length when the specific command is the write command.

7. The semiconductor memory device according to claim 6, wherein The temperature code read control signal is generated after outputting data to the external source through the data terminal in response to the read latency control signal, or after receiving the data through the data terminal in response to the write latency control signal.

8. The semiconductor memory device according to claim 6, wherein The maximum temperature code or the temperature range code is output through the data terminal.

9. The semiconductor memory device according to claim 6, wherein The maximum temperature code or the temperature range code is serially output through a separate temperature code output terminal.

10. The semiconductor memory device according to claim 5, wherein The command and address generator decodes the command signal to further generate the temperature code reading control signal, or the mode setting register receives the mode setting code to generate the temperature code reading control signal, and The mode setting register receives the mode setting code to set the at least one temperature range designation code.

11. A semiconductor memory device comprising: an internal clock signal generator configured to receive an external clock signal from an external source and generate an internal clock signal; a command and address generator configured to receive a command and an address from the external source in response to the external clock signal, decode a command signal included in the command and address to generate an active command, a read command, a write command, or a mode setting command, generate an address signal included in the command and address and applied together with the active command as a row address, generate the address signal included in the command and address and applied together with the read command or the write command as a column address, and generate the address signal included in the command and address and applied together with the mode setting command as a mode setting code; a mode setting register configured to receive the mode setting code in response to the mode setting command and set a read latency, a write latency, and a burst length; a latency controller configured to, when the read command is applied, generate a read latency control signal, a temperature code write control signal, and a temperature code read control signal using the read latency, the internal clock signal, or the burst length; or, when the write command is applied, generate a write latency control signal, the temperature code write control signal, and the temperature code read control signal using the write latency, the internal clock signal, or the burst length; a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal; a temperature code storage unit configured to receive the temperature signal in response to the temperature code write control signal to generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, and store a larger temperature code between the operating temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code or a temperature range code corresponding to the maximum temperature code to the external source in response to the temperature code read control signal; a row decoder configured to decode the row address to generate a plurality of word line selection signals; a column decoder configured to decode the column address to generate a plurality of column selection signals; a memory cell array including a plurality of memory cells and configured to store input data in a memory cell selected by the plurality of word line selection signals and the plurality of column selection signals or to generate output data from the selected memory cell; a data reading unit configured to receive the output data output from the memory cell array in response to the read delay control signal to output the output data to the external source through a data terminal; as well as The data writing unit is configured to receive data from the external source through the data terminal in response to the write delay control signal to output the received data to the memory cell array.

12. The semiconductor memory device according to claim 11, wherein The temperature code storage unit includes: an analog-to-digital converter configured to receive the temperature signal in response to the temperature code write control signal and perform an analog-to-digital conversion operation to generate the operating temperature code; a first comparator configured to compare the operating temperature code with the previously stored temperature code in response to the temperature code write control signal to generate an output temperature code; a pulse generator configured to generate a first read pulse signal in response to the temperature code read control signal; and A register is configured to store the output temperature code as the maximum temperature code in response to the temperature code write control signal, and output the maximum temperature code to the external source in response to the first read pulse signal.

13. The semiconductor memory device according to claim 12, wherein The pulse generator is configured to generate a second read pulse signal instead of the first read pulse signal in response to the temperature code read control signal, and The temperature code storage unit includes: a second comparator configured to receive the maximum temperature code output from the register in response to the temperature code write control signal, and compare the maximum temperature code with at least one temperature range specifying code specifying at least two temperature ranges to generate at least two programming signals, the at least two programming signals indicating to which of the at least two temperature ranges the maximum temperature code belongs; and a programming unit configured to program the temperature range code in response to the at least two programming signals and output the temperature range code, wherein the pulse generator generates the first read pulse signal or the second read pulse signal in response to a temperature code read selection signal, and The temperature code storage unit outputs the maximum temperature code or the temperature range code to the external source in response to the temperature code read selection signal.

14. The semiconductor memory device according to claim 13, wherein The mode setting register receives the mode setting code to set the at least one temperature range designation code or the temperature code read selection signal.

15. The semiconductor memory device according to claim 14, wherein The maximum temperature code or the temperature range code is output through at least one of the data terminals.

16. A memory system comprising: a control unit configured to send commands and addresses, send and receive data, and receive a maximum temperature code in response to an external clock signal; as well as a memory configured to receive the command and address, transmit and receive the data, and transmit the maximum temperature code in response to the external clock signal, Wherein, the memory includes: a temperature sensor configured to sense an internal temperature of the memory and generate a temperature signal; and A temperature code storage unit is configured to receive the temperature signal in response to a temperature code write control signal generated when an operation corresponding to a specific command is actually executed, generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, store a larger temperature code between the operating temperature code and the previously stored temperature code as the maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal.

17. The memory system according to claim 16, wherein: The temperature code storage unit includes: an analog-to-digital converter configured to receive the temperature signal in response to the temperature code write control signal and perform an analog-to-digital conversion operation to generate the operating temperature code; a first comparator configured to compare the operating temperature code with the previously stored temperature code in response to the temperature code write control signal to output an output temperature code; a pulse generator configured to generate a first read pulse signal including a first predetermined number of pulses when receiving the temperature code read control signal; and A register is configured to store the output temperature code as the maximum temperature code in response to the temperature code write control signal, and output the maximum temperature code to the external source in response to the first read pulse signal.

18. The memory system according to claim 17, wherein: The pulse generator is further configured to generate a second read pulse signal including a second predetermined number of pulses instead of the first read pulse signal when receiving the temperature code read control signal, and The temperature code storage unit further includes: a second comparator configured to receive the maximum temperature code output from the register in response to the temperature code write control signal, and compare the maximum temperature code with at least one temperature range specifying code specifying at least two temperature ranges to generate at least two programming signals, the at least two programming signals indicating to which of the at least two temperature ranges the maximum temperature code belongs; and A programming unit is configured to program a temperature range code indicating a temperature range to which the maximum temperature code belongs in response to the at least two programming signals and output the temperature range code to the external source.

19. The memory system of claim 18, wherein: The pulse generator generates the first read pulse signal or the second read pulse signal in response to a temperature code read selection signal upon receiving the temperature code read control signal, and The temperature code storage unit outputs the maximum temperature code or the temperature range code to the external source in response to the temperature code read selection signal.

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