Semiconductor device and method of forming the same

Abstract

The present disclosure relates to a semiconductor device and a method of forming the same. A device includes: a semiconductor fin; and a gate stack located on sidewalls and a top surface of the semiconductor fin. The gate stack includes: a high-k dielectric layer; a work function layer overlapping a bottom of the high-k dielectric layer; and a blocking layer overlapping a second bottom of the work function layer. A low-resistance metal layer overlaps and contacts the work function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than a second resistivity value of both the work function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of forming the same. Background Art

[0002] Metal-oxide-semiconductor (MOS) devices typically include a metal gate, which is formed to address the poly depletion effect in conventional polysilicon gates. The polysilicon depletion effect occurs when the applied electric field removes carriers from the gate region near the gate dielectric, forming a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized immobile donor sites, while in a p-doped polysilicon layer, the depletion layer includes ionized immobile acceptor sites. The depletion effect results in an increase in the effective gate dielectric thickness, making it more difficult to form an inversion layer on the surface of the semiconductor.

[0003] The metal gate may include multiple layers to meet the requirements of NMOS devices and PMOS devices. The formation of the metal gate typically involves depositing multiple metal layers, forming a fill metal region with tungsten, and then performing a chemical mechanical polishing (CMP) process to remove the excess portions of the metal layers. The remaining portions of the metal layers form the metal gate. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a first semiconductor fin; a first gate stack located on sidewalls and a top surface of the first semiconductor fin, wherein the first gate stack includes: a high-k dielectric layer; a work function layer overlapping a first bottom of the high-k dielectric layer; a first barrier layer overlapping a second bottom of the work function layer; and a first low-resistance metal layer overlapping and contacting the work function layer and the first barrier layer, wherein the first low-resistance metal layer has a first resistivity value, and the first resistivity value is lower than a second resistivity value of both the work function layer and the first barrier layer; and a first gate spacer contacting sidewalls of the first gate stack.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a high-k dielectric layer; a work function layer located above and contacting the high-k dielectric layer; a barrier region located above and contacting the work function layer; a metal layer located above the work function layer and the barrier region and contacting the work function layer and the barrier region, wherein the metal layer is planar and the metal layer does not include a portion extending into the barrier region; a gate spacer located on sidewalls of the high-k dielectric layer; and a dielectric fill region overlapping and contacting the gate spacer, the high-k dielectric layer, and the metal layer.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, including: forming a dummy gate stack over a semiconductor region; forming gate spacers on opposite sides of the dummy gate stack; replacing the dummy gate stack with a replacement gate stack, wherein the replacement gate stack includes: a gate dielectric layer; a work function layer located above the gate dielectric layer; and a high-resistance conductive layer located above the work function layer; deeply etching the replacement gate stack and the gate spacers; and depositing a metal layer on the work function layer and the high-resistance conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figures 1 - 6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B and Figures 9 - 15 show cross-sectional views and perspective views of intermediate stages of forming a fin field-effect transistor (FinFET) in accordance with some embodiments.

[0009] Figure 16 show a plan view of a FinFET in accordance with some embodiments.

[0010] Figure 17 show a flow chart of a process for forming a FinFET in accordance with some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, spatial relative terms may be used herein (e.g., "below", "beneath", "lower", "above", "upper", etc.) to facilitate the description of the relationship of one element or feature shown in the figures with respect to another (one or more) element or (one or more) feature. These spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0013] According to some embodiments, a transistor and a method of forming the same are provided. According to some embodiments, an intermediate stage of forming a transistor is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order. According to an embodiment, the concept of the present disclosure is explained by taking the formation of a fin field-effect transistor (FinFET) as an example. Other types of transistors (e.g., planar transistors) may also adopt the concept of the present disclosure. According to some embodiments of the present invention, a metal (replacement) gate for a FinFET is formed. Then, the metal gate is etched and recessed to create a groove. A low-resistivity conductive layer is formed over and in contact with the recessed metal gate. The resistivity of the low-resistivity conductive layer is lower than the resistivity of each layer in the metal gate, thereby reducing the overall gate resistance of the metal gate.

[0014] Figures 1 - 6 , Figure 7A , Figure 7B , Figure 8A , Figure 8B and Figures 9 - 15 A cross-sectional view and a perspective view showing an intermediate stage of forming a FinFET according to some embodiments of the present disclosure are shown. The processes shown in these figures are also schematically reflected in the process flow 300 shown in Figure 17 .

[0015] Refer to Figure 1, a substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 20 can be a part of the wafer 10, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, usually a silicon or glass substrate. Other substrates can also be used, such as, multi-layer or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate 20 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0016] Further referring to Figure 1 , a well region 22 is formed in the substrate 20. The corresponding process is shown as process 302 in the process flow 300 shown in Figure 17 . According to some embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities (which can be boron, indium, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting n-type impurities (which can be phosphorus, arsenic, antimony, etc.) into the substrate 20. The formed well region 22 can extend to the top surface of the substrate 20. The n-type or p-type impurity concentration can be equal to or less than 10 18 cm -3 , for example, in the range between about 10 17 cm -3 and about 10 18 cm -3 .

[0017] Referring to Figure 2 , an isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is optionally referred to as a shallow trench isolation (STI) region. The corresponding process is shown in Figure 17is shown as process 304 in the process flow 300 shown in. The portion of the substrate 20 between adjacent STI regions 24 is referred to as the semiconductor strip 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also be used as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. Then, the patterned photoresist is used as an etch mask to pattern the hard mask layer 30 to form a hard mask 30 as shown in Figure 2 shown.

[0018] Next, the patterned hard mask layer 30 is used as an etch mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with a (one or more) dielectric material. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove the excess portion of the dielectric material, and the remaining portion of the (one or more) dielectric material is the STI region 24. The STI region 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of the surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 24 may also include a dielectric material above the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material above the liner dielectric may include silicon oxide.

[0019] The top surface of the hard mask layer 30 and the top surface of the STI region 24 can be substantially flush with each other. The semiconductor strip 26 is located between adjacent STI regions 24. According to some embodiments of the present disclosure, the semiconductor strip 26 is part of the original substrate 20, so the material of the semiconductor strip 26 is the same as that of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor strip 26 is a replacement strip formed by the following process: etching the portion of the substrate 20 between the STI regions 24 to form a groove, and performing epitaxy to regrow another semiconductor material in the groove. Therefore, the semiconductor strip 26 is formed of a semiconductor material different from that of the substrate 20. According to some embodiments, the semiconductor strip 26 is formed of silicon germanium, silicon carbide, or a group III-V compound semiconductor material.

[0020] Reference Figure 3 , the STI region 24 is recessed so that the top of the semiconductor strip 26 protrudes above the top surface 24A of the rest of the STI region 24 to form a protruding fin 36. The corresponding process is shown as process 306 in the process flow 300 shown in Figure 17 . A dry etching process can be used to perform the etching, where, for example, HF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, a wet etching process is used to recess the STI region 24. The etching chemical can include, for example, HF.

[0021] In the above embodiments, the fins can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fins, including double patterning or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitch than can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer or mandrel can then be used to pattern the fins.

[0022] Reference Figure 4 , a dummy gate stack 38 is formed to extend over the top surface and sidewalls of the (protruding) fin 36. The corresponding process is shown in Figure 17is shown as process 308 in the process flow 400 shown in. The dummy gate stack 38 may include a dummy gate dielectric 40 and a dummy gate electrode 42 above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed of, for example, polysilicon and may also use other materials. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fin 36.

[0023] Next, a gate spacer 46 is formed on the sidewalls of the dummy gate stack 38. The corresponding process is also shown as process 308 in the process flow 300 shown in Figure 17 According to some embodiments of the present disclosure, the gate spacer 46 is formed of one (or more) dielectric materials such as silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The dielectric constant (k value) of the gate spacer 46 is less than 3.8 and may be less than about 3.0, for example, in the range between about 2.5 and 3.0.

[0024] Then, an etching process is performed to etch the portions of the protruding fin 36 that are not covered by the dummy gate stack 38 and the gate spacer 46, thereby generating Figure 5 the structure shown in. The corresponding process is shown as process 310 in the process flow 300 shown in Figure 17 The recess may be anisotropic, so that the portion of the fin 36 directly under the dummy gate stack 38 and the gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 may be lower than the top surface 24A of the STI region 24. Accordingly, a groove 50 is formed. The groove 50 includes portions on opposite sides of the dummy gate stack 38 and portions between the remaining portions of the protruding fins 36.

[0025] Next, an epitaxial region (source / drain region) 54 is formed by selectively growing (by epitaxy) semiconductor material in the groove 50, thereby generating Figure 6 the structure in. The corresponding process is in Figure 17is shown as process 312 in the process flow 300 shown in. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in-situ as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 comprises a group III-V compound semiconductor, for example, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof, etc. After the trench 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and facets can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. Voids (air gaps) 56 may be generated. According to some embodiments of the present disclosure, when the top surface of the epitaxial region 54 is still wavy, or when the top surface of the merged epitaxial regions 54 has become flat (which is achieved by further growth on the epitaxial region 54, as Figure 6 shown), the formation of the epitaxial region 54 can be completed.

[0026] After the epitaxial step, the epitaxial region 54 can be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted by the reference numeral 54 in the drawings. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is doped with p-type or n-type impurities in-situ during epitaxy, the implantation step is skipped.

[0027] Figure 7A A perspective view of the structure after the formation of the contact etch stop layer (CESL) 58 and the interlayer dielectric (ILD) 60 is shown. The corresponding process is shown as process 314 in the process flow 300 shown in Figure 17 . The CESL 58 can be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. The ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The ILD 60 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based material, for example, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical polishing process can be performed to make the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacers 46 flush with each other.

[0028] Figure 7BA cross-sectional view of an intermediate structure in which a short-channel device and a long-channel device (which may be a FinFET) are formed on the same substrate 20 is shown. The short-channel device is formed in the device region 100, and the long-channel device is formed in the device region 200. The channel length Lg1 of the short-channel device is less than the channel length Lg2 of the long-channel device, as shown. According to some embodiments, the ratio Lg2 / Lg1 may be greater than about 1.5 or 2.0 and may be in the range between about 1.5 and about 10. According to some embodiments of the present disclosure, the channel length Lg1 of the short-channel device may be less than about 30 nm, and the channel length Lg2 of the long-channel device may be greater than about 45 nm. According to some embodiments, the short-channel device is a core transistor or a transistor in other circuits such as a static random access memory (SRAM), and the long-channel device is a transistor in a driver circuit, a peripheral circuit, etc. The cross-sectional view of either the short-channel device or the long-channel device may correspond to a cross-sectional view obtained from a vertical plane including line A-A in FIG. 7.

[0029] To distinguish features in the short-channel device from features in the long-channel device, features in the short-channel device are denoted by adding the number 100 to the reference numeral of the corresponding feature in Figure 7A and features in the long-channel device are denoted by adding the number 200 to the reference numeral of the corresponding feature in Figure 7A For example, Figure 7B the source / drain regions 154 and 254 in Figure 7A correspond to the source / drain region 54 in Figure 7A The gate spacers in the short-channel device region and the long-channel device region are denoted as 146 and 246, respectively, and they correspond to the gate spacer 46 in

[0030] The corresponding features in the short-channel device and the long-channel device may be formed in a common process, and some example processes are discussed in the preceding and following paragraphs. Figure 7A and 7B After forming the structure shown in Figure 8A and 8B The dummy gate stacks 138 and 238 are replaced with a metal gate and a replacement gate dielectric, as shown in Figure 8B and 9 -14, the top surfaces 124A and 224A of the STI region 24 are shown, and the semiconductor fins 136 and 236 protrude above the top surfaces 124A and 224A, respectively.

[0031] To form the replacement gate, first, the hard mask layers 144 and 244, the dummy gate electrodes 142 and 242, and the dummy gate dielectrics 140 and 240 shown in Figure 7B are removed, thereby forming Figure 8BOpenings 159 and 259 shown. The corresponding process is shown as process 316 in process flow 300 shown in Figure 17 . The opening 59 in Figure 8A corresponds to the opening 159 in device region 100 and the opening 259 in device region 200. The top surfaces and sidewalls of the protruding fins 136 and 236 are respectively exposed to the openings 159 and 259.

[0032] Next, referring to Figure 9 , gate dielectrics 162 and 164 (hereinafter referred to as 162 / 164) and gate dielectrics 262 and 264 (hereinafter referred to as 262 / 264) are formed, which extend into the openings 159 and 259 respectively. The corresponding process is shown as process 318 in process flow 300 shown in Figure 17 . According to some embodiments of the present invention, the gate dielectrics include interface layers (ILs) 162 and 262, which are respectively formed on the exposed surfaces of the protruding fins 136 and 236. The ILs 162 and 262 may include oxide layers, such as silicon oxide layers, which are formed by thermal oxidation, chemical oxidation processes or deposition processes of the protruding fins 136 and 236. The gate dielectrics may further include high-k dielectric layers 164 and 264 above the corresponding ILs 162 and 262. The high-k dielectric layers 164 and 264 may be formed of high-k dielectric materials such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, combinations thereof, multi-layers thereof, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, may be higher than about 7.0, and sometimes even as high as 21.0 or higher. The high-k dielectric layers 164 and 264 overlie and may contact the corresponding underlying ILs 162 and 262. The high-k dielectric layers 164 and 264 form conformal layers and extend on the sidewalls of the protruding fins 136 and 236 and the top surfaces and sidewalls of the gate spacers 146 and 246 respectively. According to some embodiments of the present disclosure, the high-k dielectric layers 164 and 264 are formed using ALD, CVD, etc. The high-k dielectric layers 164 and 264 may be part of the same dielectric layer and are formed simultaneously with the same material and the same thickness, or are formed separately with different materials and / or different thicknesses.

[0033] According to some embodiments, an adhesion layer (which is also a diffusion barrier layer) 166 and 266 is formed on the high-k dielectric layers 164 and 264. The adhesion layers 166 and 266 can be formed of TiN or titanium silicon nitride (TSN). The TiN layer can be formed using ALD or CVD, and the TSN layer can include alternately deposited TiN layers and SiN layers, which are formed using ALD, for example. Since the TiN layer and the SiN layer are very thin, these layers may not be distinguishable from each other and are thus referred to as the TSN layer. According to an alternative embodiment, the adhesion layers 166 and 266 are not formed, and the subsequently formed work function layers 168 and 268 are in contact with the corresponding underlying high-k dielectric layers 164 and 264.

[0034] With further reference Figure 9 , the work function layers 168 and 268 are formed by deposition. The corresponding process is shown as process 320 in the process flow 300 shown in Figure 17 . Each of the work function layers 168 and 268 includes at least one homogeneous layer having an entirety formed of the same material, or may include a plurality of sub-layers formed of materials different from each other. The corresponding layers in the work function layers 168 and 268 may or may not be formed in a common deposition process. The specific materials of the layers in the work function layers 168 and 268 can be selected according to whether each FinFET formed in the device regions 100 and 200 is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, each of the work function layers 168 and 268 may include an n work function layer, which includes a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, an aluminum base layer (formed of, for example, TiAl, TiAlN, TiAlC, TaAlN, TaAl, or TaAlC), WC, a combination thereof, and multiple layers thereon. When the FinFET is a p-type FinFET, the corresponding work function layers 168 and 268 may include a p work function layer, such as a TiN layer, a tungsten carbon nitride layer (W x C y N z ), etc. It can be understood that W x C y N z can be an n work function layer or a p work function layer, depending on the ratio of tungsten, carbon, and nitrogen. For example, when the value z is close to zero, the corresponding W x C y N z layer is an n work function layer. On the other hand, W 0.55 C 0.12 N 0.28 O 0.05The layer is a p work function layer. According to some embodiments, the work function layer of an n-type FinFET may further include an n work function layer and a p work function layer above the n work function layer, where the n work function layer dominates the work function of the corresponding FinFET. Similarly, the work function layer of a p-type FinFET may further include a p work function layer and an n work function layer above the p work function layer, where the p work function layer dominates the work function of the corresponding FinFET. According to other embodiments, the FinFET has a single uniform work function layer.

[0035] According to some embodiments of the present disclosure, barrier layers 170 and 270 (which are also adhesion layers) are respectively formed above the work function layers 168 and 268. The corresponding process is shown as process 320 in the process flow 300 shown in Figure 17 The barrier layers 170 and 270 may be metal-containing layers, which may be formed of TiN according to some embodiments. The materials of the barrier layers 170 and 270 may have a high resistivity, and thus are also referred to as high-resistivity conductive layers. Other materials such as TaN may also be used. According to some embodiments, the barrier layers 170 and 270 are formed using ALD, CVD, etc. The barrier layers 170 and 270 may be part of the same metal-containing layer, which are formed simultaneously with the same material and having the same thickness, or are formed separately using different materials and / or having different thicknesses.

[0036] According to some embodiments, the barrier layer 170 completely fills the remaining opening 159 ( Figure 8B ), because the opening 159 is narrow. On the other hand, Figure 9 the barrier layer 264 in Figure 8B partially fills the remaining opening 259 (

[0037] Next, a gap filling process is performed to fill the remaining opening 259 with the metal layer 272, and the metal layer 272 completely fills the opening 259. In the same process of forming the metal layer 272, the metal layer 172 is also deposited. Since the opening 159 has been completely filled, the metal layer 172 is deposited above the barrier layer 170 and outside the opening 159 ( Figure 8B ). According to some embodiments, the formation of the metal layers 172 and 272 includes, for example, growing a nucleation layer using ALD and then performing a deposition process using another method (such as CVD). The metal layers 172 and 272 may be formed of a low-resistance conductive material (which may be a metal) such as tungsten, cobalt, or a combination thereof. In an example process using tungsten, the process gas may include WF6 and H2, as well as some carrier gases such as argon.

[0038] After the metal layers 172 and 272 are formed, a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process, is performed to remove, for example, Figure 9Excess portions of the deposited layers shown, thereby creating gate stacks 174 and 274 as shown in Figure 10 The gate stacks 174 and 274 respectively include gate dielectrics 162 / 164 and 262 / 264 and gate electrodes 176 and 276.

[0039] Figure 11 A first etch-back process performed on the gate stacks 174 and 274 and the gate spacers 146 and 246 is shown, where the etching is represented by arrow 77. The corresponding process is shown as process 322 in the process flow 300 shown in Figure 17 Accordingly, grooves 161 and 261 are generated. The first etch-back process may include a dry etching process and / or a wet etching process. In addition, the etching can be isotropic or anisotropic. According to some embodiments of the present disclosure, the deep etch process is performed using an etchant that etches the gate spacers 146 and 246 and the gate stacks 174 and 274, and does not etch the CESLs 58 and 60. According to some embodiments when using a dry etching process, the etching gas includes an F-based etchant (such as CF4, C2F6, NF3, etc.) or a combination thereof. According to some embodiments when using a wet etching process, the etching chemical may include a diluted HF solution, NH4OH (ammonia solution), or a combination thereof. According to some embodiments, after the first deep etch process, the height of the gate stack 174 (or 274) is H1, which may be in the range of about 8 nm to about 16 nm. The vertical distance from the top surface of the protruding fin 136 (or 236) to the top surface of the ILD 60 is denoted as H2. The ratio H1 / H2 may be in the range of about 0.1 to about 0.25. The recess depth D1 (or D2) may be in the range of about 50 nm to about 80 nm. It should be understood that the value of the recess depth D1 cannot be too high or too low. If the value is too high, some portions (such as the horizontal portions) of the gate stacks 174 and 274 may be disadvantageously removed, resulting in device failure. If the value is too low, insufficient grooves will be created to accommodate the subsequently filled low-resistivity conductive layer.

[0040] After the first deep etch process as shown in Figure 11 is performed, a second deep etch process is performed, as shown in Figure 12 where the etching is represented by arrow 77'. The corresponding process is shown in Figure 17is shown as process 324 in the process flow 300 shown in. Grooves 178 and 278 are thus formed between opposite portions of the corresponding high-k dielectric layers 164 and 264. The second deep etching process is performed using an etching gas or an etching chemical solution different from that used in the first deep etching process. The second deep etching process may include a dry etching process and / or a wet etching process. In addition, the etching may be isotropic or anisotropic. According to some embodiments of the present disclosure, the second deep etching process is performed using an etchant that etches the gate electrodes 176 and 276 and does not etch the gate spacers 146 and 246, the high-k dielectric layers 164 and 264, the CESL 58, and the ILD 60. According to some embodiments when using a dry etching process, the etching gas may include BCl3, Cl2, WF6, or a combination thereof. According to some embodiments when using a wet etching process, the etching chemical may include NH4OH, etc. According to some embodiments, the recess depth D2 may be in the range of about 2 nm to about 10 nm. It should be understood that the value of the recess depth D2 should not be too high or too low either. If the value is too high, some portions of the gates 176 and 276 may be undesirably removed, resulting in device failure. If the value is too low, insufficient grooves will be produced to accommodate the subsequently filled low-resistivity conductive layer.

[0041] Due to the selectivity of the etchant for different materials, the top surface 146TS of the gate spacer 146 may be flush with, higher than, or lower than the top surface 164TS of the high-k dielectric layer 164. Similarly, the top surface 246TS of the gate spacer 246 may be flush with, higher than, or lower than the top surface 264TS of the high-k dielectric layer 264. However, the height difference between the top surface 164TS and the adjacent top surface 264TS of the same FinFET is low, for example, less than about 2 nm or about 1 nm. Some possible example positions of the top surfaces 146TS, 164TS, 246TS, and 264TS are shown using dashed lines.

[0042] Reference Figure 13 , the low-resistivity conductive layers 180 and 280 (which may be metal layers) are formed using a selective deposition process. Throughout the description, the low-resistivity conductive layers 180 and 280 may also be regarded as parts of the corresponding gate electrodes. According to some embodiments of the present disclosure, the low-resistivity conductive layers 180 and 280 are formed of molybdenum (Mo), tungsten (W), cobalt, their alloys, etc. The corresponding process is in Figure 17In the process flow 300 shown, it is shown as process 326. The resistivity of the low-resistivity conductive layers 180 and 280 is lower than that of the layers in the gate electrodes 176 and 276 (including layers 166, 266, 168, 268, 170, and 270). The low-resistivity conductive layers 180 and 280 are formed on the gate electrodes 176 and 276 respectively, rather than on the exposed surfaces of the gate spacers 146 and 246, the high-k dielectric layers 164 and 264, the CESL 58, and the ILD 60. According to some exemplary embodiments, the deposition is performed using ALD or CVD. The precursor may include metal halides (such as WCl5) and reducing agents (such as H2). The deposition process can be a thermal process performed at a high temperature, for example, in the range of about 275 °C to about 500 °C. The deposition can also be performed with plasma turned on.

[0043] Due to selective deposition, the low-resistivity conductive layers 180 and 280 can be conformal layers. Additionally, if the top surfaces of the gate electrodes 176 and 276 are planar respectively, the low-resistivity conductive layers 180 and 280 can be substantially planar. Alternatively, the low-resistivity conductive layers 180 and 280 are curved and have a topology that follows the top surface profile of the corresponding underlying gate electrodes 176 and 276. The thicknesses of the low-resistivity conductive layers 180 and 280 are selected such that the resistivities of the low-resistivity conductive layers 180 and 280 are low enough. For example, the thicknesses of the low-resistivity conductive layers 180 and 280 can be in the range of about 2 nm to about 6 nm. According to some embodiments, the top surfaces of the low-resistivity conductive layers 180 and 280 are lower than the top surfaces (edges) of the corresponding high-k dielectric layers 164 and 264, such that the entire low-resistivity conductive layers 180 and 280 are located in the corresponding grooves 178 and 278. This provides some process margin to ensure that the low-resistivity conductive layers 180 and 280 do not form outside the grooves 178 and 278 respectively. In other cases, the low-resistivity conductive layers 180 and 280 can extend on the top surfaces of the gate spacers 146 and 246 and the high-k dielectric layers 164 and 264. If this occurs, if process variations cause the subsequently formed source / drain contact plugs to be inappropriately shifted to the gate spacers 146 and 246, the subsequently formed source / drain contact plugs can be electrically short-circuited to the low-resistivity conductive layers 180 and 280. According to alternative embodiments, the top surfaces of the low-resistivity conductive layers 180 and 280, shown with dashed lines, are coplanar with the top edges of the corresponding high-k dielectric layers 164 and 264 and / or the top edges of the corresponding gate spacers 146 and 246.

[0044] Next, the remaining openings 161 / 178 and 261 / 278 are filled with a dielectric material to form dielectric fill regions 182 and 282, as Figure 14 shown. The corresponding process is inFigure 17 In the process flow 300 shown, it is shown as process 328. The dielectric fill regions 182 and 282 may be formed of a uniform low-k dielectric material, which may be formed of porous silicon nitride, porous silicon oxynitride, porous silicon carbonitride, etc. The dielectric fill regions 182 and 282 are also planarized such that their top surfaces are coplanar with the top surface of the ILD 60. The sidewalls of the dielectric fill regions 182 and 282 are in contact with the sidewalls of the CESL 58.

[0045] Figure 15 The formation of the gate contact plugs 184 and 284, the source / drain silicide regions 186 and 286, and the source / drain contact plugs 187 and 287 is shown. The corresponding processes are shown as process 330 in the process flow 300 shown in Figure 17 The formation of the source / drain contact plugs 187 and 287 includes forming contact openings by etching the ILD 60 to expose the underlying portion of the CESL 58, and then etching the exposed portion of the CESL 58 to expose the source / drain regions 154 and 254. In a subsequent process, a metal layer (such as a Ti layer) is deposited to extend into the contact openings.

[0046] A metal nitride barrier layer (such as a TiN layer) may be performed. Then an annealing process is performed to react the metal layer with the tops of the source / drain regions 154 / 254 to form the silicide regions 186 and 286. Next, either the previously formed metal nitride layer is left unremoved or the previously formed metal nitride layer is removed and then a new metal nitride layer (such as a titanium nitride layer) is deposited. Then a fill metal material (such as tungsten, cobalt, etc.) is filled into the contact openings and then planarized to remove the excess material, thereby creating the source / drain contact plugs 187 and 287. The formation of the gate contact plugs 184 and 284 may include etching the dielectric fill regions 182 and 282 to expose the low-resistivity conductive layers 180 and 280 and forming the gate contact plugs 184 and 284 in the corresponding openings. The gate contact plugs 184 and 284 may also include a diffusion barrier layer (such as titanium nitride) and a metal (such as copper, tungsten, cobalt, etc.) above the diffusion barrier layer. Thus, the FinFETs 190 and 290 are formed.

[0047] Figure 16 A top view of certain portions of the FinFET 190 or 290 is shown. The gate electrode 176 (or 276) and the overlying low-resistivity conductive layer 180 (or 280). The vertical portions of the high-k dielectric layer 164 (or 264) may form a ring that surrounds the corresponding gate stack 176 (or 276) and the corresponding overlying low-resistivity conductive layer 180 (or 280). The gate contact plugs 184 (or 284), the protruding fins 136 (or 246), and the source / drain regions 154 (or 254) are also shown in the figure.

[0048] Experiments show that by forming a low-resistivity conductive layer on the gate electrode, the gate resistance Rg of a short-channel transistor can be reduced to approximately 10% of the gate resistance Rg of a short-channel transistor without the low-resistivity conductive layer. For example, a sample gate is formed on a silicon wafer, and the resistance value of the corresponding gate electrode is measured. The results show that with the formation of the low-resistivity conductive layer, the resistance values of 100% of the sample gates are less than the first value. In comparison, if the low-resistivity conductive layer is not formed, the resistance values of more than 50% of the gate electrodes are higher than four times the first value.

[0049] Embodiments of the present disclosure have some advantageous features. In a short-channel device, the gate electrode is formed of a high-resistivity layer such as a work function layer and a barrier layer, and there may be no low-resistivity layer in the gate electrode. As a result, the gate resistance Rg of the resulting gate electrode is very high. Therefore, the performance of the corresponding transistor is significantly reduced. According to some embodiments of the present disclosure, a low-resistivity layer is formed on the gate electrode to reduce the gate resistance Rg.

[0050] According to some embodiments of the present disclosure, a device includes: a first semiconductor fin; a first gate stack located on sidewalls and a top surface of the first semiconductor fin, wherein the first gate stack includes: a high-k dielectric layer; a work function layer overlapping a first bottom of the high-k dielectric layer; a first barrier layer overlapping a second bottom of the work function layer; and a first low-resistance metal layer overlapping and contacting the work function layer and the first barrier layer, wherein the first low-resistance metal layer has a first resistivity value that is lower than a second resistivity value of both the work function layer and the first barrier layer; and a first gate spacer contacting sidewalls of the first gate stack. In an embodiment, the device further includes: a contact etch stop layer including a vertical portion contacting sidewalls of the first gate spacer, wherein the vertical portion extends above the first gate spacer. In an embodiment, the device further includes: a dielectric fill region located above and contacting the first gate spacer and the high-k dielectric layer, wherein the dielectric fill region further contacts the vertical portion of the contact etch stop layer. In an embodiment, the dielectric fill region includes a low-k dielectric material. In an embodiment, the high-k dielectric layer has a first top edge and the first gate spacer has a second top edge, and wherein the first top edge is higher than the second top edge. In an embodiment, the high-k dielectric layer has a first top edge and the first gate spacer has a second top edge, and wherein the first top edge is lower than the second top edge. In an embodiment, the high-k dielectric layer has a first top edge and the first gate spacer has a second top edge, and wherein the first top edge is flush with the second top edge. In an embodiment, the device further includes a second gate stack of a transistor, the second gate stack including: a second barrier layer formed of the same material as the first barrier layer; a metal region located between opposite vertical portions of the second barrier layer; and a second low-resistance metal layer overlapping and contacting the second barrier layer and the metal region, wherein the first low-resistance metal layer and the second low-resistance metal layer are formed of the same material.

[0051] According to some embodiments of the present disclosure, a device includes: a high-k dielectric layer; a work function layer located above and in contact with the high-k dielectric layer; a blocking region located above and in contact with the work function layer; a metal layer located above the work function layer and the blocking region and in contact with the work function layer and the blocking region, wherein the metal layer is planar and the metal layer does not include a portion extending into the blocking region; a gate spacer located on a sidewall of the high-k dielectric layer; and a dielectric fill region overlapping and contacting the gate spacer, the high-k dielectric layer, and the metal layer. In an embodiment, the dielectric fill region extends between opposite portions of the high-k dielectric layer. In an embodiment, the dielectric fill region is formed of a low-k dielectric material. In an embodiment, the device further includes: a source / drain region located on a side of the high-k dielectric layer; and a contact etch stop layer including a horizontal portion and a vertical portion, the horizontal portion being located above and in contact with the source / drain region, and the vertical portion contacting both the high-k dielectric layer and the dielectric fill region. In an embodiment, the device further includes: an interlayer dielectric overlapping and contacting the horizontal portion of the contact etch stop layer, wherein a top surface of the interlayer dielectric is higher than a top surface of the gate spacer. In an embodiment, the work function layer includes opposite sidewall portions, and all materials located between the opposite sidewall portions and overlapping the bottom of the work function layer include titanium nitride.

[0052] According to some embodiments of the present disclosure, a method includes: forming a dummy gate stack above a semiconductor region; forming gate spacers on opposite sides of the dummy gate stack; replacing the dummy gate stack with a replacement gate stack, wherein the replacement gate stack includes: a gate dielectric layer; a work function layer located above the gate dielectric layer; and a high-resistance conductive layer located above the work function layer; deeply etching the replacement gate stack and the gate spacers; and depositing a metal layer on the work function layer and the high-resistance conductive layer. In an embodiment, deeply etching the replacement gate stack and the gate spacers includes: performing a first deep etching process to recess the gate spacers and the replacement gate stack; and performing a second deep etching process to recess the work function layer and the high-resistance conductive layer, wherein the gate spacers and the gate dielectric layer are not etched in the second deep etching process. In an embodiment, the metal layer is lower than a top surface of the gate dielectric layer. In an embodiment, during depositing the metal layer, the metal layer is selectively deposited on the work function layer and the high-resistance conductive layer and is not deposited on dielectric materials exposed when the depositing of the metal layer is performed. In an embodiment, the gate dielectric layer includes a vertical portion that forms a ring having four sides, and the metal layer contacts sidewalls of all four sides. In an embodiment, depositing the metal layer includes depositing a tungsten layer.

[0053] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0054] Example 1 is a semiconductor device including: a first semiconductor fin; a first gate stack located on sidewalls and a top surface of the first semiconductor fin, wherein the first gate stack includes: a high-k dielectric layer; a work function layer overlapping a first bottom of the high-k dielectric layer; a first barrier layer overlapping a second bottom of the work function layer; and a first low-resistance metal layer overlapping and contacting the work function layer and the first barrier layer, wherein the first low-resistance metal layer has a first resistivity value that is lower than a second resistivity value of both the work function layer and the first barrier layer; and a first gate spacer contacting sidewalls of the first gate stack.

[0055] Example 2 is the device of Example 1, further including: a contact etch stop layer including a vertical portion contacting sidewalls of the first gate spacer, wherein the vertical portion extends above the first gate spacer.

[0056] Example 3 is the device of Example 2, further including: a dielectric fill region located above and contacting the first gate spacer and the high-k dielectric layer, wherein the dielectric fill region also contacts the vertical portion of the contact etch stop layer.

[0057] Example 4 is the device of Example 3, wherein the dielectric fill region includes a low-k dielectric material.

[0058] Example 5 is the device of Example 1, wherein the high-k dielectric layer has a first top edge, and the first gate spacer has a second top edge, and wherein the first top edge is higher than the second top edge.

[0059] Example 6 is the device of Example 1, wherein the high-k dielectric layer has a first top edge, and the first gate spacer has a second top edge, and wherein the first top edge is lower than the second top edge.

[0060] Example 7 is the device described in Example 1, wherein the high-k dielectric layer has a first top edge, and the first gate spacer has a second top edge, and wherein the first top edge is flush with the second top edge.

[0061] Example 8 is the device described in Example 1, further comprising: a second gate stack of a transistor, the second gate stack comprising: a second barrier layer formed of the same material as the first barrier layer; a metal region located between opposite vertical portions of the second barrier layer; and a second low-resistance metal layer overlapping and contacting the second barrier layer and the metal region, wherein the first low-resistance metal layer and the second low-resistance metal layer are formed of the same material.

[0062] Example 9 is a semiconductor device comprising: a high-k dielectric layer; a work function layer located above and in contact with the high-k dielectric layer; a barrier region located above and in contact with the work function layer; a metal layer located above and in contact with the work function layer and the barrier region, wherein the metal layer is planar and the metal layer does not include a portion extending into the barrier region; a gate spacer located on a sidewall of the high-k dielectric layer; and a dielectric fill region overlapping and contacting the gate spacer, the high-k dielectric layer, and the metal layer.

[0063] Example 10 is the device described in Example 9, wherein the dielectric fill region extends between opposite portions of the high-k dielectric layer.

[0064] Example 11 is the device described in Example 9, wherein the dielectric fill region is formed of a low-k dielectric material.

[0065] Example 12 is the device described in Example 9, further comprising: source / drain regions located on sides of the high-k dielectric layer; and a contact etch stop layer comprising a horizontal portion and a vertical portion, the horizontal portion located above and in contact with the source / drain regions, and the vertical portion in contact with both the high-k dielectric layer and the dielectric fill region.

[0066] Example 13 is the device described in Example 12, further comprising: an interlayer dielectric overlapping and contacting the horizontal portion of the contact etch stop layer, wherein a top surface of the interlayer dielectric is higher than a top surface of the gate spacer.

[0067] Example 14 is the device described in Example 9, wherein the work function layer includes opposite sidewall portions, and all materials located between the opposite sidewall portions and overlapping the bottom of the work function layer include titanium nitride.

[0068] Example 15 is a method for forming a semiconductor device, including: forming a dummy gate stack over a semiconductor region; forming gate spacers on opposite sides of the dummy gate stack; replacing the dummy gate stack with a replacement gate stack, wherein the replacement gate stack includes: a gate dielectric layer; a work function layer located over the gate dielectric layer; and a high-resistance conductive layer located over the work function layer; deeply etching the replacement gate stack and the gate spacers; and depositing a metal layer on the work function layer and the high-resistance conductive layer.

[0069] Example 16 is the method according to Example 15, wherein deeply etching the replacement gate stack and the gate spacers includes: performing a first deep etching process to recess the gate spacers and the replacement gate stack; and performing a second deep etching process to recess the work function layer and the high-resistance conductive layer, wherein the gate spacers and the gate dielectric layer are not etched during the second deep etching process.

[0070] Example 17 is the method according to Example 15, wherein the metal layer is below the top surface of the gate dielectric layer.

[0071] Example 18 is the method according to Example 15, wherein during deposition of the metal layer, the metal layer is selectively deposited on the work function layer and the high-resistance conductive layer and is not deposited on dielectric materials exposed when the deposition of the metal layer is performed.

[0072] Example 19 is the method according to Example 15, wherein the gate dielectric layer includes a vertical portion that forms a ring having four sides, and the metal layer contacts the sidewalls of all four sides.

[0073] Example 20 is the method according to Example 15, wherein depositing the metal layer includes: depositing a tungsten layer.

Claims

1. A semiconductor device, comprising: A first semiconductor fin; A first gate stack located on sidewalls and a top surface of the first semiconductor fin, wherein the first gate stack comprises: A high-k dielectric layer; A work function layer overlapping a first bottom of the high-k dielectric layer; A first barrier layer overlapping a second bottom of the work function layer; and A first low-resistance metal layer overlapping and contacting the work function layer and the first barrier layer, wherein the first low-resistance metal layer has a first resistivity value that is lower than a second resistivity value of both the work function layer and the first barrier layer; and A first gate spacer contacting sidewalls of the first gate stack, wherein the high-k dielectric layer has a first top edge, and the first gate spacer has a second top edge, and wherein the first top edge is flush with the second top edge.

2. The device according to claim 1, further comprising: A contact etch stop layer, the contact etch stop layer comprising a vertical portion contacting sidewalls of the first gate spacer, wherein the vertical portion extends above the first gate spacer.

3. The device according to claim 2, further comprising: A dielectric fill region located above and contacting the first gate spacer and the high-k dielectric layer, wherein the dielectric fill region also contacts the vertical portion of the contact etch stop layer.

4. The device according to claim 3, wherein The dielectric fill region comprises a low-k dielectric material.

5. The device according to claim 1, further comprising: A second gate stack of a transistor, the second gate stack comprising: A second barrier layer formed of the same material as the first barrier layer; A metal region located between opposite vertical portions of the second barrier layer; and A second low-resistance metal layer overlapping and contacting the second barrier layer and the metal region, wherein the first low-resistance metal layer and the second low-resistance metal layer are formed of the same material.

6. A semiconductor device, comprising: A high-k dielectric layer; A work function layer located above and contacting the high-k dielectric layer; A barrier region located above and contacting the work function layer; A metal layer located above and contacting the work function layer and the barrier region, wherein the metal layer is planar, and a resistivity value of the metal layer is lower than resistivity values of the work function layer and the barrier region; A gate spacer located on sidewalls of the high-k dielectric layer; and A dielectric fill region overlapping and contacting the gate spacer, the high-k dielectric layer, and the metal layer.

7. The device according to claim 6, wherein, The dielectric fill region extends between opposite portions of the high-k dielectric layer.

8. The device according to claim 6, wherein, The dielectric fill region is formed of a low-k dielectric material.

9. The device according to claim 6, further comprising: Source / drain regions located on sides of the high-k dielectric layer; And A contact etch stop layer comprising a horizontal portion and a vertical portion, the horizontal portion located above and contacting the source / drain regions, and the vertical portion contacting both the high-k dielectric layer and the dielectric fill region.

10. The device according to claim 9, further comprising: An interlayer dielectric that overlaps and contacts a horizontal portion of the contact etch stop layer, wherein a top surface of the interlayer dielectric is higher than a top surface of the gate spacer.

11. The device according to claim 6, wherein The work function layer includes opposing sidewall portions, and all materials located between the opposing sidewall portions and overlapping a bottom of the work function layer include titanium nitride.

12. A method for forming a semiconductor device, comprising: Forming a dummy gate stack over a semiconductor region; Forming gate spacers on opposing sides of the dummy gate stack; Replacing the dummy gate stack with a replacement gate stack, wherein the replacement gate stack includes: A gate dielectric layer; A work function layer located above the gate dielectric layer; and A conductive layer located above the work function layer; Deep etching the replacement gate stack and the gate spacers, wherein deep etching the replacement gate stack and the gate spacers includes: Performing a first deep etching process to recess the gate spacers and the replacement gate stack; and Performing a second deep etching process to recess the work function layer and the conductive layer, wherein the gate spacers and the gate dielectric layer are not etched during the second deep etching process; and Depositing a metal layer on the work function layer and the conductive layer, wherein a resistivity value of the metal layer is lower than resistivity values of the conductive layer and the work function layer.

13. The method according to claim 12, wherein, The metal layer is lower than a top surface of the gate dielectric layer.

14. The method according to claim 12, wherein, During deposition of the metal layer, the metal layer is selectively deposited on the work function layer and the conductive layer and is not deposited on dielectric materials exposed when deposition of the metal layer is performed.

15. The method according to claim 12, wherein The gate dielectric layer includes a vertical portion that forms a ring having four sides, and the metal layer contacts sidewalls of all four sides.

16. The method according to claim 12, wherein, Depositing the metal layer includes: depositing a tungsten layer.

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