A gate oxide layer burning circuit and burning method

Abstract

The present invention relates to a gate oxide layer burning circuit, the burning circuit comprises a high-voltage PMOS tube HP1, high-voltage NMOS tubes HN1 and HN2, low-voltage NMOS tubes LN1 and LN2, a high-voltage power supply VH and a low-voltage power supply VL, the high-voltage power supply VH is connected to the drain of the high-voltage PMOS tube HP1, the source of the high-voltage PMOS tube HP1 is connected to the drain of the high-voltage NMOS tube HN1, the drain of the high-voltage NMOS tube HN1 is grounded, and the high-voltage NMOS tube HN2 is connected between the low-voltage NMOS tubes LN1 and LN2; the technical solution can be carried out after chip packaging, so that the impact of packaging on the chip can be corrected. At the same time, the circuit designed by the patent method can have a very small chip area and low production cost.

Description

Technical Field

[0001] The invention relates to a programming circuit, in particular to a gate oxide layer programming circuit and a programming method, and belongs to the technical field of analog integrated circuits. Background Art

[0002] In the process of analog integrated circuit design, in order to achieve accurate design of some important parameters, such as reference voltage, bias current, oscillator frequency, etc., it is usually necessary to add a burning circuit during the circuit design process. After the integrated circuit is produced, the important parameters in the circuit are burned and corrected according to the test results.

[0003] There are two common burning structures:

[0004] Structure 1, such as Figure 1 As shown, during wafer testing before integrated circuit packaging, two probes are used to pierce the window area on the circuit, and voltage is applied to the two probes. The connecting medium between the two windows is melted by thermal power consumption. The connecting medium is usually a metal resistor or a polycrystalline resistor with a low resistance value. Whether the connecting medium is melted or not can be read as a logic "1" or "0" to achieve control of the internal logic circuit. The advantages of structure 1 are: simple structure, small chip area, and low implementation cost. The disadvantages of structure 1 are: burning can only be performed before chip packaging, because the impact of packaging on the chip cannot be corrected.

[0005] Structure 2. The circuit diagram of this structure is as follows Figure 2 As shown, the PMOS tube P1, the polycrystalline resistor R1 and the NMOS tube N1 are connected in series between the power supply and the ground. When the finished product is tested after the integrated circuit is packaged, the PMOS tube P1 and the NMOS tube N1 are turned on at the same time by an external signal, and the power supply voltage will form a large current on the polycrystalline resistor R1, which is usually about 50mA to 100mA. The heat power consumption generated by the voltage and current will fuse the polycrystalline resistor R1. Whether the resistor R1 is fused or not can be judged by the Read port when reading, so as to realize the control of the internal logic circuit by "1" or "0". The advantage of structure 2 is that the burning can be carried out after the chip is packaged, so the impact of the package on the chip can be corrected. The disadvantage of structure 2 is that because a high-power current is required to fuse the polycrystalline resistor R1, both the PMOS tube P1 and the NMOS tube N1 require a very large width-to-length ratio, and the chip area cost is high. These two structures in the prior art have defects to varying degrees. Therefore, a new solution is urgently needed to solve the above technical problems. Summary of the invention

[0006] The present invention is aimed at the problems existing in the prior art and provides a gate oxide layer burning circuit. The technical solution can be carried out after the chip is packaged, so that the impact of the package on the chip can be corrected. At the same time, the circuit designed by the patent method can be made very small in chip area and low in production cost.

[0007] In order to achieve the above-mentioned purpose, the technical scheme of the present invention is as follows: a gate oxide layer burning circuit, the burning circuit includes a high-voltage PMOS tube HP1, high-voltage NMOS tubes HN1 and HN2, low-voltage NMOS tubes LN1 and LN2, a high-voltage power supply VH and a low-voltage power supply VL, the high-voltage power supply VH is connected to the drain of the high-voltage PMOS tube HP1, the source of the high-voltage PMOS tube HP1 is connected to the drain of the high-voltage NMOS tube HN1, the drain of the high-voltage NMOS tube HN1 is grounded, and the high-voltage NMOS tube HN2 is connected between the low-voltage NMOS tubes LN1 and LN2.

[0008] As an improvement of the present invention, the HP1 is a high-voltage PMOS tube, HN1 and HN2 are high-voltage NMOS tubes, LN1 and LN2 are low-voltage NMOS tubes, and the breakdown voltage of the high-voltage MOS tube exceeds the breakdown voltage of the low-voltage MOS tube by more than 3 times; the voltage value of the high-voltage power supply VH is equal to 2 times the breakdown voltage of the low-voltage MOS tube, and the voltage value of the low-voltage power supply VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube.

[0009] As an improvement of the present invention, the current source I1 is a 1 uA current source on the low voltage domain VL.

[0010] A method for programming a gate oxide layer programming circuit, the method comprising the following steps:

[0011] Step 1: Burning process:

[0012] When programming the circuit, the voltage value of the power supply VH is equal to twice the breakdown voltage of the low-voltage MOS tube, and the voltage value of VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube. The high-voltage PMOS tube HP1 is turned on, and the high-voltage NMOS tube HN1 is turned off, so the voltage of the gate of the low-voltage NMOS tube LN1 is approximately equal to the high-voltage power supply VH. The low-voltage NMOS tube LN2 is turned on, so the drain voltage of the low-voltage NMOS tube LN2 and the source voltage of the high-voltage NMOS tube HN2 are approximately 0; if the unit is to be programmed, the high-voltage NMOS tube HN2 can be turned on, then the drain voltage of HN2 drops to 0, that is, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 also drops to 0, so the gate oxide layer of the low-voltage NMOS tube LN1 will be subjected to the voltage VH, and the voltage value reaches the gate oxide layer breakdown voltage of the low-voltage NMOS tube LN1 2 times of that, so the gate oxide layer of LN1 will be broken down and generate leakage current, the leakage current is about 0.1mA; if this unit is not burned, the high-voltage NMOS tube HN2 can be turned off, then the drain voltage of HN2 is about VH, that is, the source, drain and substrate voltages of the low-voltage NMOS tube LN1 are VH, so the voltage on the gate oxide layer of the low-voltage NMOS tube LN1 is 0, the gate oxide layer of the low-voltage NMOS tube LN1 will not be broken down, so the gate oxide layer of LN1 will not generate leakage current;

[0013] Step 2: Reading process:

[0014] When reading the circuit, the voltage value of the power supply VH is equal to the voltage when the circuit is working normally, and the voltage value of the power supply VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube. The high-voltage PMOS tube HP1 is turned off, and the high-voltage NMOS tube HN1 is turned on, so the voltage of the gate of the low-voltage NMOS tube LN1 is approximately equal to 0. The low-voltage NMOS tube LN2 is turned off, and the high-voltage NMOS tube HN2 is turned on; if this unit has been burned, the gate oxide layer of the low-voltage NMOS tube LN1 has leakage, and the on-resistance is about 10KΩ~100KΩ. Considering that the current of the current source I1 is 1uA, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 is 10mV~100mV. After reading the voltage through the Read port, it can be judged as a low level; if the unit is not burned, there is no leakage in the gate oxide layer of the low-voltage NMOS tube LN1, and the on-resistance is infinite, so the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 will be pulled up by the current source I1 to close to the low voltage source voltage VL. After reading the voltage through the Read port, it can be judged as a high level

[0015] Compared with the prior art, the present invention has the following advantages: the programming of the technical solution can be performed after the chip is packaged, and the impact of the package on the chip can be corrected. In the programming process of the present invention, the programming current is less than 0.1mA, and a large-area MOS tube is not required, so the chip cost is reduced. The chip cost is only about one-tenth of the conventional programming structure, which greatly saves production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 , Figure 2 It is a schematic diagram of the prior art structure;

[0017] Figure 3 It is a schematic diagram of the circuit structure of the present invention. DETAILED DESCRIPTION

[0018] In order to deepen the understanding of the present invention, the present embodiment is described in detail below with reference to the accompanying drawings.

[0019] Example 1: See Figure 3 A gate oxide layer burning circuit, the burning circuit includes a high-voltage PMOS tube HP1, high-voltage NMOS tubes HN1 and HN2, low-voltage NMOS tubes LN1 and LN2, a high-voltage power supply VH and a low-voltage power supply VL, the high-voltage power supply VH is connected to the drain of the high-voltage PMOS tube HP1, the source of the high-voltage PMOS tube HP1 is connected to the drain of the high-voltage NMOS tube HN1, the drain of the high-voltage NMOS tube HN1 is grounded, and the high-voltage NMOS tubes LN1 and LN2 are connected between the high-voltage NMOS tubes S tube HN2, the HP1 is a high-voltage PMOS tube, HN1 and HN2 are high-voltage NMOS tubes, LN1 and LN2 are low-voltage NMOS tubes, the breakdown voltage of the high-voltage MOS tube exceeds 3 times the breakdown voltage of the low-voltage MOS tube; the voltage value of the high-voltage power supply VH is equal to 2 times the breakdown voltage of the low-voltage MOS tube, the voltage value of the low-voltage power supply VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube, and the current source I1 is a 1uA current source on the low-voltage domain VL.

[0020] Implementation principle: The patent of this invention is as follows Figure 3 As shown in the figure, HP1 is a high-voltage PMOS tube, HN1 and HN2 are high-voltage NMOS tubes, LN1 and LN2 are low-voltage NMOS tubes, and the breakdown voltage of the high-voltage MOS tube is more than 3 times that of the low-voltage MOS tube. The power supplies VH and VL are high and low voltage sources respectively. The voltage value of VH is equal to 2 times the breakdown voltage of the low-voltage MOS tube, and the voltage value of VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube. The current source I1 is a 1uA current source on the low voltage domain VL.

[0021] Step 1: Programming process: When programming the circuit, the voltage value of the power supply VH is equal to twice the breakdown voltage of the low-voltage MOS tube, and the voltage value of VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube. The high-voltage PMOS tube HP1 is turned on, and the high-voltage NMOS tube HN1 is turned off, so the voltage of the gate of the low-voltage NMOS tube LN1 is approximately equal to the high-voltage power supply VH. The low-voltage NMOS tube LN2 is turned on, so the drain voltage of the low-voltage NMOS tube LN2 and the source voltage of the high-voltage NMOS tube HN2 are approximately 0. If the unit is to be programmed, the high-voltage NMOS tube HN2 can be turned on, and the drain voltage of HN2 is reduced to 0, that is, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 is also reduced to 0, so the gate oxide layer of the low-voltage NMOS tube LN1 will bear a voltage VH, and the voltage value reaches 2 times the breakdown voltage of the gate oxide layer of the low-voltage NMOS tube LN1, so the gate oxide layer of LN1 will be broken down and generate a leakage current, which is about 0.1mA. If the unit is not programmed, the high-voltage NMOS tube HN2 can be turned off, and the drain voltage of HN2 is about VH, that is, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 is VH, so the voltage on the gate oxide layer of the low-voltage NMOS tube LN1 is 0, and the gate oxide layer of the low-voltage NMOS tube LN1 will not be broken down, so the gate oxide layer of LN1 will not generate leakage current.

[0022] Step 2: Reading process: When reading the circuit, the voltage value of the power supply VH is equal to the voltage when the circuit is working normally, and the voltage value of the power supply VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube. The high-voltage PMOS tube HP1 is turned off, and the high-voltage NMOS tube HN1 is turned on, so the voltage of the gate of the low-voltage NMOS tube LN1 is approximately equal to 0. The low-voltage NMOS tube LN2 is turned off, and the high-voltage NMOS tube HN2 is turned on. If this unit has been burned, there is leakage in the gate oxide layer of the low-voltage NMOS tube LN1, and the on-resistance is about 10KΩ~100KΩ. Considering that the current of the current source I1 is 1uA, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 is 10mV~100mV. After reading the voltage through the Read port, it can be judged as a low level. If the unit is not programmed, the gate oxide layer of the low-voltage NMOS tube LN1 does not have leakage, and the on-resistance is infinite, so the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 will be pulled up by the current source I1 to close to the low voltage source voltage VL. After reading the voltage through the Read port, it can be judged as a high level.

[0023] According to the above analysis, the programming method of the present invention can be performed after chip packaging, and the impact of packaging on the chip can be corrected. At the same time, during the programming process of the present invention, the programming current is less than 0.1mA, and a large-area MOS tube is not required, so the chip cost is reduced.

[0024] It should be noted that the above embodiments are not intended to limit the protection scope of the present invention, and equivalent changes or substitutions made on the basis of the above technical solutions all fall within the protection scope of the claims of the present invention.

Claims

1. A gate oxide layer burning circuit, characterized in that: The programming circuit comprises a high-voltage PMOS tube HP1, high-voltage NMOS tubes HN1 and HN2, low-voltage NMOS tubes LN1 and LN2, a high-voltage power supply VH and a low-voltage power supply VL, wherein the high-voltage power supply VH is connected to the drain of the high-voltage PMOS tube HP1, the source of the high-voltage PMOS tube HP1 is connected to the drain of the high-voltage NMOS tube HN1, the drain of the high-voltage NMOS tube HN1 is grounded, and the high-voltage NMOS tube HN2 is connected between the low-voltage NMOS tubes LN1 and LN2; The HP1 is a high-voltage PMOS tube, HN1 and HN2 are high-voltage NMOS tubes, LN1 and LN2 are low-voltage NMOS tubes, and the breakdown voltage of the high-voltage MOS tube is more than 3 times the breakdown voltage of the low-voltage MOS tube; the voltage value of the high-voltage power supply VH is equal to 2 times the breakdown voltage of the low-voltage MOS tube, and the voltage value of the low-voltage power supply VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube; The current source I1 is a 1uA current source on the low voltage power supply VL; it is characterized in that the programming method of the polar oxide layer programming circuit comprises the following steps: Step 1: Burning process: When programming the circuit, the voltage value of the high-voltage power supply VH is equal to twice the breakdown voltage of the low-voltage MOS tube, the voltage value of the low-voltage power supply VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube, the high-voltage PMOS tube HP1 is turned on, and the high-voltage NMOS tube HN1 is turned off, so the voltage of the gate of the low-voltage NMOS tube LN1 is approximately equal to the high-voltage power supply VH, and the low-voltage NMOS tube LN2 is turned on, so the drain voltage of the low-voltage NMOS tube LN2 and the source voltage of the high-voltage NMOS tube HN2 are approximately 0; To program this unit and turn on the high-voltage NMOS tube HN2, the drain voltage of HN2 will drop to 0, that is, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 will also drop to 0, so the gate oxide layer of the low-voltage NMOS tube LN1 will be subjected to the high-voltage power supply VH. The voltage value of the high-voltage power supply VH reaches 2 times the breakdown voltage of the gate oxide layer of the low-voltage NMOS tube LN1, so the gate oxide layer of LN1 will be broken down and generate leakage current, which is about 0.1mA. If the unit is not programmed, and the high-voltage NMOS tube HN2 is turned off, the drain voltage of HN2 is the high-voltage power supply VH, that is, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 is the high-voltage power supply VH, so the voltage on the gate oxide layer of the low-voltage NMOS tube LN1 is 0, and the gate oxide layer of the low-voltage NMOS tube LN1 will not be broken down, so the gate oxide layer of LN1 will not generate leakage current; Step 2: Reading process: When reading the circuit, the voltage value of the high-voltage power supply VH is equal to the voltage when the circuit is working normally, the voltage value of the low-voltage power supply VL is equal to the normal working voltage of the low-voltage MOS tube, which is lower than the breakdown voltage of the low-voltage MOS tube, the high-voltage PMOS tube HP1 is turned off, and the high-voltage NMOS tube HN1 is turned on, so the voltage of the gate of the low-voltage NMOS tube LN1 is approximately equal to 0, the low-voltage NMOS tube LN2 is turned off, and the high-voltage NMOS tube HN2 is turned on; When this unit has been programmed, the gate oxide layer of the low-voltage NMOS tube LN1 has leakage, and the on-resistance is 10KΩ~100KΩ. Considering that the current of the current source I1 is 1uA, the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 is 10mV~100mV. After reading the voltage through the Read port, it is judged to be a low level; When this unit is not programmed, there is no leakage in the gate oxide layer of the low-voltage NMOS tube LN1, and the on-resistance is infinite, so the voltage of the source, drain and substrate of the low-voltage NMOS tube LN1 will be pulled up by the current source I1 to a voltage close to the low-voltage power supply VL, and the voltage of the low-voltage power supply VL is read through the Read port and judged to be a high level.

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