State switching method, apparatus, device, and storage medium

Abstract

The application provides a state switching method and device, equipment and a storage medium. The method comprises the following steps: a PON optical line terminal (OLT) verifies a received PSync field, and switches a current state according to a verification result. In this way, the probability of downlink synchronization detection can be effectively improved, and the probability of downlink synchronization missed detection can be reduced, so that the normal operation of the PON system is ensured.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a state switching method, apparatus, device, and storage medium. Background Technology

[0002] The 10 Gigabit-capable Passive Optical Network Unit (XGPON ONU) allows K=2 bit errors in the Physical Synchronization Sequence (PSync) field during its downlink synchronization state machine. That is, if the number of error bits in the received 64-bit PSync is less than or equal to 2, it is considered that a PSync has been received; otherwise, it is considered that a non-PSync has been received. Furthermore, when transitioning from the Hunt State to the Pre-Sync State, a perfect PSync match is required. During the state transition, it is necessary not only to determine whether a correct PSync has been received, but also whether a correct Superframe Counter Structure (SFC) has been received. Under the condition that the system's pre-correction bit error rate (Pe) is 1e-3, the above state transition conditions can guarantee the accuracy of XGPON downlink synchronization, and the probability of successful downlink synchronization on the first attempt is 93.79%. On average, a downlink synchronization failure occurs once every 7.86 years (i.e., the average synchronization failure detection time is 7.86 years), and an downlink synchronization failure occurs once every 3.29E+43 years (i.e., the average synchronization failure detection time is 3.29E+43 years).

[0003] However, for high-speed PON systems, in order to reduce the requirements of optical link performance, the bit error rate before correction is relaxed to 1e-2 or even 2e-2. If the downlink synchronization method described above is still followed, the downlink synchronization detection probability is very low, while the missed detection probability is very high, which affects the normal operation of the PON system. Summary of the Invention

[0004] To address at least one of the aforementioned technical problems, embodiments of this application provide the following solutions.

[0005] This application provides a state switching method, including:

[0006] The optical network unit verifies the received PSync field;

[0007] The optical network unit switches its current state based on the verification results.

[0008] This application provides a state switching device, including:

[0009] The verification module is used to verify the received PSync field;

[0010] The switching module is used to switch the current state based on the verification results.

[0011] This application provides an apparatus including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the state switching method provided in this application.

[0012] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the state switching method provided in this application.

[0013] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a downlink PHY frame structure provided in one embodiment;

[0015] Figure 2 A schematic diagram of a PSBd structure is provided for one embodiment;

[0016] Figure 3 A schematic diagram of an existing downlink frame synchronization state switching process provided in one embodiment;

[0017] Figure 4 A schematic diagram of a state switching process is provided for one embodiment;

[0018] Figure 5 A schematic diagram of a downlink frame synchronization state switching process is provided in one embodiment;

[0019] Figure 6 A schematic diagram of a state switching device provided in one embodiment;

[0020] Figure 7 This is a schematic diagram of a device structure provided in one embodiment. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0022] Furthermore, in the embodiments of this application, terms such as "optionally" or "exemplarily" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "optionally" or "exemplarily" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "optionally" or "exemplarily" is intended to present the relevant concepts in a specific manner.

[0023] To facilitate understanding of the solutions in the embodiments of this application, illustrative descriptions of some concepts related to this application are provided for reference. As shown below:

[0024] Frame synchronization in passive optical access systems (Gigabit-Capable PON, GPON) and XGPON is achieved by detecting PSync and (SFC) in the downlink physical synchronization field (PSBd). The structures of PSBd, PSync, and SFC are as follows: Figure 1 , Figure 2 As shown.

[0025] PSync contains a fixed 64-bit pattern with a field encoding of 0xC5E5 1840FD59 BB49. The Optical Network Unit (ONU) uses this sequence to synchronize the downlink physical (PHY) frame boundaries.

[0026] The SFC structure is a 64-bit field containing a 51-bit SFC and a 13-bit Header Error Check (HEC) field. The SFC value of each downlink PHY frame increases by 1 relative to the previous PHY frame. When the SFC reaches its maximum value (each bit is 1), the value is set to 0 in the next downlink PHY frame.

[0027] like Figure 3 As shown, the specific process of the downlink frame synchronization state machine is as follows: The ONU starts from the Hunt state. In the Hunt state, the ONU searches for the PSync field in all possible synchronization locations (including bits and bytes) in the downlink signal. If the searched PSync field is confirmed to match exactly with the PSync field specified in Section 10.1.1.1 of the existing standard, the ONU will verify whether the 64 bits immediately following the PSync field constitute a valid HEC-protected SFC structure. If the 64-bit protected SFC structure is uncorrectable, the ONU will remain in the Hunt state and continue searching for the PSync field. If the 64-bit protected SFC structure is valid, the ONU will store a backup of the SFC value and switch to the pre-synchronization state.

[0028] When the ONU leaves the Hunt state, it performs PSync and SFC verification at each subsequent PHY frame boundary (e.g., every 155520 bytes) and executes the corresponding transition of the downlink synchronization state machine. Before verifying PSync and SFC, the ONU increments its local SFC value by 1. The first 64-bit sequence received at the downlink PHY frame boundary is considered the PSync field, and subsequent 64-bit sequences are considered the SFC structure. If at least 62 bits of the received 64-bit sequence match the fixed PSync field, the PSync verification is successful; otherwise, it fails. If the received 64-bit sequence is a valid HEC protection field, and the received SFC value equals the locally stored SFC value (limited to incremented SFC values), the SFC verification is successful; otherwise, it fails.

[0029] If the ONU enters the pre-sync state and both PSync and SFC are successfully verified, the ONU switches to the sync state. If either PSync or SFC fails to verify, the ONU switches to the search state.

[0030] If the ONU enters the synchronization state and both PSync and SFC are successfully verified, the ONU remains in the synchronization state. If either PSync or SFC fails to verify, the ONU switches to the re-sync state.

[0031] If the ONU enters the resynchronization state and both PSync and SFC are successfully verified, the ONU switches to the synchronization state. However, for M-1 consecutive PHY frames, if either PSync or SFC fails to verify, the ONU confirms the downlink synchronization loss, discards the local SFC backup, and switches to the search state. The value of the parameter M can be 3.

[0032] The existing downlink synchronization methods include downlink synchronization detection, downlink synchronization missed detection, and downlink synchronization false detection. Downlink synchronization detection is performed after the ONU is initialized and PSync and SFC are successfully verified, and then the system switches from the search state to the pre-synchronization state and the synchronization state in sequence.

[0033] The method used to determine the detection probability of PSync is as follows: if the number of bits in the PSync codeword received by the ONU that do not match the PSync stored in its own memory is less than or equal to K, then it is determined that PSync has been correctly received. Here, PSync is a specific codeword with a length of N bits.

[0034] Assuming the bit error rate is Pe, then the detection probability of PSync, i.e. the probability of correct reception, is P. sync_true The expression is

[0035]

[0036] In a PON system, downlink synchronization detection must consider both PSync and SFC. The SFC field has a total length of 64 bits and uses HEC checksum, which can correct 2-bit errors. Therefore, the correct reception probability P of the SFC codeword is... SFC_true This is a special case where the detection probability of PSync is N=64 and K=2. Furthermore, when the PON system transitions from the search state to the pre-synchronization state in the downlink, a precise match of PSync is required, meaning its detection probability P... sync_true This is a special case when K=0. Therefore, the detection probability in the pre-synchronization state is...

[0037] P true_PON_presync =P sync_true(K＝0) *P sync_true(N＝64,K＝2) (2)

[0038] Furthermore, when successfully switching from the pre-synchronization state to the synchronization state, it is required that PSync and SFC can be correctly received simultaneously in the next frame after entering the pre-synchronization state. Therefore, the detection probability in the synchronization state is...

[0039] P true_PON_sync =P true_PON_presync *P sync_true *P sync_true(N＝64,K＝2) (3)

[0040] Based on the above formulas (2) and (3), in the 50GPON system, assuming N=64, K=2, Pe=0.02, as shown in Table 1, the detection probability of the downlink pre-synchronization state is 0.2370, and the detection probability of the synchronization state is 0.1766, which are relatively low.

[0041] Table 1

[0042] K Pre-synchronization state detection probability Synchronization state detection probability 0 0.236954529 0.056147449 1 0.236954529 0.129482892 2 0.236954529 0.176627105 3 0.236954529 0.196511059 4 0.236954529 0.202699433 5 0.236954529 0.204214953

[0043] Downlink synchronization failure indicates that after the PON system enters the synchronization state, it incorrectly enters the resynchronization state or search state because PSync and / or SFC are not correctly detected.

[0044] Similarly, if the number of bits in the PSync codeword received by the ONU that do not match the PSync stored in its own memory is less than or equal to K, then it is determined that the PSync has been received correctly.

[0045] Assuming the bit error rate is Pe, the probability of correct reception in synchronized mode is P. sync_true Then the false negative probability P miss_sync The expression is

[0046]

[0047] Because downlink synchronization missed detection in a PON system needs to consider not only PSync but also SFC, and the correct reception probability P of the SFC codeword... SFC_true This is a special case where the detection probability of PSync is N=64 and K=2. Therefore, the probability P of PSync and SFC simultaneously detecting correctly in a single run is... true for

[0048] P true =P sync_true *P SFC_true =P sync_true *P sync_true(N＝64，K＝2) (5)

[0049] The probability of a single PSync or SFC missed detection is

[0050] P miss =1-P true (6)

[0051] The probability of M consecutive PSync or SFC missed detections, i.e., the downlink synchronization missed detection probability P. miss_PON_sync for

[0052] P miss_PON_sync =P miss M (7)

[0053] Based on formula (7), in a 50GPON system, assuming N=64, K=2, M=3, Pe=0.01, as shown in Table 2, the downlink synchronization missed detection probability is 1.43E-4, and the average missed detection occurs once every 2.77E-8 years.

[0054] Table 2

[0055] K Synchronous missed detection probability Average time to missed detection (unit: year) 2 1.43E-04 2.77E-08 3 2.80E-05 1.42E-07 4 1.96E-05 2.02E-07 5 1.87E-05 2.12E-07 6 1.86E-05 2.13E-07 7 1.86E-05 2.13E-07 8 1.86E-05 2.13E-07 9 1.86E-05 2.13E-07 10 1.86E-05 2.13E-07

[0056] When N=64, K=2, M=3, and Pe=0.02, as shown in Table 3, the downlink synchronization missed detection probability is 1.65E-2, and the average missed detection occurs once every 2.4E-10 years.

[0057] Table 3

[0058]

[0059]

[0060] As can be seen from Tables 2 and 3, even when K is increased to 10, the false negative probability of 50G PON is still very high, and when K is greater than 6, the false negative probability basically no longer decreases.

[0061] Downlink synchronization false detection refers to the probability that, after ONU initialization, in the search state, PSync and SFC are incorrectly detected, thus switching to the pre-synchronization state and the synchronization state in sequence.

[0062] Similar to the above method, PSync is a specific codeword with a length of N bits. When the number of bits that do not match the PSync codeword received by the ONU with the PSync codeword stored in the ONU is less than or equal to K, it is considered that the PSync has been received correctly.

[0063] Assuming the bit error rate is Pe, then the probability of a false detection is P. false_sync for

[0064]

[0065] In a PON system, both downlink PSync and SFC require false detections to result in erroneous synchronization. Switching from the search state to the pre-synchronization state requires precise PSync matching (K=0). However, a downlink frame has L bits in length, and during the switch to the pre-synchronization state, PSync and SFC can appear at any position within those L bits. Therefore, the downlink synchronization false detection probabilities in the pre-synchronization and synchronization states are respectively...

[0066] P false_PON_presync =(LN-64)*P false_sync(K＝0) *P false_SFC (9)

[0067] P false_PON_sync =P false_PON_presync *P false_sync *P false_SFC (10)

[0068] Based on formula (10), in a 50GPON system, assuming N=64, K=2, M=3, Pe=0.01, as shown in Table 4, the downlink synchronization false detection probability is 4.84E-61, with an average of one false detection every 1.32E42 years.

[0069] Table 4

[0070]

[0071]

[0072] When N=64, K=2, M=3, and Pe=0.02, as shown in Table 5, the downlink synchronization false detection probability is 4.84E-61, with an average of one false detection every 1.32E42 years.

[0073] Table 5

[0074] K Synchronous false detection probability Average false positive time (in years) 2 4.84E-61 1.32E+42 3 1.02E-59 6.26E+40 4 1.58E-58 4.03E+39 5 1.93E-57 3.30E+38 6 1.94E-56 3.29E+37 7 1.64E-55 3.89E+36 8 1.19E-54 5.34E+35 9 7.60E-54 8.38E+34 10 4.28E-53 1.49E+34

[0075] As can be seen from the table above, the false detection probability increases with the increase of the K value, but even if the K value increases to 10, the false detection probability of the 50G PON system is still very small.

[0076] Based on the above analysis of detection probability, missed detection probability, and false detection probability, it can be seen that for a 50G PON system, under the condition of a 0.02 bit error rate before correction, the probability of successful downlink synchronization detection is 17.66%, and an erroneous downlink synchronization loss occurs on average once every 2.4E-10 years, that is, an erroneous synchronization loss occurs on average every less than 8ms. The downlink synchronization detection probability is very low, while the missed detection probability is very high, which will affect the normal operation of the PON system.

[0077] To address the aforementioned shortcomings, this application proposes a state switching method, such as... Figure 4 As shown, the method includes:

[0078] S401, The optical network unit verifies the received PSync field.

[0079] The aforementioned optical network unit can be understood as a receiver. When it receives a PSync, it can verify the PSync.

[0080] For example, the optical network unit can verify the PSync field by determining whether the number of error bits in the received PSync field is less than or equal to K, where K is an integer greater than or equal to 0.

[0081] S402. The optical network unit switches its current state based on the verification results.

[0082] For example, when the optical network unit determines that the number of error bits in the received PSync field is less than or equal to K, it determines that the verification result is that the PSync field verification is successful; when the optical network unit determines that the number of error bits in the received PSync field is greater than K, it determines that the verification result is that the PSync field verification is unsuccessful.

[0083] Then, the optical network unit switches its current state based on the acquired verification results.

[0084] Optionally, the current state can be any one of the following: search state, pre-synchronization state, synchronization state, or resynchronization state.

[0085] Since the optical network unit does not verify the received SFC, but only switches between different states based on the verification result of PSync, and allows PSync to have K-bit errors, it can effectively improve the probability of downlink synchronization detection and reduce the probability of downlink synchronization missed detection, so as to ensure the normal operation of the PON system.

[0086] The above verification results are divided into two categories: verification passed and verification failed. Figure 5 As shown, when the verification result is successful, meaning the number of error bits received by the optical network unit (ONU) in PSync is less than or equal to K, the ONU can switch its current state based on the verification result as follows:

[0087] In one example, if the current state is the search state, the optical network unit will switch the search state to the pre-synchronization state;

[0088] In one example, if the current state is pre-synchronization, the optical network unit will switch the pre-synchronization state to the synchronization state;

[0089] In one example, if the current state is a synchronization state, the optical network unit will switch the synchronization state to a synchronization state;

[0090] In one example, if the current state is resynchronization, the optical network unit will switch from resynchronization to synchronization.

[0091] When the verification result is "verification failed," meaning the number of error bits in the PSync received by the optical network unit is greater than K, the optical network unit can switch its current state based on the verification result as follows:

[0092] In one example, if the current state is pre-synchronization, the optical network unit will switch the pre-synchronization state to the search state.

[0093] In one example, if the current state is a synchronization state, the optical network unit will switch the synchronization state to a resynchronization state.

[0094] In one example, if the current state is a resynchronization state, the optical network unit will switch the resynchronization state to a resynchronization state.

[0095] In one example, if the current state is resynchronization and the M-1 consecutive verification results are unsuccessful, the optical network unit will switch the resynchronization state to the search state, where M is an integer greater than 1.

[0096] Assuming the bit error rate is Pe, the probability of correctly receiving PSync in the pre-synchronization state and the synchronization state is determined based on the above method. That is, the detection probability of PSync is respectively...

[0097]

[0098] P' true_PON_presync =P sync_true (12)

[0099] P' true_PON_sync =P' true_PON_presync *P sync_true=P sync_true 2 (13)

[0100] Based on the above formulas (12) and (13), in the 50GPON system, assuming N=64, M=3, Pe=0.01, when K=5, as shown in Table 6, the detection probabilities in the pre-synchronization state and the synchronization state are 0.99995 and 0.99991, respectively.

[0101] Table 6

[0102]

[0103]

[0104] Assuming N=64, M=3, Pe=0.02, when K=7, as shown in Table 7, the detection probabilities in the pre-synchronization state and the synchronization state are 0.99996 and 0.99992, respectively.

[0105] Table 7

[0106] K Pre-synchronization state detection probability Synchronization state detection probability 0 0.274453545 0.075324748 1 0.632923481 0.400592132 2 0.86336844 0.745405062 3 0.960562912 0.922681108 4 0.990812212 0.98170884 5 0.998220204 0.996443576 6 0.999706842 0.999413769 7 0.999958227 0.999916455 8 0.99999478 0.99998956 9 0.999999422 0.999998843 10 0.999999943 0.999999885

[0107] It can be seen that during state transition, only the PSync verification is checked, without verifying the SFC. Furthermore, when transitioning from the search state to the pre-synchronization state, there is no need to perform an exact match on PSync, allowing PSync to have less than or equal to K error bits. Therefore, the probability of synchronization detection can be improved.

[0108] Similarly, based on the above verification method, the determined downlink synchronization missed detection probability is:

[0109] P' miss_PON_sync =P' miss M =(1-P') true ) M =(1-P sync_true ) M (14)

[0110] Based on the above formula (14), in the 50GPON system, assuming N=64, M=3, Pe=0.01, as shown in Table 8, when K is greater than or equal to 5, the acceptable probability of missed detection can be obtained, and the average missed detection time is 41.7 years.

[0111] Table 8

[0112] K Synchronous missed detection probability Average time to missed detection (unit: year) 2 1.86E-05 2.13E-07 3 6.13E-08 6.46E-05 4 1.02E-10 3.89E-02 5 9.50E-14 4.17E+01 6 5.37E-17 7.39E+04 7 1.94E-20 2.04E+08 8 4.72E-24 8.40E+11 9 7.94E-28 4.99E+15 10 9.53E-32 4.16E+19

[0113] Assuming N=64, M=3, Pe=0.02, as shown in Table 9, when K is greater than or equal to 7, an acceptable false negative probability can be obtained, with an average false negative time of 54.4 years.

[0114] Table 9

[0115]

[0116]

[0117] Since only PSync is verified when switching from synchronization state to resynchronization state or search state, and SFC is not verified, the problem of high downlink synchronization missed detection probability caused by high SFC missed detection probability can be avoided, thereby reducing the downlink synchronization missed detection probability.

[0118] Furthermore, since the downlink synchronization detection criteria have changed, allowing PSync to have K-bit errors and no longer detecting SFC, the downlink synchronization false detection probabilities in the pre-synchronization state and the synchronization state are respectively...

[0119] P' false_PON_presync =(LN)*P false_sync (15)

[0120] P' false_PON_sync =P' false_PON_presync *P false_sync (16)

[0121] Based on formula (16), in a 50GPON system, assuming N=64, M=3, Pe=0.01, as shown in Table 9, when K equals 5, the downlink synchronization false detection probability is 2.03E-25, and the average annual false detection occurs once every 3.14E6 years.

[0122] Table 9

[0123] K Synchronous false detection probability Average false positive time (in years) 2 1.27E-32 5.01E+13 3 5.62E-30 1.13E+11 4 1.36E-27 4.70E+08 5 2.03E-25 3.14E+06 6 2.04E-23 3.13E+04 7 1.46E-21 4.37E+02 8 7.74E-20 8.24E+00 9 3.14E-18 2.03E-01 10 9.97E-17 6.39E-03

[0124] When N=64, K=2, M=3, Pe=0.02, as shown in Table 10, when K equals 7, the downlink synchronization false detection probability is 1.46E-21, with an average of one false detection every 437 years.

[0125] Table 10

[0126] K Synchronous false detection probability Average false positive time (in years) 2 1.27E-32 5.01E+13 3 5.62E-30 1.13E+11 4 1.36E-27 4.70E+08 5 2.03E-25 3.14E+06 6 2.04E-23 3.13E+04 7 1.46E-21 4.37E+02 8 7.74E-20 8.24E+00 9 3.14E-18 2.03E-01 10 9.97E-17 6.39E-03

[0127] Figure 6 One embodiment provides a state switching device, such as Figure 6 As shown, the device includes: a verification module 601 and a switching module 602;

[0128] The verification module is used to verify the received PSync field.

[0129] The switching module is used to switch the current state based on the verification results.

[0130] The current state can be any one of the following: search state, pre-synchronization state, synchronization state, or resynchronization state.

[0131] Furthermore, the aforementioned state switching device may also include: a determination module;

[0132] The determination module is used to determine whether the PSync verification is successful when the number of error bits received by the PSync is less than or equal to K.

[0133] Alternatively, if the number of error bits received by PSync is greater than K, the PSync verification is determined to have failed, where K is an integer greater than or equal to 0.

[0134] In one example, when the verification result is successful, a switching module is used to switch the search state to the pre-synchronization state when the current state is search state;

[0135] Alternatively, when the current state is pre-synchronization, switch the pre-synchronization state to the synchronization state;

[0136] Alternatively, when the current state is a synchronized state, switch the synchronized state to a synchronized state;

[0137] Alternatively, when the current state is resynchronization, switch the resynchronization state to synchronization.

[0138] In one example, when the verification result is that the verification failed, a switching module is used to switch the pre-synchronization state to the search state when the current state is pre-synchronization state;

[0139] Alternatively, when the current state is synchronized, switch the synchronized state to the resynchronized state;

[0140] Alternatively, when the current state is a resynchronization state, switch the resynchronization state to a resynchronization state;

[0141] Alternatively, when the current state is resynchronization and the verification results are M-1 consecutive failures, the resynchronization state is switched to the search state, where M is an integer greater than 1.

[0142] Furthermore, the value of M can be 3.

[0143] In one example, when the system's pre-correction bit error rate is 0.01, the value of K ranges from 5 to 8, or when the system's pre-correction bit error rate is 0.02, the value of K ranges from 7 to 8.

[0144] In one example, the number of bits in the PSync field is N, and N has a value of 64.

[0145] Figure 7 A schematic diagram of the structure of a device provided in one embodiment, such as Figure 7 As shown, the device includes a processor 701 and a memory 702; the number of processors 701 in the device can be one or more. Figure 7 Taking a processor 701 as an example; the processor 701 and memory 702 in the device can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0146] The memory 702, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, as described in this application. Figure 1 The program instructions / modules corresponding to the network access method in the embodiments (e.g., Figure 6 The processor 701 implements the above-mentioned state switching method by running software programs, instructions, and modules stored in the memory 702 (verification module 601 and switching module 602).

[0147] The memory 702 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created based on the use of the device. Furthermore, the memory 702 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device.

[0148] This application also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a network access method, the method comprising:

[0149] The optical network unit verifies the received PSync field;

[0150] The optical network unit switches its current state based on the verification results.

[0151] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0152] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0153] Embodiments of this application can be implemented by executing computer program instructions through a data processor of an information transmission device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0154] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored in memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Multifunction Discs, DVDs, or CDs), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, processors with general-purpose computer, special-purpose computer, microprocessor, digital signal processor (DSP), application-specific integrated circuit (ASIC), programmable logic device (FPGA) core processor architecture.

[0155] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of the invention. Therefore, the proper scope of the invention will be determined by the claims.

Claims

1. A state switching method, characterized in that, include: The optical network unit verifies the received physical synchronization sequence (PSync) field; The optical network unit switches its current state based on the verification result. The current state can be any one of the following: search state, pre-synchronization state, synchronization state, or resynchronization state. The optical network determines the verification result as follows: when the optical network unit determines that the number of error bits in the received PSync field is less than or equal to K, the PSync field verification is deemed successful; when the optical network unit determines that the number of error bits in the received PSync field is greater than K, the PSync field verification is deemed unsuccessful, where K is an integer greater than or equal to 0; when the system pre-correction bit error rate is 0.01, the value range of K is 5 ≤ ​​K ≤ 8. The optical network unit switches its current state based on the verification result, including: when the current state is a search state, if the verification result is successful, the optical network unit switches from the search state to a pre-synchronization state; when the current state is a pre-synchronization state, if the verification result is successful, the optical network unit switches from the pre-synchronization state to a synchronization state; when the current state is a synchronization state, if the verification result is successful, the optical network unit remains in the synchronization state; when the current state is a resynchronization state, if the verification result is successful, the optical network unit switches from the resynchronization state to the synchronization state.

2. The method according to claim 1, characterized in that, The optical network unit switches its current state based on the verification results, including: When the current state is a pre-synchronization state and the verification result is that the verification failed, the optical network unit switches the pre-synchronization state to the search state; Alternatively, when the current state is a synchronization state and the verification result is that the verification failed, the optical network unit switches the synchronization state to a resynchronization state; Alternatively, when the current state is a resynchronization state and the verification result is that the verification failed, the optical network unit will switch the resynchronization state to the resynchronization state. Alternatively, when the current state is a resynchronization state and M-1 consecutive verification results are unsuccessful, the optical network unit switches the resynchronization state to a search state, where M is an integer greater than 1.

3. The method according to claim 1 or 2, characterized in that, When the system's pre-correction bit error rate is 0.02, the value range of K is 7≤K≤8.

4. The method according to claim 3, characterized in that, The PSync field has N bits, where N is 64 and M is 3.

5. A state switching device, characterized in that, include: The verification module is used to verify the received physical synchronization sequence PSync field; The switching module is used to switch the current state according to the verification result. The current state is any one of the following: search state, pre-synchronization state, synchronization state, and resynchronization state. The verification module determines the verification result by: determining that the PSync field verification is successful when the number of error bits in the received PSync field is less than or equal to K; and determining that the PSync field verification is unsuccessful when the number of error bits in the received PSync field is greater than K, where K is an integer greater than or equal to 0; and when the system pre-correction error rate is 0.01, the value range of K is 5≤K≤8. The optical network unit switches its current state based on the verification result, including: when the current state is a search state and the verification result is successful, the optical network unit switches the search state to a pre-synchronization state; when the current state is a pre-synchronization state and the verification result is successful, the optical network unit switches the pre-synchronization state to a synchronization state; when the current state is a synchronization state and the verification result is successful, the optical network unit switches the synchronization state to a synchronization state; when the current state is a resynchronization state and the verification result is successful, the optical network unit switches the resynchronization state to a synchronization state.

6. A communication device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the state switching method as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the state switching method according to any one of claims 1-4.

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