Multi-layer feature filling

Abstract

The present invention describes a method and apparatus for filling a semiconductor substrate structure with a conductive material. The method includes depositing multiple layers of a bulk metal film in the structure, where one or more deposition conditions are changed when transitioning from layer to layer. The method results in high fill quality, high throughput, low precursor consumption, and low roughness. A multi-station chamber for performing the method is also provided.

Description

[0001] Incorporation by reference

[0002] The PCT application form is filed simultaneously with this specification as part of this application. Each application for which this application claims the benefit or priority thereof, as identified in the PCT application form filed simultaneously, is incorporated herein by reference in its entirety and for all purposes. Background of the Invention

[0003] The deposition of tungsten-containing and other metal-containing materials is an integral part of many semiconductor manufacturing processes. These materials can be used for horizontal interconnects, vias between adjacent metal layers, and contacts between metal layers and devices. However, as devices are scaled down and more complex patterning schemes are used in the industry, the deposition of tungsten thin films has become a challenge. Deposition in complex high aspect ratio structures (such as 3D NAND structures) is particularly challenging.

[0004] The background description provided herein is for the purpose of generally presenting the background of the disclosure. The work of the currently named inventors is neither expressly nor impliedly admitted to be prior art to the disclosure to the extent that it is described in this background art section and in the aspects of the specification that could not be determined to be prior art at the time of filing the application. Summary of the Invention

[0005] One aspect of the present disclosure relates to a method of fabricating a 3-D structure of a semiconductor substrate made of a partially filled conductive material, the 3-D structure including sidewalls with a plurality of openings leading to a plurality of features having a plurality of internal regions that are fluidly accessible through the openings, the method comprising: depositing a first bulk layer of the conductive material within the 3-D structure such that the first bulk layer partially fills the plurality of internal regions of the 3-D structure; depositing a second bulk layer of the conductive material within the 3-D structure on top of the first bulk layer such that the second bulk layer at least partially fills the plurality of internal regions of the 3-D structure; and depositing a third bulk layer of the conductive material within the 3-D structure on the sidewalls, wherein the first bulk layer, the second bulk layer, and the third bulk layer are deposited under different conditions. According to various embodiments, the method may include one or more of the following features. In the method, the conductive material is tungsten. In the method, the first bulk layer and the second bulk layer are deposited by an atomic layer deposition (ALD) process. In the method, the third bulk layer is deposited by an ALD process. In the method, the third bulk layer is deposited by a chemical vapor deposition (CVD) process. In the method, each of the ALD processes includes consecutive pulses of a metal precursor and a reducing agent. In the method, one or more of the flow rate and the pulse time of the pulses of the metal precursor are greater during the deposition of the first bulk layer. The method further includes depositing a fourth bulk layer of the conductive material on the third bulk layer. In the method, the conductive material is molybdenum, ruthenium, or cobalt. The method further includes exposing the substrate to a nitrogen (N2) soak between the depositions of two of the bulk layers.

[0006] Another aspect of the present disclosure also relates to a method that includes: providing a substrate to a multi-station deposition chamber; depositing a first metal bulk layer on the substrate at a first station of the multi-station deposition chamber under a first set of conditions; transferring the substrate to a second station of the multi-station deposition chamber and depositing a second metal bulk layer on the first bulk layer under a second set of conditions; and transferring the substrate to a third station of the multi-station deposition chamber and depositing a third metal bulk layer on the second bulk layer under a third set of conditions, wherein transitioning from the first set of conditions to the second set of conditions includes one or more of the following: changing the pulse time of the metal precursor, changing the metal precursor flow rate, and changing the susceptor temperature, and transitioning from the second set of conditions to the third set of conditions includes one or more of the following: changing the pulse time of the metal precursor, changing the metal precursor flow rate, and changing the susceptor temperature. Changing process conditions (e.g., susceptor temperature) involves setting different conditions at different stations; e.g., a first susceptor temperature at the first station and a second susceptor temperature at the second station.

[0007] According to various embodiments, the method may include one or more of the following features. In the method, the metal is one of tungsten, molybdenum, cobalt, and ruthenium. In the method, transitioning from the first set of conditions to the second set of conditions includes increasing the flow rate of the metal precursor or increasing the pulse time of the metal precursor. In the method, transitioning from the first set of conditions to the second set of conditions includes increasing the sweep time. In the method, transitioning from the first set of conditions to the second set of conditions includes decreasing the flow rate of the metal precursor or decreasing the pulse time of the metal precursor.

[0008] Another aspect of the present disclosure relates to a multi-station chamber, comprising: a first station, comprising a first nozzle and a first pedestal; a second station, comprising a second nozzle and a second pedestal; a first station, comprising a third nozzle and a third pedestal; and a controller, comprising machine-readable instructions to: deposit a first metal bulk layer on the substrate in the first station of the multi-station deposition chamber under a first set of conditions; transfer the substrate to the second station of the multi-station deposition chamber, and deposit a second metal bulk layer on the first bulk layer under a second set of conditions; transfer the substrate to the third station of the multi-station deposition chamber, and deposit a third metal bulk layer on the second bulk layer under a third set of conditions, wherein the transition from the first set of conditions to the second set of conditions includes one or more of the following items: changing the pulse time of the metal precursor, changing the flow rate of the metal precursor, and changing the pedestal temperature, and the transition from the second set of conditions to the third set of conditions includes one or more of the following items: changing the pulse time of the metal precursor, changing the flow rate of the metal precursor, and changing the pedestal temperature.

[0009] These and other aspects are further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A cross section of a vertical feature in a substrate that may be designed to be filled with tungsten material or other conductive material is shown according to various embodiments.

[0011] Figure 1B Shown with Figure 1A An example of a similar feature, but this example has a concave profile due to the presence of an underlying layer lining the bottom, sidewalls and opening of the feature.

[0012] Figure 1C A top-down view of a horizontal feature is shown according to various embodiments, the horizontal feature exhibiting a constriction approximately in the middle of its sidewalls, which may be filled with tungsten material or other conductive material. In some embodiments, such a horizontal feature may be a feature known as a word line feature in a vertically integrated memory structure.

[0013] Figure 1D shows a side view with the same horizontal features as Figure 1C but here shows an opening leading to a vertical structure, thus forming part of the vertical structure.

[0014] Figure 2A Presents a cross-sectional side view of a 3D vertical memory NAND (VNAND) structure (formed on a semiconductor substrate), the structure having VNAND stacks (left and right), a central vertical structure, and multiple stacked horizontal features having openings on opposite sidewalls of the central vertical structure.

[0015] Figure 2B Presents Figure 2A a top-down cross-sectional view of the VNAND structure shown in the side view of Figure 2A wherein the cross-sectional view is obtained by taking a horizontal section along the dashed horizontal line indicated in

[0016] Figure 3A Shows a vertical cross-section (cut) of a VNAND structure similar to the VNAND structure shown in Figure 2A but in Figure 3A focuses on a single pair of word lines and additionally schematically shows a tungsten filling process that results in voids being formed in the word lines.

[0017] Figure 3B Shows a horizontal cross-section (cut) of a VNAND structure similar to the VNAND structure shown in Figure 2A and also schematically shows Figure 3A the presence of voids in

[0018] Figure 3C Shows a single word line viewed from a top cross-section and shows how the normally conformal deposition of tungsten material begins to pinch off the interior of the shown word line features due to the presence of the pillars shown in the figure.

[0019] Figure 4 Shows a process flow diagram illustrating certain operations in a method for filling a 3D NAND structure with tungsten or other conductive material, according to various embodiments.

[0020] Figure 5 Provides a schematic diagram of a single word line of a 3D NAND structure, which includes multiple body layers of conductive material.

[0021] Figure 6A Shows an overall integration scheme for forming a 3D NAND structure, which includes a multi-layer body deposition process, according to various embodiments.

[0022] Figure 6BShows a portion of an example of a fabricated 3D NAND structure that includes conductive word lines, oxide layers, and vias.

[0023] Figure 7 Is a block diagram of a processing system suitable for performing a deposition process according to embodiments described herein. Detailed Description

[0024] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known processing operations have not been described in detail to avoid unnecessarily obscuring the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that it is not intended to limit the disclosed embodiments.

[0025] Metal filling of features is used in the fabrication of semiconductor devices to form electrical contacts. In some deposition processes, a metal nucleation layer is first deposited into the features. Typically, the nucleation layer is a thin conformal layer that is used to facilitate the subsequent formation of the bulk material thereon. The nucleation layer may be deposited to conformally coat the feature surfaces (sidewalls and bottom if present). Conformality to these surfaces may be critical to support high-quality deposition. The nucleation layer is typically deposited using atomic layer deposition (ALD) methods.

[0026] In ALD technology, pulses of reactants are sequentially introduced into the reaction chamber. These pulses are typically purged from the reaction chamber by pulses of a purge gas between the reactants. The first reactant may be adsorbed onto the substrate and may be used to react with the next reactant. The process is repeated in a periodic manner until the desired thickness is achieved. Depositing the nucleation layer using consecutive pulses of reactants may also be referred to as pulsed nucleation layer (PNL) technology. In the context of the disclosed embodiments, chemical vapor deposition (CVD) encompasses processes in which reactants are introduced together into a reactor for gas-phase or surface reactions. PNL and ALD processes are different from CVD processes and vice versa.

[0027] After depositing the metal nucleation layer, typically by CVD or ALD processes, the bulk metal may be deposited. The bulk metal film is different from the metal nucleation layer. As used herein, bulk metal refers to the metal used to fill most or all of the feature (e.g., at least about 50% of the feature). Different from the nucleation layer, which is a thin conformal film that is used to facilitate the subsequent formation of the bulk material, the bulk metal is used to carry current. Compared to the nucleation film, it may be characterized by a larger grain size and lower resistivity. In various embodiments, the bulk material is deposited to a thickness of at least 50 angstroms thickness.

[0028] As devices are scaled down to smaller technology nodes and use more complex patterning structures, tungsten filling faces various challenges. For example, conventional deposition of tungsten involves using the fluorine-containing precursor tungsten hexafluoride (WF6). However, the use of WF6 results in some degree of fluorine incorporation into the deposited tungsten film. The presence of fluorine can cause electromigration and / or fluorine diffusion into adjacent components and damage the contacts, thereby degrading the performance of the device. One challenge is to reduce the fluorine content in the deposited tungsten film. The effects of certain fluorine concentrations increase as the feature size decreases. This is because thinner films are deposited in smaller features, and the fluorine in the deposited tungsten film is more likely to diffuse through the thinner film.

[0029] Another challenge is to achieve uniform step coverage, especially when depositing into high aspect ratio and complex structures (such as 3D NAND structures). This is because it may be difficult to achieve uniform exposure to the deposition gas, especially when some parts of the structure are more accessible to the deposition gas. Deposition in small features or features with high aspect ratios can result in the formation of voids within the deposited tungsten. A void is simply an area within a structure or feature that will not be filled after the surrounding area is filled. Typically, void formation is due to a disproportionate buildup of deposition material near the feature entrance, causing the entrance to be blocked and pinching off the internal space of the feature, thus preventing further deposition within the internal volume space. Once blocked or pinched off, there is no entry path for the reactive deposition precursor material to enter the internal space, preventing any further deposition from occurring within these areas.

[0030] Methods, apparatuses, and systems for filling semiconductor substrate structures with a conductive material are described herein. One or more of the following advantages can be achieved by implementations of the methods described herein. In some embodiments, good (i.e., low void) filling is achieved in challenging fill structures. In the same or other embodiments, precursor consumption is controlled and can be balanced across a multi-layer process to minimize total consumption. In the same or other embodiments, yield is increased.

[0031] As described above, significant issues related to filling semiconductor substrate structures and features with tungsten material are the formation of seams and voids in the tungsten filling process. In particular, structures having features (which have one or more narrow and / or concave openings or constrictions or simply have a relatively high aspect ratio) can be problematic. Figure 1A A cross-section of a vertical feature 101 in a substrate 103 that can be filled with tungsten material is shown. Such a vertical feature has a feature opening 105 and sidewalls 107. The vertical feature 101 can have an aspect ratio of at least about 2:1, or at least about 4:1, or at least about 6:1, or at least about 10:1, or at least about 20:1, or even higher. The diameter of the feature opening 105 can be between about 10 nanometers and 500 nanometers, for example, between about 25 and 300 nanometers.

[0032] Similarly, Figure 1B An example of a similar feature 101 is shown, but due to the presence of a lower layer 113 lining the bottom, sidewalls, and opening of the feature 101, it has a concave profile. The concave profile exhibits a narrowing of the cross-section at some position between the feature opening and the bottom or closed end of the feature, thus showing a "bottleneck" cross-section in the profile. In some cases, the concave profile may taper inwards from the feature opening, or may include a protrusion just at the feature opening itself. Figure 1B An example of the latter is again shown, where the narrowing is due to the presence of a lower layer 113 that is thicker near the feature opening than on the bottom of the feature or further below the feature sidewall 107, thus forming a protrusion 115. The lower layer 113 can be, for example, a diffusion barrier layer, an adhesion layer, a nucleation layer, or any combination of the foregoing, or any other potentially useful or advantageous material layer.

[0033] In some embodiments, one or more constrictions in the sidewalls of the feature may make it difficult to achieve uniform tungsten filling. Figure 1C A top view of an exemplary horizontal feature 121 is shown, which generally presents a constriction 109 that restricts access to the internal region 110 in the middle of its sidewall 107. In some embodiments, such a horizontal feature can be a feature referred to as a "word line" in a vertical integrated memory structure, such as a 3-D vertical NAND (VNAND) structure described in more detail below. Figure 1D A side view of the same horizontal feature 121 is shown, which has an opening 105 leading to a vertical structure 122, thus forming part of the vertical structure 122. In some embodiments, and for certain deposition chemistries and processes, achieving uniform tungsten filling in such a structure can be challenging because a sufficient amount of each deposition precursor must travel vertically down to the bottom of the structure 122 and then horizontally across the horizontal feature 121, especially across the constricted region 109. Again, note that Figure 1C A top view representation of the horizontal feature 121 and the constriction 109 is shown, while Figure 1D A side view of it is shown. Thus, from these figures, it is apparent that in this embodiment, the constriction 109 extends horizontally and vertically inwards from the sidewall 107 of the feature 121. However, it should be understood that in other embodiments, the constriction within the feature may only be present in one of the two cross-sectional dimensions, and any type of constriction (whether one-dimensional or two-dimensional) may make uniform tungsten filling more challenging.

[0034] The methods, apparatuses, and systems described herein can be used to fill vertical features (e.g., vias) as well as horizontal features (e.g., horizontal word lines within a vertical NAND (VNAND) structure), which will be described in more detail below. The substrate having the structure or feature to be filled can be a 200 mm, 300 mm, or 450 mm semiconductor wafer, or a wafer having a diameter between about 200 mm and 300 mm, or between about 300 mm and 450 mm, or greater than about 450 mm, or a wafer of any suitable size. Additionally, the methods, apparatuses, and systems can be used to fill features with tungsten on other types of substrates, including panels, display substrates, etc. Although the following description primarily relates to tungsten, these methods and apparatuses can also be used to fill any metal that can be deposited using CVD and ALD techniques, including molybdenum, ruthenium, and cobalt.

[0035] In some embodiments, the structure to be filled on a semiconductor substrate can be a vertical structure having a plurality of horizontal features, the horizontal features having openings in the sidewalls of the vertical structure that lead to a plurality of internal spaces (of the horizontal features), which can be fluidically accessible from the main vertical structure through the feature openings.

[0036] For example, Figure 2A A cross-sectional side view of a 3D vertical memory NAND (VNAND) structure 200 (formed on a semiconductor substrate 201) is presented, the structure 200 having VNAND stacks (left 205 and right 206), a central vertical structure 210, and a plurality of horizontal stacked features 220 having openings 230 in opposite sidewalls 240 of the central vertical structure 210. Note that Figure 2A Two "stacks" of the illustrated VNAND structure are shown, which together form a "trench-like" central vertical structure 210. However, in some embodiments, there may be more than two "stacks" arranged in sequence and extending spatially parallel to each other, with the gap between each pair of adjacent "stacks" forming the central vertical structure 210, as Figure 2A is clearly shown therein. In this embodiment, the horizontal features 220 are actually 3D memory "word lines", which can be fluidically accessed from the vertical structure 210 through the openings 230. Although not explicitly indicated in the figure, in Figure 2AThe horizontal feature 220 that exists in both of the two VNAND stacks 205, 206 shown (i.e., the left VNAND stack and the right VNAND stack 206) can also enter from the other side of the VNAND stack (located at the leftmost and rightmost respectively) through similar vertical structures formed by additional VNAND stacks (the leftmost and rightmost respectively, not shown). In other words, each VNAND stack 205, 206 contains stacked word lines that can be fluidly accessed from both sides of the VNAND stack through the central vertical structure 210. In Figure 2A In the specific example schematically shown in, each VNAND stack contains 6 pairs of stacked word lines. However, in other embodiments, the 3-D VNAND memory layout can contain 8 pairs, or 16 pairs, or 32 pairs or 64 pairs of vertically stacked word lines, corresponding to 16, or 32, or 64 or 128 stacked horizontal word line features 220 with openings 230. Note that the word lines in the VNAND stack are typically formed by depositing alternating stacked silicon oxide layers and silicon nitride layers and then using a process to remove the nitride layers, leaving gaps between the stacked oxide layers.

[0037] These gaps are word line features to be filled with tungsten (also simply referred to as word lines in the following description). In principle, any number of word lines can be vertically stacked in such a VNAND structure as long as there are technologies enabling their formation and technologies that can successfully (substantially) achieve void-free filling of the vertical features. Thus, for example, the VNAND stack can include between 2 and 256 horizontal word line features, or between 8 and 128 horizontal word line features, or between 16 and 64 horizontal word line features, and so on (the listed ranges are understood to include the endpoints). Figure 2B Shows a top cross-sectional view of the same VNAND structure 200 as shown in the side view of Figure 2A where the cross-section is taken through the horizontal portion 260 shown in Figure 2A (i.e., shown by the horizontal dashed line). Figure 2B The cross-sectional view of shows Figure 2A several rows of pillars 250 shown in, which extend vertically from the bottom of the semiconductor substrate 201 to the top of the VNAND stack 200. In some embodiments, these pillars 250 are formed of polysilicon material and are important to the VNAND structure 200 in terms of structure and function. In some applications, such polysilicon pillars can be used as gate electrodes for stacked memory cells formed by word lines. Figure 2B The top view of shows the constriction of the pillar 250 into the word line 220 in the opening 230, i.e., the fluid accessibility of the word line 220 from the vertical structure 210 via the opening 230 (as Figure 2Bis suppressed by the struts 250 (as indicated by the arrows in). In some embodiments, the size of the horizontal gap between adjacent polysilicon pillars is between about 1 nm and 20 nm. This reduction in fluid accessibility increases the difficulty of uniformly filling the word lines 220 with tungsten material.

[0038] The structure of the word lines 220 and the challenges of uniformly filling the word lines with tungsten material due to the presence of the pillars 250 are further illustrated in Figure 3A , 3B and 3C. Figure 3A shows a vertical through VNAND structure 200 similar to that shown in Figure 2A , but here focused on a pair of word lines 220, and additionally schematically shows a tungsten filling process, which results in the formation of voids 275 in the word lines 220. Figure 3B The voids 270 are also schematically shown, but in this figure, they are shown by horizontally passing through the struts 250, similar to the horizontal cut shown in Figure 2B . Figure 3B shows the accumulation of tungsten material around the struts 250 in the constriction, which results in the pinching off of the opening 230, such that no additional tungsten material can be deposited in the region of the voids 270. According to Figure 3A and 3B it is apparent that void-free tungsten filling depends on a sufficient amount of deposition precursors migrating downward through the vertical structure 210, through the opening 220, past the constricted struts 250 and into the outermost reaches of the word lines 220, and then the accumulated deposited tungsten around the struts 250 will cause the pinching off of the opening 220 and prevent further precursor migration into the word lines 230. Figure 3C shows a single word line 230 viewed from an upper cross-section, and shows how the normally conformal deposition of tungsten material begins to pinch off the interior of the word line 220 due to the significant width of the struts 250 acting to partially block, and / or constrict and / or limit what would otherwise be an open path through the word line 220. (It should be noted that Figure 3C The example in can be understood as Figure 3B a 2-D rendering of the 3-D features of the strut structure of the pillar constriction shown in, and thus illustrates the constriction as would be seen in a plan view rather than a cross-sectional view.)

[0039] When depositing tungsten into the word lines described above, low resistivity and low stress are important. However, the bulk deposition processes that can provide low resistivity and low stress may result in rough sidewalls of the word lines. That is, the tungsten film deposited on the sidewalls 240 of the 3D NAND structure may have high roughness, which may cause problems in subsequent integration processes. In particular, when tungsten is etched back to remove it, the roughness can be transferred to the underlying and subsequently deposited layers.

[0040] Figure 4A process flow diagram illustrating certain operations in a method of filling a 3D NAND structure with tungsten is shown. First, a tungsten nucleation layer can be deposited in the word line features of the 3D NAND structure (block 401). The deposition of the nucleation layer involves alternating pulses of a tungsten precursor and a reducing agent. Examples of tungsten precursors include tungsten fluoride (WF x ), tungsten chloride (WCl x ), and tungsten hexacarbonyl (W(CO)6). Specific examples include tungsten hexafluoride (WF6), tungsten pentachloride (WCl5), tungsten hexachloride (WCl6), and tungsten oxychloride (e.g., WO x Cl y ). Examples of reducing agents include silane (e.g., SiH4) and borane, e.g., diborane (B2H6). In some embodiments, the nucleation layer may not be necessary.

[0041] Next, a first body layer is deposited in the word line features using a first set of conditions (block 403). In some embodiments, the body layer is characterized by a low resistivity, and in some embodiments, it is characterized by low stress and / or low fluorine. Since the word line features are not filled (except for the nucleation layer if deposited), relatively fast deposition techniques can be used. In some embodiments, this involves alternating pulses of a tungsten precursor and hydrogen (H2) or other reducing agent in an ALD process to deposit a first tungsten layer. A purge operation may separate the pulses. Relatively short pulse times can be used for deposition to increase throughput.

[0042] In some embodiments, the tungsten precursor is a fluorine-containing precursor, such as WF6. However, other tungsten precursors can be used, which include WF x , WCl x , and W(CO)6, examples including WCl5, WCl6, and WO x Cl y , where both x and y are greater than 0.

[0043] Once these features start to close, the deposition conditions can be changed to avoid pinching off. At operation 405, a second body layer is deposited using a second set of conditions. Like the first body layer, the second body layer is a low resistivity layer, and in some embodiments, it is a low stress and / or low fluorine layer. As in operation 403, the second body layer can be deposited by ALD, where the second set of conditions includes one or more different timings, flow rates, and temperatures relative to operation 403.

[0044] For example, in some embodiments, operation 405 involves an increased pulse time and an increased purge time relative to operation 403. In certain embodiments, the tungsten precursor pulse time can be increased. Increasing the pulse and / or purge time can facilitate the diffusion of reactants into the word line. In some embodiments, the temperature can also be changed from operation 403 to operation 405; for example, a higher temperature can be used to speed up the reaction time. In some embodiments, a lower temperature can be used to allow the reactants to diffuse into the word line features prior to reaction. In some embodiments, the second set of conditions can include a change in the flow rate. For example, the flow rate of the tungsten precursor and / or the reducing agent can be increased.

[0045] At operation 407, a third body layer is deposited under a third set of conditions. This can be characterized as a capping layer, for example, a capping layer deposited on sidewalls such as sidewall 240 in a 3D NAND structure. The layer can be characterized by a low roughness. As tungsten is removed, a higher resistivity and fluorine concentration can be tolerated. The third set of conditions can include any of the following: faster timing, provided that ALD is used and the pulse time is shorter than the pulse time of operation 405; using CVD instead of ALD; introducing nitrogen (N2) during or between the flow of one or more reaction gases; and B2H6 / WF6 ALD. Figure 5 A schematic diagram of a single word line 500 of a 3D NAND structure is provided, which includes a first body layer 503, a second body layer 505, and a third body layer 507.

[0046] In some embodiments, the tungsten precursor can be changed between body layer depositions.

[0047] Figure 6A An overall integration scheme for forming a 3D NAND structure is shown, which includes the multi-layer body deposition process described above. In operation 682, a substrate is provided. In various embodiments, the substrate is a semiconductor substrate. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including wafers having one or more layers of materials, such as dielectric, conductive, or semiconductive materials deposited thereon.

[0048] In operation 684, a film stack of alternating oxide and nitride films is deposited on the substrate. In various embodiments, the deposited oxide layer is a silicon oxide layer. In various embodiments, the deposited nitride layer is a silicon nitride layer. In some embodiments, each oxide layer and nitride layer is deposited to approximately the same thickness, such as between about 60 nm and about 600 nm, or about

[0049] The film stack may include alternating oxide and nitride layers between 48 and 562 layers, where each oxide layer or nitride layer constitutes one layer. A film stack including alternating oxide and nitride layers may be referred to as an ONON stack.

[0050] After depositing the ONON stack, channels may be etched in the substrate. Subsequently, referring to Figure 6A , in operation 686, a stepped pattern is formed on the substrate. The "stepped pattern" as referred to herein includes two or more steps, and each step includes an oxide layer and a nitride layer. The top layer of each set of oxide and nitride layers may be the oxide or nitride for forming a step in the staircase. In some examples, the stepped pattern includes between 24 and 256 steps. A variety of patterning techniques may be used to form the stepped pattern. For example, one technique may include depositing a sacrificial layer over the substrate and masking regions of the substrate to etch each set of oxide and nitride layers, thereby forming steps.

[0051] Each step includes a nitride layer and an oxide layer, and may be between about 650 nm and about 6000 nm, for example about 500 nm. The region of each step that extends from the edge of the step above may be referred to as a "pad". In Figure 6A operation 688, an oxide is deposited over the substrate. In various embodiments, the oxide may have the same composition as the oxide deposited in the layers of the ONON stack. The deposition temperature may be between room temperature and about 600 °C. After depositing the oxide, vertical slits may subsequently be etched into the substrate.

[0052] In operation 690, the nitride is etched selectively with respect to the oxide on the substrate. In some examples, a selective dry etching process may be used to perform the etching. This operation removes the nitride layer from the ONON stack such that the etchant flows into the vertical slits and selectively etches the nitride. It should be understood that selective etching involves etching a first material at a faster rate than a second material. For example, etching the nitride selectively with respect to the oxide means etching the nitride at a faster rate than the oxide. The nitride is selectively etched using a wet etching process, such as by exposing the substrate to phosphoric acid (H3PO4) and / or dilute hydrofluoric acid ("DHF") or a mixture of these solutions.

[0053] In operation 692, tungsten is deposited into the gaps of the substrate to form tungsten word lines. This may be done by referring to Figure 4 and Figure 5The described multi-layer process deposits bulk tungsten. In some embodiments, a barrier layer and / or a tungsten nucleation layer are deposited before depositing the bulk tungsten. The third bulk tungsten layer may be etchback. In operation 694, the oxide is vertically etched to form a via. The oxide may be etched by dry etching. In operation 696, tungsten is deposited in the via to form an interconnect that connects the tungsten wordlines. Figure 6B The resulting structure is shown, which includes tungsten wordlines 140 and an oxide layer 111 and a via 142 in the oxide 162.

[0054] Although Figure 4 - 6B exemplary applications of multi-layer bulk tungsten are provided, the method may be applied to fill other structures including Figure 1A and 1B the structures shown. The process may be adjusted at each stage to deposit the film at different rates and with different step coverages, fluorine content, stress, and roughness. According to various embodiments, any multi-layer bulk layer may involve one of the following operations: 1) H2 / WF6 ALD process; 2) H2 / WF6 ALD process with N2 co-flow; 3) H2 / WF6 CVD process; and 4) B2H6 / WF6 ALD.

[0055] In some embodiments, before depositing a subsequent bulk layer, the bulk layer is exposed to nitrogen (N2) or a nitrogen-containing soak. Such treatment may create an interface to interrupt crystal growth such that the subsequent bulk layer continues to grow with the growth of smaller crystals.

[0056] In some embodiments, the above method may be implemented to control precursor consumption. Shorter pulse times and / or lower flow rates of the metal-containing precursor may be used to fill structures with relatively accessible features (e.g., as shown in operation 403 and / or operation 407 of Figure 4 . The relatively low consumption thus generated may balance the longer pulse times and / or higher flow rates used to fill relatively inaccessible portions of the structure (e.g., as shown in operation 405 of Figure 4 .

[0057] The substrate temperature may also be controlled to adjust the deposition rate, fluorine incorporation, and stress. The exemplary temperature range for depositing bulk tungsten in a 3D NAND structure is 300 °C to 500 °C.

[0058] Tungsten-containing precursors that may be used include

[0059] Although the above description mainly describes a multilayer tungsten layer, these methods can be implemented using any material, such as molybdenum, cobalt, and ruthenium, to fill the features of a complex structure. For example, precursor consumption can be controlled by first using a faster deposition before the feature is closed, and then transitioning to a second bulk layer using a longer pulse time or a higher flow rate.

[0060] To deposit molybdenum (Mo), molybdenum-containing precursors can be used, including molybdenum hexafluoride (MoF6), molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxychloride (MoOCl4), and molybdenum hexacarbonyl (Mo(CO)6).

[0061] To deposit ruthenium (Ru), Ru precursors can be used. Examples of ruthenium precursors that can be used for oxidation reactions include (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0), (1-isopropyl-4-methylbenzyl)(1,3-cyclohexadienyl)Ru(0), (2,3-dimethyl-1,3-butadienyl)Ru(0) tricarbonyl, (1,3-cyclohexadienyl)Ru(0) tricarbonyl, and (cyclopentadienyl)(ethyl)Ru(II) dicarbonyl. Examples of ruthenium precursors that react with non-oxidizing reactants are bis(5-methyl-2,4-hexanedionato)Ru(II) dicarbonyl and bis(ethylcyclopentadienyl)Ru(II).

[0062] To deposit cobalt (Co), cobalt-containing precursors can be used, including cyclopentadienylcobalt(I) dicarbonyl, cobalt carbonyl, various amidinocobalt precursors, cobalt diazabutadiene complexes, amidinocobalt / guanidinocobalt precursors, and combinations thereof.

[0063] To deposit nickel (Ni), nickel precursors including cyclopentadienylallylnickel (CpAllylNi) and MeCp2Ni can be used.

[0064] More generally, the methods and apparatuses can be applied to the feature filling of complex structures using any conductive material to deposit multiple bulk layers. Metal precursor consumption, yield optimization, roughness control, and fill quality can be improved by multilayer bulk deposition.

[0065] In some embodiments, the multilayer film can include more than one metal. In a specific example, molybdenum and tungsten can be used for feature filling. Referring to Figure 5 , for example, the first bulk layer 503 can be a molybdenum layer, the second bulk layer 505 can be an ALD tungsten layer, and the third bulk layer 507 can be a CVD tungsten layer.

[0066] Device

[0067] Any suitable chamber can be used to implement the disclosed embodiments. Exemplary deposition apparatuses include a variety of systems, such as and Max, which is available from Lam Research Corp. of Fremont, California, or any of a variety of other commercially available processing systems. The process can be carried out in a single deposition station or in parallel on multiple deposition stations. Figure 7 is a block diagram of a processing system suitable for performing a deposition process according to the embodiments described herein. System 700 includes a transfer module 703. The transfer module 703 provides a clean, pressurized environment to minimize the risk of substrate contamination as the substrate being processed moves between the various reactor modules. According to the embodiments described herein, a chamber 709 capable of performing PNL, ALD, and CVD depositions is mounted on the transfer module 703. The chamber 709 may include a plurality of stations 711, 713, 715, and 717 that can perform these operations sequentially or in parallel. For example, the chamber 709 may be configured to deposit a nucleation layer at station 711, while stations 713 - 717 deposit the bulk layers as described above, respectively. In some embodiments, stations 713 and 715 may perform ALD, while station 717 performs CVD. In some embodiments, each of stations 713 - 717 performs ALD.

[0068] Each deposition station may include a heated wafer pedestal and a showerhead, a dispersion plate, or other gas inlets. Each station may also be connected to a gas source. Each of temperature, gas flow, and timing can be controlled independently of the other stations.

[0069] Also mounted on the transfer module 703 may be one or more single - or multi - station modules 707 that can perform plasma or chemical (non - plasma) pre - cleaning. The module can also be used for a variety of other processes, such as reductant soak. The system 700 further includes one or more (in this case, two) wafer source modules 701 in which wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 719 can first move the wafer from the source module 701 to the load lock 721. The wafer transfer device (usually a robotic arm unit) in the transfer module 703 moves the wafer from the load lock 721 to the modules mounted on the transfer module 703 and moves the wafer between these modules.

[0070] In certain embodiments, a system controller 729 is employed to control the process conditions during deposition. The controller will typically include one or more memory devices and one or more processors. The processor may include a CPU or a computer, analog and / or digital input / output connections, a stepper motor controller board, etc.

[0071] The controller can control the activities of all deposition apparatuses. The system controller runs system control software, which includes an instruction set for controlling timing, gas mixing, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power level (if used), wafer chuck or pedestal position, and other parameters of a particular process. In some embodiments, other computer programs stored on a memory device associated with the controller can be used.

[0072] Generally, there will be a user interface associated with the controller. The user interface can include a display screen, a graphical software display of the apparatus and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0073] The system control logic can be configured in any suitable manner. Generally, the logic can be designed or configured in hardware and / or software. The instructions for controlling the drive circuit can be hard-coded or provided as software. The instructions can be provided by "programming". Such programming is understood to include any form of logic, which includes hard-coded logic in a digital signal processor, application-specific integrated circuit, and other devices having a specific algorithm implemented as hardware. Programming is also understood to include software or firmware instructions executable on a general-purpose processor. The system control software can be encoded in any suitable computer-readable programming language. Alternatively, the control logic can be hard-coded in the controller. Application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays or FPGAs), etc. can be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally equivalent hard-coded logic can be used instead.

[0074] The computer program code for controlling deposition and other processes can be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by a processor to perform the tasks identified in the program.

[0075] The controller parameters relate to process conditions such as, for example, process gas composition and flow rate, temperature, pressure, cooling gas pressure, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and can be input using the user interface.

[0076] Signals for monitoring the process can be provided through the analog and / or digital input connections of the system controller. Signals for controlling the process are output through the analog and digital output connectors of the deposition apparatus.

[0077] The system software can be designed or configured in many different ways. For example, multiple chamber component subroutines or control objectives can be written to control the operation of the chamber components required to perform the deposition process of the present invention. Examples of programs or program segments for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code.

[0078] In some embodiments, the controller 729 is part of a system that can be part of the above-described embodiments. Such systems include semiconductor processing apparatuses that include one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer chucks, gas flow systems, etc.). These systems can be integrated with electronics to control the operation of these systems before, during, or after the processing of semiconductor wafers or substrates. The electronics can be referred to as a "controller" that can control various components or sub-parts of one or more systems. Depending on the processing requirements and / or the type of system, the controller 729 can be programmed to control any of the processes disclosed in the present invention, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, flow rate settings, fluid delivery settings, position and operation settings, the loading and unloading of wafers into and out of the tool and other transfer tools, and / or the transfer of load locks connected to or interfacing with a particular system.

[0079] Broadly speaking, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuit can include a chip storing program instructions in the form of firmware, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions delivered to the controller or system in various different settings (or program files), and the different settings (or program files) define operating parameters for performing specific processes on or for a semiconductor wafer. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or bare chips on a wafer.

[0080] In some embodiments, the controller 729 can be part of or coupled to a computer that is integrated with, coupled to, or networked to the system or combinations thereof. For example, the controller 729 can be in the "cloud" or be all or part of the main computer system of a wafer fab, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review trends or performance criteria for multiple manufacturing operations, to change the parameters of the current process, set processing steps to follow the current process or initiate a new process. In some embodiments, a remote computer (e.g., a server) can provide a process recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that allows for the input or programming of parameters and / or settings, which are then transferred from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify the parameters for each processing step to be performed during one or more operations. It should be understood that these parameters can be specific to the type of process to be performed as well as the type of tool that the controller is configured to connect to or control. Thus, as described above, the controller can be distributed, for example, by including one or more discrete controllers that are connected together via a network and work towards a common goal (e.g., the processes and controls described herein). An example of a distributed controller for these purposes would be one or more integrated circuits in the chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer), which combine to control the processes in the chamber.

[0081] Exemplary systems can include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems that can be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0082] As described above, depending on the one or more process steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, combined tools, other tool interfaces, adjacent tools, adjoining tools, tools located throughout the factory, a host, another controller, or tools used in material handling that transport a container of wafers between tool locations and / or load ports in a semiconductor manufacturing facility.

[0083] The controller 729 may include different programs. The substrate positioning program may include program code for controlling the chamber components for loading a substrate onto a pedestal or chuck and for controlling the spacing between the substrate and other components of the chamber such as gas inlets and / or targets. The process gas control program may include code for controlling the gas composition, flow rate, and optionally for flowing gas into the chamber prior to deposition to stabilize the pressure in the chamber. The pressure control program may include code for controlling the pressure in the chamber by adjusting a throttle valve in the exhaust system in the chamber, for example. The heater control program may include code for controlling the current to a heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas such as helium to the wafer chuck.

[0084] Examples of chamber sensors that may be monitored during deposition include mass flow controllers, pressure sensors such as pressure gauges, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain the desired process conditions.

[0085] Implementations of embodiments of the present disclosure in single-chamber or multi-chamber semiconductor processing tools have been described above.

[0086] The foregoing has described implementations of embodiments of the present disclosure in single-chamber or multi-chamber semiconductor processing tools. The devices and processes described herein may be used in conjunction with lithographic patterning tools or processes, for example, for fabricating or manufacturing semiconductor devices, displays, LEDs, photovoltaic panels, etc. Generally, although not necessarily, these tools / processes will be used or operated together in a common manufacturing facility. Lithographic patterning of a film typically includes some or all of the following steps, each step enabling multiple viable tools: (1) coating a photoresist on a workpiece, i.e., a substrate, using a spin-coating or spraying tool; (2) curing the photoresist using a hot plate or furnace or ultraviolet curing tool; (3) exposing the photoresist to visible light or ultraviolet light or X-rays using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern to the underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as a radio frequency or microwave plasma resist stripper.

[0087] Conclusion

[0088] Although the above embodiments have been described in some detail for purposes of clear understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the embodiments of the present invention. Accordingly, the embodiments of the present invention are to be considered illustrative rather than restrictive, and these embodiments are not limited to the details given herein.

Claims

1. A method of manufacturing a 3-D structure of a semiconductor substrate filled in part with a conductive material, the 3-D structure including sidewalls, a plurality of openings in the sidewalls leading to a plurality of features having a plurality of internal regions, the plurality of internal regions being fluidly accessible through the openings, the method comprising: Depositing a first bulk layer of the conductive material within the 3-D structure such that the first bulk layer partially fills the plurality of internal regions of the 3-D structure; Depositing a second bulk layer of the conductive material within the 3-D structure, on the first bulk layer, such that the second bulk layer at least partially fills the plurality of internal regions of the 3-D structure; And Depositing a third bulk layer of the conductive material on the sidewalls within the 3-D structure, wherein the first bulk layer, the second bulk layer, and the third bulk layer are deposited under different conditions, Wherein one or more of a flow rate and a pulse time of pulses of a metal-containing precursor during deposition of the first bulk layer is greater than one or more of the flow rate and the pulse time of pulses of the metal-containing precursor during deposition of the second bulk layer and the third bulk layer.

2. The method according to claim 1, wherein The conductive material is tungsten.

3. The method according to claim 1, wherein The first bulk layer and the second bulk layer are deposited by an atomic layer deposition process.

4. The method according to claim 3, wherein the third bulk layer is deposited by an atomic layer deposition process.

5. The method according to claim 3, wherein, The third bulk layer is deposited by a chemical vapor deposition process.

6. The method according to claim 3, wherein Each of the atomic layer deposition processes includes consecutive pulses of the metal-containing precursor and a reducing agent.

7. The method according to any one of claims 1-6, further comprising depositing a fourth bulk layer of the conductive material on the third bulk layer.

8. The method according to claim 1, wherein, The conductive material is molybdenum, ruthenium, or cobalt.

9. The method according to claim 1, further comprising exposing the substrate to a nitrogen (N2) soak between depositions of two of the bulk layers.

10. A deposition method, comprising: Providing a substrate to a multi-station deposition chamber; Depositing a first metal bulk layer on the substrate at a first station of the multi-station deposition chamber under a first set of conditions; Transferring the substrate from the first station to a second station of the multi-station deposition chamber and depositing a second metal bulk layer on the first metal bulk layer under a second set of conditions; transferring the substrate from the second station to a third station of the multi-station deposition chamber and depositing a third metal bulk layer on the second metal bulk layer under a third set of conditions, wherein transitioning from the first set of conditions to the second set of conditions includes one or more of the following: changing a pulse time of a metal-containing precursor, changing a metal-containing precursor flow rate, and changing a susceptor temperature, and transitioning from the second set of conditions to the third set of conditions includes one or more of the following: changing a pulse time of a metal-containing precursor, changing the flow rate of the metal-containing precursor, and changing a susceptor temperature, Wherein transitioning from the first set of conditions to the second set of conditions includes: increasing the flow rate of the metal-containing precursor or increasing the pulse time of the metal-containing precursor.

11. The method according to claim 10, wherein, The metal of the first metal main body layer, the second metal main body layer, and the third metal main body layer is one of tungsten, molybdenum, cobalt, and ruthenium.

12. The method according to any one of claims 10 - 11, wherein transitioning from the first set of conditions to the second set of conditions comprises: Increase the cleaning time.

13. The method according to any one of claims 10-11, wherein, Transitioning from the first set of conditions to the second set of conditions includes: reducing the flow rate of the metal-containing precursor or reducing the pulse time of the metal-containing precursor.

14. A multi-station chamber, comprising: A first station including a first showerhead and a first susceptor; A second station including a second showerhead and a second susceptor; A third station including a third showerhead and a third susceptor; And A controller including machine-readable instructions to: Deposit a first metal main body layer on a substrate in the first station of the multi-station chamber under a first set of conditions; transfer the substrate to the second station of the multi-station chamber, and deposit a second metal main body layer on the first metal main body layer under a second set of conditions; transfer the substrate to the third station of the multi-station chamber, and deposit a third metal main body layer on the second metal main body layer under a third set of conditions, wherein transitioning from the first set of conditions to the second set of conditions includes one or more of the following: changing the pulse time of the metal-containing precursor, changing the flow rate of the metal-containing precursor, and changing the susceptor temperature, and transitioning from the second set of conditions to the third set of conditions includes one or more of the following: changing the pulse time of the metal-containing precursor, changing the flow rate of the metal-containing precursor, and changing the susceptor temperature, Wherein, transitioning from the first set of conditions to the second set of conditions includes: increasing the flow rate of the metal-containing precursor or increasing the pulse time of the metal-containing precursor.

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