Method for forming a device using aspect ratio dependent etching effect, related device, memory device and electronic system

Abstract

A method of forming a device is disclosed, comprising forming a patterned shielding material including parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned shielding material and the mask includes additional parallel structures and parallel apertures extending at a second different angle from about 0° to about 90° relative to the lateral direction. The patterned shielding material is further patterned using the mask to form a patterned shielding structure including elongated structures separated by the parallel trenches and the additional parallel trenches. Exposed portions of a hard mask material underlying the patterned shielding structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductor material underlying the patterned hard mask material are removed to form a semiconductor pillar structure. Devices and electronic systems are also described.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application serial number 16 / 111,499, filed on August 24, 2018, entitled "Methods of Forming Semiconductor Devices Using Aspect Ratio Dependent Etching Effects, and Related Semiconductor Devices, Memory Devices, and Electronic Systems." Technical Field

[0003] Embodiments of the present invention relate to the field of semiconductor device design and manufacturing. More specifically, embodiments of the present invention relate to methods of forming semiconductor devices using aspect ratio dependent etching effects and related semiconductor devices, memory devices, and electronic systems. Background Art

[0004] Semiconductor device designers generally desire to increase the integration or density of features within a semiconductor device by reducing the size of individual features and by reducing the separation distance between adjacent features. In addition, semiconductor device designers generally desire designs that are not only compact, but also provide performance advantages and simplify the architecture of the design.

[0005] A relatively common semiconductor device is a memory device. A memory device may include a memory array having a number of memory cells arranged in a grid pattern. One type of memory cell is a dynamic random access memory (DRAM). In the simplest design configuration, a DRAM cell includes one access device (e.g., a transistor) and one storage device (e.g., a capacitor). Modern applications of memory devices may utilize a large number of DRAM cell cells arranged in an array of rows and columns. DRAM cells may be electrically accessed through digit lines and word lines arranged along the rows and columns of the array.

[0006] Reducing the size and spacing of memory device features places increasing demands on the methods used to form memory device features. For example, one of the limiting factors in the continued shrinking of memory devices is the resistance of the contacts associated therewith. As used herein, "contact" refers to a connection that facilitates a conductive path between at least two structures. For example, in a DRAM device exhibiting a dual-bit memory cell structure, a digit line contact is provided between a digit line and an access device (e.g., a transistor) formed in or above a substrate, and a storage node contact is formed between the access device and a storage node (e.g., a capacitor) in which charge can be stored. When the size of a memory device (e.g., a DRAM device) feature is reduced, the size of the contacts associated therewith is also reduced, resulting in increased contact resistance. The increased contact resistance reduces the drive current of the memory device, which may adversely affect the performance of the memory device.

[0007] One method for reducing contact resistance within a memory device is to increase the surface area of ​​its contacts. For example, material may be removed from multiple surfaces of a memory device feature to form three-dimensional (3D) contacts, thereby presenting a larger contact surface area than the memory device feature would otherwise present. However, conventional methods of forming 3D contacts for DRAM device structures that present lower critical dimensions, such as critical dimensions less than about 20 nanometers (nm), may require complex and expensive processes to adequately form and align the 3D storage node contacts relative to digit line (e.g., bit line) contacts to ensure proper performance of the DRAM device.

[0008] For example, one conventional method of forming 3D contacts exhibiting lower critical dimensions includes transferring a pattern of openings and features in a mask structure into a hard mask material overlying a semiconductor material, and then using the patterned hard mask material to selectively etch (e.g., selectively dry etch) the underlying semiconductor material and form semiconductor pillars that each include two storage node (e.g., memory element) contact regions and a digit line contact region laterally between the two storage node contact regions. However, transferring the pattern of the mask structure into the hard mask material typically requires aspect ratio dependent etching (ARDE) of the hard mask material, which can achieve undesirable structural properties in the subsequently formed semiconductor pillars. During ARDE, the rate at which material (e.g., hard mask material) is removed depends on the aspect ratio of the opening (e.g., trench) being formed, which is defined as the ratio of the depth to the width (e.g., diameter) of the opening. Openings with relatively high aspect ratios are etched more slowly than openings with relatively small aspect ratios. In other words, in terms of linear depth etched per unit time, the etch rate is smaller for high aspect ratio openings than for low aspect ratio openings. Thus, some features of patterned hard mask materials (e.g., pillar structures) may exhibit variable lateral dimensions across their heights, depending on variations in the width of the openings in the mask structure. Such variable lateral dimensions, in turn, may enable undesirable lateral dimensions and shapes in semiconductor pillars formed using patterned hard mask materials, which may leave very little process margin to avoid digit line to storage element (e.g., memory element) shorts in DRAM devices that include semiconductor pillars.

[0009] Therefore, there is a need for new, simple, and cost-effective methods of forming semiconductor device structures for semiconductor devices such as DRAM devices, such as DRAM device structures having critical dimensions of less than about 20 nm, for example. Summary of the invention

[0010] Methods for forming devices using the ARDE effect, as well as related devices, memory devices, and electronic systems are described herein. For example, in some embodiments, the method for forming a device includes forming a patterned shielding material over a hard mask material overlying a semiconductor material. The patterned shielding material includes parallel line structures and parallel linear grooves each extending laterally at a first angle in a range from about 30 degrees to about 75 degrees relative to a first lateral direction. A mask is provided above the patterned shielding material. The mask includes additional parallel line structures and parallel linear pores each extending laterally at a second angle different from the first angle and in a range from about 0 degrees to about 90 degrees relative to the first lateral direction. The patterned shielding material is further patterned using a mask to form a patterned shielding structure including an elongated column structure separated from each other by parallel linear grooves extending laterally at a first angle and additional parallel linear grooves extending laterally at a second angle. The overlapping region of the parallel linear grooves and the additional parallel linear grooves is positioned to be laterally adjacent to the corners of the elongated column structure. The portions of the hard mask material not covered by the elongated pillar structures are subjected to aspect ratio dependent etching to form a patterned hard mask material including portions of the elongated hard mask structure exhibiting lateral boundaries of and within the parallel linear trenches and overlap regions of the additional parallel linear trenches vertically underlying the patterned shielding structure. The portions of the semiconductor material not covered by the elongated hard mask structure are removed to form a patterned semiconductor material including the elongated semiconductor pillar structures.

[0011] In an additional embodiment, a device includes elongated semiconductor pillars that each individually include a digit line contact region disposed laterally between two storage node contact regions. Each of the two storage node contact regions has a greater width than the digit line contact region.

[0012] In another embodiment, a memory device includes a memory controller, a row decoder, a column decoder, a word line, a digital line, a memory cell, and an elongated semiconductor column. The row decoder is operably coupled to the memory controller. The column decoder is operably coupled to the memory controller. The word line is operably coupled to the row decoder. The digital line is operably coupled to the column decoder. The memory cell is positioned adjacent to the intersection of the word line and the digital line, and includes a storage node structure and an access device electrically connected to the storage node structure. The elongated semiconductor column is operably coupled to the storage node structure memory cell and the digital line. The elongated semiconductor column each includes a storage node contact area, and a digital line contact area laterally between the memory cell contact areas and exhibiting a narrower width than the memory cell contact area.

[0013] In yet another embodiment, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes at least one elongated semiconductor pillar, the at least one elongated semiconductor pillar including a digit line contact region, and storage node contact regions laterally flanking the digit line contact region. Each of the storage node contact regions individually exhibits a larger lateral cross-sectional area than the digit line contact region. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figures 1A to 7B is a simplified partial top view illustrating a method of forming a semiconductor device structure according to an embodiment of the present invention ( Figure 1A , 2A , 3A, 4A, 5A, 6A and 7A) and simplified partial cross-sectional views ( Figure 1B , 2B , 3B, 4B, 5B, 6B and 7B).

[0015] Figures 8A to 8E is a simplified partial top view illustrating a method of forming another semiconductor device structure according to an additional embodiment of the present invention.

[0016] Figures 9A to 9E is a simplified partial top view illustrating a method of forming another semiconductor device structure according to an additional embodiment of the present invention.

[0017] Fig.10 is a functional block diagram of a memory device according to an embodiment of the present invention.

[0018] Fig.11 is a schematic block diagram of an electronic system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Methods for forming semiconductor devices using the ARDE effect, as well as related semiconductor devices, memory devices, and electronic systems are described herein. In some embodiments, the method for forming a semiconductor device includes forming a patterned shielding material over a hard mask material overlying a semiconductor material. The patterned shielding material may include parallel line structures and parallel linear grooves each extending laterally at a first angle in a range from about 30 degrees to about 75 degrees relative to a first lateral direction (e.g., an X direction). A mask (e.g., an etching mask, a subtractive removal mask, a chop mask) may be provided over the patterned shielding material. The mask may include additional parallel line structures and parallel linear pores each extending laterally at a second angle different from the first angle and in a range from about 0 degrees to about 90 degrees relative to the first lateral direction. Portions of the patterned shielding material not covered by the additional parallel line structures of the mask may be selectively removed to form a patterned shielding structure including an elongated column structure separated from each other by parallel linear grooves extending laterally at a first angle and additional parallel linear grooves extending laterally at a second angle. The overlap region of the parallel linear trenches and the additional parallel linear trenches of the patterned shielding structure is positioned laterally adjacent to the tip (e.g., corner) of the elongated pillar structure. The portion of the hard mask material not covered by the elongated pillar structure is subjected to ARDE to form a patterned hard mask material including a portion of the elongated hard mask structure that exhibits a lateral boundary vertically underlying and within the overlap region of the parallel linear trenches and the additional parallel linear trenches of the patterned shielding structure. The portion of the semiconductor material not covered by the elongated hard mask structure is selectively removed to form a patterned semiconductor material including the elongated semiconductor pillar structure. The method of the present invention can facilitate improved reliability and performance in semiconductor device structures (e.g., DRAM device structures, such as DRAM cells), semiconductor devices (e.g., DRAM devices), and electronic systems that rely on high feature density.

[0020] The following description provides specific details such as material type, material thickness, and processing conditions in order to provide a detailed description of embodiments of the present invention. However, those skilled in the art will appreciate that embodiments of the present invention may be practiced without adopting these specific details. In fact, embodiments of the present invention may be practiced in conjunction with conventional manufacturing techniques used in the industry. In addition, the description provided below does not form a complete process flow for manufacturing semiconductor devices. The semiconductor device structure described below does not form a complete semiconductor device. Only the process behaviors and structures necessary for understanding embodiments of the present invention are described in detail below. Additional behaviors of forming a complete semiconductor device from a semiconductor device structure may be performed by conventional manufacturing techniques. It is also noted that any drawings attached to this application are for illustrative purposes only and are therefore not drawn to scale. In addition, common elements between the figures may retain the same element symbols.

[0021] As used herein, the term "configured" refers to the size, shape, material composition, material distribution, orientation, and arrangement of at least one structure and at least one device in a predetermined manner to facilitate operation of the structure and one or more of the devices.

[0022] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0023] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] As used herein, the terms "longitudinal", "vertical", "lateral", and "horizontal" refer to the principal plane of a substrate (e.g., a substrate material, a substrate structure, a substrate configuration, etc.) in or on which one or more structures and / or features are formed and are not necessarily defined by the earth's gravitational field. A "lateral" or "horizontal" direction is a direction substantially parallel to the principal plane of the substrate, while a "longitudinal" or "vertical" direction is a direction substantially perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by a surface of the substrate having a relatively larger area than other surfaces of the substrate.

[0025] As used herein, for ease of description, spatially relative terms such as "below," "beneath," "lower," "bottom," "above," "up," "top," "front," "rear," "left," "right," and the like may be used to describe the relationship of one element or feature to another element or feature(s), as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, an element described as "below" or "beneath" or "below" or "on the bottom" of other elements or features would then be oriented "above" or "on top" of the other elements or features. Thus, the term "below" may encompass both above and below orientations, depending on the context in which the term is used, which will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein are interpreted accordingly.

[0026] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes to the extent that one skilled in the art will understand that the given parameter, property, or condition is met with some degree of variation, such as within an acceptable tolerance. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0027] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and those skilled in the art will understand a certain degree of variation in the numerical value within the acceptable tolerance of the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0028] Figures 1A to 7B 1 is a simplified partial top view illustrating an embodiment of a method of forming a semiconductor device structure (eg, a memory device structure, such as a DRAM device structure) for a semiconductor device (eg, a memory device, such as a DRAM device) Figure 1A , 2A , 3A, 4A, 5A, 6A and 7A) and simplified partial cross-sectional views ( Figure 1B , 2B , 3B, 4B, 5B, 6B and 7B). Using the description provided below, it will be readily apparent to those skilled in the art that the methods described herein can be used in a variety of devices. In other words, the methods of the present invention can be used whenever it is desired to form a semiconductor device.

[0029] Common Reference Figure 1A and 1B , the semiconductor device structure 100 may include a semiconductor material 102 ( Figure 1B ), hard mask material 104 on or over semiconductor material 102, and patterned masking material 106 on or over hard mask material 104. Semiconductor material 102 may, for example, include one or more of a silicon material, a silicon germanium material, a germanium material, a gallium arsenide material, a gallium nitride material, and an indium phosphide material. In some embodiments, semiconductor material 102 includes at least one silicon material. As used herein, the term "silicon material" means and includes a material that includes elemental silicon or a compound of silicon. Semiconductor material 102 may, for example, include one or more of single crystal silicon and polycrystalline silicon.

[0030] The hard mask material 104 may include a layer suitable for use as an etch mask to pattern the semiconductor material 102 after patterning the hard mask material 104. Figure 1B), as described in further detail below. By way of non-limiting example, the hard mask material 104 may be formed of and include at least one of amorphous carbon, silicon, silicon oxide, silicon nitride, silicon oxycarbide, aluminum oxide, and silicon oxynitride. In some embodiments, the hard mask material 104 includes at least one oxide dielectric material (e.g., one or more of silicon dioxide and aluminum oxide). The hard mask material 104 may be homogenous (e.g., may include a single material), or may be heterogeneous (e.g., may include a stack including at least two different materials).

[0031] The semiconductor material 102 and the hard mask material 104 may each be individually formed using conventional processes including, but not limited to, one or more of physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), in-situ growth, spin-on coating, and blanket coating. CVD includes, but is not limited to, plasma enhanced CVD ("PECVD") and low pressure CVD ("LPCVD"). PVD includes, but is not limited to, sputtering, evaporation, and ionized PVD. Such processes are known in the art and therefore are not described in detail herein.

[0032] The patterned masking material 106 may include parallel line structures 108 separated from each other by parallel linear trenches 110. As used herein, the term "parallel" means substantially parallel. Each of the parallel line structures 108 may, for example, be formed of and include a material having an etch selectivity relative to the hard mask material 104. At least some portions of the parallel line structures 108 may be selectively removed relative to the hard mask material 104 by one or more material removal processes, and / or at least some portions of the hard mask material 104 may be selectively removed relative to the parallel line structures 108 by one or more other material removal processes. In some embodiments, the parallel line structures 108 include a nitride dielectric material (e.g., silicon nitride). In additional embodiments, the parallel line structures 108 include a photoresist material.

[0033] Each of the parallel line structures 108 of the patterned masking material 106 may have at least substantially the same width (e.g., a smaller lateral dimension) and may be regularly spaced apart by substantially the same distance (corresponding to the width of each of the parallel linear trenches 110). Accordingly, the spacing between the center lines of adjacent parallel line structures 108 may be substantially uniform throughout the patterned masking material 106. The size and spacing of the parallel line structures 108 (and thus the parallel linear trenches 110) of the patterned masking material 106 may be selected to provide the desired lateral dimensions and lateral spacing for features subsequently formed by the hard mask material 104 when considering the ARDE effect, as described in further detail below. In some embodiments, the width of each of the parallel line structures 108 is less than or equal to about 20 nm, and the distance between laterally adjacent parallel line structures 108 is greater than or equal to the width of the parallel line structures 108.

[0034] like Figure 1A , each of the parallel line structures 108 of the patterned masking material 106 can be formed at a first angle θ offset from a first lateral direction (e.g., an X direction) in which one or more subsequently formed structures (e.g., access lines, such as word lines) can extend laterally. The first angle θ of the parallel line structures 108 (and thus the parallel linear trenches 110) can be, for example, greater than zero (0) degrees and less than or equal to about ninety (90) degrees relative to the first lateral direction, such as within a range from about ten (10) degrees to about eighty (80) degrees, from about thirty (30) degrees to about seventy-five (75) degrees, or from about forty (40) degrees to about seventy (70) degrees. The first angle θ of the parallel line structures 108 can be selected based at least in part on the desired architecture of the semiconductor device structure 100, and based on the desired size of a feature to be formed from a portion of the hard mask material 104 using the patterned masking material 106, as described in further detail below. The first angle θ of the parallel line structures 108 and the parallel linear trenches 110 partially affects the size and shape of the features formed by the ARDE from the hard mask material 104, which in turn affects the size and shape of the features formed from the semiconductor material 102. In some embodiments, the first angle θ of the parallel line structures 108 is about sixty-nine (69) degrees. Figure 1A In the figure, line AA extends in the X direction and corresponds to Figure 1B A cross section of a semiconductor device structure 100 is depicted in FIG.

[0035] The patterned masking material 106 may be formed using conventional processes not described in detail herein (e.g., conventional deposition processes, such as one or more of in-situ growth, spin coating, blanket coating, CVD, ALD, and PVD; conventional patterning and material removal processes, such as conventional photolithography exposure processes, conventional development processes, conventional etching processes) and conventional processing equipment.

[0036] Next, refer to Figure 2A , a mask 112 (e.g., an etching mask, a trimming mask) may be provided on or over the patterned shielding material 106. The mask 112 may be formed of and include at least one material suitable for use as a barrier to selectively remove portions of the additional parallel line structures 114 of the patterned shielding material 106, as described in further detail below. The material composition of the mask 112 may depend, at least in part, on the material composition of the additional parallel line structures 114 of the patterned shielding material 106, and on the characteristics of the material removal process to be employed with the mask 112 (e.g., an etchant). By way of non-limiting example, the mask 112 may be formed of and include at least one of amorphous carbon, silicon, silicon oxide, silicon nitride, silicon oxycarbide, aluminum oxide, and silicon oxynitride. The mask 112 may be homogeneous (e.g., may include a single material layer), or may be heterogeneous (e.g., may include a stack exhibiting at least two different material layers). Figure 2B is in Figure 2A The surrounding line AA ( Figure 2A ) is a simplified partial cross-sectional view of a semiconductor device structure 100.

[0037] The mask 112 reveals the desired pattern to be transferred into the additional parallel line structure 114 of the patterned masking material 106. For example, Figure 2A , the mask 112 may include additional parallel line structures 114 separated from each other by parallel linear apertures 116 (e.g., parallel linear openings, parallel linear trenches). Each of the additional parallel line structures 114 of the mask 112 may have substantially the same width (e.g., smaller lateral dimension) and may be regularly spaced by substantially the same distance (corresponding to the width of each of the parallel linear apertures 116). Accordingly, the spacing between the centerlines of laterally adjacent additional parallel line structures 114 may be substantially uniform throughout the mask 112. The size and spacing of the additional parallel line structures 114 (and thus the parallel linear apertures 116) of the patterned masking material 106 may be selected to provide a desired lateral size, lateral shape, and lateral spacing for features formed by the additional parallel line structures 114, which in turn may be selected to provide a desired lateral size and lateral shape for features formed by the hard mask material 104 and the semiconductor material 102 when considering the ARDE effect, as described in further detail below. In some embodiments, the width of each of the additional parallel line structures 114 of the mask 112 is greater than the width of each of the parallel line structures 108 of the patterned masking material 106, and the distance between laterally adjacent additional parallel line structures 114 of the mask 112 (for example, corresponding to the width of each of the parallel linear pores 116) is substantially the same as the distance between laterally adjacent parallel line structures 108 of the patterned masking material 106.

[0038] like Figure 2A , the additional parallel line structures 114 and the parallel linear apertures 116 of the mask 112 may be formed at a second angle α relative to a first lateral direction (e.g., the X direction) that is different from (e.g., smaller than, larger than) a first angle θ of the parallel line structures 108 and the parallel linear trenches 110 of the patterned masking material 106, respectively. The second angle α may be selected in view of the first angle θ based on a desired architecture of the semiconductor device structure 100, and based on desired lateral dimensions and lateral shapes of features to be formed by the additional parallel line structures 114, which in turn may be selected to provide a desired lateral dimension and lateral shape for features formed by the hard mask material 104 and the semiconductor material 102 ( Figure 2B ) to provide a desired lateral size and a desired lateral shape for features formed by ARDE. For example, the second angle α may be selected relative to the first angle θ to control the lateral size and lateral position of intersections between the parallel linear trenches 110 of the patterned masking material 106 and additional parallel linear trenches formed in the patterned masking material 106 using the mask 112. The lateral size and lateral position of such intersections may affect the amount and position of hard mask material 104 removed during a subsequent ARDE using the remainder of the parallel line structure 108 so as to affect the lateral size and lateral shape of features formed by the hard mask material 104 by ARDE and the subsequent removal of such features from the semiconductor material 102 ( Figure 2B ) The lateral dimensions and lateral shapes of the features formed. In some embodiments, the second angle α of the additional parallel line structures 114 and the parallel linear pores 116 is about forty-one (41) degrees.

[0039] In additional embodiments, mask 112 may exhibit Figure 2A By way of non-limiting example, mask 112 may exhibit multiple series of discrete, elongated (e.g., non-circular, non-equilateral) apertures (e.g., oval apertures, rectangular apertures) in place of each of parallel linear apertures 116. The discrete, elongated apertures may be laterally surrounded and defined by a single continuous mask structure in place of additional parallel linear structures 114. Each series of discrete, elongated apertures may be substantially aligned with one another and may individually and collectively have substantially the same Figure 2A 106 (e.g., the same second angle α relative to the X-direction). Each discrete, elongated aperture of each series of discrete, elongated apertures may be individually positioned laterally to vertically overlie a portion of one of the parallel line structures 108 of the patterned masking material 106. Thus, the discrete, elongated apertures (and the single continuous mask structure that laterally surrounds and defines the discrete, elongated apertures) may facilitate selective removal of portions of the parallel line structures 108 of the patterned masking material 106 in a manner substantially similar to the parallel linear apertures 116.

[0040] Return to reference Figure 2A The mask 112 (including its additional parallel line structures 114 and parallel linear pores 116) can be formed and positioned using conventional processes not described in detail herein (e.g., conventional deposition processes, such as one or more of in situ growth, spin-on coating, blanket coating, CVD, ALD, and PVD; conventional photolithography procedures; conventional material removal processes; conventional alignment processes) and conventional processing equipment.

[0041] Next, refer to Figure 3A , remain unmasked 112 ( Figure 2A and 2B ) of the additional parallel line structure 114 ( Figure 2A and 2B ) covered with patterned masking material 106 ( Figure 2A and 2B ) of parallel line structure 108( Figure 2A and 2B ) may be subjected to at least one material removal process to form the patterned shielding structure 118. Figure 3A , the patterned shielding structure 118 may include an elongated column structure 120, parallel linear grooves 110, and additional parallel linear grooves 122. The elongated column structures 120 may be separated from each other in a lateral direction by the parallel linear grooves 110, and may be separated from each other in an additional lateral direction by the additional parallel linear grooves 122. The elongated column structures 120 may each exhibit a parallelogram lateral cross-sectional shape. The elongated column structures 120 may each individually include first opposing side surfaces 117 extending parallel to each other at a first angle θ, second opposing side surfaces 119 extending parallel to each other at a second angle α, and a tip 126 (e.g., a corner, such as an angled corner) between the first opposing side surfaces 117 and the second opposing side surfaces 119. In addition, as Figure 3A As shown in FIG. 1 , after forming the patterned shielding structure 118, the mask 112 ( Figure 2A and 2B ). Figure 3B is in Figure 3A The surrounding line AA ( Figure 3A ) is a simplified partial cross-sectional view of a semiconductor device structure 100.

[0042] like Figure 3A As shown in FIG. 1 , the intersections (eg, junctions, cross-points) between the parallel linear grooves 110 and the additional parallel linear grooves 122 of the patterned shielding structure 118 may define overlapping groove regions 124 (denoted by the intersections) between the tips 126 of the laterally adjacent elongated pillar structures 120 in the laterally direction. Figure 3A). The lateral shape and lateral dimensions of the overlapping trench region 124 depend, at least in part, on the first angle θ of the parallel linear trenches 110 and the second angle α of the additional parallel linear trenches 122. The lateral spacing between laterally adjacent elongated pillar structures 120 within the lateral boundaries of the overlapping trench region 124 may be greater than the lateral spacing between laterally adjacent elongated pillar structures 120 outside the lateral boundaries of the overlapping trench region 124. The overlapping trench region 124 may effectively serve as a larger critical dimension opening that is laterally adjacent to a smaller critical dimension opening (e.g., an opening defined by non-intersecting portions of the parallel linear trenches 110 and the additional parallel linear trenches 122). Accordingly, during a subsequent ARDE of the hard mask material 104, portions of the hard mask material 104 underlying the overlapping trench region 124 may be removed (e.g., vertically etched) at a different rate than other portions of the hard mask material 104 not underlying the overlapping trench region 124. This removal rate variability can enable the formation of features having regions that exhibit variable lateral dimensions throughout their height (eg, vertical dimension), as described in further detail below.

[0043] The material removal process for forming the patterned masking structure 118 may include removing the patterned masking material 106 ( Figure 2A and 2B ) of parallel line structure 108( Figure 2A and 2B ) of the material, which is not described in detail herein. For example, depending on the parallel line structure 108 ( Figure 2A and 2B ) of the material composition, the material removal process may include removing the parallel line structure 108 ( Figure 2A and 2B ) is exposed to one or more of anisotropic dry etching (e.g., reactive ion etching (RIE), deep RIE, plasma etching, reactive ion beam etching, chemically assisted ion beam etching) and anisotropic wet etching (e.g., hydrofluoric acid (HF) etching, buffered HF etching, buffered oxide etching). In addition, the mask 112 ( ) may be selectively removed after forming the patterned shielding structure 118 using one or more other conventional material removal processes (e.g., conventional wet etching processes, conventional dry etching processes) not described in detail herein. Figure 2A and 2B )'s remainder.

[0044] Next, refer to Figure 4A , the hard mask material 104 ( Figure 3A and 3B ) to form a patterned hard mask material 128. Figure 3A, the patterned hard mask material 128 may include an elongated hard mask structure 130, a first trench 132, and a second trench 134. The elongated hard mask structures 130 may be separated from each other in one lateral direction by the first trench 132, and may be separated from each other in a different lateral direction by the second trench 134. The elongated hard mask structures 130 may each individually include a first opposing side surface 121, a second opposing side surface 123, and a tip 127 (e.g., a corner, such as a radiused corner) between the first opposing side surface 121 and the second opposing side surface 123. Figure 4B is in Figure 4A The surrounding line AA ( Figure 4A ) is a simplified partial cross-sectional view of a semiconductor device structure 100.

[0045] like Figure 4A and 4B As shown in FIG. 1 , a portion of the elongated hard mask structure 130 may be formed in the hard mask material 104 ( Figure 3A and 3B ) is then positioned vertically below and within the lateral boundaries of the overlapping trench region 124 of the patterned shielding structure 118. For example, one or more portions of one or more of the first opposing side surface 121, the second opposing side surface 123, and the tip 127 of the elongated hard mask structure 130 may be vertically underlying and within the lateral boundaries of the overlapping trench region 124 of the patterned shielding structure 118. Figure 4B , portions of one or more of the first opposing side surfaces 121 of the elongated hard mask structure 130 vertically below and within the lateral boundaries of the overlapping trench region 124 may be tapered (e.g., angled) relative to the upper surface of the semiconductor material 102 such that vertically lower regions of the portions of the first opposing side surfaces 121 extend laterally inwardly (e.g., protrude laterally) farther than the area underlying the overlapping trench region 124 than vertically higher regions of the portions of the first opposing side surfaces 121. In some embodiments, portions of the first opposing side surfaces 121 of the elongated hard mask structure 130 vertically underlying and within the lateral boundaries of the overlapping trench region 124 have at least one angle less than 90°, such as an angle between about 80° and about 90°, relative to the upper surface of the semiconductor material 102. The second opposing side surfaces 123 ( Figure 4A ) and tip 127( Figure 4A) may exhibit a taper similar to that of the portion of the first opposing side surface 121 of the elongated hard mask structure 130 vertically beneath and within the lateral boundary of the overlapping trench region 124. Other portions of the first opposing side surface 121, the second opposing side surface 123, and the tip 127 of the elongated hard mask structure 130 outside the lateral boundary of the overlapping trench region 124 of the patterned shielding structure 118 may exhibit less of a taper such that the other portions have an angle closer to 90° relative to the upper surface of the semiconductor material 102. Thus, the vertical lower regions of the portion of the laterally adjacent elongated hard mask structure 130 vertically beneath and within the lateral boundary of the overlapping trench region 124 of the patterned shielding structure 118 may be closer together (e.g., less laterally separated) than the vertical lower regions of other portions of the laterally adjacent elongated hard mask structure 130 that non-vertically beneath and within the lateral boundary of the overlapping trench region 124. The tapering of the first opposing side surface 121, the second opposing side surface 123, and the tip 127 of the elongated hard mask structure 130 vertically underlying the lateral boundaries of the overlapping trench region 124 of the patterned shielding structure 118 and within the elongated hard mask structure 130 may be due to the hard mask material 104 ( Figure 3A and 3B )'s surface is relatively passivated.

[0046] Next, refer to Figure 5A , the elongated hard mask structure 130 ( Figure 4A and 4B ) covered semiconductor material 102 ( Figure 4B ) to form a patterned semiconductor material 136. Figure 5A , the patterned semiconductor material 136 may include an elongated semiconductor pillar 138, a first trench 140, and a second trench 142. The elongated semiconductor pillars 138 may be separated from each other in a first lateral direction by the first trench 140, and may be separated from each other in a second, different lateral direction by the second trench 142. The elongated semiconductor pillars 138 may each individually include a first opposing side surface 137, a second opposing side surface 139, and a tip 141 (e.g., a corner, such as a rounded corner) between the first opposing side surface 137 and the second opposing side surface 139. In addition, as shown in FIG. Figure 5A As shown in FIG. 1 , after forming the patterned semiconductor material 136, the patterned hard mask material 128 may be removed. Figure 4A and 4B ) and patterned shielding structure 118 ( Figure 4A and 4B ) (if any). Figure 5B is in Figure 5AThe surrounding line AA ( Figure 5A ) is a simplified partial cross-sectional view of a semiconductor device structure 100.

[0047] like Figure 5A , each of the elongated semiconductor pillars 138 may include a digit line (e.g., bit line) contact region 138a, and a storage node (e.g., memory cell) contact region 138b. The storage node contact region 138b may be positioned proximate to the second opposing side surface 139 of each of the elongated semiconductor pillars 138, and the digit line contact region 138a may be positioned laterally between the storage node contact regions 138b and proximate to the center of each of the elongated semiconductor pillars 138. For some elongated semiconductor pillars 138 that are laterally adjacent to each other in the X direction, the digit line contact region 138a of one of the laterally adjacent elongated semiconductor pillars 138 may be positioned laterally adjacent to one of the storage node contact regions 138b of another of the laterally adjacent elongated semiconductor pillars 138.

[0048] The storage node contact region 138b of each of the elongated semiconductor pillars 138 may each individually exhibit a larger lateral dimension than the digit line contact region 138a therebetween. The storage node contact region 138b may be wider (e.g., have a larger smaller lateral dimension) than the digit line contact region 138a, such that the first opposing side surfaces 137 of the elongated semiconductor pillars 138 are each substantially non-coplanar. The storage node contact region 138b may exhibit a larger lateral cross-sectional area relative to conventional storage node contact regions of many conventional semiconductor pillars. The lateral geometric configuration (e.g., lateral shape, lateral dimension) of the elongated semiconductor pillars 138 may increase the storage node (e.g., memory cell) alignment margin, may improve the storage node contact area, may allow for an increase in the storage node lateral dimension, and / or may reduce the risk of short circuits and junction leakage compared to conventional semiconductor pillar lateral geometric configurations. The lateral shape and lateral size of the elongated semiconductor pillar 138 (including the lateral shape and lateral size of the storage node contact region 138b and the digit line contact region 138a thereof) may correspond to the elongated hard mask structure 130 ( Figure 4A and 4B ) of the lateral shape and lateral dimensions of the vertical lowest area. Accordingly, if the parallel linear grooves 110 ( Figure 4A and 4B ) and the additional parallel linear grooves 122 ( Figure 4A and 4B ) of the patterned shielding structure 118 ( Figure 4A and 4B ) of the overlapping trench region 124 ( Figure 4A and 4B ) contributes to the lateral shape and lateral dimensions of the elongated hard mask structure 130 ( Figure 4Aand 4B ) during the ARDE effect so as to allow desired and predetermined manipulation of the lateral shape and lateral dimensions of the elongated semiconductor pillars 138.

[0049] Therefore, according to an embodiment of the present invention, a method for forming a semiconductor device includes forming a patterned shielding material above a hard mask material overlying a semiconductor material. The patterned shielding material includes parallel line structures and parallel linear grooves each extending laterally at a first angle in a range from about 30 degrees to about 75 degrees relative to a first lateral direction. A mask is provided above the patterned shielding material. The mask includes additional parallel line structures and parallel linear pores each extending laterally at a second angle different from the first angle and in a range from about 0 degrees to about 90 degrees relative to the first lateral direction. The patterned shielding material is further patterned using the mask to form a patterned shielding structure including an elongated column structure separated from each other by parallel linear grooves extending laterally at the first angle and additional parallel linear grooves extending laterally at the second angle. The overlapping area of ​​the parallel linear grooves and the additional parallel linear grooves is positioned to be laterally adjacent to the corners of the elongated column structure. The portions of the hard mask material not covered by the elongated pillar structures are subjected to aspect ratio dependent etching to form a patterned hard mask material including portions of the elongated hard mask structure exhibiting lateral boundaries of and within the parallel linear trenches and overlap regions of the additional parallel linear trenches vertically underlying the patterned shielding structure. The portions of the semiconductor material not covered by the elongated hard mask structure are removed to form a patterned semiconductor material including the elongated semiconductor pillar structures.

[0050] Furthermore, the semiconductor device according to an embodiment of the present invention comprises an elongated semiconductor pillar, each of which individually comprises a digit line contact region disposed laterally between two storage node contact regions. Each of the two storage node contact regions has a greater width than the digit line contact region.

[0051] After forming the elongated semiconductor pillars 138, the semiconductor device structure 100 may be subjected to additional processing. By way of non-limiting example, reference is made to Fig. 6A, the storage node contact region 138b and the digit line contact region 138a of each of the elongated semiconductor pillars 138 may be separated from each other by an isolation trench having a word line 143 formed therein. In addition, a storage node contact 144 may be formed in the storage node contact region 138b of the elongated semiconductor pillar 138, a digit line contact 146 may be formed in the digit line contact region 138a of the elongated semiconductor pillar 138, and a digit line 148 may be formed on or over the digit line contact 146. The word line 143 may extend in a first lateral direction (e.g., the X direction) and the digit line 148 may extend in a second, different lateral direction (e.g., the Y direction). Furthermore, one or more isolation materials (e.g., a dielectric material) may be formed in the spaces between the features of the semiconductor device structure 100 (e.g., the first trench 140, the second trench 142, the additional openings). Furthermore, as in Fig. 6A The surrounding line AA ( Fig. 6A ) is a simplified partial cross-sectional view of a semiconductor device structure 100 Figure 6B As shown in FIG. 4 , a dielectric cap structure 150 (eg, a nitride dielectric cap structure) may be formed on or over digit line contact 146 .

[0052] Word line 143, storage node contact 144, digit line contact 146, and digit line 148 may each individually be formed of and include at least one conductive material, including, but not limited to, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), and a conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium). By way of non-limiting example, word line 143, storage node contact 144, digit line contact 146, and digit line 148 may each individually include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental iridium (Ir), iridium oxide (IrO), or the like. x ), elemental ruthenium (Ru), ruthenium oxide (RuO x ), and one or more of their alloys.

[0053] The word lines 143, storage node contacts 144, digit line contacts 146, and digit lines 148 may each be formed individually using conventional processes not described in detail herein (e.g., conventional deposition processes, such as one or more of in-situ growth, spin coating, blanket coating, CVD, ALD, and PVD; conventional patterning and material removal processes, such as conventional alignment processes, conventional photolithography exposure processes, conventional development processes, conventional etching processes) and conventional processing equipment.

[0054] Next, refer to Fig. 7A A redistribution material (RDM) structure 152 (also referred to as a “redistribution layer (RDL) structure”) may be formed on or above the storage node contact 144, and a storage node structure 154 (e.g., a capacitor structure) may be formed above the RDM structure 152 and electrically connected to the RDM structure 152. Figure 7B is in Fig. 7A The surrounding line AA ( Fig. 7A ) is a simplified partial cross-sectional view of a semiconductor device structure 100.

[0055] The RDM structures 152 may be configured to effectively shift (e.g., stagger, adjust, modify) the lateral positions (e.g., along the X direction) of the storage node contacts 144 to accommodate a desired arrangement (e.g., a hexagonal close-packed arrangement) of the storage node structures 154 over and in electrical communication with the storage node contacts 144. The RDM structures 152 may each individually be formed of and include a conductive material including, but not limited to, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), and a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium). By way of non-limiting example, the RDM structures 152 may individually include TiN, TaN, WN, TiAlN, Ti, Pt, Rh, Ir, IrO, or the like. x 、Ru、RuO x , and one or more of their alloys.

[0056] The storage node structure 154 may be configured to store a charge representing a programmable logic state. For example, the charged state of the storage node structure 154 may represent a first logic state (e.g., logic 1), and the uncharged state of the storage node structure 154 may represent a second logic state (e.g., logic 0). In some embodiments, the storage node structure 154 includes a dielectric material configured to store a charge associated with a logic state. The dielectric material may, for example, include one or more of silicon dioxide, silicon nitride, polyimide, titanium dioxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (e.g., ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT), etc.), and high-k dielectric materials. In some embodiments, storage node structure 154 includes zirconium oxide.

[0057] The RDM structure 152 and the storage node structure 154 may each be formed individually using conventional processes not described in detail herein (e.g., conventional deposition processes, such as one or more of in-situ growth, spin coating, blanket coating, CVD, ALD, and PVD; conventional patterning and material removal processes, such as conventional alignment processes, conventional photolithography exposure processes, conventional development processes, conventional etching processes) and conventional processing equipment.

[0058] Return to reference Figure 5A and 5B In an additional embodiment, the semiconductor device structure 100 is formed by modifying the parallel line structure 108 ( Figure 1A and 1B ) and parallel linear grooves 110 ( Figure 1A and 1B ) of the first angle θ, and the mask 112 ( Figure 2A and 2B ) of the additional parallel line structure 114 ( Figure 2A and 2B ) and parallel linear pores 116 ( Figure 2A and 2B ) is formed to exhibit different lateral geometric configurations (e.g., different lateral shapes, different lateral dimensions) of the elongated semiconductor pillars 138. By way of non-limiting example, Figures 8A to 9E 1 is a simplified partial top view of an embodiment of a method for forming an additional semiconductor device structure of the present invention. Figures 8A to 9E Specifically, unless otherwise described below, features designated by an element number that is a 100 increment of the element number of a previously described feature (regardless of whether the previously described feature was first described before this paragraph or first described after this paragraph) will be understood to be substantially similar to the previously described feature and will also be understood to be formed in substantially the same manner as the previously described feature.

[0059] According to an additional embodiment of the present invention, Figures 8A to 8E is a simplified partial top view illustrating a method of forming a semiconductor device structure 200. Fig. 8A , semiconductor device structure 200 may include patterned masking material 206 on or over hard mask material 204. Hard mask material 204 may be positioned substantially similar to the previous reference Figure 1B On or above the semiconductor material described in the semiconductor material 102. Fig. 8A , the patterned masking material 206 may include parallel line structures 208 separated from each other by parallel linear grooves 210, wherein the configurations of the parallel line structures 208 and the parallel linear grooves 210 are substantially similar to those of the previous reference 1. Figure 1A and1B Configuration of parallel line structures 108 and parallel linear trenches 110 are depicted. In some embodiments, parallel line structures 208 and parallel linear trenches 210 are each formed at a first angle θ of about sixty-nine (69) degrees from a first lateral direction (eg, X-direction).

[0060] Next, refer to Figure 8B , a mask 212 (eg, an etching mask, a trimming mask) including additional parallel line structures 214 and parallel linear apertures 216 may be provided on or over patterned masking material 206. Additional parallel line structures 214 and parallel linear apertures 216 may be substantially similar to those described previously with reference to Figure 2A and 2B The additional parallel line structures 114 and the parallel linear apertures 116 of the mask 112 described above may be formed in the same manner as the additional parallel line structures 114 ( Figure 2A and 2B ) and parallel linear pores 116 ( Figure 2A and 2B ) is oriented at a different second angle α relative to the first lateral direction (e.g., the X direction). For example, the second angle α of the additional parallel line structure 214 and the parallel linear pores 216 may be greater than forty-one (41) degrees, such as greater than forty-one (41) degrees and less than or equal to ninety (90) degrees. In some embodiments, the second angle α of the additional parallel line structure 214 and the parallel linear pores 216 is about ninety (90) degrees. The additional parallel line structure 214 and the parallel linear pores 216 are oriented relative to the additional parallel line structure 114 ( Figure 2A and 2B ) and parallel linear pores 116 ( Figure 2A and 2B ) at different orientations (e.g., different second angles α) affect the lateral dimensions and lateral shapes of features formed from the hard mask material 204 by ARDE and the lateral dimensions and lateral shapes of features subsequently formed from semiconductor material underlying the hard mask material 204 using such features formed from the hard mask material 204, as further described in detail below.

[0061] Next, refer to Figure 8C , remain unmasked 212 ( Figure 8B ) of the additional parallel line structure 214 ( Figure 8B ) covered with patterned masking material 206 ( Fig. 8A ) of parallel line structure 208( Fig. 8A) may be subjected to at least one material removal process to form a patterned masking structure 218 including an elongated column structure 220, parallel linear grooves 210, and additional parallel linear grooves 222. The elongated column structures 220 may each exhibit a parallelogram lateral cross-sectional shape. In addition, the elongated column structures 220 may each individually include first opposing side surfaces 217 extending parallel to each other at a first angle θ, second opposing side surfaces 219 extending parallel to each other at a second angle α, and a tip 226 (e.g., a corner, such as an angled corner) intermediate the first opposing side surfaces 217 and the second opposing side surfaces 219. Figure 8C As shown in FIG. 21, mask 212 ( Figure 8B ) of parallel linear pores 216 ( Figure 8B ) relative to mask 112 ( Figure 2A and 2B ) of parallel linear pores 116 ( Figure 2A and 2B ) modifies the configuration of the intersections between the parallel linear trenches 210 and the additional parallel linear trenches 222 such that the overlapping trench regions 224 defined by the intersections exhibit different lateral dimensions and lateral positioning relative to the elongated pillar structures 220. For example, the overlapping trench regions 224 laterally between the tips 226 of laterally adjacent elongated pillar structures 220 may terminate laterally closer to the center regions of some of the laterally adjacent elongated pillar structures 220. The relatively different configurations of the overlapping trench regions 224 may, in turn, modify the lateral shapes and lateral dimensions of features subsequently formed from the hard mask material 204, as described in further detail below. For example, the modified configuration of the overlapping trench regions 224 (relative to the overlapping trench regions 124 of the patterned shielding structure 218) may modify the location and / or magnitude of regions of subsequently formed features that exhibit variable lateral dimensions throughout their height (e.g., vertical dimension).

[0062] Next, refer to Fig.8D , the elongated pillar structures 220 ( Figure 8C ) covered with a hard mask material 204 ( Figure 8C ) to form a patterned hard mask material 228 including an elongated hard mask structure 230, a first trench 232, and a second trench 234. The elongated hard mask structure 230 may each individually include a first opposing side surface 221, a second opposing side surface 223, and a tip 227 (e.g., a corner, such as a rounded corner) between the first opposing side surface 221 and the second opposing side surface 223. Fig.8D As shown in FIG. 2 , due to the overlapping trench region 224 of the patterned shielding structure 218 (relative to the previous reference Figure 4A and 4BDue to the modified configuration of the overlapping trench region 124 of the patterned shielding structure 118 described above, the portion (e.g., the vertical lower portion) of the elongated hard mask structure 230 of the patterned hard mask material 228 that extends laterally outward beyond the lateral boundaries of the elongated pillar structures 220 of the patterned shielding structure 218 may have a different lateral position, lateral shape, and lateral size than the portion (e.g., the vertical lower portion) of the elongated hard mask structure 230 that extends laterally outward beyond the lateral boundaries of the elongated pillar structures 220 of the patterned shielding structure 118. Figure 4A and 4B ) of the elongated column structure 120 ( Figure 4A and 4B ) outside the lateral boundaries of the patterned hard mask material 128 ( Figure 4A and 4B ) of the elongated column structure 120 ( Figure 4A and 4B ). For example, due to the different termination points of the overlapping trench regions 224, a region (e.g., a vertical lower region) of the first opposing side surface 221 of the elongated hard mask structure 230 positioned at the center region of the elongated hard mask structure 230 may extend laterally (e.g., protrude laterally) into the area of ​​the overlapping trench regions 224 underlying the patterned shielding structure 218.

[0063] Next, refer to Fig. 8E , the hard mask material 228 remaining unpatterned may be selectively removed ( Fig.8D ) of the elongated hard mask structure 230 ( Fig.8D ) covered semiconductor material 202 ( Fig.8D ) to form a patterned semiconductor material 236 including an elongated semiconductor pillar 238, a first trench 240, and a second trench 242. The elongated semiconductor pillars 238 may each individually include a first opposing side surface 237, a second opposing side surface 239, and a tip 241 (e.g., a corner, such as a rounded corner) between the first opposing side surface 237 and the second opposing side surface 239. In addition, the elongated semiconductor pillars 238 may each include a storage node contact region 238b adjacent to the second opposing side surface 239 thereof, and a digit line contact region 238a positioned laterally between the storage node contact regions 238b and adjacent to the center of the elongated semiconductor pillar 238. The lateral shape and lateral dimensions of the elongated semiconductor pillars 238 (including the lateral shapes and lateral dimensions of the storage node contact regions 238b and the digit line contact regions 238a thereof) may correspond to the elongated hard mask structure 230 ( Fig.8D ) is the lateral shape and lateral dimensions of the vertically lowermost portion. For example, Fig. 8E As shown in FIG. 1 , by passing through parallel linear grooves 210 ( Fig.8D ) and the patterned shielding structure 218 ( Fig.8D) of additional parallel linear grooves 222 ( Fig.8D ) is selected to control the hard mask material 204 ( Figure 8C ) ARDE, the elongated semiconductor pillar 238 can be formed, so that (before removing the elongated pillar structure 220) its storage node contact region 238b and the digit line contact region 238a portion extend outwardly to the patterned shielding structure 218 ( Fig.8D ) of the elongated column structure 220 ( Fig.8D ). (Before removing the patterned shielding structure 218) extending laterally outward to the second opposite side surface 219 ( Fig.8D ) can allow storage node contact regions 238 b of the elongated semiconductor pillars 238 to exhibit a larger lateral cross-sectional area relative to conventional storage node contact regions of many conventional semiconductor pillars. Accordingly, the lateral geometric configuration (e.g., lateral shape, lateral dimensions) of the elongated semiconductor pillars 238 can increase storage node (e.g., memory cell) alignment margins, can improve storage node contact areas, can allow for increased storage node lateral dimensions, and / or can reduce the risk of short circuits and junction leakage compared to conventional semiconductor pillar lateral geometric configurations.

[0064] After forming the elongated semiconductor pillars 238, the semiconductor device structure 200 may be subjected to additional processing as desired. The semiconductor device structure 200 may, for example, be subjected to additional processing activities previously described with respect to the semiconductor device structure 100 after forming the elongated semiconductor pillars 138 (e.g., see FIG. Figures 6A to 7B additional processing behavior described in ).

[0065] According to an additional embodiment of the present invention, Figures 9A to 9E is a simplified partial top view illustrating a method of forming a semiconductor device structure 300. Fig. 9A , semiconductor device structure 300 may include patterned masking material 306 on or over hard mask material 304. Hard mask material 304 may be positioned substantially similar to the previous reference Figure 1B On or above the semiconductor material described in the semiconductor material 102. Fig. 9A , the patterned masking material 306 may include parallel line structures 308 separated from each other by parallel linear grooves 310. The parallel line structures 308 and the parallel linear grooves 310 may be substantially similar to those previously described with reference to Figure 1A and 1B The parallel line structures 108 and the parallel linear grooves 110 of the patterned masking material 106 described above may be arranged in a manner similar to the parallel line structures 108 ( Figure 1A and 1B ) and parallel linear grooves 110 ( Figure 1A and 1B ) are oriented at different first angles θ relative to a first lateral direction (e.g., the X direction). For example, the first angle θ of the parallel line structure 308 and the parallel linear grooves 310 may be less than sixty-nine (69) degrees, such as between sixty-nine (69) degrees and zero (0) degrees. In some embodiments, the first angle θ of the parallel line structure 308 and the parallel linear grooves 310 is about forty-nine (49) degrees. The parallel line structure 308 and the parallel linear grooves 310 are oriented at different first angles θ relative to the first lateral direction (e.g., the X direction). For example, the first angle θ of the parallel line structure 308 and the parallel linear grooves 310 may be less than sixty-nine (69) degrees, such as between sixty-nine (69) degrees and zero (0) degrees. In some embodiments, the first angle θ of the parallel line structure 308 and the parallel linear grooves 310 is about forty-nine (49) degrees. Figure 1A and 1B ) and parallel linear grooves 110 ( Figure 1A and 1B ) at least partially affects the lateral dimensions and lateral shapes of features formed from the hard mask material 304 by ARDE, as well as the lateral dimensions and lateral shapes of features subsequently formed from semiconductor material underlying the hard mask material 304 using such features formed from the hard mask material 304, as further described in detail below.

[0066] Next, refer to Fig. 9B , a mask 312 (e.g., an etching mask, a trimming mask) including additional parallel line structures 314 and parallel linear apertures 316 may be provided on or over patterned masking material 306. Additional parallel line structures 314 and parallel linear apertures 316 may be substantially similar to those previously described with reference to Figure 8B 2 and 3. The additional parallel line structures 214 and parallel linear apertures 216 of the mask 212 are depicted. In some embodiments, the additional parallel line structures 314 and parallel linear apertures 316 are each formed at a second angle α that is about ninety (90) degrees away from a first lateral direction (e.g., the X direction). The orientations (e.g., second angle α) of the additional parallel line structures 314 and parallel linear apertures 316 relative to the different orientations (e.g., different first angles θ) of the parallel line structures 308 and parallel linear trenches 310 of the patterned masking material 306 affect the lateral size and lateral shape of features formed from the hard mask material 304 by ARDE, as well as the lateral size and lateral shape of features to be subsequently formed from semiconductor material underlying the hard mask material 304 using such features formed from the hard mask material 304, as described in further detail below.

[0067] Next, refer to Fig. 9C , remain unmasked 312 ( Fig. 9B ) of the additional parallel line structure 314 ( Fig. 9B ) covered with patterned masking material 306 ( Fig. 9A ) of parallel line structure 308( Fig. 9A) may be subjected to at least one material removal process to form a patterned masking structure 318 including an elongated column structure 320, parallel linear grooves 310, and additional parallel linear grooves 322. The elongated column structures 320 may each exhibit a parallelogram lateral cross-sectional shape. In addition, the elongated column structures 320 may each individually include first opposing side surfaces 317 extending parallel to each other at a first angle θ, second opposing side surfaces 319 extending parallel to each other at a second angle α, and a tip 326 (e.g., a corner, such as an angled corner) intermediate the first opposing side surfaces 317 and the second opposing side surfaces 319. Fig. 9C In the display, the parallel line structure 308 ( Fig. 9A ) and parallel linear grooves 310 ( Fig. 9A ) relative to the parallel line structure 108 ( Figure 1A and 1B ) and parallel linear grooves 110 ( Figure 1A and 1B ) of the smaller first angle θ combined with the mask 312 ( Fig. 9B ) of parallel linear pores 316 ( Fig. 9B ) relative to mask 112 ( Figure 2A and 2B ) of parallel linear pores 116 ( Figure 2A and 2B ) modifies the configuration of the intersections between the parallel linear grooves 310 and the additional parallel linear grooves 322 so that the overlapping groove regions 324 of the patterned shielding structures 318 exhibit an angle relative to the patterned shielding structures 118, 218 ( Figure 3A and 8C ) of the overlapping trench regions 124, 224 ( Figure 3A and 8C ) of different lateral shapes, lateral dimensions, and lateral positioning. For example, the overlapping groove region 324 between the tips 326 of the laterally adjacent elongated pillar structures 320 may exhibit the same lateral shapes, lateral dimensions, and lateral positioning as the overlapping groove regions 124, 224 ( Figure 3A and 8C ) and may terminate laterally closer to the second opposing side surface 319 of the elongated pillar structure 320. The relatively different configuration of the overlapping trench region 324 may, in turn, modify the lateral shape and lateral dimensions of features subsequently formed from the hard mask material 304, as described in further detail below. For example, the modified configuration of the overlapping trench region 324 (relative to the overlapping trench region 224 of the patterned shielding structure 218) may modify the location and / or magnitude of regions of subsequently formed features that exhibit variable lateral dimensions throughout their height (e.g., vertical dimension).

[0068] Next, refer to Fig.9D , the elongated pillar structures 320 ( Fig. 9C ) covered with a hard mask material 304 ( Fig. 9C ) to form a patterned hard mask material 328 including an elongated hard mask structure 330, a first trench 332, and a second trench 334. The elongated hard mask structure 330 may each individually include a first opposing side surface 321, a second opposing side surface 323, and a tip 327 (e.g., a corner, such as a rounded corner) between the first opposing side surface 321 and the second opposing side surface 323. Fig.9D As shown in FIG. 1 , due to the overlapping trench region 324 of the patterned shielding structure 318 (relative to the previous reference Figure 4A and 8D Due to the modified configuration of the overlapping trench regions 124, 224 of the patterned shielding structures 118, 218 described above, the lateral position, lateral shape, and lateral size of the portion (e.g., the vertical lower portion) of the elongated pillar structure 320 that extends laterally outward beyond the lateral boundary of the elongated pillar structure 320 of the patterned shielding structure 318 may be different from the portion (e.g., the vertical lower portion) that extends laterally outward from the lateral boundary of the elongated pillar structure 320 of the patterned shielding structure 118, 218. Figure 4A and 8D ) of the elongated column structures 120, 220 ( Figure 4A and 8D ) outside the lateral boundary of the elongated column structure 120, 220 ( Figure 4A and 8D ). For example, due to the different termination points of the overlapping trench region 324, a region (e.g., a vertically lower region) of one or more portions of the first opposing side surface 321, the second opposing side surface 323, and the tip 327 of the elongated hard mask structure 330 that is positioned at and / or proximate to the tip 327 of the elongated hard mask structure 330 may extend laterally (e.g., protrude laterally) into an area of ​​the overlapping trench region 324 underlying the patterned shielding structure 318.

[0069] Next, refer to Fig.9E , the hard mask material 328 remaining unpatterned may be selectively removed ( Fig.9D ) of the elongated hard mask structure 330 ( Fig.9D ) covered semiconductor material 302 ( Fig. 9C) to form a patterned semiconductor material 336 including an elongated semiconductor pillar 338, a first trench 340, and a second trench 342. The elongated semiconductor pillars 338 may each individually include a first opposing side surface 337, a second opposing side surface 339, and a tip 341 (e.g., a corner, such as a rounded corner) between the first opposing side surface 337 and the second opposing side surface 339. In addition, the elongated semiconductor pillars 338 may each include a storage node contact region 338b adjacent to the second opposing side surface 339 thereof, and a digit line contact region 338a positioned laterally between the storage node contact regions 338b and adjacent to the center of the elongated semiconductor pillars 338. The lateral shape and lateral dimensions of the elongated semiconductor pillars 338 (including the lateral shapes and lateral dimensions of the storage node contact regions 338b and the digit line contact regions 338a thereof) may correspond to the elongated hard mask structure 330 ( Fig.9D ) is the lateral shape and lateral dimensions of the vertically lowermost portion. For example, Fig.9E As shown in FIG. 1 , by passing through parallel linear grooves 310 ( Fig.9D ) and the patterned shielding structure 318 ( Fig.9D ) of additional parallel linear grooves 322 ( Fig.9D ) is selected to control the hard mask material 304 ( Fig. 9C ) ARDE, the elongated semiconductor pillar 338 can be formed, so that (before removing the elongated pillar structure 320) a portion of the storage node contact region 338b extends outwardly to the patterned shielding structure 318 ( Fig.9D ) of the elongated column structure 320 ( Fig.9D ) and the digit line contact region 338a is substantially confined to the lateral boundary of the elongated pillar structure 320 ( Fig.9D ). Extends laterally outwardly (before removing patterned shielding structure 318) to a position at or immediately adjacent to tip 326 ( Fig.9D ) of the elongated column structure 320 ( Fig.9D ) of the first opposite side surface 317 ( Fig.9D ), the second opposite side surface 319 ( Fig.9D ), and tip 326 ( Fig.9D ) can allow storage node contact regions 338 b of the elongated semiconductor pillars 338 to exhibit a larger lateral cross-sectional area relative to conventional storage node contact regions of many conventional semiconductor pillars. Accordingly, the lateral geometric configuration (e.g., lateral shape, lateral dimensions) of the elongated semiconductor pillars 338 can increase storage node (e.g., memory cell) alignment margins, can improve storage node contact areas, can allow for increased storage node lateral dimensions, and / or can reduce the risk of short circuits and junction leakage, compared to conventional semiconductor pillar lateral geometric configurations.

[0070] After forming the elongated semiconductor pillars 338, the semiconductor device structure 300 may be subjected to additional processing as desired. The semiconductor device structure 300 may, for example, be subjected to additional processing activities previously described with respect to the semiconductor device structure 100 after forming the elongated semiconductor pillars 138 (e.g., see FIG. Figures 6A to 7B additional processing behavior described in ).

[0071] Fig.10 1 is a functional block diagram of a memory device 400 according to an embodiment of the present invention. The memory device 400 may include, for example, an embodiment of the semiconductor device structure 100 previously described herein. Fig.10 4, a memory device 400 may include a memory cell 402, a digit line 404 (eg, corresponding to Figures 6A to 7B The semiconductor device structure 100 shown in FIG. 1 includes a digital line 148 and a word line 406 (eg, corresponding to Fig. 6A and 7A ), a row decoder 408, a column decoder 410, a memory controller 412, a sensing device 414, and an input / output device 416 of the semiconductor device structure 100 shown in FIG.

[0072] The memory cells 402 of the memory device 400 are programmable to at least two different logic states (e.g., logic 0 and logic 1). Each memory cell 402 may individually include a capacitor and a transistor (e.g., a pass transistor). The capacitor stores a charge representing the programmable logic state of the memory cell 402 (e.g., a charged capacitor may represent a first logic state, such as logic 1; and an uncharged capacitor may represent a second logic state, such as logic 0). The transistor grants access to the capacitor to perform operations (e.g., read, write, rewrite) on the capacitor when a minimum threshold voltage is applied (e.g., through one of the word lines 406) to its semiconductor channel.

[0073] The digit line 404 is connected to the capacitor of the memory cell 402 (eg, corresponding to Fig. 7A and 7B404). The word lines 406 extend perpendicular to the digit lines 404 and are connected to the gates of the transistors of the memory cells 402. Operations may be performed on the memory cells 402 by activating the appropriate digit lines 404 and word lines 406. Activating the digit lines 404 or word lines 406 may include applying a voltage potential to the digit lines 404 or word lines 406. Each column of the memory cells 402 may be individually connected to one of the digit lines 404, and each row of the memory cells 402 may be individually connected to one of the word lines 406. Individual memory cells 402 may be addressed and accessed through intersections (e.g., cross points) of the digit lines 404 and word lines 406.

[0074] The memory controller 412 may control the operation of the memory cell 402 through various components including a row decoder 408, a column decoder 410, and a sensing device 414. The memory controller 412 may generate row address signals that are directed to the row decoder 408 to activate (e.g., apply a voltage potential to) predetermined word lines 406, and may generate column address signals that are directed to the column decoder 410 to activate (e.g., apply a voltage potential to) predetermined digit lines 404. The memory controller 412 may also generate and control various voltage potentials employed during operation of the memory device 400. In general, the amplitude, shape, and / or duration of the applied voltage may be adjusted (e.g., changed), and may be different for various operations of the memory device 400.

[0075] During use and operation of the memory device 400, after being accessed, the memory cell 402 may be read (e.g., sensed) by the sensing device 414. The sensing device 414 may compare the signal (e.g., voltage) of the appropriate digital line 404 with a reference signal in order to determine the logic state of the memory cell 402. If, for example, the digital line 404 has a higher voltage than the reference voltage, the sensing device 414 may determine that the stored logic state of the memory cell 402 is a logic 1, and vice versa. The sensing device 414 may include transistors and amplifiers to detect and amplify the difference in the signal (often referred to as "latching" in the art). The detected logic state of the memory cell 402 may be output to the input / output device 416 by the column decoder 410. In addition, the memory cell 402 may be set (e.g., written) by similarly activating the appropriate word line 406 and the appropriate digital line 404 of the memory device 400. By controlling the digital lines 404 when the word lines 406 are activated, the memory cells 402 can be set (e.g., a logic value can be stored in the memory cells 402). The column decoder 410 can accept data from the input / output device 416 to be written to the memory cells 402. In addition, the memory cells 402 can also be refreshed (e.g., recharged) by reading the memory cells 402. The read operation places the contents of the memory cells 402 on the appropriate digital lines 404, which are then pulled up to a full level (e.g., fully charged or discharged) by the sensing device 414. When the word line 406 associated with the memory cell 402 is deactivated, all memory cells 402 in the row associated with the word line 406 are restored to a full charge or discharge.

[0076] Therefore, a memory device according to an embodiment of the present invention includes a memory controller, a row decoder, a column decoder, a word line, a digital line, a memory cell, and an elongated semiconductor column. The row decoder is operably coupled to the memory controller. The column decoder is operably coupled to the memory controller. The word line is operably coupled to the row decoder. The digital line is operably coupled to the column decoder. The memory cell is positioned adjacent to the intersection of the word line and the digital line, and includes a storage node structure and an access device electrically connected to the storage node structure. The elongated semiconductor column is operably coupled to the storage node structure memory cell and the digital line. The elongated semiconductor column each includes a storage node contact area, and a digital line contact area laterally between the memory cell contact areas and exhibiting a narrower width than the memory cell contact area.

[0077] The semiconductor device structures (eg, semiconductor device structures 100, 200, 300) and semiconductor devices (eg, memory device 400) according to embodiments of the present invention may be used in embodiments of electronic systems of the present invention. For example, Fig.115 is a block diagram of an illustrative electronic system 500 according to an embodiment of the invention. The electronic system 500 may include, for example, a computer or computer hardware component, a server or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular enabled tablet computer (e.g., or The electronic system 500 includes at least one memory device 502. The memory device 502 may include, for example, one or more embodiments of the semiconductor device structures (e.g., semiconductor device structures 100, 200, 300) and semiconductor devices (e.g., memory device 400) previously described herein. The electronic system 500 may further include at least one electronic signal processor device 504 (commonly referred to as a "microprocessor"). The electronic signal processor device 504 may optionally include embodiments of the semiconductor device structures (e.g., semiconductor device structures 100, 200, 300) and semiconductor devices (e.g., memory device 400) previously described herein. The electronic system 500 may further include one or more input devices 506 for inputting information into the electronic system 500 by a user, such as, for example, a mouse or other pointer device, a keyboard, a touch pad, a button, or a control panel. The electronic system 500 may further include one or more output devices 508 for outputting information (e.g., visual or audio output) to a user, such as, for example, a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 506 and the output device 508 may include a single touch screen device that can be used to input information to the electronic system 500 and output visual information to the user. The input device 506 and the output device 508 may be in electrical communication with one or more of the memory device 502 and the electronic signal processor device 504.

[0078] Thus, an electronic system according to an embodiment of the present invention comprises an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device comprises at least one elongated semiconductor pillar, the at least one elongated semiconductor pillar comprising a digit line contact region, and storage node contact regions laterally flanking the digit line contact region. Each of the storage node contact regions individually exhibits a larger lateral cross-sectional area than the digit line contact region.

[0079] The method of the present invention provides an efficient and reliable way to manipulate the size, shape, and spacing of features (e.g., elongated semiconductor pillars 138, 238, 338) of semiconductor device structures (e.g., semiconductor device structures 100, 200, 300) of semiconductor devices (e.g., memory devices, such as DRAM devices) using the ARDE effect. The method facilitates simple and cost-effective formation and alignment of digit line contacts and storage node contacts, wherein the risk of shorts and junction leakage is reduced compared to conventional methods of forming and aligning digit line contacts and storage node contacts of semiconductor device structures. Compared to conventional methods of forming and aligning contacts (e.g., digit line contacts, storage node contacts) of semiconductor device structures, the method of the present invention can facilitate improved device performance, lower cost, increased miniaturization of components, improved pattern quality, and greater packaging density.

[0080] Additional non-limiting example embodiments of the invention are described below.

[0081] Embodiment 1: A method of forming a device, the method comprising: forming a patterned shielding material over a hard mask material overlying a semiconductor material, the patterned shielding material comprising parallel line structures and parallel linear grooves each extending laterally at a first angle in a range from about 30 degrees to about 75 degrees relative to a first lateral direction; providing a mask over the patterned shielding material, the mask comprising additional parallel line structures and parallel linear pores each extending laterally at a second angle different from the first angle and in a range from about 0 degrees to about 90 degrees relative to the first lateral direction; further patterning the patterned shielding material using the mask to form a device comprising the parallel linear grooves extending laterally at the first angle; and a patterned shielding structure of an elongated columnar structure separated from each other by additional parallel linear trenches extending laterally at the second angle, wherein the overlapping region of the parallel linear trenches and the additional parallel linear trenches is positioned to be laterally adjacent to the corner of the elongated columnar structure; subjecting the portion of the hard mask material not covered by the elongated columnar structure to aspect ratio-dependent etching to form a patterned hard mask material of an elongated hard mask structure including a portion thereof exhibiting lateral boundaries of and within the overlapping region of the parallel linear trenches and the additional parallel linear trenches vertically underlying the patterned shielding structure; and removing the portion of the semiconductor material not covered by the elongated hard mask structure to form a patterned semiconductor material including an elongated semiconductor columnar structure.

[0082] Embodiment 2: The method of Embodiment 1, wherein forming the patterned masking material comprises selecting the first angle to be approximately 69 degrees relative to the first lateral direction.

[0083] Embodiment 3: The method of one of embodiments 1 and 2, wherein providing a mask over the patterned masking material comprises selecting the second angle to be within a range from about 41 degrees to about 90 degrees relative to the first lateral direction.

[0084] Embodiment 4: The method of Embodiment 1, wherein forming a patterned masking material comprises selecting the first angle to be approximately 41 degrees relative to the first lateral direction.

[0085] Embodiment 5: The method of one of embodiments 1 and 4, wherein providing a mask over the patterned masking material comprises selecting the second angle to be less than or equal to approximately 90 degrees relative to the first lateral direction.

[0086] Embodiment 6: The method of any one of embodiments 1 to 5, wherein further patterning the patterned masking material using the mask to form a patterned masking structure comprising elongated pillar structures comprises forming each of the elongated pillar structures to exhibit a parallelogram lateral cross-sectional shape.

[0087] Embodiment 7: A method according to any one of embodiments 1 to 6, wherein subjecting the portion of the hard mask material not covered by the elongated pillar structure to aspect ratio-dependent etching includes forming lateral boundaries of the overlapping regions of the parallel linear grooves and the additional parallel linear grooves vertically underlying the patterned shielding structure and the portion of the elongated hard mask structure therein to exhibit tapered sidewalls.

[0088] Embodiment 8: The method according to Embodiment 7 further includes forming other portions of the elongated hard mask structure outside the lateral boundaries of the overlapping areas of the parallel linear grooves and the additional parallel linear grooves of the patterned shielding structure to exhibit less tapered sidewalls than those of the portions of the elongated hard mask structure.

[0089] Embodiment 9: A method according to any one of embodiments 1 to 8, wherein removing portions of the semiconductor material not covered by the elongated hard mask structure to form a patterned semiconductor material includes forming each of the elongated semiconductor pillar structures to individually include a first contact region laterally disposed between relatively wider second contact regions.

[0090] Embodiment 10: A method according to any one of embodiments 1 to 9, wherein removing the portion of the semiconductor material not covered by the elongated hard mask structure includes forming the elongated semiconductor pillar structure to exhibit a lateral shape and lateral dimensions substantially similar to the vertical lowermost region of the elongated hard mask structure.

[0091] Embodiment 11: The method according to any one of embodiments 1 to 10 further includes: forming a digital line contact at a lateral center position of an elongated semiconductor pillar structure; forming a storage node contact located on the flank of the digital line contact and adjacent to the end of the elongated semiconductor pillar structure; forming a digital line electrically connected to the digital line contact; forming a word line extending laterally in a direction different from the digital line; and forming a storage node structure electrically connected to the storage node contact and positioned adjacent to the intersection of the digital line and the word line.

[0092] Embodiment 12: The method according to Embodiment 11 further includes forming a redistribution structure electrically connected to the storage node contact and the storage node structure and extending therebetween, wherein an upper portion of the redistribution structure underlies the storage node structure and is laterally offset from a lower portion of the redistribution structure overlying the storage node contact.

[0093] Embodiment 13: A device comprising elongated semiconductor pillars each individually comprising a digit line contact region disposed laterally between two storage node contact regions, each of the two storage node contact regions having a greater width than the digit line contact region.

[0094] Embodiment 14: The device according to embodiment 13 further comprises: a first groove adjacent to a first relative side surface of the elongated semiconductor column and oriented at a first angle in a range from about 30 degrees to about 75 degrees from the first lateral direction; and a second groove adjacent to a second relative side surface of the elongated semiconductor column and oriented at a second different angle in a range from about 0 degrees to about 90 degrees from the first lateral direction.

[0095] Embodiment 15: The device of Embodiment 14, wherein the first opposing side surface and the second opposing side surface of each of the elongated semiconductor pillars are substantially perpendicular.

[0096] Embodiment 16: The device of one of embodiments 14 and 15, wherein at least the first opposing side surface of each of the elongated semiconductor pillars is substantially non-planar.

[0097] Embodiment 17: The device of any of embodiments 14 to 16, wherein the first angle is approximately 69 degrees and the second angle is approximately 41 degrees.

[0098] Embodiment 18: The device of any of Embodiments 14 to 16, wherein the first angle is approximately 69 degrees and the second angle is approximately 90 degrees.

[0099] Embodiment 19: The device of any one of embodiments 14 to 16, wherein the first angle is about 49 degrees and the second angle is about 90 degrees.

[0100] Embodiment 20: The device of any one of embodiments 13 to 19, further comprising: a digit line contact located in the digit line contact region of each of the elongated semiconductor pillar structures; a storage node contact located in the two storage node contact regions of each of the elongated semiconductor pillar structures; a digit line electrically connected to the digit line contact of each of the elongated semiconductor pillar structures; a word line extending laterally in a direction different from that of the digit line; and a storage node structure electrically connected to the storage node contact and positioned proximate to the intersection of the digit line and the word line.

[0101] Embodiment 21: The device according to Embodiment 20 further comprises a redistribution structure electrically connected to the storage node contact and the storage node structure and extending therebetween, wherein an upper portion of the redistribution structure underlies the storage node structure and is laterally offset from a lower portion of the redistribution structure overlying the storage node contact.

[0102] Embodiment 22: A memory device comprising: a memory controller; a row decoder operably coupled to the memory controller; a column decoder operably coupled to the memory controller; a word line operably coupled to the row decoder; a digit line operably coupled to the column decoder; a digit line operably coupled to the column decoder; a memory cell positioned proximate to the intersection of the word line and the digit line, the memory cell comprising a storage node structure and an access device electrically connected to the storage node structure; and an elongated semiconductor pillar operably coupled to the storage node structure memory cell and the digit line, and each comprising: a storage node contact region; and a digit line contact region laterally disposed between the memory cell contact regions and exhibiting a narrower width than the memory cell contact regions.

[0103] Embodiment 23: The memory device of Embodiment 22, wherein the elongated semiconductor pillars extend laterally at an angle of approximately 69 degrees from the direction in which the word lines extend laterally.

[0104] Embodiment 24: The memory device of Embodiment 22, wherein the elongated semiconductor pillars extend laterally at an angle of approximately 49 degrees from the direction in which the word lines extend laterally.

[0105] Embodiment 25: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one elongated semiconductor pillar, the at least one elongated semiconductor pillar comprising: a digit line contact region; and storage node contact regions laterally located on either side of the digit line contact region, each of the storage node contact regions individually exhibiting a larger lateral cross-sectional area than the digit line contact region.

[0106] Although the present invention is susceptible to various modifications and alternative forms, specific embodiments have been shown in the drawings by way of example and have been described in detail herein. However, the present invention is not intended to be limited to the specific forms disclosed. Specifically, the present invention will cover all modifications, equivalents, and substitutions that fall within the scope of the present invention as defined by the appended claims and their legal equivalents.

Claims

1. A method for forming a semiconductor device, comprising: forming a patterned masking material over the hard mask material overlying the semiconductor material, the patterned masking material comprising parallel line structures and parallel linear trenches each extending laterally at a first angle in a range from 30 degrees to 75 degrees relative to a first lateral direction; providing a mask over the patterned masking material, the mask comprising additional parallel line structures and parallel linear apertures each extending laterally at a second angle different from the first angle and in a range from 0 degrees to 90 degrees relative to the first lateral direction, the parallel linear apertures of the mask overlapping some of the parallel linear trenches of the patterned masking material; further patterning the patterned masking material using the mask to form a patterned masking structure including elongated pillar structures separated from each other by the parallel linear trenches extending laterally at the first angle and additional parallel linear trenches extending laterally at the second angle, wherein overlapping regions of the parallel linear trenches and the additional parallel linear trenches are positioned laterally adjacent to corners of the elongated pillar structures; subjecting portions of the hard mask material not covered by the elongated pillar structures to an aspect ratio dependent etch to form a patterned hard mask material including portions of the elongated hard mask structure exhibiting lateral boundaries of the parallel linear trenches and the overlap region of the additional parallel linear trenches vertically underlying the patterned shielding structure; and removing portions of the semiconductor material not covered by the elongated hard mask structure to form a patterned semiconductor material including elongated semiconductor pillar structures, Wherein removing portions of the semiconductor material not covered by the elongated hard mask structures to form patterned semiconductor material includes forming each of the elongated semiconductor pillar structures to individually include a first contact region laterally between relatively wider second contact regions.

2. The method according to claim 1, wherein: forming the patterned masking material comprises selecting the first angle to be 69 degrees relative to the first lateral direction; and Providing a mask over the patterned masking material includes selecting the second angle to be within a range from 41 degrees to 90 degrees relative to the first lateral direction.

3. The method according to claim 1, wherein: forming the patterned masking material comprises selecting the first angle to be 41 degrees relative to the first lateral direction; and Providing a mask over the patterned masking material includes selecting the second angle to be less than or equal to 90 degrees relative to the first lateral direction.

4. The method of any one of claims 1 to 3, wherein further patterning the patterned masking material using the mask to form a patterned masking structure including elongated pillar structures comprises: Each of the elongated column structures is formed to exhibit a parallelogram lateral cross-sectional shape.

5. The method of any one of claims 1 to 3, wherein subjecting portions of the hard mask material not covered by the elongated pillar structures to an aspect ratio dependent etch comprises: The portion of the elongated hard mask structure vertically underlying the parallel linear trenches of the patterned shielding structure and within lateral boundaries of the overlapping regions of the additional parallel linear trenches is formed to exhibit tapered sidewalls.

6. The method according to claim 5, further comprising: Other portions of the elongated hard mask structure outside the lateral boundaries of the overlapping regions of the parallel linear trenches and the additional parallel linear trenches of the patterned shielding structure are formed to exhibit less tapered sidewalls than the portions of the elongated hard mask structure.

7. The method of any one of claims 1 to 3, wherein removing portions of the semiconductor material not covered by the elongated hard mask structure comprises: The elongated semiconductor pillar structures are formed to exhibit lateral shapes and lateral dimensions substantially similar to the vertically lowermost regions of the elongated hard mask structures.

8. The method according to any one of claims 1 to 3, further comprising: forming a digit line contact at a lateral center of the elongated semiconductor pillar structure; forming a storage node contact flanking the digit line contact and proximate to an end of the elongated semiconductor pillar structure; forming a digit line in electrical communication with the digit line contact; forming a word line extending laterally in a direction different from the digit line; and A storage node structure is formed in electrical communication with the storage node contact and positioned proximate to the intersection of the digit line and the word line.

9. The method according to claim 8, further comprising: A redistribution structure is formed that is electrically connected to the storage node contact and the storage node structure and extends therebetween, wherein an upper portion of the redistribution structure underlies the storage node structure and is laterally offset from a lower portion of the redistribution structure that overlies the storage node contact.

10. A semiconductor device comprising: An elongated semiconductor pillar, each individually comprising a digit line contact region disposed laterally between two storage node contact regions, each of the two storage node contact regions having a greater width than the digit line contact region, the elongated semiconductor pillar comprising: first opposing side surfaces, each of which is separated from an adjacent first opposing side surface by a first groove; and The second opposing side surfaces are each separated from an adjacent second opposing side surface by a second groove.

11. The semiconductor device according to claim 10, wherein: The first groove is oriented at a first angle ranging from 30 degrees to 75 degrees from the first lateral direction; and The second groove is oriented at a second different angle ranging from 0 degrees to 90 degrees from the first lateral direction. 12 . The semiconductor device of claim 11 , wherein the first opposing side surface and the second opposing side surface of each of the elongated semiconductor pillars are substantially vertical. 13 . The semiconductor device of claim 12 , wherein at least the first opposing side surface of each of the elongated semiconductor pillars is substantially non-planar. 14 . The semiconductor device of claim 11 , wherein the first angle is 69 degrees and the second different angle is 41 degrees. 15 . The semiconductor device of claim 11 , wherein the first angle is 69 degrees and the second different angle is 90 degrees. 16 . The semiconductor device of claim 11 , wherein the first angle is 49 degrees and the second different angle is 90 degrees.

17. The semiconductor device according to any one of claims 10 to 16, further comprising: a digit line contact at the digit line contact region of each of the elongated semiconductor pillars; a storage node contact at the two storage node contact regions of each of the elongated semiconductor pillars; a digit line in electrical communication with the digit line contact of each of the elongated semiconductor pillars; a word line extending laterally in a different direction than the digit line; storage node structures individually in electrical communication with the storage node contacts and positioned proximate to intersections of the digit lines and the word lines; and A redistribution structure is electrically connected to the storage node contacts and the storage node structure and extends therebetween, wherein an upper portion of the redistribution structure underlies the storage node structure and laterally deviates from a lower portion of the redistribution structure overlying the storage node contacts.

18. A memory device comprising: Memory controller; a row decoder operably coupled to the memory controller; a column decoder operably coupled to the memory controller; a word line operably coupled to the row decoder; a digital line operatively coupled to the column decoder; a memory cell positioned proximate to an intersection of the word line and the digit line, the memory cell comprising a storage node structure and an access device electrically connected to the storage node structure; and The elongated semiconductor pillar of the device of claim 10, operably coupled to the storage node structure and the digit line of the memory cell.

19. An electronic system comprising: Input device; Output device; a processor device operatively coupled to the input device and the output device; and The device of claim 10, operatively coupled to the processor device.

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