Half-tone mask and thin film transistor array substrate manufacturing method
By using a specific design halftone mask plate in the process of thin film transistor array substrate, the etching of the photoresist layer is solved, and the electrostatic release effect and yield rate are improved.
Patent Information
- Application Number
- CN202011393349.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-02
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2040-12-02
AI Technical Summary
There is often a problem of over-etching of the electrostatic ring in the halftone mask process of existing TFT array substrates, resulting in failure of the electrostatic ring, poor electrostatic release effect and low yield.
Using a specific halftone mask plate, the fully transmitted area, shading area and semi-transmissive area are set in the process of thin film transistor array substrate, and the transmittance of incident light is controlled to define The pattern of the electrostatic ring prevents excessive etching of the photoresist layer and ensures the integrity of the electrostatic ring.
It effectively improves the electrostatic release effect of the TFT array substrate, improves the yield rate, prevents excessive etching of the semiconductor layer, and ensures the effectiveness of the electrostatic ring.
Smart Images
Figure CN112526818B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of liquid crystal displays, and in particular to a method for manufacturing a half-tone mask and a thin film transistor array substrate. Background Art
[0002] With the rapid development of color display, the colorization trend of LCD (liquid crystal display) is in the ascendant. The market share of color LCD (liquid crystal display) increases year by year. In order to reduce production costs, increase corporate profits and enhance market competitiveness. Halftone mask (Half Tone Mask, also called halftone mask) is more and more widely used in the production process of liquid crystal display. By using halftone mask, the processes completed by two exposure processes are combined into one, saving one exposure process, shortening the production cycle, improving production efficiency, reducing production costs, and improving market competitiveness.
[0003] However, in the existing TFT (Thin Film Transistor) half-tone mask process, there is often a problem of over-etching of the electrostatic ring on the TFT array substrate, which leads to failure of the electrostatic ring on the TFT array substrate, poor electrostatic release effect of the TFT array substrate, and low yield rate. Summary of the invention
[0004] The main purpose of the present application is to provide a half-tone mask and a thin film transistor array substrate manufacturing method that can improve the electrostatic discharge effect of a TFT array substrate and improve the yield rate.
[0005] To achieve the above-mentioned purpose, the half-tone mask proposed in the present application is applied to the manufacturing process of a thin film transistor array substrate, and the half-tone mask is provided with a pattern for etching an electrostatic ring on the gate of a thin film transistor, and the half-tone mask is divided into:
[0006] The fully transparent area is used to define the outer structure of the electrostatic ring;
[0007] at least two light shielding areas, spaced apart from each other, for defining the connection end of the electrostatic ring; and
[0008] A semi-transparent area, provided between at least two of the light-shielding areas, for defining the pattern of the electrostatic ring;
[0009] The transmittance of the semi-transparent area to the incident light used in the process is 25%-40%.
[0010] In some embodiments, the transmittance of the semi-transparent region to the incident light used in the process is 30%-35%.
[0011] In some embodiments, the orthographic projection of the semi-transparent area is a closed figure, and the closed figure has a first width and a first length, the first width corresponds to the width of the groove of the photoresist layer formed on the substrate after etching by incident light, and the first length corresponds to the length of the groove of the photoresist layer formed on the substrate after etching by incident light.
[0012] In some embodiments, the first width is 3.0um-5.0um, and the first length is 30um-60um.
[0013] In some embodiments, the first width is 3.5um-4.8um, and the first length is 35um-55um.
[0014] In some embodiments, the closed figure has at least a first side, a second side, a third side and a fourth side, the first side and the second side extend along the first length direction, the third side and the fourth side extend along the first width direction, the ends of the first side and the second side extending toward the third side extend toward the outside of the closed figure and are connected to the third side, and the ends of the first side and the second side extending toward the fourth side extend toward the outside of the closed figure and are connected to the fourth side, so that the closed figure is I-shaped as a whole.
[0015] In some embodiments, the closed figure also has a second length consistent with the first length direction, the second length is the length from the end of the first side extending to the third side and the fourth side, and the second length is the length from the end of the second side extending to the third side and the fourth side, and the second length is 2.0um-3.5um.
[0016] The present application also proposes a half-tone mask, which is applied to the manufacturing process of a thin film transistor array substrate. The half-tone mask is provided with a pattern for etching an electrostatic ring on a gate of a thin film transistor. The half-tone mask is divided into:
[0017] The fully transparent area is used to define the outer structure of the electrostatic ring;
[0018] at least two light shielding areas, spaced apart from each other, for defining the connection end of the electrostatic ring; and
[0019] A semi-transparent area, provided between at least two of the light-shielding areas, for defining the pattern of the electrostatic ring;
[0020] Wherein, the transmittance of the semi-transparent area to the incident light used in the process is 30%-35%;
[0021] The orthographic projection of the semi-transparent area is a closed figure, and the closed figure has a first width and a first length, the first width corresponds to the width of the groove of the photoresist layer formed on the substrate after etching by incident light, and the first length corresponds to the length of the groove of the photoresist layer formed on the substrate after etching by incident light;
[0022] The first width is 3.5um-4.8um, and the first length is 35um-55um;
[0023] The closed figure has at least a first side, a second side, a third side and a fourth side, the first side and the second side extend along the first length direction, the third side and the fourth side extend along the first width direction, the ends of the first side and the second side extending toward the third side extend toward the outside of the closed figure and are connected to the third side, and the ends of the first side and the second side extending toward the fourth side extend toward the outside of the closed figure and are connected to the fourth side, so that the closed figure is I-shaped as a whole.
[0024] The present application also provides a method for manufacturing a thin film transistor array substrate, comprising:
[0025] S1. providing a substrate, depositing a gate metal layer on the substrate, and performing a patterning process on the gate metal layer to obtain a gate layer;
[0026] S2, depositing a gate insulating layer and a semiconductor layer on the gate layer and the substrate in sequence, and performing ion doping treatment on the semiconductor layer to form an ohmic contact layer on the upper surface of the semiconductor layer;
[0027] S3, depositing a source-drain metal layer on the semiconductor layer, coating a photoresist layer on the source-drain metal layer, and exposing the photoresist layer using the aforementioned half-tone mask;
[0028] S4, etching the source and drain metal layer, and partially etching the ohmic contact layer on the upper surface of the semiconductor layer to obtain source and drain electrodes;
[0029] S5, connecting one end of the wire to the source electrode, and connecting the other end of the wire to the drain electrode, and extending the wire to the outside of the array substrate to form an electrostatic ring.
[0030] The present application sets the transmittance of the incident light used in the manufacturing process of the thin film transistor array substrate in the semi-transparent area to 25%-40%, thereby reducing the etching of the photoresist layer on the gate of the thin film transistor by the incident light through the half-tone mask, so that sufficient photoresist is retained in the groove of the photoresist layer. Sufficient photoresist in the groove of the photoresist layer will prevent the semiconductor layer on the substrate from being over-etched in the subsequent process, resulting in the disconnection and failure of the electrostatic ring. Thereby improving the electrostatic discharge effect of the TFT array substrate and improving the yield rate. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.
[0032] Figure 1 A schematic plan view of an embodiment of a half-tone mask of the present application;
[0033] Figure 2 A cross-sectional schematic diagram of an embodiment of a half-tone mask of the present application;
[0034] Figure 3 It is a structural schematic diagram of an embodiment of step S1 of the method for manufacturing a thin film transistor array substrate of the present application;
[0035] Figure 4 This is a structural schematic diagram of an embodiment of step S2 of the method for manufacturing a thin film transistor array substrate of the present application;
[0036] Figure 5 It is a structural schematic diagram of an embodiment of step S3 of the method for manufacturing a thin film transistor array substrate of the present application;
[0037] Figure 6 Another structural schematic diagram of an embodiment of step S3 of the method for manufacturing a thin film transistor array substrate of the present application;
[0038] Figure 7 It is a structural schematic diagram of an embodiment of step S4 of the method for manufacturing a thin film transistor array substrate of the present application;
[0039] Figure 8 Another structural schematic diagram of an embodiment of step S4 of the method for manufacturing a thin film transistor array substrate of the present application;
[0040] Fig. 9 It is a structural schematic diagram of an embodiment of step S6 of the method for manufacturing a thin film transistor array substrate of the present application;
[0041] Fig.10 It is a structural schematic diagram of an embodiment of step S7 of the method for manufacturing a thin film transistor array substrate of the present application;
[0042] Fig.11 It is a structural schematic diagram of a thin film transistor array substrate in a conventional thin film transistor manufacturing process.
[0043] Description of Figure Numbers:
[0044]
[0045]
[0046] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0048] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0049] In this application, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0050] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.
[0051] Please refer to Figures 1 to 3 In an embodiment of the present application, the halftone mask 100 includes:
[0052] A half-tone mask is used in the manufacturing process of a thin film transistor array substrate. The half-tone mask is provided with a pattern for etching an electrostatic ring on a gate of a thin film transistor. The half-tone mask is divided into:
[0053] The fully transparent region 10 is used to define the outer structure of the electrostatic ring;
[0054] At least two light shielding areas 20 are spaced apart from each other and are used to define the connection ends of the electrostatic loop; and
[0055] A semi-transparent area 30, provided between at least two of the light-shielding areas 20, for defining the pattern of the electrostatic ring;
[0056] The transmittance of the semi-transparent area 30 to the incident light used in the process is 25%-40%.
[0057] The above-mentioned “fully light-transmitting area 10” refers to an area that allows incident light to fully transmit, the above-mentioned “light-shielding area 20” refers to an area that does not allow incident light to transmit, and the above-mentioned “semi-light-transmitting area 30” refers to an area that allows incident light to partially transmit.
[0058] The present application sets the transmittance of the semi-transparent area 30 to the incident light used in the process of the thin film transistor array substrate to 25%-40%, thereby reducing the etching of the photoresist layer on the gate of the thin film transistor by the incident light through the half-tone mask, so that sufficient photoresist is retained in the groove of the photoresist layer. Sufficient photoresist in the groove of the photoresist layer will prevent the semiconductor layer on the substrate from being over-etched in the subsequent process, resulting in the disconnection and failure of the electrostatic ring. Thereby improving the electrostatic discharge effect of the TFT array substrate and improving the yield rate.
[0059] Furthermore, in some embodiments, the transmittance of the semi-transparent area 30 to the incident light used in the process is 30%-35%. In a preferred embodiment, the transmittance of the semi-transparent area 30 to the incident light used in the process is 30%. At this time, there is enough photoresistance retained in the groove of the photoresist layer, and the sufficient photoresistance in the groove of the photoresist layer will prevent the semiconductor layer on the substrate from being over-etched in the subsequent process, resulting in the disconnection and failure of the electrostatic ring. The TFT array substrate has a better electrostatic release effect and a high yield rate of the TFT array substrate.
[0060] For details, please refer to Figure 1 In some embodiments, the orthographic projection of the semi-transparent area 30 is a closed figure, and the closed figure has a first width W1 and a first length L1, the first width W1 corresponds to the width of the groove of the photoresist layer formed on the substrate after the incident light etching, and the first length L1 corresponds to the length of the groove of the photoresist layer formed on the substrate after the incident light etching.
[0061] The closed pattern is a projection pattern formed when parallel incident light is incident perpendicularly to the semi-transparent area 30 (ie, a pattern during orthographic projection), or a pattern observed when the half-tone mask is observed from a top-down perspective.
[0062] Please refer to Figure 1 In some embodiments, the closed figure has at least a first side 31, a second side 32, a third side 33 and a fourth side 34, the first side 31 and the second side 32 extend along the first length L1 direction, the third side 33 and the fourth side 34 extend along the first width W1 direction, the ends of the first side 31 and the second side 32 extending to the third side 33 extend to the outside of the closed figure and are connected to the third side 33, and the ends of the first side 31 and the second side 32 extending to the fourth side 34 extend to the outside of the closed figure and are connected to the fourth side 34, so that the closed figure is I-shaped as a whole. Specifically, the ends of the first side 31 and the second side 32 are connected to the third side 33 in a straight line, and the ends of the first side 31 and the second side 32 are connected to the fourth side 34 in a straight line. It can be understood that in other embodiments, the ends of the first side 31 and the second side 32 can also be connected to the third side 33 in a curved line or a bent line. The ends of the first side 31 and the second side 32 can also be connected to the fourth side 34 in a curved line or a bent line.
[0063] Please refer to Figure 1 In order to retain more photoresistance in the photoresist layer, the effect can be achieved by reducing the length and width of the channel of the photoresist layer. In some embodiments, the first width W1 is 3.0um-5.0um, and the first length L1 is 30um-60um. By setting the first width W1 to 3.0um-5.0um, and setting the first length L1 to 30um-60um, the width of the groove formed by the etching of the photoresist layer of the thin film transistor substrate by the incident light through the semi-transparent area 30 becomes narrower and the length becomes shorter, so as to retain more photoresistance in the photoresist layer as much as possible for subsequent process etching, avoiding the subsequent process due to the increase in etching amount, resulting in excessive etching of the semiconductor layer on the substrate, resulting in the disconnection and failure of the electrostatic ring. Thereby improving the electrostatic release effect of the TFT array substrate and improving the yield rate.
[0064] Further, the first width W1 is 3.5um-4.8um, and the first length L1 is 35um-55um. For example, in some embodiments, the first width W1 can be set to 3.5um, or 4.2um, or 4.5um, or 4.8um. The first length L1 can be set to 35um, or 40um, or 48um, or 55um.
[0065] In some embodiments, the closed figure also has a second length L2 that is consistent with the first length L1, the second length L2 is the length of the end of the first side 31 extending to the third side 33 and the fourth side 34, and the second length L2 is the length of the end of the second side 32 extending to the third side 33 and the fourth side 34, and the second length is 2.0um-3.5um. The second length L2 is 2.0um-3.5um. In some embodiments, the second length L2 can be set to 2.0um, 2.5um, 3.0um, or 3.5um.
[0066] It should be noted that the above dimensions correspond to the process of manufacturing a 4.5 micron pixel size. For processes of other pixel sizes, the first width L1, the first length L1 and the second length L2 can be set to appropriate values to reduce photoresist removal and avoid over-etching in subsequent processes.
[0067] The present application also proposes a method for manufacturing a thin film transistor array substrate, comprising:
[0068] Please refer to Figure 3 , S1, providing a substrate 200, depositing a gate metal layer on the substrate 200, and performing a patterning process on the gate metal layer to obtain a gate layer 300;
[0069] Please refer to Figure 4 S2, depositing a gate insulating layer 400 and a semiconductor layer 500 on the gate layer 300 and the substrate 200 in sequence, and performing ion doping treatment on the semiconductor layer to form an ohmic contact layer 510 on the upper surface of the semiconductor layer 500;
[0070] Please refer to Figure 5 and Figure 6 S3, depositing a source-drain metal layer 600 on the semiconductor layer 500, coating a photoresist layer 700 on the source-drain metal layer 600, and exposing the photoresist layer 700 using the aforementioned half-tone mask 100;
[0071] Please refer to Figure 7 and Figure 8 , S4, etching the source and drain metal layer 600, and partially etching the ohmic contact layer 510 on the upper surface of the semiconductor layer 500 to obtain the source and drain (610, 620);
[0072] S5, connecting one end of the wire to the source 610, and connecting the other end of the wire to the drain 620, and extending the wire to the outside of the array substrate to form an electrostatic ring (not shown);
[0073] Please refer to Fig. 9S6, depositing a passivation layer 800 on the source electrode 610, the drain electrode 620, the semiconductor layer 500, and the gate insulating layer 400, and patterning the passivation layer 800 using a mask plate and a photoprocess to obtain a via corresponding to the drain electrode;
[0074] Please refer to Fig.10 S7, depositing a transparent electrode layer on the passivation layer, and patterning the transparent electrode layer using a mask plate and a photomask process to obtain a pixel electrode 900.
[0075] It should be noted that the incident direction of the incident light and the extending direction of the full light-transmitting area 10 of the half-tone mask are perpendicular to each other.
[0076] Please refer to Fig.11 In the conventional thin film transistor manufacturing process, the semiconductor layer 500 is prone to over-etching, that is, the semiconductor layer 500 between the source 610 and the drain 620 for forming a conductive channel is partially etched, so that the electrostatic loop formed by the source 610 and the drain 620 connected by the wire is "broken", and there is no electrical connection between the source 610 and the drain 620, resulting in the failure of the electrostatic loop on the TFT array substrate, poor electrostatic release effect of the TFT array substrate, and low yield rate.
[0077] Please refer to Figure 8 By using the halftone mask 100 of the present application, the etching of the photoresist layer on the gate of the thin film transistor by the incident light through the halftone mask is reduced, so that sufficient photoresist is retained in the groove of the photoresist layer. Sufficient photoresist in the groove of the photoresist layer will prevent the semiconductor layer 500 on the substrate from being over-etched in the subsequent process, resulting in the disconnection and failure of the electrostatic ring. Thereby, the electrostatic discharge effect of the TFT array substrate is improved, and the yield rate is improved.
[0078] It should be noted that in step S4, the source and drain (610, 620) can be obtained by a one-dry-one-wet etching process or a two-dry-two-wet process in the industry. Since the one-dry-one-wet etching process or the two-dry-two-wet process is a technical means well known to those skilled in the art, no further details will be given here.
[0079] In addition, the substrate 200 may be a glass substrate, the semiconductor layer 500 may be an active layer (also called an amorphous silicon layer), the gate insulating layer 400 may be made of silicon nitride, and the pixel electrode 900 may be made of indium tin oxide or indium zinc oxide.
[0080] The present application also proposes a half-tone mask, which is applied to the manufacturing process of a thin film transistor array substrate. The half-tone mask is provided with a pattern for etching an electrostatic ring on a gate of a thin film transistor. The half-tone mask is divided into:
[0081] The fully transparent region 10 is used to define the outer structure of the electrostatic ring;
[0082] At least two light shielding areas 20 are spaced apart from each other and are used to define the connection ends of the electrostatic loop; and
[0083] A semi-transparent area 30, provided between at least two of the light-shielding areas 20, for defining the pattern of the electrostatic ring;
[0084] The transmittance of the semi-transparent area 30 to the incident light used in the process is 30%-35%;
[0085] The orthographic projection of the semi-transparent area 30 is a closed figure, and the closed figure has a first width W1 and a first length L1, the first width W1 corresponds to the width of the groove of the photoresist layer formed on the substrate after the incident light etching, and the first length L1 corresponds to the length of the groove of the photoresist layer formed on the substrate after the incident light etching;
[0086] The first width W1 is 3.5um-4.8um, and the first length L1 is 35um-55um;
[0087] The closed figure has at least a first side 31, a second side 32, a third side 33 and a fourth side 34, the first side 31 and the second side 32 extend along the first length L1 direction, the third side 33 and the fourth side 34 extend along the first width W1 direction, the ends of the first side 31 and the second side 32 extending toward the third side 33 extend toward the outside of the closed figure and are connected to the third side 33, and the ends of the first side 31 and the second side 32 extending toward the fourth side 34 extend toward the outside of the closed figure and are connected to the fourth side 34, so that the closed figure is I-shaped as a whole.
[0088] The present application sets the transmittance of the semi-transparent area 30 to the incident light used in the process of the thin film transistor array substrate to 30%-35%, thereby reducing the etching of the photoresist layer on the gate of the thin film transistor by the incident light through the half-tone mask, so that sufficient photoresist is retained in the groove of the photoresist layer. Sufficient photoresist in the groove of the photoresist layer will prevent the semiconductor layer on the substrate from being over-etched in the subsequent process, resulting in the disconnection and failure of the electrostatic ring. Thereby improving the electrostatic discharge effect of the TFT array substrate and improving the yield rate.
[0089] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application.
Claims
1. A half-tone mask, characterized in that: In the process of manufacturing a thin film transistor array substrate, the half-tone mask is provided with a pattern for etching an electrostatic ring on a gate of a thin film transistor, and the half-tone mask is divided into: The fully transparent area is used to define the outer structure of the electrostatic ring; at least two light shielding areas, spaced apart from each other, for defining the connection end of the electrostatic ring; and A semi-transparent area, provided between at least two of the light-shielding areas, for defining the pattern of the electrostatic ring; Wherein, the transmittance of the semi-transparent area to the incident light used in the process is 25%-40%; The orthographic projection of the semi-transparent area is a closed figure, and the closed figure has a first width and a first length, the first width corresponds to the width of the groove of the photoresist layer formed on the substrate after etching by incident light, and the first length corresponds to the length of the groove of the photoresist layer formed on the substrate after etching by incident light; The closed figure has at least a first side, a second side, a third side and a fourth side, the first side and the second side extend along the first length direction, the lengths of the first side and the second side are both the first length, the distance between the first side and the second side is the first width, the third side and the fourth side extend along the first width direction, the ends of the first side and the second side extending toward the third side extend toward the outside of the closed figure and are connected to the third side, and the ends of the first side and the second side extending toward the fourth side extend toward the outside of the closed figure and are connected to the fourth side, so that the closed figure is I-shaped as a whole; The first width is 3.0um-5.0um, and the first length is 30um-60um; The closed figure also has a second length consistent with the first length direction, the second length is the distance from the end of the first side close to the third side to the third side, or the distance from the end of the first side close to the fourth side to the fourth side, and the second length is the distance from the end of the second side close to the third side to the third side, or the distance from the end of the second side close to the fourth side to the fourth side, and the second length is 2.0um-3.5um.
2. The half-tone mask according to claim 1, wherein: The transmittance of the semi-transparent area to the incident light used in the process is 30%-35%.
3. The half-tone mask according to claim 1, wherein: The first width is 3.5um-4.8um, and the first length is 35um-55um.
4. The half-tone mask according to claim 1, wherein: The closed figure also has a second length consistent with the first length direction, the second length is the distance from the end of the first side close to the third side to the third side, or the distance from the end of the first side close to the fourth side to the fourth side, and the second length is the distance from the end of the second side close to the third side to the third side, or the distance from the end of the second side close to the fourth side to the fourth side, and the second length is 2.0um-3.5um.
5. A half-tone mask, characterized in that: In the process of manufacturing a thin film transistor array substrate, the half-tone mask is provided with a pattern for etching an electrostatic ring on the gate of a thin film transistor, and the half-tone mask is divided into: The fully transparent area is used to define the outer structure of the electrostatic ring; at least two light shielding areas, spaced apart from each other, for defining the connection end of the electrostatic ring; and A semi-transparent area, provided between at least two of the light-shielding areas, for defining the pattern of the electrostatic ring; Wherein, the transmittance of the semi-transparent area to the incident light used in the process is 30%-35%; The orthographic projection of the semi-transparent area is a closed figure, and the closed figure has a first width and a first length, the first width corresponds to the width of the groove of the photoresist layer formed on the substrate after etching by incident light, and the first length corresponds to the length of the groove of the photoresist layer formed on the substrate after etching by incident light; The first width is 3.5um-4.8um, and the first length is 35um-55um; The closed figure has at least a first side, a second side, a third side and a fourth side, the first side and the second side extend along the first length direction, the lengths of the first side and the second side are both the first length, the distance between the first side and the second side is the first width, the third side and the fourth side extend along the first width direction, the ends of the first side and the second side extending toward the third side extend toward the outside of the closed figure and are connected to the third side, and the ends of the first side and the second side extending toward the fourth side extend toward the outside of the closed figure and are connected to the fourth side, so that the closed figure is I-shaped as a whole.
6. A method for manufacturing a thin film transistor array substrate, characterized in that: include: S1. providing a substrate, depositing a gate metal layer on the substrate, and performing a patterning process on the gate metal layer to obtain a gate layer; S2, depositing a gate insulating layer and a semiconductor layer on the gate layer and the substrate in sequence, and performing ion doping treatment on the semiconductor layer to form an ohmic contact layer on the upper surface of the conductor layer; S3, depositing a source-drain metal layer on the semiconductor layer, coating a photoresist layer on the source-drain metal layer, and exposing the photoresist layer using a half-tone mask as claimed in any one of claims 1 to 5; S4, etching the source and drain metal layers, and partially etching the ohmic contact layer on the upper surface of the semiconductor layer to obtain source and drain electrodes; S5, connecting one end of the wire to the source electrode, and connecting the other end of the wire to the drain electrode, and extending the wire to the outside of the array substrate to form an electrostatic ring.
7. The method for manufacturing a thin film transistor array substrate according to claim 6, wherein: The incident direction of the incident light and the extending direction of the full light-transmitting area of the half-tone mask are arranged perpendicular to each other.