Shift control method in semiconductor device manufacturing

Abstract

A shift control method in semiconductor device manufacturing includes at least the following steps: determining an overlay offset of a first target of a semiconductor die and a second target of the semiconductor die, wherein the second target is disposed on the first target; placing the semiconductor die on a carrier, wherein placing the semiconductor die includes feeding back the overlay offset to obtain position control of the semiconductor die; post-processing the semiconductor die to form a semiconductor device. Other shift control methods in semiconductor device manufacturing are also provided.

Description

Technical Field

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, and more particularly to a shift control method in the manufacture of a semiconductor device. Background Art

[0002] Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras and other electronic devices. As the demand for shrinking electronic devices grows, there is a need for smaller and more innovative semiconductor die packaging technologies. Therefore, packaging such as wafer level packaging (WLP) has been developed, such as encapsulating a semiconductor die in an insulating material and forming a redistribution layer (RDL) on the insulating material to fan out the wiring of the contact pads of the semiconductor die to make electrical contacts at a larger pitch than the contact pads of the semiconductor die.

[0003] However, these relatively new semiconductor package types face manufacturing challenges, such as when positioning the semiconductor die on a carrier wafer and forming an insulating material to cover the semiconductor die, the semiconductor die may undergo undesirable movement, which may cause problems in aligning the subsequently formed RDL material layers. As a result, such die movement during package formation can result in reduced yield. Summary of the invention

[0004] According to some embodiments, a shift control method in semiconductor device manufacturing includes at least the following steps: determining an overlay offset of a first target of a semiconductor die and a second target of the semiconductor die, wherein the second target is disposed on the first target; placing the semiconductor die on a carrier, wherein placing the semiconductor die includes feeding back the overlay offset to obtain position control of the semiconductor die; and post-processing the semiconductor die to form a semiconductor device.

[0005] According to some embodiments, a method for controlling displacement in semiconductor device manufacturing includes at least the following steps: encapsulating a plurality of semiconductor dies with an insulating encapsulation body on a carrier, wherein at least a portion of the plurality of semiconductor dies is displaced after encapsulation; and forming a photolithographic pattern on at least the plurality of semiconductor dies, wherein forming the photolithographic pattern includes compensating for displacement of a portion of the plurality of semiconductor dies.

[0006] According to some embodiments, a shift control method in semiconductor device manufacturing includes at least the following steps: placing a plurality of semiconductor dies at a first position on a carrier in response to an overlay offset of each of the plurality of semiconductor dies; forming an insulating encapsulation on the carrier to encapsulate the plurality of semiconductor dies, wherein a portion of the plurality of semiconductor dies is shifted from the first position to a second position; and post-processing the plurality of semiconductor dies to form a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the embodiments of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments.

[0009] Figure 2 is a schematic top view showing a semiconductor wafer before singulation according to some embodiments.

[0010] Figure 3 is a schematic top view illustrating a plurality of semiconductor dies placed on a carrier in accordance with some embodiments.

[0011] 4A to 4F are schematic cross-sectional views of various stages in the fabrication of a semiconductor device according to some embodiments.

[0012] Figure 5 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments.

[0013] Figure 6 and Figure 7 is a schematic cross-sectional view illustrating overlay offset of semiconductor dies according to some embodiments.

[0014] Figure 8 is a schematic scatter plot illustrating overlay offset of semiconductor dies according to some embodiments.

[0015] Fig. 9 is a schematic top view illustrating a plurality of semiconductor dies placed on a carrier after conditioning in accordance with some embodiments.

[0016] Fig.10 is a schematic top view illustrating the distribution of semiconductor dies after encapsulation according to some embodiments.

[0017] Fig.11A is a schematic top view illustrating the distribution of semiconductor dies after encapsulation according to some embodiments.

[0018] Fig. 11B is shown according to some embodiments along Fig.11A Schematic cross-sectional view of a partial semiconductor die taken along line CC' in FIG.

[0019] Fig.12 is a schematic perspective view showing a photolithography system for forming a redistribution layer according to some embodiments.

[0020] Fig.13 and Fig.14 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of the present invention. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed "on" or "on" a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, embodiments of the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0023] In addition, for ease of description, terms such as "first", "second", "third", etc. may be used herein to describe similar elements or features or different elements or features shown in the figures, and may be used interchangeably depending on the order of presentation or the context of description.

[0024] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate so that the 3D package or 3DIC can be tested, probes and / or probe cards can be used, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with a test method that includes intermediate verification of a known good die to improve yield and reduce costs.

[0025] Figure 1 is a flowchart showing a method for manufacturing a semiconductor device. Figure 2 is a schematic top view showing a semiconductor wafer before singulation, Figure 3 is a schematic top view showing a plurality of semiconductor dies placed on a carrier, 4A to 4F is a schematic cross-sectional view of various stages in the manufacture of a semiconductor device, wherein 4A to 4F Can be along Figure 3 A schematic cross-sectional view taken along line AA in FIG. Figures 1 to 4F A semiconductor device and a method for manufacturing the same are described.

[0026] Reference Figure 1 and Figure 2 , method 100 begins at step 102, singulating the semiconductor wafer SW to form a plurality of semiconductor dies SD. In some embodiments, the semiconductor wafer SW is processed to complete all layers including the front-end-of-line (FEOL) layer and the back-end-of-line (BEOL) layer. For example, a plurality of die regions DL are arranged in columns and rows on the entire semiconductor wafer SW. Each die region DL is part of the same semiconductor wafer SW and may include various manufactured integrated circuit components. The integrated circuit components may include transistors, capacitors, resistors, combinations of these, or other suitable components that can be used to generate the structural and functional requirements of the design of the semiconductor die SD. In some embodiments, each semiconductor die SD is of a single size, but each die region DL may include a different design or product. It should be noted that the size, shape, and design of the semiconductor die SD may be different from each other, and the semiconductor die SD may not necessarily be arranged in columns and rows.

[0027] In some embodiments, the semiconductor wafer SW is attached to a tape frame (not shown) to hold the semiconductor wafer SW in place during the singulation process. Subsequently, a cutting or singulation process may be performed on the semiconductor wafer SW. For example, a mechanical saw, a laser saw, or other suitable tool is used to cut the entire semiconductor wafer SW along dicing lines (e.g., a series of horizontal and vertical lines) so that several semiconductor dies SD are separated or singulated from each other.

[0028] Reference Figure 1 , Figure 3 and Figure 4A , the method 100 proceeds to step 104, placing the semiconductor die SD on the temporary carrier TC. The temporary carrier TC may include any suitable material capable of providing structural support during semiconductor processing. For example, the temporary carrier TC includes metal (e.g., steel), glass, ceramic, silicon (e.g., bulk silicon), combinations thereof, multilayers thereof, and the like. A release layer (not shown) is formed on the temporary carrier TC as needed to be used for bonding and peeling the temporary carrier TC with a structure subsequently formed thereon. For example, the release layer includes a layer of light-to-heat-conversion (LTHC) release coating and a layer of related adhesive (e.g., an ultraviolet (UV) curable adhesive layer or a heat curable adhesive layer), and the like.

[0029] For example, the semiconductor dies SD are respectively arranged on the temporary carrier TC by the pick-and-place process. In some embodiments, the rear surface 312b of the semiconductor die SD is attached to the temporary carrier TC by the die attach film DAF. The die attach film DAF attached to the rear surface 312b of the semiconductor die SD may be provided for the semiconductor die SD before the pick-and-place process. As another option, the die attach film DAF is omitted. In some embodiments, the individual semiconductor dies SD are spatially separated from each other and a gap G is formed between adjacent semiconductor dies SD. In some embodiments, the die attach film DAF does not exist in the gap G.

[0030] For example, the semiconductor die SD includes a digital die, an analog die, or a mixed signal die (such as an application-specific integrated circuit (ASIC) die, a logic die, a sensor die), but is not limited thereto. It should be noted that for illustration purposes, 4A to 4FOnly one semiconductor die SD is shown in the figure, however, the number of semiconductor dies SD may be one or more than one, but is not limited thereto. In some embodiments, an additional semiconductor die singulated from another semiconductor wafer may be provided and placed on the temporary carrier TC, and the additional semiconductor die and the semiconductor die SD may be of the same type or of different types.

[0031] In some embodiments, each semiconductor die SD includes a semiconductor substrate 312, a plurality of conductive pads 314 disposed on the semiconductor substrate 312, a plurality of conductive connectors 316 disposed on each conductive pad 314, and a protective layer 318 partially covering the conductive connectors 316 and the conductive pads 314. In one embodiment, the semiconductor substrate 312 is a silicon substrate, including active components (such as diodes, transistors, etc.) and passive components (such as resistors, capacitors, inductors, etc.) formed therein. In one embodiment, the conductive pads 314 are made of aluminum or its alloys, etc. The conductive pads 314 can be electrically coupled to the active / passive components formed in the semiconductor substrate 312 via an interconnect structure (not shown in the figure) disposed between the semiconductor substrate 312 and the conductive pads 314, and the conductive connectors 316 can be electrically connected to the conductive pads 314 to provide external connections to the integrated circuit components formed in the semiconductor substrate 312. In some embodiments, the surface on which the conductive connectors 316 are distributed is referred to as the active surface of the semiconductor die SD.

[0032] In one embodiment, the conductive connector 316 includes a copper through hole, a copper alloy through hole or other suitable metal through hole. In some embodiments, the conductive connector 316 includes a lead-based material or a lead-free material with / without additional impurities formed on the top, but is not limited thereto. In some embodiments, a protective layer 318 is formed on the semiconductor substrate 312 to prevent any possible damage to the conductive connector 316. In some embodiments, the protective layer 318 includes a passivation sublayer having an opening for exposing at least a portion of the conductive connector 316 in a touchable manner. The protective layer 318 can be made of a polybenzoxazole (PBO) layer, a polyimide (PI) layer, or a suitable polymer or inorganic material. In an embodiment, the top surface of the conductive connector 316 is substantially flush with the top surface of the protective layer 318. The number of conductive pads 314 and conductive connectors 316 can be selected based on demand, which is not limited in the embodiment of the present invention. It should be noted that the illustrations of the semiconductor die SD and other components in all the drawings are schematic and not drawn to scale.

[0033] Reference Figure 1 and Figure 4B, the method 100 proceeds to step 106, encapsulating the semiconductor die SD with an insulating encapsulant 320. As an example, the insulating encapsulant 320 includes a molding compound, an epoxy resin, a silica filler and / or an anti-etching material, but other materials can be used for the insulating encapsulant 320. The insulating encapsulant 320 can be filled into the gap G between adjacent semiconductor dies SD. For example, the formation of the insulating encapsulant 320 includes: forming an insulating material (not shown in the figure) by over-molding to encapsulate the semiconductor die SD, wherein a curing process can be performed to solidify the insulating material; and planarizing the insulating material until at least the conductive connector 316 is exposed in a touchable manner for external connection, wherein the planarization may include grinding, chemical-mechanical polishing (CMP), etching, etc. In some embodiments, after planarization, the insulating encapsulant 320 may not exist on the semiconductor die SD. In a top view of the structure, the semiconductor die SD is laterally covered and surrounded by the insulating encapsulant 320. In some embodiments, the top surface of the insulating encapsulation body 320 is substantially flush with the top surface of the semiconductor die SD. Figure 4B as shown in .

[0034] Reference Figure 1 and Figure 4C, the method 100 proceeds to step 108, forming a redistribution layer (RDL) 330 on the semiconductor die SD and the insulating encapsulation body 320. For example, the RDL 330 includes at least one patterned dielectric layer and at least one patterned conductive layer alternately stacked on top of each other. In an exemplary embodiment, the formation of the RDL 330 includes at least the following steps. For example, a patterned dielectric layer 332 having an opening is formed on the semiconductor die SD and the insulating encapsulation body 320 by using deposition, photolithography, etching and / or other suitable methods. The conductive connector 316 of the semiconductor die SD may be at least partially exposed by the opening of the patterned dielectric layer 332. The material of the patterned dielectric layer 332 may include polyimide (PI), polybenzoxazole (PBO), benzocyclobutane (BCB) or other suitable electrical insulating materials. Next, a patterned conductive layer 334 is formed on the patterned dielectric layer 332 using plating, sputtering, photolithography, etching and / or other suitable methods. The material of the patterned conductive layer 334 may include copper, tungsten, aluminum, silver, gold, etc. or a combination thereof. For example, a through-hole portion of the patterned conductive layer 334 is formed in an opening of the patterned dielectric layer 332 to physically and electrically contact the conductive connector 316 of the semiconductor die SD below. A portion of the patterned conductive layer 334 extending on the surface of the patterned dielectric layer 332 can reroute the electrical signal of the semiconductor die SD to extend to a wider range than a given area.

[0035] In some embodiments, the above steps may be performed multiple times to obtain a multi-layer rewiring structure required for the circuit design. That is, the number of patterned dielectric layers 332 and patterned conductive layers 334 may be selected based on demand and is not limited in the embodiments of the present invention. In other embodiments, the patterned conductive layer 334 is formed before the patterned dielectric layer 332 is formed. It should be noted that the order of formation of the patterned dielectric layer 332 and the patterned conductive layer 334 depends on the design requirements and is not interpreted as a limitation on the embodiments of the present invention. In some embodiments, the topmost layer of the patterned conductive layer 334 includes a plurality of patterns for electrical connection to components formed later. For example, the patterns include under-ball metallurgy (UBM) patterns for ball mounting and / or connection pads for mounting electronic components.

[0036] Reference Figure 1 and Figure 4D, the method 100 proceeds to step 110 to form a conductive terminal 340 on the RDL 330. In some embodiments, the conductive terminal 340 is disposed on the UBM pattern of the patterned conductive layer 334 by a ball planting process, a plating process, or other suitable processes. For example, the conductive terminal 340 includes a controlled collapse chip connection (C4) bump, a microbump, a solder ball, a ball grid array (BGA) ball, or other suitable terminals for providing external connections to the semiconductor die SD. Other possible forms and shapes of the conductive terminal 340 may be utilized according to design requirements. In some embodiments, a soldering process and a reflow process may be performed as needed to enhance the adhesion between the conductive terminal 340 and the RDL 330.

[0037] Reference Figure 1 and FIG. 4E to FIG. 4F The method 100 proceeds to step 112, where the resulting structure is singulated to form a plurality of semiconductor devices SP. For example, after forming the conductive terminals 340, the temporary carrier TC is peeled off or removed from the resulting structure, such as Figure 4E In some embodiments, external energy such as UV laser, visible light or heat is applied to the release layer to make it lose its adhesiveness so that the insulating encapsulation body 320 and the semiconductor die SD can be detached from the temporary carrier TC. Figure 4E The resulting structure is shown being fixed on a tape frame TF, which provides mechanical and structural support during the subsequent singulation of the semiconductor device SP from the adjacent semiconductor devices. The resulting structure can be flipped over to be fixed on the tape frame TF before or after peeling off the temporary carrier TC. The die attach film DAF is removed during or after removal of the temporary carrier TC as needed. The singulated structure is then removed from the tape frame TF, leaving a Figure 4F In some embodiments, the semiconductor device SP is referred to as a fan-out type semiconductor package.

[0038] It should be noted that semiconductor devices may take various forms. 4A to 4F Additional processes are provided before, during, and after the processes described in, and only some of the other processes are briefly described herein. In some embodiments, the semiconductor device SP may be electrically mounted on a printed circuit board (PCB), a printed wiring board, an interposer, a package substrate, an additional semiconductor package, and / or other carrier capable of carrying an integrated circuit. Other packaging technologies may be used, which is not limited in the embodiments of the present invention. The semiconductor device SP may be part of an electronic system such as a computing device, a wireless communication device, a computer-related peripheral device, an entertainment device, etc. It should be noted that other applications may exist.

[0039] During the production of the semiconductor device SP, it is important to properly align the conductive connector 316 of the semiconductor die SD with the patterned conductive layer 334 of the RDL 330. Improper alignment may be caused by various reasons during production. For example, the semiconductor die SD is displaced from a predetermined position on the temporary carrier TC during placement. In some embodiments, when the insulating material is cured to form the insulating encapsulation 320, the insulating material is deformed and may apply uneven stress to the individual semiconductor die SD, causing the semiconductor die SD to shift from its original position after placement. When the semiconductor die SD is shifted from one manufacturing process to a subsequent manufacturing process, the pattern in the upper layer becomes misaligned with the pattern in the lower layer. Such misalignment may cause an undesirable electrical short circuit in the semiconductor device SP due to the misalignment of the subsequent photolithography process used to form the RDL 330 relative to the shifted semiconductor die. As the alignment margin is reduced due to the increase in demand for semiconductor die SD with higher integration density, improper alignment may become more and more problematic. As will be discussed below, there are many operational factors that may be taken into account when managing improper alignment.

[0040] Figure 5 is a flowchart showing a method for manufacturing a semiconductor device. Figure 6 and Figure 7 is a schematic cross-sectional view showing the stack offset of semiconductor dies, wherein Figure 6 and Figure 7 The upper part can be along Figure 1 A schematic cross-sectional view taken along line BB' in FIG. Figure 6 and Figure 7 The lower part is shown Figure 6 and Figure 7 A schematic top view of the stacking offset of the semiconductor dies shown in the upper half of FIG. Figure 8 is a schematic scatter plot showing the overlay offset of semiconductor dies, Fig. 9 is a schematic top view showing a plurality of semiconductor dies placed on a carrier after adjustment, Fig.10 and Fig.11A is a schematic top view showing the distribution of semiconductor dies after encapsulation, Fig. 11B It is shown along Fig.11A A schematic cross-sectional view of a local semiconductor die taken along line CC' in FIG. Fig.12 is a schematic perspective view showing a photolithography system for forming a redistribution layer.

[0041] Reference Figures 5 to 11B A semiconductor device and a method for manufacturing the same are described. It should be noted that Figure 5 Zhongyu Figure 1Some steps that are identical or similar to the steps described in the method 200 are represented by identical or similar reference numbers, and the detailed description is simplified for the sake of brevity. Although method 200 is shown and described as a series of actions or events below, it should be understood that the order of these actions or events should not be interpreted as having a limiting meaning. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than the actions or events shown and / or described herein. In addition, it may not be necessary for all the actions shown to implement one or more aspects or embodiments described herein. In addition, one or more actions illustrated herein can be implemented in one or more separate actions and / or stages.

[0042] Reference Figures 5 to 8 The method 200 begins at step 101' by performing an overlay measurement. Figure 2 Before the semiconductor wafer SW shown in the figure is singulated, an overlay measurement process is performed using an overlay metrology apparatus (not shown in the figure) to determine the overlay offset between the conductive connectors of the semiconductor die and the corresponding conductive pads. For example, the overlay offset is the position difference or misalignment between a target on one layer of the semiconductor wafer and another target on another layer below the semiconductor wafer. For example, the overlay measurement value is generated by image scanning performed by the overlay metrology apparatus. In some embodiments, the overlay metrology apparatus includes a scanning unit, a light source, and other suitable components for performing overlay measurement. For example, an image of the semiconductor wafer is obtained by irradiating or scanning the semiconductor wafer with a light source and determining an image (for example, based on the reflection of the radiation). In some embodiments, the scanning unit of the overlay metrology apparatus includes a camera that is operable to scan and generate an image. The step of generating an image can be performed once or several times to capture images of different parts of the semiconductor wafer. It should be noted that the measurement of the overlay offset using the overlay metrology apparatus can be performed in various ways, which is not limited in the embodiments of the present invention.

[0043] In some embodiments, step 101' is adapted to provide a measurement of the overlay offset after the fabrication of the conductive connectors is completed. For example, the measurement of the overlay offset may be performed by comparing a first image having a distribution of conductive pads with a second image having a distribution of conductive connectors thereon, wherein reference marks may be provided on any layer of the semiconductor wafer to provide alignment of the first image with the second image. Other metrology methods may be used to detect the overlay offset of the conductive pads and the corresponding conductive connectors. In some embodiments, certain areas of the die area DL of the semiconductor wafer SW are selected to measure values ​​representing the overlay offset of the corresponding die area DL. For example, each die area DL includes more than one area on which conductive connectors are densely distributed, and such an area may be considered as a specific area for overlay measurement. It should be noted that other feature areas may be defined as specific areas for overlay measurement.

[0044] In the embodiments, reference Figure 2 and Figure 6 , measuring the overlay offset between consecutive layers of the die region DL of the semiconductor wafer SW. For example, the die region DL of the semiconductor wafer SW includes a conductive connector 316A and a corresponding conductive pad 314A, wherein the conductive connector 316A is offset relative to the corresponding conductive pad 314A in a first direction D1 by an overlay offset value +A. The overlay offset value +A may be a distance including an approximate distance from a situation where the conductive connector 316A is precisely aligned with the corresponding conductive pad 314A. In some embodiments, the overlay offset value +A is measured from a certain point (e.g., the center, the midpoint of an edge, the end, the vertex, etc.) of the conductive connector 316A to a corresponding point (e.g., the center, the midpoint of an edge, the end, the vertex, etc.) of the conductive pad 314A. The offset direction may be set as a reference point based on a certain point on the conductive pad 314A.

[0045] In another embodiment, referring to Figure 2 and Figure 7 , the die region DL of the semiconductor wafer SW includes a conductive connector 316B and a corresponding conductive pad 314B, wherein the conductive connector 316B is offset relative to the corresponding conductive pad 314B in a second direction D2 opposite to the first direction D1 by an overlay offset value -B. The overlay offset value -B may be a distance between the conductive connector 316B and the corresponding conductive pad 314B when they are directly aligned. For example, the center of the conductive connector 316B is laterally offset relative to the center of the corresponding conductive pad 314B in the second direction D2.

[0046] For ease of description and without intending to limit the structures disclosed herein to any particular orientation, for convenience, the first direction D1 and the second direction D2 are referred to herein as the “right side” and the “left side”, respectively. Figure 6In the illustrated embodiment, the conductive connector 316A is offset to the right of the corresponding conductive pad 314A. Figure 7 In the illustrated embodiment, the conductive connector 316B is offset to the left of the corresponding conductive pad 314B. It should be noted that although two embodiments of the overlay offset are illustrated, there may be numerous other embodiments, including variations of the overlay offset in different dimensional directions (e.g., the first direction D1, the second direction D2, the third direction D3, the fourth direction D4, combinations thereof, etc.). For example, in a top view, the conductive connector may be offset to, for example, the lower left side, the lower right side, the upper left side, or the upper right side of the corresponding conductive pad, wherein for the convenience of describing the embodiments of the present invention, the offset to the top and to the right is a positive overlay offset, while the offset to the bottom and to the left is a negative overlay offset.

[0047] In some embodiments, to ensure that successive layers are correctly stacked, reference marks AM may be used when manufacturing the semiconductor wafer SW. For example, the overlay offset value (e.g., +A, -B) is determined by calculating the relative position difference between the conductive connector (e.g., 316A, 316B) and the corresponding conductive pad (e.g., 314A, 314B) relative to the reference marks AM on the semiconductor wafer SW. In some embodiments, the reference marks AM and the conductive pad 314A are set at the same layer and used as a reference point for measuring (or identifying) the relative position of the conductive pad 314A. In some embodiments, the reference marks AM and the conductive pad 314A are formed during the same step and may be made of the same or similar materials. In some embodiments, the reference marks AM are also used as reference points for position measurement of the conductive connector (e.g., 316A, 316B). In other embodiments, additional reference marks (not shown in the figure) may also be set at the same layer as the conductive connector and used as reference points for measuring (or identifying) the relative position of the conductive connector. The overlay offset between the conductive connector and the corresponding conductive pad may be measured by these reference marks. In some embodiments, the reference mark AM may be an optically readable mark or pattern formed on a layer of the semiconductor wafer, and a scanning unit of the overlay metrology apparatus may be configured to scan the reference mark AM to identify the location of the conductive pad and / or conductive connector. Other types and forms of reference marks AM may be used.

[0048] In some embodiments, a plurality of points are plotted with respect to overlay offset values ​​to generate an overlay offset profile. Figure 6 , Figure 7 and Figure 8 , for example, the overlay offset values ​​(e.g., +A, -B) associated with each of the die regions DL are Figure 8, where the overlay offset values ​​(e.g., +A, -B) represent the degree of alignment of the conductive connectors (e.g., 316A, 316B) with the corresponding conductive pads (e.g., 314A, 314B). For example, the conductive pads 314A and the conductive connectors 316A of the die region DL have an overlay offset (i.e., +A) of 1 unit in the first direction D1 (i.e., +A). Figure 8 The conductive pads 314B and the conductive connectors 316B in the die region DL may have an overlay offset of 1 unit (ie, −B) in the second direction D2 (in the coordinate system shown). Figure 8 The plotted points (i.e., overlay offset values) can be considered as dimensional values ​​(or vectors) representing the degree of offset in a particular dimensional direction. These overlay offset values ​​can be converted into overlay correction values ​​associated with corresponding semiconductor dies for subsequent placement steps as described later.

[0049] The method 200 proceeds to step 102 of singulating the semiconductor wafer SW to form individual semiconductor dies SD. After determining the overlay offset value corresponding to each die region DL, a singulation or singulation process may be performed along the dicing street to separate the die regions DL from each other to form a plurality of semiconductor dies SD. Figure 1 The step 102 described in FIG. 1 is similar to the step 102 described in FIG. 1 , and therefore will not be described in detail for the sake of brevity.

[0050] Reference Figure 5 and Fig. 9 The method 200 proceeds to step 104', where the semiconductor die SD is placed on the temporary carrier TC. In some embodiments, the overlay offset value (e.g., +A, -B) is used to determine the extent to which the position of the semiconductor die SD to be placed should be adjusted. For example, the overlay offset value (e.g., +A, -B) is converted into an overlay correction value (e.g., -A, +B), and then based on the overlay correction value (e.g., -A, +B), the pick-and-place tool and / or the wafer stage (not shown) can adjust the position of the semiconductor die to be placed accordingly.

[0051] In some embodiments, a host computing device (not shown) that controls an overlay metrology apparatus (not shown) outputs an overlay correction value (e.g., from Figure 8The pick-and-place device and / or wafer stage compensates for the expected overlay offset of each semiconductor die SD according to the overlay correction values ​​output from the host computer. The overlay correction values ​​are dimensional values ​​used to position the semiconductor die at a modified position in the corresponding dimensional direction. In some embodiments, during the correction at the placement position, the wafer stage or the pick-and-place tool is moved along the X-axis and / or the Y-axis by a distance equal to the overlay correction value, but in the opposite direction of the overlay offset, to compensate for the overlay offset in the position of the semiconductor die.

[0052] In some embodiments, the conductive connectors 316A of the semiconductor dies SDA singulated from the semiconductor wafer SW are offset in the first direction D1 relative to the conductive pads 314A ( Figure 6 ), the semiconductor die SDA may then be placed at a modified position PA', which is offset relative to the original position PA in a second direction D2 opposite to the first direction D1. The original position PA is an ideal position, and for example, if the overlay correction value is zero, the semiconductor die SDA is placed at the original position PA. The modified position PA' is a correction position for compensating for the overlay offset of the semiconductor die SDA. For example, the conductive connector 316A of the semiconductor die SDA is offset to the right by 1 unit relative to the conductive pad 314A, and then during placement, the overlay offset value +A is compensated by placing the semiconductor die SDA to the left by 1 unit of overlay correction (i.e., -A). Similarly, the conductive connector 316B of the semiconductor die SDB is shifted to the left by 1 unit of overlay offset (e.g., -B) relative to the conductive pad 314B, and thus the semiconductor die SDB may be placed at a modified position PB' offset by 1 unit of overlay correction (i.e., +B) relative to the original position PB in the opposite direction (i.e., to the right). It should be understood that the above compensation method and Fig. 9 The configuration shown in is exemplary and variations thereof may be implemented within the scope of the embodiments of the invention.

[0053] Reference Figure 5 and Fig.10 The method 200 proceeds to step 106, encapsulating the semiconductor die (e.g., SDA, SDB) with an insulating encapsulant 320. For example, after placing the semiconductor die (e.g., SDA, SDB) at the modified position (e.g., PA', PB'), the insulating encapsulant 320 is formed on the temporary carrier TC to encapsulate the semiconductor die (e.g., SDA, SDB). The formation process of the insulating encapsulant 320 can be the same as that of the present invention. Figure 4BThe processes described in are similar to those described in , and therefore will not be described in detail for the sake of brevity. As described above, the placement of the semiconductor die (e.g., SDA, SDB) on the temporary carrier TC may shift during the encapsulation process (e.g., curing, cooling, grinding, CMP and / or other processes). For example, the semiconductor die SDA moves from a modified position PA' to a shifted position PA", and the semiconductor die SDB may move from a modified position PB' to a shifted position PB". It has been found empirically that such position shifts may not be uniform on the temporary carrier TC, which is a condition that may not be desirable to compensate for in a linear manner in subsequent processes. In some embodiments, after encapsulation, the displacement of the semiconductor die behaves in a nonlinear manner. Therefore, in subsequent processes, correction parameters may be calculated to take into account the nonlinear variation of die shifting.

[0054] In some embodiments, one or more semiconductor dies SD are shifted away from the modified position (eg, PA', PB') to a shifted position (eg, PA", PB"). For example, the gap G ( Figure 3 In some embodiments, the gap between adjacent semiconductor dies SD after encapsulation may be larger than the gap G before encapsulation. In some embodiments, the difference in the gap after encapsulation and before encapsulation is different between two different semiconductor dies SD, and this difference may be presented in a nonlinear manner. In some embodiments, the semiconductor die SD may be displaced in different directions. In some embodiments, the semiconductor die SD away from the center of the die array on the temporary carrier TC may have a larger displacement than the semiconductor die SD placed at or near the center of the die array on the temporary carrier TC. For example, the semiconductor dies SDA and SDB are arranged on the periphery of the die array on the temporary carrier TC and are away from each other, and the shortest distance Dm between the modified positions PA' and PB' may be smaller than the shortest distance Ds between the shifted positions PA" and PB". Fig.10 An example with nonlinear position shift after the encapsulation process is shown. It should be understood that Fig.10 The non-linear displacements shown in are exemplary and variations thereof may be implemented within the scope of embodiments of the present invention.

[0055] Reference Figure 5 , Fig.11A and Fig. 11B The method 200 proceeds to step 107' to perform a shift measurement, wherein Fig. 11B Can be along Fig.11ASchematic cross-sectional view taken along line CC' in FIG. For example, the degree of overlay offset of the corresponding semiconductor die SD is measured after the encapsulation process. In some embodiments, a shift metrology apparatus (not shown in the figure) is configured to perform shift measurement by image scanning and / or detecting reference marks of the semiconductor die SD and determining the distance between the reference marks. For example, similar to the overlay metrology apparatus, the shift metrology apparatus includes a scanning unit, a light source, a processor communicating with the scanning unit and the light source, and / or other suitable components for performing shift measurement. In some embodiments, an image is obtained by irradiating or scanning a target portion of the semiconductor die SD with a light source and determining an image. For example, the scanning unit of the shift metrology apparatus may include a camera, which may be operated to scan a target portion focused by the camera and generate an image of the target portion. The step of generating an image may be performed once or several times to capture images of different portions of the semiconductor die SD on the temporary carrier TC. It should be noted that the shift measurement performed using the shift metrology apparatus may be performed in various ways, which is not limited in the embodiments of the present invention.

[0056] For example, the processor of the shift metrology device is configured to divide each semiconductor die SD into several parts (e.g., GPs depicted by two-point chain lines), and then the reference coordinates generated by the shift metrology device can be set to correspond to the corresponding parts (e.g., GPs). The origin of the reference coordinates can be aligned with the reference point of one semiconductor die SD in the selected part GP to determine the relative displacement between the semiconductor die SD in the selected part GP. The degree of displacement of other semiconductor die SD in the selected part GP can be estimated based on the alignment of the one semiconductor die SD. In some embodiments, the reference coordinates can be constructed as a square grid with a given spacing P, and can be mapped on the semiconductor die SD of the selected part (e.g., GP). For example, each of the semiconductor die SD includes a reference mark RM, and the reference mark RM of one semiconductor die SD located at the center of the selected part GP is aligned with the center point CP of the square grid, so that the displacement values ​​of the remaining semiconductor die SD in the selected part GP relative to the semiconductor die SD located in the center can be identified or measured. The shift value can be a dimensional value (or vector) used to represent the degree of displacement in a specific dimensional direction. It should be noted that Fig.11A The illustration in is exemplary only, and the origin of the reference coordinates (or the center of the grid) may be aligned with a reference mark on any one of the target semiconductor dies in the selected portion for measuring relative displacement.

[0057] The reference mark may be or may include the conductive pad 314, the conductive connector 316, or an alignment mark disposed at the same level as the conductive connector 316 (in Figure 6As another option, the reference mark may be another reference mark (not shown) set elsewhere on the semiconductor die or the temporary carrier TC may be used to measure the displacement value of the semiconductor die. In some embodiments, the position of the conductive pad 314 and / or the conductive connector 316 may be estimated by identifying the position of the reference mark, so that the relative displacement between the semiconductor dies SD may be further estimated by calculating the distance Dp between certain points (e.g., the center, the midpoint of the edge, the end, the vertex, etc.) of the conductive pad 314 or calculating the distance Dc between certain points of the conductive connector 316. In some embodiments, the relative displacement is determined by identifying the position of the target conductive connector 316 of each semiconductor die SD in the selected part GP, and by setting one semiconductor die SD in the selected part GP as a reference point, the displacement value of other semiconductor dies SD in the selected part GP relative to the reference point may be estimated. In some embodiments, the displacement between the semiconductor dies SD on the temporary carrier TC presents a nonlinear dimensional change. As another option, step 107' is skipped, and the displacement of the corresponding semiconductor die may be identified during subsequent steps.

[0058] Reference Figure 5 and Fig.12 The method 200 proceeds to step 108' to form an RDL 330 on the semiconductor die SD and the insulating encapsulation 320. The RDL 330 may include a patterned dielectric layer 332 having a patterned conductive layer 334 formed therein and on a top surface thereof. The patterned conductive layer 334 may provide a fan-out to the conductive connector 316 of the semiconductor die SD (see, for example, Figure 4C ). In some embodiments, a photolithography and etching process is used to form an opening for the patterned dielectric layer 332, thereby depositing and patterning a photoresist, and then using the photoresist as a mask during the etching process to remove portions of the dielectric material and expose portions of the underlying conductive connectors 316. In some embodiments, the patterned conductive layer 334 is formed by conformally depositing a seed layer on the patterned dielectric layer 332, forming a photoresist material layer on the seed layer, baking the photoresist material layer, performing photolithography on the photoresist material layer to form an opening on the photoresist material layer, plating a conductive material in the opening of the photoresist material layer, and removing the photoresist material layer and excess seed layer. Therefore, during the formation of the RDL 330, the photolithography process (i.e., exposure and development process) can be performed several times.

[0059] In some embodiments, the step of forming the RDL 330 may be considered as forming a lithographic pattern on at least the semiconductor die SD using the lithography tool 400. In some embodiments, after measuring the shift of the semiconductor die position to generate a measurement result, the measurement result may be fed back to the lithography tool used to form the RDL 330. Various methods may be used to compensate for the shift value by adjusting process correction parameters involved in the lithography operation.

[0060] exist Fig.12 4 shows an exemplary photolithography tool 400 including an irradiation unit 410, a photomask (also referred to as a mask or a reticle) 420, and a projection unit 430. It should be noted that Fig.12 The components in are shown in a simplified manner, and the lithography tool 400 may include other technologies and / or components. For example, the irradiation unit 410 includes a light source (e.g., a UV light source, a deep UV light source, an extreme UV light source, and an X-ray source), an electron beam (E-Beam) light source, an ion beam light source, etc.), an optical assembly (e.g., a lens, a shadow mask, etc.) and / or other suitable components. The temporary carrier TC carrying the semiconductor die SD encapsulated in the insulating package 320 is all disposed on the wafer stage 440, and the wafer stage 440 is configured to fasten and move the temporary carrier TC in a translational and / or rotational manner to align the semiconductor die SD with the photomask 420. In some embodiments, the photomask 420 includes a transparent substrate and a patterned absorption layer, wherein the patterned absorption layer may have one or more openings through which the light beam can travel. As another option, the photomask 420 may be a reflective mask. The projection unit 430 may include a magnifying lens, a refractive optical device, or a reflective optical device to guide the patterned light to the target semiconductor die. During the photolithography exposure process, the target semiconductor die SD may be exposed to a pattern (not shown) on the photomask 420 to transfer the pattern of the photomask 420 to the target semiconductor die SD having the photoresist material deposited thereon.

[0061] Various methods may be used to compensate for the shift value between semiconductor dies SD before, during, or after exposure. In some embodiments, the wafer stage 440 provides compensated movement of the temporary carrier TC in the X, Y, and / or Z directions during various operations (e.g., alignment, focusing, leveling, exposure, etc.) in the lithography tool 400, so that the pattern of the photomask 420 is accurately transferred to the target semiconductor die SD. In other embodiments, the photomask 420 is stepped on the semiconductor die SD carried by the wafer stage 440 by a stepping machine (not shown), and the photomask 420 is stepped by a stepping distance for each exposure. In some embodiments, the value of the stepping distance varies according to the shift value and other factors. As another option, the irradiation unit 410 and / or the projection unit 430 may be adjusted to correct or compensate for the shift between the semiconductor dies SD. Other process variables of the lithography tool 400 may be adjusted in response to the overlay correction value and / or the shift value to achieve better accuracy.

[0062] In certain embodiments where step 107' is skipped, the displacement of each semiconductor die caused by the encapsulation step can be identified die by die during the lithography operation, and then the lithography tool is adjusted to compensate for the displacement of the corresponding semiconductor die. The displacement measurement and compensation displacement value can reduce the adverse effects on the formation of each successive layer and the displacement compensation during the exposure operation can reduce time-consuming rework.

[0063] The method 200 proceeds to step 110 and then step 112 by forming conductive terminals 340 on the RDL 330 and singulating the resulting structure to form a plurality of semiconductor devices SP. FIG. 4D to FIG. 4F The cross-sectional views of some embodiments are shown corresponding to step 110 and step 112. The process of forming the conductive terminals 340 and singulation can be similar to the above-mentioned process, and thus will not be described in detail for the sake of brevity.

[0064] Continue to refer to Figure 5 , method 200 proceeds to step 204, in which another round of die placement is performed. In some embodiments, the operating method includes feedback correction of subsequent semiconductor dies processed by the same process (e.g., die placement). For example, the host computing device is coupled to an overlay metrology device and / or a shift metrology device. The overlay offset data collected in step 101' (i.e., overlay measurement) and / or the shift data collected in step 107' (i.e., shift measurement) can be transmitted to the host computing device, and the host computing device can be configured to process the overlay offset data and the shift data and can communicate with the processing tool to adjust the process variables. Based on the overlay offset data and / or the shift data, the process recipe can be adjusted and / or other changes can be made for the next round of semiconductor device production.

[0065] For example, when semiconductor dies are placed on a temporary carrier in another round of semiconductor device fabrication (e.g., step 104 or 104'), feedback correction is performed in response to the overlay measurement (performed in this round) and the shift measurement (performed in the previous round) to determine compensation values ​​for the positions of the respective semiconductor dies. In some embodiments, Figure 5 The method 200 shown in FIG. 2 can be performed multiple times as a pilot sample to collect sample data so that the host computing device can determine appropriate compensation values ​​for the positions of various semiconductor dies based on the sample data. In some embodiments, when a sufficient amount of sample data is obtained, the operating method can automatically perform adjustments to correct the shift problem of the die, thereby reducing manpower requirements.

[0066] The semiconductor device SP can achieve better shift control by taking into account the overlay offset of each semiconductor die and the shift of each packaged semiconductor die during manufacturing. For example, if the overlay offset value and the shift value are not taken into account, the shift control value (mean plus standard deviation) is greater than 10μm. In certain embodiments in which the overlay offset value and the shift value are compensated during processing, the shift control value is controlled to be less than 5μm, for example in the range of about 3μm to about 5μm. According to some embodiments, such an improvement can meet the growing demand for semiconductor devices with higher integration density. It should be noted that overlay measurement and / or shift measurement can be applied to other types of packaging technologies, 4A to 4F The process stages shown are exemplary embodiments only.

[0067] Fig.13 and Fig.14 is a flow chart showing a method for manufacturing a semiconductor device according to some embodiments. It should be noted that Fig.13 and Fig.14 Zhongyu Figure 1 and Figure 5 Some steps that are identical or similar to the steps described in the method 500 and 600 are represented by identical or similar reference numbers, so for the sake of brevity, they are not described in detail. Although methods 500 and 600 are shown and described as a series of actions or events respectively below, it should be understood that the order in which these actions or events are shown should not be interpreted as having a limiting meaning. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than the actions or events shown and / or described herein. In addition, all the actions shown may not be required to implement one or more aspects or embodiments described herein. In addition, one or more actions illustrated herein may be implemented in one or more separate actions and / or stages.

[0068] Reference Fig.13In some embodiments, the method 500 begins at step 101' by performing overlay measurement, wherein an exemplary embodiment of this step is as described above. Next, the method 500 proceeds to step 102, singulating the semiconductor wafer to form individual semiconductor dies. Next, the method 500 proceeds to step 104', placing the semiconductor dies on a temporary carrier while compensating for the overlay offset values ​​of the corresponding semiconductor dies, and then proceeds to step 106, encapsulating the semiconductor dies with an insulating encapsulation. Next, the method 500 proceeds to step 108, forming an RDL on the semiconductor die and the insulating encapsulation, wherein although the displacement of the semiconductor die after encapsulation behaves in a non-linear manner, the displacement of the semiconductor die is compensated in a linear manner during the lithography process of forming the RDL. In some embodiments, process variables of the lithography tool are adjusted to compensate for the overlay offset determined during the overlay measurement step, such as adjusting the position of the photomask, moving the wafer stage on which the temporary carrier is placed, etc. Subsequently, the method 500 proceeds to step 110 and then step 112 to form conductive terminals on the RDL and then singulate the resulting structure to form a plurality of semiconductor devices. The semiconductor devices fabricated using the method 500 can achieve a certain degree of shift control. For example, the shift control value is controlled to be less than 10 μm, such as in the range of about 7 μm to about 10 μm.

[0069] Reference Fig.14 , method 600 begins at step 102, singulating the semiconductor wafer to form individual semiconductor dies. Next, method 600 proceeds to step 104 and step 106, placing the semiconductor dies on a temporary carrier and encapsulating the semiconductor dies with an insulating encapsulant. Next, method 600 proceeds to step 108', forming an RDL on the semiconductor dies and the insulating encapsulant. At this step, the displacement of the semiconductor dies can be compensated for the displacement value of each semiconductor die during the lithography process of forming the RDL, wherein the displacement value can be obtained by performing a displacement measurement (such as Figure 5 The actual shift value obtained by the RDL (described in step 107') may be an estimated shift value determined by data previously collected in a trial sample. Subsequently, the method 600 proceeds to step 110 and then step 112 to form conductive terminals on the RDL and then singulate the resulting structure to form a plurality of semiconductor devices. The semiconductor devices fabricated using the method 600 can achieve a certain degree of shift control. For example, the shift control value is controlled to be less than 10 μm, such as in the range of about 5 μm to about 7 μm.

[0070] According to some embodiments, a shift control method in semiconductor device manufacturing includes at least the following steps: determining an overlay offset of a first target of a semiconductor die and a second target of the semiconductor die, wherein the second target is disposed on the first target; placing the semiconductor die on a carrier, wherein placing the semiconductor die includes feeding back the overlay offset to obtain position control of the semiconductor die; and post-processing the semiconductor die to form a semiconductor device.

[0071] In some embodiments, determining the overlay offset of the first target and the second target is performed before singulating the semiconductor die from a semiconductor wafer. In some embodiments, the first target is a conductive pad of the semiconductor die, the second target is a conductive connector of the semiconductor die electrically connected to the conductive pad, and determining the overlay offset of the first target and the second target includes calculating a relative position difference between the conductive connector and the conductive pad relative to a reference mark on the semiconductor die. In some embodiments, the overlay offset represents a degree of offset between the first target and the second target in a dimensional direction, and feedback of the overlay offset includes placing the semiconductor die at a position that compensates for the degree of offset. In some embodiments, post-processing the semiconductor die includes forming an insulating encapsulation on the carrier to encapsulate the semiconductor die, wherein after forming the insulating encapsulation, the position of the semiconductor die on the carrier is shifted, and the displacement of the semiconductor die is measured after forming the insulating encapsulation. In some embodiments, post-processing the semiconductor die further includes compensating for the displacement of the semiconductor die when forming a photolithography pattern on the semiconductor die, wherein forming the photolithography pattern is performed after forming the insulating encapsulation. In some embodiments, placing the semiconductor die further comprises placing a plurality of the semiconductor dies on the carrier, wherein a gap exists between two adjacent ones of the plurality of the semiconductor dies, and after forming the insulating encapsulation, the gap filled by the insulating encapsulation changes. In some embodiments, measuring the displacement of the semiconductor die after forming the insulating encapsulation comprises setting one of the plurality of the semiconductor dies as a reference point, and determining the relative displacement of the plurality of the semiconductor dies relative to the reference point.

[0072] According to some alternative embodiments, a method for shift control in semiconductor device manufacturing includes at least the following steps: encapsulating a plurality of semiconductor dies with an insulating encapsulation body on a carrier, wherein at least a portion of the plurality of semiconductor dies are shifted after encapsulation; forming a photolithographic pattern on at least the plurality of semiconductor dies, wherein forming the photolithographic pattern includes compensating for a shift in position of the portion of the plurality of semiconductor dies.

[0073] In some embodiments, the shift control method further includes measuring the displacement of the position of the portion of the plurality of semiconductor dies before forming the lithographic pattern to obtain a measurement result, and feeding back the measurement result to a lithographic tool used to form the lithographic pattern. In some embodiments, measuring the displacement of the position of the portion of the plurality of semiconductor dies includes setting a reference coordinate to map the portion of the plurality of semiconductor dies, wherein an origin of the reference coordinate is aligned with one of the portions of the plurality of semiconductor dies. In some embodiments, there is an overlay offset between a first target of one of the plurality of semiconductor dies and a second target of the one of the plurality of semiconductor dies, the first target and the second target being stacked one above the other, and the method further includes compensating for the overlay offset when the one of the plurality of semiconductor dies is placed on the carrier before encapsulating with the insulating encapsulant. In some embodiments, the shift control method further includes measuring the overlay offset of the one of the plurality of semiconductor dies before singulating the one of the plurality of semiconductor dies from a semiconductor wafer. In some embodiments, the first target is a conductive pad of the one of the plurality of semiconductor dies, the second target is a conductive connector of the one of the plurality of semiconductor dies disposed on the conductive pad, and measuring the overlay offset includes calculating a relative position difference between the conductive connector and the conductive pad relative to a reference mark on the one of the plurality of semiconductor dies.

[0074] According to some alternative embodiments, a shift control method in semiconductor device manufacturing includes at least the following steps: placing a plurality of semiconductor dies at a first position on a carrier in response to an overlay offset of each of the plurality of semiconductor dies; forming an insulating encapsulation on the carrier to encapsulate the plurality of semiconductor dies, wherein a portion of the plurality of semiconductor dies is shifted from the first position to a second position; and post-processing the plurality of semiconductor dies to form a semiconductor device.

[0075] In some embodiments, the shift control method further includes measuring the degree of displacement of the conductive connector of the one of the plurality of semiconductor dies relative to the conductive pad of the one of the plurality of semiconductor dies before placing the one of the plurality of semiconductor dies, wherein the conductive connector is stacked on the conductive pad. In some embodiments, placing the one of the plurality of semiconductor dies includes positioning the one of the plurality of semiconductor dies at the first position to compensate for the degree of displacement of the conductive connector relative to the conductive pad. In some embodiments, the shift control method further includes measuring the displacement of the portion of the plurality of semiconductor dies after forming the insulating encapsulation. In some embodiments, measuring the displacement of the portion of the plurality of semiconductor dies includes aligning the one of the plurality of semiconductor dies with an origin of a reference coordinate, wherein the reference coordinate is mapped on the portion of the plurality of semiconductor dies, and determining the relative displacement between other semiconductor dies in the portion of the plurality of semiconductor dies relative to the one of the plurality of semiconductor dies. In some embodiments, post-processing the plurality of semiconductor dies includes forming a photolithographic pattern on the portion of the plurality of semiconductor dies in response to the displacement of the portion of the plurality of semiconductor dies.

[0076] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

[0077] [Explanation of Symbols]

[0078] 100, 200, 500, 600: Method

[0079] 101', 102, 104, 104', 106, 107', 108, 108', 110, 112, 204: Steps

[0080] 312: Semiconductor substrate

[0081] 312b: rear surface

[0082] 314, 314A, 314B: Conductive pads

[0083] 316, 316A, 316B: Conductive connectors

[0084] 318: Protective layer

[0085] 320: Insulation enclosure

[0086] 330: Redistribution Layer (RDL)

[0087] 332: Patterned dielectric layer

[0088] 334: Patterned conductive layer

[0089] 340: Conductive terminal

[0090] 400: Lithography tools

[0091] 410: Irradiation unit

[0092] 420: Photomask

[0093] 430: Projection Unit

[0094] 440: Wafer stage

[0095] +A, -B: Overlay offset value

[0096] -A, +B: Overlay correction values

[0097] AA, B-B', C-C': Line

[0098] AM, RM: Reference mark

[0099] CP: Center Point

[0100] D1: First direction

[0101] D2: Second direction

[0102] D3: Third direction

[0103] D4: The fourth direction

[0104] DAF: Die Attach Film

[0105] DL: Die area

[0106] Dc, Dp: distance

[0107] G: Gap

[0108] GP: Semiconductor die part

[0109] P: Spacing

[0110] PA, PB: Original position

[0111] PA', PB': modified position

[0112] PA”, PB”: shift position

[0113] SD, SDA, SDB: semiconductor die

[0114] SP: Semiconductor Devices

[0115] SW: Semiconductor wafer

[0116] TC: Temporary Carrier

[0117] TF: with frame

Claims

1. A shift control method in semiconductor device manufacturing, comprising: determining an overlay offset of a first target of a semiconductor die and a second target of the semiconductor die, wherein the second target is disposed on the first target; placing the semiconductor die on a carrier, wherein placing the semiconductor die includes feeding back the overlay offset to obtain position control of the semiconductor die; as well as Post-processing the semiconductor die to form a semiconductor device includes: forming an insulating encapsulation on the carrier to encapsulate the semiconductor die, wherein after forming the insulating encapsulation, the position of the semiconductor die on the carrier is shifted; as well as Displacement of the semiconductor die is measured after forming the insulating encapsulation. 2 . The shift control method in semiconductor device manufacturing according to claim 1 , wherein determining the overlay offset of the first target and the second target is performed before singulating the semiconductor die from a semiconductor wafer.

3. The shift control method in semiconductor device manufacturing according to claim 1, wherein The first target is a conductive pad of the semiconductor die, the second target is a conductive connector of the semiconductor die electrically connected to the conductive pad, and Determining the overlay offset of the first target and the second target includes calculating a relative position difference between the conductive connector and the conductive pad with respect to a reference mark on the semiconductor die.

4. The shift control method in semiconductor device manufacturing according to claim 1, wherein the overlay offset represents the degree of offset between the first target and the second target in a dimensional direction, and feeding back the overlay offset comprises: The semiconductor die is placed at a position that compensates for the degree of offset.

5. The method of claim 1 , wherein measuring the displacement of the semiconductor die comprises: A reference coordinate is set to map the plurality of semiconductor dies, wherein an origin of the reference coordinate is aligned with one of the plurality of semiconductor dies.

6. The shift control method in semiconductor device manufacturing according to claim 1, wherein post-processing the semiconductor die further comprises: The displacement of the semiconductor die is compensated when a photolithography pattern is formed on the semiconductor die, the forming of the photolithography pattern being performed after forming the insulating encapsulation.

7. The shift control method in semiconductor device manufacturing according to claim 1, wherein placing the semiconductor die further comprises: A plurality of the semiconductor dies are placed on the carrier, wherein a gap exists between two adjacent ones of the plurality of the semiconductor dies, and after the insulating encapsulation body is formed, the gap filled by the insulating encapsulation body changes.

8. The method of claim 7 , wherein measuring the displacement of the semiconductor die after forming the insulating encapsulation comprises: setting one of the plurality of the semiconductor dies as a reference point; as well as A relative displacement of the plurality of the semiconductor dies relative to the reference point is determined.

9. A shift control method in semiconductor device manufacturing, comprising: encapsulating a plurality of semiconductor dies with an insulating encapsulation over a carrier, wherein at least a portion of the plurality of semiconductor dies are displaced after encapsulation; measuring a displacement of the semiconductor die where the displacement occurs; as well as A photolithographic pattern is formed on at least the plurality of semiconductor dies, wherein forming the photolithographic pattern includes compensating for the displacement of the position of the portion of the plurality of semiconductor dies.

10. The shift control method in semiconductor device manufacturing according to claim 9, further comprising: Before forming the lithographic pattern, measuring the displacement of the position of the portion of the plurality of semiconductor dies to obtain a measurement result; as well as The measurement results are fed back to a lithography tool used to form the lithographic pattern.

11. The shift control method in semiconductor device manufacturing according to claim 9, wherein measuring the displacement of the position of the portion of the plurality of semiconductor dies comprises: A reference coordinate is set to map the portion of the plurality of semiconductor dies, wherein an origin of the reference coordinate is aligned with one of the portion of the plurality of semiconductor dies.

12. The shift control method in semiconductor device manufacturing according to claim 9, wherein there is an overlay offset between a first target of one of the plurality of semiconductor dies and a second target of the one of the plurality of semiconductor dies, the first target and the second target being stacked on top of each other, the method further comprising: The overlay offset is compensated when the one of the plurality of semiconductor dies is placed over the carrier prior to encapsulation with the insulating encapsulation.

13. The shift control method in semiconductor device manufacturing according to claim 12, further comprising: The overlay offset of the one of the plurality of semiconductor dies is measured prior to singulating the one of the plurality of semiconductor dies from a semiconductor wafer.

14. The shift control method in semiconductor device manufacturing according to claim 13, wherein: The first target is a conductive pad of the one of the plurality of semiconductor dies, the second target is a conductive connector disposed on the conductive pad of the one of the plurality of semiconductor dies, and Measuring the overlay offset includes calculating a relative position difference between the conductive connector and the conductive pad with respect to a reference mark on the one of the plurality of semiconductor dies.

15. A shift control method in semiconductor device manufacturing, comprising: measuring a degree of displacement of a conductive connector of one of a plurality of semiconductor dies relative to a conductive pad of the one of the plurality of semiconductor dies, wherein the conductive connector is stacked on the conductive pad; placing the plurality of semiconductor dies at a first position over a carrier in response to an overlay pair offset of respective ones of the plurality of semiconductor dies; forming an insulating encapsulation on the carrier to encapsulate the plurality of semiconductor dies, wherein a portion of the plurality of semiconductor dies is displaced from the first position to a second position; as well as The plurality of semiconductor dies are post-processed to form semiconductor devices.

16. The shift control method in semiconductor device manufacturing according to claim 15, wherein measuring the degree of displacement of the conductive connection of the one of the plurality of semiconductor dies relative to the conductive pad of the one of the plurality of semiconductor dies is performed before singulating the semiconductor die from a semiconductor wafer.

17. The shift control method in semiconductor device manufacturing according to claim 15, wherein placing the one of the plurality of semiconductor dies comprises: The one of the plurality of semiconductor dies is positioned at the first location to compensate for the degree of offset of the conductive connector relative to the conductive pad.

18. The shift control method in semiconductor device manufacturing according to claim 15, further comprising: A displacement of the portion of the plurality of semiconductor dies is measured after forming the insulating encapsulation.

19. The method of claim 18, wherein measuring the displacement of the portion of the plurality of semiconductor dies comprises: aligning one of the plurality of semiconductor dies with an origin of a reference coordinate, wherein the reference coordinate is mapped onto the portion of the plurality of semiconductor dies, and Relative displacements between other semiconductor dies in the portion of the plurality of semiconductor dies relative to the one of the plurality of semiconductor dies are determined.

20. The shift control method in semiconductor device manufacturing according to claim 18, wherein post-processing the plurality of semiconductor dies comprises: A photolithographic pattern is formed on the portion of the plurality of semiconductor dies in response to the displacement of the portion of the plurality of semiconductor dies.

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