Storage Devices

Abstract

A memory device includes: a first semiconductor chip including a memory cell array disposed on a first substrate and a first bonding metal on a first uppermost metal layer of the first semiconductor chip; and a second semiconductor chip including a circuit device disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit device providing a peripheral circuit for operating the memory cell array. The first semiconductor chip and the second semiconductor chip are electrically connected to each other in a bonding region through the first bonding metal and the second bonding metal. Wiring electrically connected to the peripheral circuit is disposed in one or both of the first uppermost metal layer and the second uppermost metal layer, and is disposed in a non-bonding region in which the first semiconductor chip and the second semiconductor chip are not electrically connected to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0108359 filed on September 2, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to memory devices. Background Art

[0004] A storage device may provide a function of recording and erasing data or reading recorded data. Storage devices may be classified as nonvolatile storage devices or volatile storage devices. In a nonvolatile storage device, recorded data may be retained even when its power is cut off. The data storage capacity required for storage devices is increasing, and various methods for improving the integration of storage devices have been proposed. Summary of the invention

[0005] One aspect provides a memory device having improved integration by reducing a chip size.

[0006] According to aspects of one or more embodiments, a memory device is provided, comprising: a first semiconductor chip comprising a memory cell array arranged on a first substrate, and a first bonding metal on a first topmost metal layer of the first semiconductor chip; and a second semiconductor chip comprising a circuit device arranged on a second substrate, and a second bonding metal on a second topmost metal layer of the second semiconductor chip, the circuit device providing a peripheral circuit for operating the memory cell array, wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other in a bonding region through the first bonding metal and the second bonding metal, and wiring electrically connected to the peripheral circuit is arranged in at least one of the first topmost metal layer or the second topmost metal layer, and is arranged in a non-bonding region, wherein the first semiconductor chip and the second semiconductor chip are not electrically connected to each other in the non-bonding region.

[0007] According to aspects of one or more embodiments, a memory device is provided, comprising: a memory cell region, comprising word lines stacked on a first substrate, bit lines arranged on the word lines, a channel structure passing through the word lines and connected to the bit lines, and a common source line; a peripheral circuit region, arranged on a second substrate and comprising a peripheral circuit for operating a memory cell array included in the memory cell region; a bonding metal, electrically connecting the uppermost metal layer of the memory cell region and the uppermost metal layer of the peripheral circuit region to each other in the bonding region; and a wiring, electrically connected to the peripheral circuit in a non-bonding region, in which the memory cell region and the peripheral circuit region are not electrically connected to each other; wherein the bonding region of the memory cell region comprises a cell contact plug electrically connected to the word line and the peripheral circuit, and the cell contact plug is located between the non-bonding regions.

[0008] According to aspects of one or more embodiments, a memory device is provided, comprising: a first semiconductor chip, comprising a first bonding area and a first non-bonding area arranged around the first bonding area; and a second semiconductor chip, comprising a second bonding area and a second non-bonding area, the second bonding area being arranged at a position corresponding to the position of the first bonding area, the second non-bonding area being arranged at a position corresponding to the position of the first non-bonding area and being arranged around the second bonding area, wherein a metal contact arranged on an uppermost metal layer of the first bonding area and a metal contact arranged on an uppermost metal layer of the second bonding area are electrically connected to each other, a metal contact arranged in the uppermost metal layer of the first non-bonding area and a metal contact arranged on the uppermost metal layer of the second non-bonding area are not electrically connected to each other, a metal contact arranged in the uppermost metal layer of the second non-bonding area forms a wiring, the first bonding area surrounds at least a portion of the first non-bonding area, and the second bonding area surrounds at least a portion of the second non-bonding area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram schematically illustrating a memory device according to example embodiments;

[0011] Figure 2 is a circuit diagram schematically illustrating a memory device according to example embodiments;

[0012] Figure 3 is a schematic plan view illustrating a memory device according to example embodiments;

[0013] FIG. 4A to FIG. 4D is a schematic plan view showing a memory device according to example embodiments;

[0014] Figures 5 to 8 It is taken along line I-I' and line II-II' Figure 3 A cross-sectional view of the memory device shown;

[0015] Fig. 9 is a schematic plan view illustrating a memory device according to example embodiments; and

[0016] Fig.10 is a block diagram illustrating an electronic device including a memory device according to an exemplary embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, example embodiments will be described with reference to the accompanying drawings. In the present specification, the phrase "at least one of A or B" includes "only A", "only B" and "both A and B".

[0018] Figure 1 is a block diagram schematically illustrating a memory device according to example embodiments.

[0019] refer to Figure 1 , the memory device 10 may include a memory cell array 20 and a peripheral circuit 30. The peripheral circuit 30 may include a row decoder 31, a voltage generator 32, a page buffer 33, an input / output circuit 34, a control logic 35, and the like.

[0020] The memory cell array 20 may include a plurality of memory cells and may be divided into a plurality of blocks BLK1 to BLKn. The plurality of memory cells may be connected to the row decoder 31 through a string selection line SSL, a word line WL, and a ground selection line GSL, and the plurality of memory cells may be connected to the page buffer 33 via a bit line BL. In one example, in each of the blocks BLK1 to BLKn, a plurality of memory cells arranged at the same height from the substrate are connected to the same word line WL, and a plurality of memory cells arranged at the same position on a plane parallel to the upper surface of the substrate may be provided with a memory cell string sharing one channel region. In addition, a portion of the memory cell string included in each of the blocks BLK1 to BLKn may be connected to the same bit line BL.

[0021] The row decoder 31 may generate and transmit a voltage for driving the word line WL by decoding address data ADDR received from the control logic 35, etc. The row decoder 31 may input the word line voltage generated by the voltage generator 32 to the word line WL under the control of the control logic 35. For example, the row decoder 31 may be connected to the word line WL through a pass transistor, and may input the word line voltage to the word line WL when the pass transistor is turned on.

[0022] The page buffer 33 may be connected to the memory cell array 20 through the bit lines BL and read data stored in the memory cells or write data to the memory cells. The page buffer 33 may include a column decoder and a sense amplifier. The column decoder may select at least a portion of the bit lines BL of the memory cell array 20, and the sense amplifier may read data of the memory cells connected to the bit lines BL selected by the column decoder during a read operation.

[0023] The input / output circuit 34 may receive data (DATA) during a program operation and transfer the data to the page buffer 33, and may output data read from the memory cell array 20 to the outside through the page buffer 33 during a read operation. The input / output circuit 34 may transfer an address or command input from an external memory controller to the control logic 35.

[0024] The control logic 35 may control operations of the row decoder 31 , the voltage generator 32 , the page buffer 33 , etc. In example embodiments, the control logic 35 may be operated by a control signal and an external voltage transmitted from an external memory controller, etc.

[0025] The voltage generator 32 may use an external input power supply voltage to generate a control voltage required for the operation of the memory device 10, for example, a program voltage, a read voltage, an erase voltage, a pass voltage, etc. The voltage generated by the voltage generator 32 may be provided to the peripheral circuit 30, or may be input to the memory cell array 20 through a row decoder 31 or the like.

[0026] For example, a program voltage may be input to a selected word line connected to a selected memory cell to which data is written in a program operation. A channel voltage lower than the program voltage may be input to an unselected word line connected to an unselected memory cell included in a memory cell string with the selected memory cell and sharing a channel region with the selected memory cell. The program operation may be performed in units of pages.

[0027] In an example embodiment, in a read operation, a read voltage is input to a selected word line connected to a selected memory cell to read data, and a channel voltage may be input to an unselected word line connected to an unselected memory cell that shares a channel region with the selected memory cell. In an example embodiment in which each memory cell stores data having a plurality of bits, the row decoder 31 may input a plurality of read voltages having different amplitudes to the selected word line. The read operation may be performed in units of pages.

[0028] Figure 2 is a circuit diagram schematically illustrating a memory device according to example embodiments.

[0029] refer to Figure 2, one memory block BLK may include a plurality of memory cell strings CS, and at least a portion of the memory cell strings CS may share word lines WL1 to WLn and / or bit lines BL1 to BL3 .

[0030] Each memory cell string CS may include a plurality of memory cells MC connected between the first and second string selection transistors SST1 and SST2 and the ground selection transistor GST. Figure 2 In the example shown, four memory cells MC are shown. However, this is only an example, and in other embodiments, the number may be greater than or less than four. The first string selection transistor SST1 and the second string selection transistor SST2 are connected in series to each other, and the second string selection transistor SST2 arranged on the first string selection transistor SST1 may be connected to one of the bit lines BL1 to BL3. The ground selection transistor GST may be connected to the common source line CSL. The memory cells MC included in each memory cell string CS may share one channel region.

[0031] A plurality of memory cells MC may be connected in series between the first string selection transistor SST1 and the second string selection transistor SST2 and the ground selection transistor GST. According to example embodiments, the number of string selection transistors SST1 and SST2 and the ground selection transistor GST may be modified differently, and each memory cell string CS may further include at least one dummy memory cell. For example, the dummy memory cell may be connected between the first string selection transistor SST1 and the memory cell MC, and / or between the ground selection transistor GST and the memory cell MC.

[0032] Gate electrodes of memory cells MC may be connected to word lines WL1 to WLn, gate electrodes of ground selection transistors GST may be connected to ground selection lines GSL, and gate electrodes of first and second string selection transistors SST1 and SST2 may be connected to string selection lines SSL11 to SSL23.

[0033] The ground selection line GSL, the word lines WL1 to WLn, and the string selection lines SSL11 to SSL23 may be stacked in a first direction perpendicular to the upper surface of the substrate. The ground selection line GSL, the word lines WL1 to WLn, and the string selection lines SSL11 to SSL23 may be penetrated by a channel structure including a channel region. The channel structure may be connected to one of the bit lines BL1 to BL3.

[0034] In order to improve the integration of a memory device, it is advantageous to effectively secure a space for a signal line for transmitting a signal or a power line for supplying power.

[0035] According to example embodiments, wirings may be formed in the uppermost metal layer of a non-bonding region where a cell region and a peripheral circuit region are not electrically connected. Therefore, since there is no need to ensure a separate space for separate wirings, the chip size may be reduced.

[0036] Figure 3 is a schematic plan view illustrating a memory device according to example embodiments.

[0037] refer to Figure 3 , the memory device 100 may include a peripheral circuit region PERI and a cell region CELL disposed on the peripheral circuit region PERI. The peripheral circuit region PERI and the cell region CELL may be arranged along a vertical direction (ie, along Figure 3 The peripheral circuit area PER1 can be composed of Figure 1 The peripheral circuit 30. The cell region CELL can be composed of Figure 1 The memory cell array 20 of FIG. 1 may include a row decoder, a page buffer, and other peripheral circuits. The cell region CELL may include a memory cell array.

[0038] In the peripheral circuit area PERI, the row decoder can be connected with the above reference Figure 1 The row decoder 31 described above corresponds to the page buffer, and the page buffer can be the same as the Figure 1 In some embodiments, other peripheral circuits may be Figure 1 The control logic 35 and the voltage generator 32 of the embodiment, and for example, in some embodiments, other peripheral circuits may include a latch circuit, a cache circuit or a sense amplifier. In addition, in some embodiments, other peripheral circuits may include Figure 1 The input / output circuit 34 may include an electrostatic discharge (ESD) device or a data input / output circuit. In an example embodiment, the input / output circuit 34 may be arranged to form a separate area around other peripheral circuits.

[0039] In the peripheral circuit region PERI, at least a portion of the row decoder, the page buffer, and other peripheral circuits may be disposed below the memory cell array of the cell region CELL. For example, the page buffer may be disposed below the memory cell array to overlap with the memory cell array. However, in some embodiments, the circuits included in the peripheral circuit region PERI and their arrangement may be changed differently, and therefore, the circuits disposed to overlap with the memory cell array may be changed differently.

[0040] In the cell region CELL, the memory cell arrays may be arranged in parallel to be spaced apart from each other. According to various embodiments, the number and arrangement of the memory cell arrays provided in the cell region CELL may be changed differently. For example, the memory cell arrays in this embodiment may have a form of continuously and repeatedly arranged.

[0041] The memory device 100 may have a chip-to-chip (C2C) structure. The C2C structure may be a structure in which an upper semiconductor chip including a cell region CELL is manufactured on a first wafer, a lower semiconductor chip including a peripheral circuit region PERI is manufactured on a second wafer different from the first wafer, and then, the upper semiconductor chip and the lower semiconductor chip are connected to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed in the uppermost metal layer of the upper semiconductor chip to a bonding metal formed in the uppermost metal layer of the lower semiconductor chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method.

[0042] In example embodiments, the upper semiconductor chip and the lower semiconductor chip may be stacked on each other at a wafer level. According to another embodiment, the upper semiconductor chip and the lower semiconductor chip may be stacked on each other at a chip level.

[0043] Each of the upper semiconductor chip and the lower semiconductor chip may include a bonding region and a non-bonding region other than the bonding region. That is, in some embodiments, the non-bonding region may be any region in the chip other than the bonding region. In order to electrically connect the upper semiconductor chip and the lower semiconductor chip to each other, the bonding metal formed in the uppermost metal layer of the upper semiconductor chip and the bonding metal formed in the uppermost metal layer of the lower semiconductor chip may be electrically connected to each other in the bonding region. The bonding metal may be used for the connection of word lines, bit lines, and well biases.

[0044] The cell region CELL may include first bit line connection pads 110-1a and 110-2a, first word line connection pads 120-1a and 120-2a, a first cell array region 150a, second bit line connection pads 130-1a and 130-2a, second word line connection pads 140-1a and 140-2a, a second cell array region 160a, and non-bonding regions 170a, 180a, and 190a. The peripheral circuit region PERI may include first bit line connection pads 110-1b and 110-2b, first word line connection pads 120-1b and 120-2b, a first non-bonding region 150b, second bit line connection pads 130-1b and 130-2b, second word line connection pads 140-1b and 140-2b, a second non-bonding region 160b, and third non-bonding regions 170b, 180b, and 190b.

[0045] The bit line connection pads 110-1a, 110-2a, 130-1a, and 130-2a and the word line connection pads 120-1a, 120-2a, 140-1a, and 140-2a in the cell region CELL may be a region including a wiring structure penetrating through the cell region CELL and connected to the peripheral circuit region PERI. The bit line connection pads 110-1a, 110-2a, 130-1a, and 130-2a and the word line connection pads 120-1a, 120-2a, 140-1a, and 140-2a may be disposed on at least one side of each of the first cell array region 150a and the second cell array region 160a, and may include, for example, a wiring structure, for example, a contact plug electrically connected to a row decoder of the peripheral circuit region PERI. In addition, a through wiring structure may also be provided in the first cell array region 150a and the second cell array region 160a, and for example, a region including a wiring structure of a page buffer electrically connected to the peripheral circuit region PERI may be included in the first cell array region 150a and the second cell array region 160a.

[0046] The first bit line connection pads 110-1a and 110-2a of the cell region CELL may be electrically connected to the first bit line connection pads 110-1b and 110-2b of the peripheral circuit region PERI, respectively, by a bonding method. Therefore, the first bit line connection pads 110-1a and 110-2a of the cell region CELL and the first bit line connection pads 110-1b and 110-2b of the peripheral circuit region PERI may be included in the bonding region.

[0047] The first word line connection pads 120-1a and 120-2a of the cell region CELL may be electrically connected to the first word line connection pads 120-1b and 120-2b of the peripheral circuit region PERI, respectively, by a bonding method. Therefore, the first word line connection pads 120-1a and 120-2a of the cell region CELL and the first word line connection pads 120-1b and 120-2b of the peripheral circuit region PERI may be included in the bonding region.

[0048] The second bit line connection pads 130-1a and 130-2a of the cell region CELL may be electrically connected to the second bit line connection pads 130-1b and 130-2b of the peripheral circuit region PERI, respectively, by a bonding method. Therefore, the second bit line connection pads 130-1a and 130-2a of the cell region CELL and the second bit line connection pads 130-1b and 130-2b of the peripheral circuit region PERI may be included in the bonding region.

[0049] The second word line connection pads 140-1a and 140-2a of the cell region CELL may be electrically connected to the second word line connection pads 140-1b and 140-2b of the peripheral circuit region PERI, respectively, by a bonding method. Therefore, the second word line connection pads 140-1a and 140-2a of the cell region CELL and the second word line connection pads 140-1b and 140-2b of the peripheral circuit region PERI may be included in the bonding region.

[0050] The first cell array region 150a and the second cell array region 160a of the cell region CELL and the first non-bonding region 150b and the second non-bonding region 160b of the peripheral circuit region PERI corresponding to the first cell array region 150a and the second cell array region 160a of the cell region CELL, respectively, may be included in the non-bonding region. In other words, the first cell array region 150a and the second cell array region 160a of the cell region CELL are not bonded. The non-bonding regions 170a, 180a, and 190a of the cell region CELL and the non-bonding regions 170b, 180b, and 190b of the peripheral circuit region PERI corresponding to the non-bonding regions 170a, 180a, and 190a of the cell region CELL, respectively, may be included in the non-bonding region.

[0051] The memory device 100 may be configured in such a manner that bonding regions 110-1a, 110-2a, 120-1a, and 120-2a are disposed to surround the first non-bonding region 150a, and similarly, bonding regions 130-1a, 130-2a, 140-1a, and 140-2a may be disposed to surround the second non-bonding region 160a.

[0052] Furthermore, the memory device 100 may be configured in such a manner that the bonding regions 110-1b, 110-2b, 120-1b, and 120-2b surround the first non-bonding region 150b, and similarly, the bonding regions 130-1b, 130-2b, 140-1b, and 140-2b surround the second non-bonding region 160b.

[0053] In the non-bonding regions 150a, 160a, 170a, 180a, 190a, 150b, 160b, 170b, 180b, and 190b, the metal pattern of the uppermost metal layer may exist as a dummy pattern, or the uppermost metal layer may be empty.

[0054] According to example embodiments, the uppermost metal layer of the non-bonding area provided as a dummy pattern or an empty space can be used as a signal line or a power line to reduce the chip size. The signal line can be a cable for transmitting a signal, and the power line can be a cable for supplying power. By using the uppermost metal layer of the non-bonding area as a wiring, the chip size can be reduced, and therefore, the integration of the memory device 100 can be increased.

[0055] FIG. 4A to FIG. 4D is a schematic plan view of a memory device according to example embodiments.

[0056] refer to Figure 4A Each of the first and second non-bonding regions 150b and 160b in the peripheral circuit region PERI may include a first side, a second side parallel to and opposite to the first side, and third and fourth sides parallel to and opposite to each other between the first and second sides.

[0057] In the memory device 100A, the bonding regions 110-2b and 120-2b may be disposed to surround the second and fourth sides of the first non-bonding region 150b in the peripheral circuit region PERI. In addition, in the memory device 100A, the bonding regions 130-1b and 140-1b may be disposed to surround the first and third sides of the second non-bonding region 160b. Figure 4A In the embodiment, the non-bonding regions 110-1b and 120-1b may be disposed to surround the first and third sides of the first non-bonding region 150b, and the non-bonding regions 130-2b and 140-2b may be disposed to surround the second and fourth sides of the second non-bonding region 160b.

[0058] refer to Figure 4B ,and Figure 4A The memory device 100A is different in that Figure 4B In the case of the memory device 100B, the bonding regions 110-1b and 120-1b may be disposed to surround the first side and the third side of the first non-bonding region 150b in the peripheral circuit region PERI. In addition, in the memory device 100B, the bonding regions 130-2b and 140-2b may be disposed to surround the second side and the fourth side of the second non-bonding region 160b. Figure 4B In the embodiment, the non-bonding regions 110-2b and 120-2b may be disposed to surround the second and fourth sides of the first non-bonding region 150b, and the non-bonding regions 130-1b and 140-1b may be disposed to surround the first and third sides of the second non-bonding region 160b.

[0059] refer to Figure 4C ,and Figure 4A The memory device 100A is different in that Figure 4CIn the case of the memory device 100C, the bonding regions 110-2b and 120-2b may be disposed to surround the second and fourth sides of the first non-bonding region 150b in the peripheral circuit region PERI. In addition, in the memory device 100C, the bonding regions 130-2b and 140-2b may be disposed to surround the second and fourth sides of the second non-bonding region 160b. Figure 4C In the embodiment, the non-bonding regions 110-1b and 120-1b may be disposed to surround the first and third sides of the first non-bonding region 150b, and the non-bonding regions 130-1b and 140-1b may be disposed to surround the first and third sides of the second non-bonding region 160b.

[0060] refer to Figure 4D ,and Figure 4A The memory device 100A is different in that Figure 4D In the case of the memory device 100D, the bonding regions 110-1b and 120-1b may be disposed to surround the first side and the third side of the first non-bonding region 150b in the peripheral circuit region PERI. In addition, in the memory device 100D, the bonding regions 130-1b and 140-1b may be disposed to surround the first side and the third side of the second non-bonding region 160b. Figure 4D In the embodiment, the non-bonding regions 110-2b and 120-2b may be disposed to surround the second and fourth sides of the first non-bonding region 150b, and the non-bonding regions 130-2b and 140-2b may be disposed to surround the second and fourth sides of the second non-bonding region 160b.

[0061] As reference FIG. 4A to FIG. 4D As described, the arrangement of the bonding region and the non-bonding region in the peripheral circuit region PERI may be variously changed. Similarly, the bonding region and the non-bonding region in the cell region CELL may also be variously changed.

[0062] Figures 5 to 8 It is taken along lines I-I' and II-II' Figure 3 A cross-sectional view of a memory device is shown.

[0063] First, refer to Figure 5 , the memory device 200 may include a peripheral circuit region PERI and a cell region CELL disposed on the peripheral circuit region PERI. Each of the peripheral circuit region PERI and the cell region CELL may include a first non-bonding region NBA1, a bonding region RA, and a second non-bonding region NBA2.

[0064] The peripheral circuit region PERI may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit devices 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c connected to the plurality of circuit devices 220a, 220b, and 220c, respectively, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c, respectively. The first metal layers 230a, 230b, and 230c may be formed of tungsten having a relatively high resistance. The second metal layers 240a, 240b, and 240c may be formed of copper having a relatively low resistance.

[0065] In this specification, only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are shown and described, but example embodiments thereof are not limited thereto. For example, a third metal layer may be formed on the second metal layers 240a, 240b, and 240c. The third metal layer may be formed of aluminum, which has a lower resistance than the copper forming the second metal layers 240a, 240b, and 240c.

[0066] An interlayer insulating layer 215 may be disposed on the first substrate 210 to cover the plurality of circuit devices 220a, 220b, and 220c, the first metal layers 230a, 230b, and 230c, and the second metal layers 240a, 240b, and 240c. The interlayer insulating layer 215 may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0067] Lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the bonding area BA. In the bonding area BA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL by a Cu-Cu bonding method.

[0068] The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 310 and a common source line 320 .

[0069] On the second substrate 310, a plurality of word lines 331 to 338 (collectively referred to as word lines 330) may be stacked in a third direction (Z direction) perpendicular to the upper surface of the second substrate 310. A string selection line and a ground selection line may be respectively disposed at the upper and lower portions of the word lines 330. A plurality of word lines 330 may be disposed between the string selection line and the ground selection line.

[0070] In the second non-bonding region NBA2, the channel structure CH may extend in a third direction (Z direction) to penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, an embedded insulating layer, etc., and the channel layer may be electrically connected to the second metal layer 360c through the first metal layer 350c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In an example embodiment, the bit line 360c may extend in the second direction (Y direction). An area provided with the channel structure CH, the bit line 360c, etc. may be defined as the second non-bonding region NBA2.

[0071] In the bonding area, the word line 330 may extend in the first direction (X direction) and may be connected to a plurality of cell contact plugs 341 to 347 (collectively referred to as contact plugs 340) in the bonding area RA. The word line 330 and the cell contact plugs 340 may be connected to each other on the pad. The first metal layer 350b and the second metal layer 360b may be sequentially stacked on the word line 330. The word line 330 may be connected to the peripheral circuit area PERI in the bonding area RA through the upper bonding metals 371b and 372b of the cell area CELL and the lower bonding metals 271b and 272b of the peripheral circuit area PERI.

[0072] In the first non-joining area NBA1, the common source line contact plug 380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, etc. The common source line contact plug 380 may be electrically connected to the common source line 320. The first metal layer 350a and the second metal layer 360a may be sequentially stacked on the common source line contact plug 380. A region where the common source line contact plug 380, the first metal layer 350a and the second metal layer 360a are disposed may be defined as the first non-joining area NBA1.

[0073] In the respective first and second non-bonding regions NBA1 and NBA2 included in each of the cell region CELL and the peripheral circuit region PERI, the metal pattern of the uppermost metal layer may exist as a dummy pattern, or the uppermost metal layer may be empty.

[0074] According to example embodiments, in order to reduce the chip size, the uppermost metal layers of the corresponding first non-joint area NBA1 and the second non-joint area NBA2 provided as dummy patterns or empty spaces may be used as signal lines or power lines. With this configuration, the chip size may be reduced by using the uppermost metal layers of the corresponding first non-joint area NBA1 and the second non-joint area NBA2 as wiring. Therefore, the integration of the memory device 200 may be increased.

[0075] refer to Figure 6In the memory device 300, wiring may be formed in the uppermost metal layer in the first non-bonding region NBA1 and the second non-bonding region NBA2 of the cell region CELL and the peripheral circuit region PERI. The wiring may be a signal line or a power line. For example, the wiring may be formed of copper.

[0076] As an example, in the first non-bonding area NBA1, the uppermost metal layer of the cell area CELL may be an empty space. In this case, the upper bonding metals 371a and 372a may be formed in the uppermost metal layer of the cell area CELL. The upper bonding metals 371a and 372a formed in the uppermost metal layer of the cell area CELL may be used as wiring.

[0077] For example, upper bonding metals 371a and 372a formed in the uppermost metal layer of the cell region CELL may be disposed on the common source line contact plug 380. The upper bonding metals (371a and 372a) formed in the uppermost metal layer of the cell region CELL may include a contact 371a and an upper metal pattern 372a. The common source line contact plug 380 and the upper metal pattern 372a may be electrically connected to each other through the contact 371a.

[0078] According to example embodiments, in the first non-bonding region NBA1 , the uppermost metal layer of the cell region CELL may further include a dummy pattern.

[0079] In the first non-bonding area NBA1, the uppermost metal layer of the peripheral circuit area PERI may be an empty space. In this case, the lower bonding metals 271a and 272a may be formed in the uppermost metal layer of the peripheral circuit area PERI. The lower bonding metals 271a and 272a formed in the uppermost metal layer of the peripheral circuit area PERI may be used as wiring.

[0080] For example, in the first non-bonding area NBA1, the lower bonding metals 271a and 272a formed in the uppermost metal layer of the peripheral circuit area PERI may be disposed on the second metal layer 240a. The lower bonding metals 271a and 272a formed in the uppermost metal layer of the peripheral circuit area PERI may include a contact 271a and an upper metal pattern 272a. The second metal layer 240a and the upper metal pattern 272a may be electrically connected to each other through the contact 271a.

[0081] In some embodiments, in the first non-bonding area NBA1, the uppermost metal layer of the peripheral circuit area PERI may further include a dummy pattern.

[0082] In the second non-bonding area NBA2, the uppermost metal layer of the peripheral circuit area PERI may be an empty space. In this case, the lower bonding metals 251 and 252 may be formed in the uppermost metal layer of the peripheral circuit area PERI. The lower bonding metals 251 and 252 formed in the uppermost metal layer of the peripheral circuit area PERI may be used as wiring.

[0083] For example, in the second non-bonding area NBA2, the lower bonding metals 251 and 252 formed in the uppermost metal layer of the peripheral circuit area PERI may be disposed on the second metal layer 240c. The lower bonding metal (251 and 252) formed in the uppermost metal layer of the peripheral circuit area PERI may include a contact 251 and a lower metal pattern 252. The second metal layer 240c and the lower metal pattern 252 may be electrically connected to each other through the contact 251.

[0084] According to example embodiments, in the second non-bonding area NBA2, the uppermost metal layer of the peripheral circuit area PERI may further include a dummy pattern.

[0085] The peripheral circuit area PERI may include a logic area and a core area. The core area may include a page buffer, a row decoder, etc. The logic area may include a voltage generator, a control logic such as a timing controller for driving the core area, etc. The logic area and the core area may be powered by one power supply. Therefore, the power provided to the logic area and the core area, respectively, may have the same level.

[0086] The signal line or the power line may be formed in the uppermost metal layer of the non-bonding region. For example, when the signal line is formed in the uppermost metal layer of the non-bonding region, the signal line may be a word line, a bit line, and a signal line of the logic region. In addition, when the power line is formed in the uppermost metal layer of the non-bonding region, the power line may be a voltage of the common source region, a power supply voltage and a ground voltage of the logic region, and a power line of the external power supply voltage EVC.

[0087] According to example embodiments, a chip size may be reduced by forming wirings in an uppermost metal layer of a non-bonding region.

[0088] For example, when the power line is formed in the uppermost metal layer of the non-bonded area, the utilization rate of the power line can be increased. Therefore, the logic area and the core area can be powered by different power supplies, respectively. As a result, the power supplied to the logic area and the core area, respectively, can have different levels. In addition, since each power supply can be controlled independently, the control load of each power supply can be reduced.

[0089] The uppermost metal layer of the non-bonding area can also be used as a power line providing a predetermined voltage level. For example, the predetermined voltage level can be a power supply voltage, a ground voltage, etc. The power line supplied with the predetermined voltage level can be located between two signal lines. As a result, the power line can prevent crosstalk between the two signal lines. Therefore, the power line formed in the uppermost metal layer of the non-bonding area can be used for signal shielding.

[0090] refer to Figure 7 In the case of the memory device 400, in the first non-bonding region NBA1 corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell region CELL, a lower metal pattern 273a having the same shape as the upper metal pattern 372a of the cell region CELL may be formed in the uppermost metal layer of the peripheral circuit region PERI. No contact may be formed on the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit region PERI.

[0091] Similarly, in the first non-bonding area NBA1 corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area PERI, an upper metal pattern 373a having the same shape as the lower metal pattern of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL. No contact may be formed on the upper metal pattern 373a formed in the uppermost metal layer of the cell area CELL.

[0092] In the second non-bonding area NBA2 corresponding to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit area PERI, an upper metal pattern 392 having the same shape as the lower metal pattern 252 of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL. No contact may be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell area CELL.

[0093] According to example embodiments, corresponding to the metal pattern formed in the uppermost metal layer of any one chip, an enhanced metal pattern having the same shape as the metal pattern may also be formed in the uppermost metal layer of another chip. In this case, a contact may not be formed on the enhanced metal pattern.

[0094] Therefore, the thickness of the metal pattern formed in any one chip can be increased. As the thickness of the metal pattern increases, the resistance of the metal pattern can be reduced. As a result, when the metal pattern formed in any one chip is used as a signal line, the signal characteristics can be improved. In addition, when the metal pattern formed in any one chip is used as a power line, power supply noise can be reduced.

[0095] The metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI and the metal pattern formed in the uppermost metal layer of the cell region CELL may be formed at the same position. Therefore, the mask used to form the metal pattern in the uppermost metal layer of the peripheral circuit region PERI and the mask used for the metal pattern in the uppermost metal layer of the cell region CELL may be the same. Since the same mask may be used to form the metal pattern of the uppermost metal layer of the peripheral circuit region PERI and the metal pattern of the uppermost metal layer of the cell region CELL, the process cost may be reduced.

[0096] refer to Figure 8 The memory device 500 may further include a contact 374a on an upper metal pattern 373a formed in the uppermost metal layer of the cell region CELL in the first non-bonding region NBA1. The contact 374a formed on the upper metal pattern 373a may not be electrically connected to the second metal layer 360a of the first non-bonding region NBA1.

[0097] Similarly, in the second non-bonding region NBA2, a contact 391 may also be provided on an upper metal pattern 392 formed in the uppermost metal layer of the cell region CELL. The contact 391 formed on the upper metal pattern 392 may not be electrically connected to the second metal layer 360c.

[0098] Chemical mechanical polishing (CMP) may refer to a process for polishing and flattening a wafer. Pressure may be applied to the wafer during the CMP process. If there is no material used as a support (e.g., a contact, etc.) below the metal pattern formed in the uppermost metal layer, the chip may collapse due to the pressure applied during the CMP process. Therefore, chip failure may occur during the CMP process.

[0099] According to example embodiments, the possibility of chip defects occurring during a CMP process may be reduced by further forming a contact not connected to the second metal layer on a reinforcement metal pattern formed in an uppermost metal layer in a non-bonding region.

[0100] Fig. 9 is a schematic plan view illustrating a memory device according to example embodiments.

[0101] refer to Fig. 9 , the peripheral circuit region of the memory device 600 may include a bonding region RA, a first non-bonding region NBA1, and a second non-bonding region NBA2. Figure 3 As described, in the bonding area BA of the peripheral circuit area, a metal pattern MP for bonding may be formed in an uppermost metal layer of the bonding area RA of the peripheral circuit area to connect the peripheral circuit area and the cell area to each other.

[0102] In the first non-bonding area NBA1 of the peripheral circuit area, the first wiring 410 may be formed in the uppermost metal layer. For example, the first wiring 410 may be used as a power supply line for supplying power to a common source line. Therefore, the chip size may be reduced.

[0103] Corresponding to the power line 410 formed in the uppermost metal layer of the peripheral circuit region, a reinforcing metal pattern having the same shape as the power line 410 formed in the uppermost metal layer of the peripheral circuit region can be formed in the uppermost metal layer of the cell region. Therefore, the resistance of the power line 410 for supplying power to the common source line can be reduced, thereby reducing power supply noise.

[0104] exist Fig. 9 The reason why the power line 410 is formed in a zigzag pattern is that the density of the metal pattern of the power line 410 should satisfy 80% or less of the entire area of ​​the first non-bonding area NBA1. In addition, in the case where the power line 410 is formed in a line pattern instead of a zigzag pattern, any one bit line may pass entirely under the power line 410, and another bit line may pass entirely between the metal patterns of the power line 410. Therefore, for each memory cell included in the cell region, the characteristics of the memory cell may vary.

[0105] In the second non-bonding area NBA2 of the peripheral circuit area, the second wiring 420 and the third wiring 430 may be formed in the uppermost metal layer. For example, the second wiring 420 may be used as a power line for supplying a power supply voltage and a ground voltage of the logic area and an external power supply voltage EVC. The third wiring 430 may be used as a signal wiring, for example, a word line, a bit line, and a signal line of the logic area. Therefore, the chip size may be reduced.

[0106] In addition, when the second wiring 420 is used as a power supply line, power supply noise can be reduced and can be used for signal shielding. When the third wiring 430 is used as a signal line, signal characteristics can be improved.

[0107] Fig.10 is a block diagram schematically illustrating an electronic device including a memory device according to an exemplary embodiment.

[0108] according to Fig.10 The electronic device 1000 of the exemplary embodiment shown in FIG. 1 may include a display 1010, a sensor unit 1020, a memory 1030, a communication unit 1040, a processor 1050, a port 1060, etc. The electronic device 1000 may also include a power supply device, an input / output device, etc. Fig.10Among the components shown, port 1060 may be a device provided for electronic device 1000 to communicate with a video card, sound card, memory card, USB device, etc. Electronic device 1000 may include not only a general desktop computer or laptop computer, but also a smart phone, tablet PC, smart wearable device, etc.

[0109] The processor 1050 may perform specific operations, instructions, tasks, etc. The processor 1050 may be a central processing unit (CPU) or a microprocessor unit (MCU), a system on a chip (SoC), etc., and may communicate with other devices connected to the port 1060 as well as the display 1010, the sensor unit 1020, the memory 1030, and the communication unit 1040 through a bus.

[0110] The memory 1030 may be a storage medium that stores data required for the operation of the electronic device 1000, multimedia data, etc. The memory 1030 may include a volatile memory such as a random access memory (RAM) or a non-volatile memory such as a flash memory. The memory 1030 may also include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical drive (ODD) as a storage device. Fig.10 In the example embodiment shown, the memory 1030 may include the memory 1030 described above. Figures 1 to 9 The memory devices of the various embodiments described above.

[0111] As described above, according to various exemplary embodiments, wiring can be formed in the uppermost metal layer of the non-bonding region, wherein the cell region and the peripheral circuit region are not electrically connected in the non-bonding region. Therefore, since there is no need to ensure a separate space for wiring, the chip size can be reduced.

[0112] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, comprising: A first semiconductor chip including a memory cell array disposed on a first substrate and a first bonding metal on a first uppermost metal layer of the first semiconductor chip; as well as a second semiconductor chip including a circuit device disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit device providing a peripheral circuit for operating the memory cell array, wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other in a bonding region by the first bonding metal and the second bonding metal, A wiring electrically connected to the peripheral circuit is provided in at least one of the first uppermost metal layer or the second uppermost metal layer and is provided in a non-bonding region where the first semiconductor chip and the second semiconductor chip are not electrically connected to each other, and The wiring is a power supply line for supplying power to the peripheral circuit of the second semiconductor chip.

2. The memory device according to claim 1, wherein: The second semiconductor chip includes a first metal layer disposed on the second substrate and a second metal layer disposed on the first metal layer, and The wiring is provided on the second uppermost metal layer in the non-bonding region and is electrically connected to the second metal layer.

3. The memory device according to claim 1, wherein: The first semiconductor chip includes a first metal layer disposed on the first substrate and a second metal layer disposed on the first metal layer, and The wiring is provided in the first uppermost metal layer and is electrically connected to the second metal layer in the non-bonding region.

4. The memory device according to claim 1, wherein: The wiring includes a first wiring disposed on the first uppermost metal layer and a second wiring disposed on the second uppermost metal layer, The first wiring includes a first contact and a first metal pattern, The second wiring includes a second contact and a second metal pattern, and The first metal pattern and the second metal pattern are not electrically connected to each other.

5. The memory device according to claim 4, wherein: The second semiconductor chip includes a first metal layer disposed on the second substrate and a second metal layer disposed on the first metal layer, and The second metal pattern is disposed on the second uppermost metal layer and is electrically connected to the second metal layer through the second contact in the non-bonding region.

6. The memory device according to claim 4, wherein: The first semiconductor chip includes a first metal layer disposed on the first substrate and a second metal layer disposed on the first metal layer, and The first metal pattern is disposed on the first uppermost metal layer and is electrically connected to the second metal layer through the first contact in the non-bonding region.

7. The memory device according to claim 5, wherein: A third metal pattern having the same shape as that of the first metal pattern is disposed on the second uppermost metal layer in a position corresponding to that of the first metal pattern disposed on the first uppermost metal layer.

8. The memory device according to claim 7, wherein: The first metal pattern and the third metal pattern are electrically connected to each other.

9. The memory device according to claim 8, wherein: The third metal pattern is provided with a third contact, and the third contact is provided on the third metal pattern.

10. The memory device according to claim 1, wherein: At least one of the first uppermost metal layer or the second uppermost metal layer includes a dummy pattern in the non-bonding region.

11. A storage device comprising: A memory cell region, comprising: word lines stacked on a first substrate, bit lines disposed on the word lines, a channel structure passing through the word lines and connected to the bit lines, and a common source line; a peripheral circuit region disposed on the second substrate and including a peripheral circuit for operating a memory cell array included in the memory cell region; a bonding metal electrically connecting the uppermost metal layer of the memory cell region and the uppermost metal layer of the peripheral circuit region to each other in a bonding region; and wiring electrically connected to the peripheral circuit in a non-bonding region, wherein the memory cell region and the peripheral circuit region are not electrically connected to each other in the non-bonding region, The bonding area of ​​the memory cell area includes a cell contact plug electrically connected to the word line and the peripheral circuit. The cell contact plug is located between the non-bonding regions, and The wiring is a power supply line for supplying power to the peripheral circuit.

12. The memory device according to claim 11, wherein: The memory cell region further includes a common source line contact plug electrically connected to the common source line, and The wiring is disposed on the common source line contact plug in the uppermost metal layer of the memory cell region.

13. The memory device according to claim 11, wherein: The memory cell region further includes a common source line contact plug electrically connected to the common source line, and The wiring is disposed on the common source line contact plug in the uppermost metal layer of the peripheral circuit region.

14. The memory device according to claim 11, wherein: The wiring includes a first wiring and a second wiring, the first wiring is included in the memory cell region, and the second wiring is included in the peripheral circuit region, and The first wiring and the second wiring have different patterns.

15. The memory device according to claim 11, wherein: The wiring includes a first wiring and a second wiring, the first wiring is included in the memory cell region, and the second wiring is included in the peripheral circuit region, and The first wiring and the second wiring have the same pattern.

16. The memory device according to claim 11, wherein: The wiring provides a predetermined voltage level and is located between signal lines that transmit signals.

17. A storage device comprising: A first semiconductor chip including a first bonding region and a first non-bonding region disposed around the first bonding region; as well as a second semiconductor chip comprising: a second bonding region and a second non-bonding region, the second bonding region being disposed in a position corresponding to the position of the first bonding region, and the second non-bonding region being disposed in a position corresponding to the position of the first non-bonding region and surrounding the second bonding region, wherein a metal contact disposed on the uppermost metal layer of the first bonding region and a metal contact disposed on the uppermost metal layer of the second bonding region are electrically connected to each other, The metal contact disposed in the uppermost metal layer of the first non-bonding region and the metal contact disposed on the uppermost metal layer of the second non-bonding region are not electrically connected to each other, The metal contact formed wiring is provided in the uppermost metal layer of the second non-bonding area, The first bonding area surrounds at least a portion of the first non-bonding area, The second bonding area surrounds at least a portion of the second non-bonding area, and The wiring is a power supply line for supplying power to a peripheral circuit of the second semiconductor chip.

18. The memory device according to claim 17, wherein: The first semiconductor chip further includes a third bonding region and a third non-bonding region disposed around the third bonding region. The second semiconductor chip further includes a fourth bonding region and a fourth non-bonding region disposed around the fourth bonding region. At least one of the first bonding region and the third bonding region is disposed between the first non-bonding region and the third non-bonding region, and At least one of the second bonding region and the fourth bonding region is provided between the second non-bonding region and the fourth non-bonding region.

19. The memory device according to claim 18, wherein: No joining region is provided between the first non-joining region and the third non-joining region.

20. The memory device according to claim 18, wherein: No joining region is provided between the second non-joining region and the fourth non-joining region.

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