Semiconductor package

Abstract

A semiconductor package is provided, which includes a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface, the first upper surface including a first flat portion extending parallel to the upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.

Description

Technical Field

[0001] The present disclosure relates to semiconductor packages. Background Art

[0002] A semiconductor package including an integrated circuit chip therein may be included in an electronic device. A semiconductor package may be manufactured by mounting a semiconductor chip on a substrate such as a printed circuit board (PCB) and electrically connecting the semiconductor chips to each other using bonding wires or bumps.

[0003] With the development of the electronics industry, there is an increasing demand for high-function, high-speed, and smaller electronic components. Accordingly, semiconductor devices or semiconductor packages having high-speed signal transmission, reduced size, and wiring redistribution have been developed. Summary of the Invention

[0004] According to an exemplary embodiment of the inventive concept, there is provided a semiconductor package including: a redistribution substrate; and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate includes: a lower protection layer; a first conductive pattern disposed on the lower protection layer; a first insulating layer surrounding the first conductive pattern and disposed on the lower protection layer, the first insulating layer including a first upper surface including a first flat portion extending parallel to the upper surface of the lower protection layer and a first recess facing the lower protection layer and directly connected to the first conductive pattern; and a second insulating layer disposed on the first insulating layer.

[0005] According to an exemplary embodiment of the inventive concept, there is provided a semiconductor package including: a lower protection layer; a first conductive pattern disposed on the lower protection layer; a first insulating layer in contact with a side surface of the first conductive pattern on the lower protection layer; a second insulating layer covering the first insulating layer and the first conductive pattern or extending on the first insulating layer and the first conductive pattern; and a semiconductor chip disposed on the second insulating layer. The first insulating layer may include a first upper surface and an inclined surface adjacent to the side surface of the first conductive pattern, and the first upper surface of the first insulating layer may extend parallel to the upper surface of the lower protection layer, and a distance from the upper surface of the lower protection layer to the inclined surface may vary toward the first conductive pattern.

[0006] According to an exemplary embodiment of the inventive concept, there is provided a semiconductor package including: a redistribution substrate; a semiconductor chip mounted on the redistribution substrate; and a molding film covering a side surface of the semiconductor chip on the redistribution substrate or extending on a side surface of the semiconductor chip. The redistribution substrate may include: a lower protective layer; a first conductive pattern disposed on the lower protective layer; a first insulating layer surrounding the first conductive pattern on the lower protective layer; a second insulating layer covering the first insulating layer and the first conductive pattern; and a terminal pad disposed on the second insulating layer and electrically connected to the semiconductor chip. The first insulating layer includes an inclined surface, a first upper surface, and a second upper surface sequentially positioned from the first conductive pattern, and the second upper surface is located at the same level as an upper surface of the first conductive pattern. The first upper surface is located at a lower level than the second upper surface, and a distance from an upper surface of the lower protective layer to the inclined surface varies from the first upper surface to the first conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0008] Figure 2A shows a plan view of a redistribution substrate of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0009] Figure 2B shows a cross-sectional view of a redistribution substrate of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0010] Figures 3A to 3C shows Figure 2B an enlarged view of region A.

[0011] Figure 4 shows a cross-sectional view of a redistribution substrate of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0012] Figure 5A is a plan view showing a redistribution substrate of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0013] Figure 5B and Figure 5C shows a cross-sectional view of a redistribution substrate of a semiconductor package according to an exemplary embodiment of the inventive concept.

[0014] Figures 6 to 11 shows a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0015] Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and their repeated description may be omitted.

[0016] Figure 1 A cross-sectional view of a semiconductor package according to an example embodiment of the inventive concept is shown. Figure 2A is a plan view of a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concept. Figure 2A Schematically shows Figure 1 the redistribution substrate of the semiconductor package, and for ease of description, some components are not shown. Figure 2B A cross-sectional view of a redistribution substrate of a semiconductor package according to an example embodiment of the inventive concept is shown and corresponds to a cross-section taken along line I-I' of Figure 2A the. Figures 3A to 3C Shows Figure 2B an enlarged view of region A of

[0017] Referring to Figure 1 , Figure 2A and Figure 2B , the semiconductor package 1000 may include a redistribution substrate 10, a semiconductor chip 20, and a molding layer 30.

[0018] The redistribution substrate 10 may include a lower protection layer 100 and first and second wiring layers 200 and 300 stacked on the lower protection layer 100.

[0019] The lower protection layer 100 may protect and support the wiring layers 200 and 300. The lower protection layer 100 may include a silicon substrate and / or an insulating substrate. For example, the lower protection layer 100 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and / or a polyamide-based polymer material, but the lower protection layer 100 is not limited thereto. The lower protection layer 100 may be omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0020] The first wiring layer 200 may be disposed on the lower protection layer 100. The first wiring layer 200 may include a first conductive pattern 210 and a first insulating layer 220.

[0021] The first conductive pattern 210 may be disposed on the lower protection layer 100. The first conductive pattern 210 may include various components that form a circuit in the first wiring layer 200. For example, the first conductive pattern 210 may be a conductive pad to which an external terminal or a conductive via is connected. In Figure 2BIn [the figure], the first conductive pattern 210 is shown as a conductive pad, but the inventive concept is not limited thereto. For example, the first conductive pattern 210 may include: a conductive via that electrically connects an upper wiring layer and a lower wiring layer; a conductive wiring that extends in a direction parallel to the upper surface of the lower protective layer 100 to form a circuit; or a conductive pad having a width wider than that of the conductive via or the conductive wiring. The conductive via, the conductive wiring, an external solder ball, etc. may be connected to the conductive pad.

[0022] As used herein, "electrically connected" (or similar language) may mean "directly or indirectly electrically connected". The first conductive pattern 210 may include a conductive material. For example, the first conductive pattern 210 may include copper (Cu), a copper alloy, and / or aluminum (Al).

[0023] A plurality of first conductive patterns 210 may be provided. As Figure 1 and Figure 2A shown, the first conductive patterns 210 may be disposed on the lower protective layer 100 and may be horizontally spaced apart from each other. In this case, the distance between the first conductive patterns 210 may be greater than the width of the first recess RS1 of the first insulating layer 220 (which will be described later). One of the first conductive patterns 210 may include a conductive pad, and another one 210' of the first conductive patterns may include a passive element.

[0024] For example, the passive element may be a capacitor as Figure 1 shown. In some embodiments, the passive element may include various passive elements, such as a resistive element. In some embodiments, the first conductive pattern 210 may include both a conductive pad and a passive element, or may include only a conductive pad or a passive element.

[0025] The first insulating layer 220 may be disposed on the lower protective layer 100. In a plan view, the first insulating layer 220 may surround the first conductive pattern 210. The first insulating layer 220 may contact a side surface 210b of the first conductive pattern 210. The first insulating layer 220 may include an insulating material. For example, the first insulating layer 220 may include a dry film resist (DFR) and / or a photoimageable dielectric (PID). The upper surface of the first insulating layer 220 may include a first upper surface 220a surrounding the first conductive pattern 210, a second upper surface 220b located between the first conductive pattern 210 and the first upper surface 220a, and a first inclined surface 220c extending from the second upper surface 220b and facing the side surface 210b of the first conductive pattern 210. That is, the second upper surface 220b may be located inside the first upper surface 220a in a plan view and may surround the first conductive pattern 210. In addition, the first inclined surface 220c may be located inside the second upper surface 220b in a plan view and may surround the first conductive pattern 210.

[0026] The first upper surface 220a may be substantially flat. The first upper surface 220a may be parallel to the upper surface of the lower protective layer 100. As Figure 3A shown, the first upper surface 220a may be at the same level as the upper surface 210a of the first conductive pattern 210. The first upper surface 220a may be coplanar with the upper surface 210a of the first conductive pattern 210, as Figure 3A shown. In some embodiments, the first upper surface 220a may be at a higher level than the upper surface 210a of the first conductive pattern 210, as Figure 3B shown. The distance between the first upper surface 220a and the lower protective layer 100 may be longer than the distance between the upper surface 210a of the first conductive pattern 210 and the lower protective layer 100, as Figure 3B shown. In some embodiments, the first upper surface 220a may be at a level lower than the upper surface of the first conductive pattern 210, as Figure 3C shown. The distance between the first upper surface 220a and the lower protective layer 100 may be shorter than the distance between the upper surface 210a of the first conductive pattern 210 and the lower protective layer 100, as Figure 3C shown. In some embodiments, the second upper surface 220b may be at a level lower than the first upper surface 220a. The distance between the second upper surface 220b and the lower protective layer 100 may be shorter than the distance between the first upper surface 220a and the lower protective layer 100, as Figure 3A , Figure 3B and Figure 3C shown. The "distance between component A and component B" (or similar language) may refer to the shortest distance between component A and component B.

[0027] For example, the first insulating layer 220 may include a first recess RS1 that is recessed toward the lower protective layer 100. The lowest (i.e., bottommost) point LP of the first recess RS1 may be lower than the first upper surface 220a. The first recess RS1 may be located between the first conductive pattern 210 and the first upper surface 220a of the first insulating layer 220. For example, as Figure 2A shown, in a plan view, the first recess RS1 may be formed in a portion of the first insulating layer 220 adjacent to the first conductive pattern 210, and the first recess RS1 may surround the first conductive pattern 210. That is, the first recess RS1 may separate the first conductive pattern 210 from the first upper surface 220a of the first insulating layer 220.

[0028] The bottom surface of the first recess RS1 may be the same component as the second upper surface 220b, and the same reference numeral may be used herein. In some embodiments, the second upper surface 220b may define the bottom surface of the first recess RS1. The distance from the upper surface of the lower protective layer 100 to the bottom surface 220b of the first recess RS1 may be, for example, 0.5 times to 1 times the distance from the upper surface of the lower protective layer 100 to the first upper surface 220a. In some embodiments, the distance from the upper surface of the lower protective layer 100 to the lower surface 220b of the first recess RS1 is 0.7 times to 0.9 times the distance from the upper surface of the lower protective layer 100 to the first upper surface 220a, as Figure 3A shown.

[0029] The first inclined surface 220c may extend from one end of the second upper surface 220b to the side surface 210b of the first conductive pattern 210. The first inclined surface 220c may be inclined with respect to the second upper surface 220b. According to Figure 3A , the first inclined surface 220c may be the first side of the first recess RS1, which extends from the bottom surface 220b of the first recess RS1 toward the side surface 210b of the first conductive pattern 210. The first inclined surface 220c may define the first side surface of the first recess RS1. Herein, the first side surface of the first recess RS1 adjacent to the first conductive pattern 210 may be the same component as the first inclined surface 220c, and thus the same reference numeral may be used.

[0030] The first side surface 220c of the first recess RS1 may be inclined with respect to both the side surface 210b of the first conductive pattern 210 and the first upper surface 220a of the first insulating layer 220. The distance between the first side surface 220c and the lower protective layer 100 may increase from the second upper surface 220b toward the first conductive pattern 210. In some embodiments, the distance between the first side surface 220c and the lower protective layer 100 may increase as the distance from the second upper surface 220b increases, as Figures 3A to 3C shown.

[0031] Specifically, as Figure 3AAs shown, a first distance D1 between a lowest point LP of a first side surface 220c of the first recess RS1 and the lower protection layer 100 may be shorter than a second distance D2 between a first upper surface 220a and the lower protection layer 100. That is, the first inclined surface 220c may be a surface extending in an obliquely upward direction from a second upper surface 220b corresponding to a bottom surface 220b of the first recess RS1. The first distance D1 may be equal to a distance between the second upper surface 220b and the lower protection layer 100. A third distance D3 between a highest point TP of the first side surface 220c of the first recess RS1 and the lower protection layer 100 may be equal to the second distance D2 between the first upper surface 220a of the first insulating layer 220 and the lower protection layer 100. That is, the highest point TP of the first side surface 220c of the first recess RS1 may be located at the same level as an upper surface 210a of the first conductive pattern 210. The highest point TP of the first side surface 220c may be the highest point of the first insulating layer 220.

[0032] In some embodiments, the highest point TP of the first side surface 220c of the first recess RS1 may be located at a level lower than an upper surface 210a of the first conductive pattern 210, as Figure 3C shown. That is, a distance between the highest point TP of the first side surface 220c of the first recess RS1 and the lower protection layer 100 may be shorter than a distance between the upper surface 210a of the first conductive pattern 210 and the lower protection layer 100.

[0033] In an exemplary embodiment, the first inclined surface 220c of the first insulating layer 220 may be inclined with respect to the second upper surface 220b. Figure 4 FIG. shows a cross-sectional view of a redistribution substrate of a semiconductor package according to an exemplary embodiment of the inventive concept. As Figure 4 shown, a distance between the first inclined surface 220c and the lower protection layer 100 may decrease as a distance from the second upper surface 220b increases. Specifically, a distance between a lowest point LP of the first inclined surface 220c and the lower protection layer 100 may be shorter than a distance between a second upper surface 220b of the first insulating layer 220 and the lower protection layer 100. That is, the first inclined surface 220c may be a surface extending downward from the second upper surface 220b. The first inclined surface 220c may extend from the second upper surface 220b toward the lower protection layer 100, as Figure 4 shown. A distance from the lower protection layer 100 to the lowest point LP of the first inclined surface 220c may be, for example, 0.5 times to 1 times a distance from the lower protection layer 100 to the first upper surface 220a. Hereinafter, reference will be made back to Figure 1 、 Figure 2A and Figure 2B for continued description.

[0034] Reference is made back to Figure 1, Figure 2A and Figure 2B , the second wiring layer 300 may be disposed on the first wiring layer 200. The second wiring layer 300 may include a second conductive pattern 310, a third conductive pattern 320, and a second insulating layer 330.

[0035] The second conductive pattern 310 and the third conductive pattern 320 may be disposed on the first wiring layer 200. Specifically, the second conductive pattern 310 may be disposed on the first conductive pattern 210. The third conductive pattern 320 may be disposed on the first insulating layer 220. The second conductive pattern 310 and the third conductive pattern 320 may include various components that form a circuit in the second wiring layer 300. For example, the second conductive pattern 310 may be a conductive pad connected to the first conductive pattern 210 of the first wiring layer 200, and the third conductive pattern 320 may be a conductive wiring that extends from the upper surface 210a of the first conductive pattern 210 to the upper surface of the first insulating layer 220 to form a circuit. In some embodiments, similar to the first conductive pattern 210 described above, the second conductive pattern 310 may include passive elements, such as capacitors or resistive elements. A plurality of second conductive patterns 310 may be provided. As Figure 2B shown, one 312 of the second conductive patterns 310 may be connected to the first conductive pattern 210, and another 314 of the second conductive patterns 310 may be provided on the first insulating layer 220. The second conductive patterns 310 may be electrically connected through the third conductive pattern 320. The third conductive pattern 320 may extend along the top surface of the first insulating layer 220.

[0036] The third conductive pattern 320 extends from the top surface 210a of the first conductive pattern 210 along the bottom surface 220b of the first recess RS1 of the first insulating layer 220. The third conductive pattern 320 may extend from the first recess RS1 to the first upper surface 220a. The thickness of the third conductive pattern 320 may be thinner than the thickness of the second conductive pattern 310. Each of the second conductive pattern 310 and the third conductive pattern 320 may include a conductive material. For example, each of the second conductive pattern 310 and the third conductive pattern 320 may independently include copper (Cu), a copper alloy, and / or aluminum (Al). In some embodiments, the second conductive pattern 310 and the third conductive pattern 320 may include different conductive materials.

[0037] The second insulating layer 330 may be disposed on the first insulating layer 220. The second insulating layer 330 may cover the first insulating layer 220 and the first conductive pattern 210. In this case, the second insulating layer 330 may fill the first recess RS1 of the first insulating layer 220. That is, the second insulating layer 330 may contact the first upper surface 220a and the second upper surface 220b of the first insulating layer 220. The second insulating layer 330 may surround the second conductive pattern 310. The second insulating layer 330 may cover the third conductive pattern 320. The second insulating layer 330 may contact the side surface 310b of the second conductive pattern 310. The second insulating layer 330 may include an insulating material. It will be understood that "element A covers element B" (or similar language) means that element A extends over element B, but does not necessarily mean that element A completely covers element B. It should also be understood that as used herein, "element A fills element B" (or similar language) means that element A is within element B, but does not necessarily mean that element A completely fills element B.

[0038] For example, the second insulating layer 330 may include a dry film resist (DFR) and / or a photoimageable dielectric (PID). The second insulating layer 330 may include a third upper surface 330a surrounding the second conductive pattern 310, a fourth upper surface 330b disposed between the second conductive pattern 310 and the third upper surface 330a, and a second inclined surface 330c extending from the fourth upper surface 330b toward the side surface 310b of the second conductive pattern 310.

[0039] The third upper surface 330a may be substantially flat. The third upper surface 330a may be parallel to the upper surface of the lower protective layer 100. The third upper surface 330a may be positioned at the same level as the upper surface 310a of the second conductive pattern 310. In some embodiments, similar to the first upper surface 220a of the first insulating layer 220, the third upper surface 330a may be located at a level higher or lower than the upper surface 310a of the second conductive pattern 310.

[0040] The fourth upper surface 330b may be located at a level lower than the third upper surface 330a. For example, the second insulating layer 330 may include a second recess RS2 that is recessed from the third upper surface 330a toward the lower protective layer 100. The lowest point of the second recess RS2 may be lower than the third upper surface 330a. The second recess RS2 may be located between the second conductive pattern 310 and the third upper surface 330a of the second insulating layer 330.

[0041] The second inclined surface 330c may extend from one end of the fourth upper surface 330b to the side surface 310b of the second conductive pattern 310. The second inclined surface 330c may be inclined with respect to the fourth upper surface 330b. According to Figures 3A to 3C, the second inclined surface 330c may be the second side surface 330c of the second recess RS2, which extends from the bottom surface 330b of the second recess RS2 towards the side surface 310b of the second conductive pattern 310. The distance between the second side surface 330c and the lower protective layer 100 may increase from the fourth upper surface 330b to the second conductive pattern 310. In some embodiments, the distance between the second side surface 330c and the lower protective layer 100 may increase as the distance from the fourth upper surface 330b increases, as Figures 3A to 3C shown.

[0042] The second inclined surface 330c may be a surface extending in an obliquely upward direction from the bottom surface 330b of the second recess RS2. The highest point of the second side surface 330c of the second recess RS2 may contact the upper surface 310a of the second conductive pattern 310. In some embodiments, the highest point of the second side surface 330c of the second recess RS2 may be directly connected to the upper surface 310a of the second conductive pattern 310. In some embodiments, the highest point of the second side surface 330c of the second recess RS2 may be located at a level lower than the top surface 310a of the second conductive pattern 310.

[0043] The upper protective layer 400 may be disposed on the second wiring layer 300. The upper protective layer 400 may cover the second insulating layer 330 and the second conductive pattern 310. In this case, the upper protective layer 400 may fill the second recess RS2 of the second insulating layer 330. That is, the upper protective layer 400 may contact the third upper surface 330a and the fourth upper surface 330b of the second insulating layer 330. The upper surface of the upper protective layer 400 may be substantially flat. The upper protective layer 400 may protect the first wiring layer 200 and the second wiring layer 300 of the redistribution substrate 10. The upper protective layer 400 may include an insulating material. For example, the upper protective layer 400 may include, but is not limited to, inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and / or polyamide-based polymer materials.

[0044] The terminal pad 410 may be disposed on the upper protective layer 400. The terminal pad 410 may be connected to the second conductive pattern 310 and may extend through the upper protective layer 400. The terminal pad 410 may include a conductive material, such as a metal. The structure of the redistribution substrate 10 of the semiconductor package is as described above.

[0045] The connection terminal 420 may be disposed on the redistribution substrate 10. For example, the connection terminal 420 may be disposed on the terminal pad 410. The connection terminal 420 may be a chip terminal of a semiconductor chip mounted on the redistribution substrate 10 or an external terminal for mounting the redistribution substrate 10 on another substrate. The connection terminal 420 may include solder balls, solder bumps, etc.

[0046] The external terminals 120 may be disposed under the redistribution substrate 10. For example, the substrate pads 110 may be disposed on the bottom surface of the lower protective layer 100 of the redistribution substrate 10. The substrate pads 110 may be connected to the first conductive pattern 210 of the first wiring layer 200 and may extend through the lower protective layer 100. The external terminals 120 may be disposed on the substrate pads 110. The external terminals 120 may be electrically connected to the first wiring layer 200 and the second wiring layer 300 through the substrate pads 110.

[0047] The semiconductor chip 20 may be mounted on the redistribution substrate 10. The lower surface of the semiconductor chip 20 facing the redistribution substrate 10 may be an active surface. The semiconductor chip 20 may be mounted on the redistribution substrate 10 in a flip-chip manner. For example, the semiconductor chip 20 may be electrically connected to the redistribution substrate 10 through connection terminals 420 provided on the bottom surface of the semiconductor chip 20. The connection terminals 420 may be connected to the chip terminals (not shown) of the semiconductor chip 20 and the terminal pads 410 of the redistribution substrate 10. The connection terminals 420 may include solder balls or solder bumps. The semiconductor chip 20 may be electrically connected to the second conductive pattern 310 through the connection terminals 420 and the terminal pads 410. The redistribution substrate 10 may electrically connect the semiconductor chip 20 using the first wiring layer 200 and the second wiring layer 300. The semiconductor chip 20 may include silicon (Si).

[0048] The molding layer 30 may be provided on the redistribution substrate 10. The molding layer 30 may cover the semiconductor chip 20 on the upper surface of the redistribution substrate 10. For example, the molding layer 30 may cover the top surface and the side surfaces of the semiconductor chip 20. The molding layer 30 may fill the space between the semiconductor chip 20 and the redistribution substrate 10. The molding layer 30 may include, for example, an insulating material such as an epoxy polymer. In some embodiments, the space between the semiconductor chip 20 and the redistribution substrate 10 may be filled with a underfill member.

[0049] Figure 5A is a plan view of a redistribution substrate of a semiconductor package showing an example embodiment according to the inventive concept, schematically showing Figure 1 the redistribution substrate of the semiconductor package, and some components may not be shown for convenience of description. Figure 5B and Figure 5C shows a cross-sectional view of a redistribution substrate of a semiconductor package showing an example embodiment according to the inventive concept, and corresponds to a cross-section taken along Figure 5A line II-II' of. For convenience of description, in the following embodiments, the same reference numerals may be used to refer to Figure 2A and Figure 2Bthe components described in the embodiments, and for the convenience of description, the description thereof may be omitted or briefly described. That is, the following description will focus on the differences from the Figure 2A and Figure 2B redistribution substrate.

[0050] Referring to Figure 5A and Figure 5B , the first upper surface 220a and the second upper surface 220b of the first insulating layer 220 may be located at the same level. The first upper surface 220a and the second upper surface 220b may be coplanar and may be substantially flat. That is, the first upper surface 220a and the second upper surface 220b may form a single surface. Hereinafter, the entirety of the first upper surface 220a and the second upper surface 220b will be referred to as a single upper surface 220a / 220b. The single upper surface 220a / 220b may be located at a level lower than the top surface 210a of the first conductive pattern 210. The distance from the lower protective layer 100 to the single upper surface 220a / 220b may be, for example, 0.5 times to 1 times the distance from the lower protective layer 100 to the upper surface 210a of the first conductive pattern 210.

[0051] The first inclined surface 220c may extend from one end of the single upper surface 220a / 220b to the side surface 210b of the first conductive pattern 210. The first inclined surface 220c may be located between the first conductive pattern 210 and the single upper surface 220a / 220b. For example, as Figure 5A shown, the first inclined surface 220c may be formed in a plan view on a portion of the first insulating layer 220 adjacent to the first conductive pattern 210, and the first inclined surface 220c may surround the first conductive pattern 210. The first inclined surface 220c may be positioned inside the single upper surface 220a / 220b in a plan view and may surround the first conductive pattern 210. That is, the first inclined surface 220c may separate the first conductive pattern 210 from the single upper surface 220a / 220b of the first insulating layer 220.

[0052] The first inclined surface 220c may be inclined with respect to the single upper surface 220a / 220b. The distance between the first inclined surface 220c and the lower protective layer 100 may increase from the single upper surface 220a / 220b toward the first conductive pattern 210. In some embodiments, the distance between the first inclined surface 220c and the lower protective layer 100 may increase as the distance from the single upper surface 220a / 220b increases, as Figure 5BAs shown. The highest point TP of the first inclined surface 220c may be located at the same level as the upper surface 210a of the first conductive pattern 210 or at a level lower than the upper surface 210a. That is, the first inclined surface 220c may be a surface that extends obliquely upward from a single upper surface 220a / 220b.

[0053] According to some embodiments, as Figure 5C shown, the first upper surface 220a and the second upper surface 220b of the first insulating layer 220 may be located at the same level. The first upper surface 220a and the second upper surface 220b may be coplanar and may be substantially flat. The first upper surface 220a and the second upper surface 220b may be located at the same level as the upper surface 210a of the first conductive pattern 210. In some embodiments, the first upper surface 220a and the second upper surface 220b may be located at a level higher or lower than the upper surface 210a of the first conductive pattern 210.

[0054] The first inclined surface 220c of the first insulating layer 220 may be inclined with respect to the second upper surface 220b. The distance between the first inclined surface 220c and the lower protective layer 100 may decrease from the second upper surface 220b toward the first conductive pattern 210. In some embodiments, the distance between the first inclined surface 220c and the lower protective layer 100 may decrease as the distance from the second upper surface 220b increases, as Figure 5C shown. Specifically, the distance between the lowest point LP of the first inclined surface 220c and the lower protective layer 100 may be less than or equal to the distance between the upper surface 210a of the first conductive pattern 210 and the lower protective layer 100. That is, the first inclined surface 220c may be a surface that extends obliquely downward from the second upper surface 220b. The distance from the lower protective layer 100 to the lowest point LP of the first inclined surface 220c may be, for example, 0.5 times to 1 times the distance from the lower protective layer 100 to the upper surface 210a of the first conductive pattern 210. The redistribution substrate 10' of the semiconductor package may be constructed as described above with reference to Figures 5A to 5C the above.

[0055] The connection terminal 420 may be provided on the redistribution substrate 10'. External terminals (for example, Figure 1 the external terminal 120 in

[0056] Figures 6 to 11The cross-sectional view shows a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0057] Referring to Figure 6 , a lower protective layer 100 may be provided. The lower protective layer 100 may include a first region RG1, a second region RG2 surrounding the first region RG1, and a third region RG3 disposed between the first region RG1 and the second region RG2. The first region RG1 may be a region of a first conductive pattern 210 in which a first wiring layer 200 (e.g., the first wiring layer 200 in Figure 1 ) is formed, and each of the second region RG2 and the third region RG3 may be a region of a first insulating layer 220 in which the first wiring layer 200 (e.g., the first insulating layer 220 in Figure 1 ) is formed.

[0058] A first wiring layer 200 including the first insulating layer 220 and the first conductive pattern 210 may be formed on the lower protective layer 100. Hereinafter, the process of forming the first wiring layer will be described in detail with reference to Figure 6 and Figure 7 .

[0059] Referring to Figure 6 , the first conductive pattern 210 may be formed on the first region RG1 of the lower protective layer 100. For example, after a seed layer is formed on the lower protective layer 100, a mask may be formed on the seed layer to expose the first region RG1. Thereafter, the first conductive pattern 210 may be formed by filling a conductive material in the pattern of the mask through a plating process or the like. In some embodiments, after a conductive film is formed on the lower protective layer 100, the first conductive pattern 210 may be formed by patterning the conductive film.

[0060] A first insulating film 222 may be formed on the lower protective layer 100. For example, the first insulating film 222 may be formed by coating or depositing an insulating material on the lower protective layer 100. The coating process of the insulating material may include a spin coating process or a roll coating process. The insulating material may include a photosensitive insulating material. For example, the insulating material may include a dry film resist (DFR) and / or a photoimageable dielectric (PID).

[0061] The thickness of the first insulating film 222 may be the same as the thickness of the first insulating layer 220 (e.g., the first insulating layer 220 in Figure 7 ) to be formed later. The first insulating film 222 may cover the first conductive pattern 210. Due to the thickness of the first conductive pattern 210 located on the upper surface of the lower protective layer 100, the first insulating film 222 disposed on the lower protective layer 100 and the first conductive pattern 210 may be raised in the third region RG3 adjacent to the first conductive pattern 210.

[0062] The upper surface of the first insulating film 222 in the third region RG3 may gradually rise from the second region RG2 toward the first region RG1. The first insulating film 222 may protrude upward in the first region RG1 and the third region RG3 adjacent to the first region RG1. The height of the upper surface of the first insulating film 222 on the first region RG1 and the third region RG3 may be higher than the height of the upper surface of the first insulating film 222 on the second region RG2. The height of the upper surface of the first insulating film 222 on the second region RG2 may be the same as the height of the upper surface of the first conductive pattern 210. In some embodiments, the upper surface of the first insulating film 222 and the upper surface of the first conductive pattern 210 on the second region RG2 may be coplanar with each other, and the upper surface of the first insulating film 222 on the first region RG1 and the third region RG3 may be higher than the upper surface of the first insulating film 222 on the second region RG2, as Figure 6 shown.

[0063] Referring Figure 7 , a first photomask PM1 may be provided above the first insulating film 222. The first photomask PM1 may be spaced apart from the first insulating film 222. The pattern PM1a of the first photomask PM1 may expose the first region RG1 and the third region RG3 of the lower protective layer 100. That is, the region exposed by the first photomask PM1 may be a part of the first insulating film 222 and the region where the first conductive pattern 210 is located. The first photomask PM1 may include a phase shift mask (PSM). For example, in the first photomask PM1, a chromium (Cr) pattern may be formed on a quartz substrate, and a phase shifter may be provided between the quartz substrate and the chromium pattern. Therefore, the resolution of the first photomask PM1 can be improved.

[0064] A part of the first insulating film 222 may be removed to form the first insulating layer 220. Specifically, a part of the first insulating film 222 in the first region RG1 and the third region RG3 may be removed. For example, an exposure process may be performed on the first insulating film 222 using the first photomask PM1. A part 222a of the first insulating film 222 may be removed from the first region RG1 through the exposure process to expose the first conductive pattern 210. In addition, a part 222b of the first insulating film 222 may be removed from the third region RG3 through the exposure process to form a first recess RS1 on the first insulating film 222. The first recess RS1 may have a shape that recesses from the upper surface 220a of the first insulating film 222 on the second region RG2 toward the lower protective layer 100.

[0065] In this case, due to variations or errors in the exposure process, the depth of the first recess RS1 formed by removing the first insulating film 222 can be shallow in the region adjacent to the side surface 210b of the first conductive pattern 210. Specifically, the depth of the removed first insulating film 222 can be shallower toward the first conductive pattern 210. Accordingly, the first side surface 220c of the first recess RS1 can be formed to be inclined with respect to the bottom surface 220b of the first recess RS1 and the side surface 210b of the first conductive pattern 210. Additionally, due to process variations or errors in the exposure process, the thickness of the first insulating film 222 increases toward the outside of the pattern PM1a of the first photomask PM1 (i.e., closer to the second region RG2). The removed depth can be shallow. Accordingly, the first recess RS1 may not extend through the first insulating film 222. In some embodiments, the first recess RS1 may have Figure 7 the shape shown.

[0066] As described above, the first wiring layer 200 having the first insulating layer 220 and the first conductive pattern 210 can be formed on the lower protection layer 100.

[0067] In an exemplary embodiment, the exposure process can be performed on the entire surface of the first insulating film 222. That is, the exposure process can be performed on the first insulating film 222 in the first region RG1, the second region RG2, and the third region RG3. The first conductive pattern 210 can be exposed in the first region RG1 by the exposure process, and the upper surface of the first insulating film 222 formed in the second region RG2 and the third region RG3 can be lower than the upper surface 210a of the conductive pattern 210. In this case, a redistribution substrate according to Figures 5A to 5C the embodiment can be formed.

[0068] When only the first insulating film 222 is removed from the first region RG1, a protruding portion of the first insulating film 222 can be retained. As Figure 8 shown, a portion 222a' of the first insulating film 222' in the first region RG1 can be removed using the first photomask PM1' to expose the first conductive pattern 210. For example, an etching process can be performed in the first region RG1, and the etching process can not be performed in the second region RG2 and the third region RG3.

[0069] Therefore, the upwardly protruding portion 222b' of the first insulating film 222' on the third region RG3 can be retained. The portion 222b' of the protruding first insulating film 222' can have a top end at a level higher than the upper surface 210a of the first conductive pattern 210. Additionally, the portion 222b' of the first insulating film 222' can have a top end at a level higher than the upper surface of the first insulating film 222' on the second region RG2. Thus, the first insulating film 222' can have a large step with the first conductive pattern 210. Accordingly, a cavity such as an air gap can be formed during a subsequent deposition process, or impurities can be generated on the first insulating film 222' and the first conductive pattern 210, which may lead to defects at the redistribution substrate.

[0070] According to an exemplary embodiment of the inventive concept, the portion 222b' of the first insulating film 222' can be removed. During the patterning process of the first insulating film 222', the exposure process can be performed on both the first region RG1 and the third region RG3, and the height of the upper surface of the first insulating film 222' can be equal to or lower than that of the first conductive pattern 210. That is, the step between the first conductive pattern 210 and the first insulating layer 220 can be small, and the occurrence of defects can be reduced during a subsequent deposition process described later.

[0071] A second wiring layer 300 including a second conductive pattern 310 and a second insulating layer 330 can be formed on the first wiring layer 200. The process of forming the second wiring layer 300 can be the same as or similar to the process of forming the first wiring layer 200.

[0072] Referring to Figure 9 , the second conductive pattern 310 and the third conductive pattern 320 can be formed on the first wiring layer 200. For example, after forming a seed layer on the first wiring layer 200, a mask can be formed that exposes a part of the seed layer formed on the first conductive pattern 210 or the first insulating layer 220. Thereafter, the second conductive pattern 310 can be formed by filling a conductive material in the pattern of the mask using a plating process or the like. For example, after forming a conductive film on the first wiring layer 200, the third conductive pattern 320 can be formed by patterning the conductive film.

[0073] In this case, the conductive film may be formed to conformally cover the upper surface of the first insulating layer 220. Accordingly, the third conductive pattern 320 may be formed to extend from the first surface of the first conductive pattern 210 to the upper surface of the first insulating layer 220. Specifically, the third conductive pattern 320 may be formed on the third region RG3 along the bottom surface of the first recess RS1 of the first insulating layer 220. In this case, since the step difference between the first conductive pattern 210 and the first insulating layer 220 is small, when the conductive film is formed, for example, no air gap or impurity may be formed under the third conductive pattern 320 adjacent to the interface between the first conductive pattern 210 and the first insulating layer 220. The thickness of the third conductive pattern 320 may be less than the thickness of the second conductive pattern 310. In some embodiments, the third conductive pattern 320 may directly contact the surfaces of the first insulating layer 220 and the first recess RS1 and may have a uniform thickness along these surfaces of the first insulating layer 220 and the first recess RS1, as Figure 9 shown. As used herein, "step difference between element A and element B" (or similar language) may refer to the height difference between element A and element B.

[0074] The second insulating film 332 may be formed on the first wiring layer 200. For example, the second insulating film 332 may be formed by coating or depositing an insulating material on the first wiring layer 200. The coating process of the insulating material may include a spin coating process or a roll coating process. The insulating material may include a photosensitive insulating material. For example, the insulating material may include a dry film resist (DFR) and / or a photoimageable dielectric (PID). In this case, the insulating material may fill the first recess RS1 of the first insulating layer 220. That is, the second insulating film 332 may contact the top surface of the first insulating layer 220, the bottom surface, and the side surfaces of the first recess RS1.

[0075] At this time, since the step difference between the first conductive pattern 210 and the first insulating layer 220 is small, when the insulating material is coated, for example, no air gap or impurity may be formed under the second insulating film 332 adjacent to the interface between the first conductive pattern 210 and the first insulating layer 220. The second insulating film 332 may cover the second conductive pattern 310 and the third conductive pattern 320. Due to the thickness of the second conductive pattern 310 located on the upper surface of the first wiring layer 200, the second insulating film 332 coated on the first wiring layer 200 and the second conductive pattern 310 may be raised in the region adjacent to the second conductive pattern 310. The second insulating film 332 may protrude upward from the second conductive pattern 310.

[0076] Refer to Figure 10, a part of the second insulating film 332 may be removed to form the second insulating layer 330. The process of forming the second insulating layer 330 may be the same as or similar to the process of forming the first insulating layer 220. For example, a second photomask PM2 may be provided over the second insulating film 332. The pattern PM2a of the second photomask PM2 may expose the second conductive pattern 310 and a portion of the second insulating film 332 adjacent to the second conductive pattern 310.

[0077] An exposure process may be performed on the second insulating film 332 using the second photomask PM2. Specifically, a portion 332a of the second insulating film 332 protruding upward on the second conductive pattern 310 may be removed. A portion 332a of the second insulating film 332 may be removed by the exposure process to expose the second conductive pattern 310. In addition, a portion 332b of the second insulating film 332 adjacent to the second conductive pattern 310 may be removed by the exposure process to form a second recess RS2 in the second insulating film 332.

[0078] According to an exemplary embodiment of the inventive concept, a protruding portion of the second insulating film 332 may be removed. During the patterning process of the second insulating film 332, an exposure process may be performed on both the second conductive pattern 310 and a region adjacent to the second conductive pattern 310, and the height of the upper surface of the second insulating film 332 may be equal to or lower than the top surface of the second conductive pattern 310. That is, the step difference between the second conductive pattern 310 and the second insulating layer 330 may be small, and the occurrence of defects may be reduced in the deposition process described later. As described above, the second wiring layer 300 including the second insulating layer 330, the second conductive pattern 310, and the third conductive pattern 320 may be formed on the first wiring layer 200.

[0079] Referring to Figure 11 , an upper protective layer 400 may be formed on the second wiring layer 300. For example, the upper protective layer 400 may be formed by depositing or coating an insulating material on the second wiring layer 300. For example, the insulating material may include, but is not limited to, inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and / or polyamide-based polymer materials. In this case, the insulating material may fill the second recess RS2 of the second insulating layer 330. That is, the upper protective layer 400 may contact the upper surface of the second insulating layer 330, the bottom surface, and the side surfaces of the second recess RS2. In this case, since the step difference between the second conductive pattern 310 and the second insulating layer 330 is small, no air gap or impurities may be formed below the upper protective layer 400 adjacent to the interface between the second conductive pattern 310 and the second insulating layer 330 when the insulating material is coated.

[0080] Returning to the reference Figure 1 , Figure 2Aand Figure 2B The terminal pad 410 and the connection terminal 420 may be formed on the redistribution substrate 10. The terminal pad 410 may be formed on the upper protection layer 400. For example, a through hole may be formed by performing an etching process on the upper protection layer 400. The through hole may expose the top surface of the second conductive pattern 310. Thereafter, the terminal pad 410 may be formed by filling the through hole with a conductive material.

[0081] The connection terminal 420 may be provided on the terminal pad 410. The connection terminal 420 may include solder balls, solder bumps, etc.

[0082] The semiconductor chip 20 may be mounted on the redistribution substrate 10. The semiconductor chip 20 may be mounted, for example, in a flip-chip manner. For example, the semiconductor chip 20 may be mounted on the redistribution substrate 10 through the connection terminal 420.

[0083] The molding layer 30 may be formed on the redistribution substrate 10. For example, after the molding material is coated on the redistribution substrate 10 to cover the semiconductor chip 20, the molding material may be cured to form the molding layer 30.

[0084] In the method of manufacturing a semiconductor package according to an embodiment of the inventive concept, the step difference or height difference between the first conductive pattern and the first insulating layer may be small, and the occurrence of defects may be reduced during a subsequent deposition process. Accordingly, the method of manufacturing a semiconductor package may manufacture a more reliable semiconductor package including fewer defects.

[0085] Various advantageous advantages and effects of the inventive concept are not limited to the above description. Example embodiments have been disclosed herein, and although specific terms have been employed, they are used and interpreted in a general descriptive sense only and not for purposes of limitation. In some cases, at the time of filing of the present application, it will be apparent to those of ordinary skill in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, those skilled in the art will understand that various changes may be made in form and detail without departing from the scope of the inventive concept as set forth in the appended claims.

[0086] This application claims priority to Korean Patent Application No. 10-2019-0115311, filed with the Korean Patent Office on September 19, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor package, comprising: A redistribution substrate; And A semiconductor chip on the redistribution substrate, Wherein, the redistribution substrate includes: A lower protective layer; A first conductive pattern on the lower protective layer; A first insulating layer surrounding the first conductive pattern and on the lower protective layer, the first insulating layer includes a first upper surface, the first upper surface includes a first flat portion extending parallel to the upper surface of the lower protective layer, the first upper surface of the first insulating layer further includes a first recess directly connected to the first conductive pattern; and A second insulating layer on the first insulating layer, Wherein the upper surface of the lower protective layer directly contacts the lower surface of the first conductive pattern and the lower surface of the first insulating layer, Wherein the first recess is closer to the upper surface of the first conductive pattern than the first flat portion.

2. The semiconductor package according to claim 1, wherein, The first flat portion of the first upper surface of the first insulating layer is coplanar with the upper surface of the first conductive pattern.

3. The semiconductor package according to claim 1, wherein, The second insulating layer contacts the first upper surface of the first insulating layer, and a part of the second insulating layer is in the first recess of the first insulating layer.

4. The semiconductor package according to claim 1, wherein, The first recess includes a side surface directly connected to the first conductive pattern and inclined with respect to the upper surface of the lower protective layer; The distance between the first part of the side surface of the first recess and the side surface of the first conductive pattern is longer than the distance between the second part of the side surface of the first recess and the side surface of the first conductive pattern, and The distance from the upper surface of the lower protective layer to the first part of the side surface of the first recess is shorter than the distance from the upper surface of the lower protective layer to the second part of the side surface.

5. The semiconductor package according to claim 1, wherein, The first recess includes a side surface and a lower surface, and the side surface of the first recess is directly connected to the first conductive pattern and is located between the first conductive pattern and the lower surface of the first recess, and The distance from the upper surface of the lower protective layer to the lower surface of the first recess is 0.7 times to 0.9 times the distance from the upper surface of the lower protective layer to the first flat portion of the first upper surface of the first insulating layer.

6. The semiconductor package according to claim 1, wherein, The first flat portion of the first upper surface of the first insulating layer is flat.

7. The semiconductor package according to claim 1, further comprising a second conductive pattern on the first conductive pattern, Among them, The second insulating layer surrounds the second conductive pattern.

8. The semiconductor package according to claim 7, wherein, The second insulating layer includes a second upper surface, the second upper surface includes a second flat portion extending parallel to the upper surface of the lower protective layer; And The second upper surface of the second insulating layer further includes a second recess, the second recess is located between the second flat portion of the second upper surface of the second insulating layer and the second conductive pattern.

9. The semiconductor package according to claim 7, further comprising a terminal pad, the terminal pad is on the second insulating layer and electrically connects the second conductive pattern to the semiconductor chip.

10. The semiconductor package according to claim 1 further includes a third conductive pattern that extends from the first conductive pattern and extends between the second insulating layer and the first insulating layer.

11. The semiconductor package according to claim 1, wherein, The distance between the first flat portion of the first upper surface of the first insulating layer and the upper surface of the lower protective layer is longer than the distance between the upper surface of the first conductive pattern and the upper surface of the lower protective layer.

12. The semiconductor package according to claim 1 further includes an upper protective layer on the second insulating layer. Among them, The first insulating layer and the second insulating layer include photosensitive insulating materials, and the upper protective layer includes an oxide or a nitride.

13. A semiconductor package includes: a lower protective layer; a first conductive pattern on the lower protective layer; a first insulating layer on the lower protective layer and in contact with a side surface of the first conductive pattern; a second insulating layer on the first insulating layer and the first conductive pattern; and a semiconductor chip on the second insulating layer, wherein the first insulating layer includes a first upper surface and an inclined surface adjacent to the side surface of the first conductive pattern, the first upper surface of the first insulating layer extends parallel to the upper surface of the lower protective layer, and the distance from the upper surface of the lower protective layer to a first portion of the inclined surface of the first insulating layer is different from the distance from the upper surface of the lower protective layer to a second portion of the inclined surface of the first insulating layer, wherein the upper surface of the lower protective layer directly contacts the lower surface of the first conductive pattern and the lower surface of the first insulating layer, wherein the inclined surface is closer to the upper surface of the first conductive pattern than the first upper surface.

14. The semiconductor package according to claim 13, wherein, The distance from the upper surface of the lower protective layer to the first upper surface of the first insulating layer is equal to or longer than the distance from the upper surface of the lower protective layer to the upper surface of the first conductive pattern.

15. The semiconductor package according to claim 13, wherein, The distance between the first portion of the inclined surface and the side surface of the first conductive pattern is longer than the distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is shorter than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

16. The semiconductor package according to claim 13, wherein, The distance between the first portion of the inclined surface and the side surface of the first conductive pattern is longer than the distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and the distance from the upper surface of the lower protective layer to the first portion of the inclined surface is longer than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

17. The semiconductor package according to claim 13 further includes: a second conductive pattern that extends through the second insulating layer and contacts the first conductive pattern, wherein the second conductive pattern is electrically connected to the semiconductor chip; and An upper protective layer on the second insulating layer and the second conductive pattern.

18. The semiconductor package according to claim 17, wherein, The first insulating layer and the second insulating layer include photosensitive insulating materials, and The upper protective layer includes an oxide or a nitride.

19. A semiconductor package, comprising: A redistribution substrate; A semiconductor chip on the redistribution substrate; And A molding film on the redistribution substrate and on a side surface of the semiconductor chip, Wherein, the redistribution substrate includes: A lower protective layer; A first conductive pattern on the lower protective layer; A first insulating layer on the lower protective layer and surrounding the first conductive pattern; A second insulating layer on the first insulating layer and the first conductive pattern; and A terminal pad on the second insulating layer and electrically connected to the semiconductor chip, and Wherein, the first insulating layer includes an inclined surface, a first upper surface, and a second upper surface, The second upper surface is coplanar with an upper surface of the first conductive pattern, A distance from the upper surface of the lower protective layer to the first upper surface is shorter than a distance from the upper surface of the lower protective layer to the second upper surface, and A distance from the upper surface of the lower protective layer to a first portion of the inclined surface is different from a distance from the upper surface of the lower protective layer to a second portion of the inclined surface, Wherein the upper surface of the lower protective layer directly contacts a lower surface of the first conductive pattern and a lower surface of the first insulating layer, Wherein the inclined surface is closer to the upper surface of the first conductive pattern than the second upper surface.

20. The semiconductor package according to claim 19, wherein, A distance between the first portion of the inclined surface and a side surface of the first conductive pattern is longer than a distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and The distance from the upper surface of the lower protective layer to the first portion of the inclined surface is shorter than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

21. The semiconductor package according to claim 19, wherein, The highest end of the inclined surface is at the same level as the second upper surface of the first insulating layer and the upper surface of the first conductive pattern.

22. The semiconductor package according to claim 19, wherein, The distance between the first portion of the inclined surface and the side surface of the first conductive pattern is longer than the distance between the second portion of the inclined surface and the side surface of the first conductive pattern, and The distance from the upper surface of the lower protective layer to the first portion of the inclined surface is greater than the distance from the upper surface of the lower protective layer to the second portion of the inclined surface.

23. The semiconductor package according to claim 19, further comprising: A second conductive pattern extending from the upper surface of the first conductive pattern onto the first insulating layer and extending between the second insulating layer and the first insulating layer, and A third conductive pattern extending through the second insulating layer and electrically connected to the second conductive pattern.

24. The semiconductor package according to claim 19, further comprising an upper protective layer on the second insulating layer, Among them, The terminal pad extends through the upper protective layer and is electrically connected to the first conductive pattern.

25. The semiconductor package according to claim 19, wherein, The first insulating layer and the second insulating layer comprise a photosensitive insulating material.

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