Packaging structure and manufacturing method thereof

Abstract

The disclosed embodiments are related to a packaging structure and a manufacturing method thereof. A packaging structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipation element, and an insulating encapsulation body. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipation element is connected to the first semiconductor die, and the first semiconductor die is located between the circuit element and the heat dissipation element, wherein the sum of the first thickness of the first semiconductor die and the third thickness of the heat dissipation element is substantially equal to the second thickness of the second semiconductor die. The insulating encapsulation body encapsulates the first semiconductor die, the second semiconductor die, and the heat dissipation element, wherein the surface of the heat dissipation element is substantially flush with the insulating encapsulation body.

Description

Technical Field

[0001] The disclosed embodiments relate to a packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor devices and integrated circuits (ICs) are typically manufactured on a single semiconductor wafer. In wafer-level processes, the die of the wafer can be processed and packaged with other semiconductor devices or other dies, and various techniques for wafer-level packaging (e.g., forming a redistribution structure / layer) have been developed. In addition, such packaging can be further integrated / integrated into a semiconductor substrate or carrier after dicing. Summary of the invention

[0003] The disclosed embodiment provides a packaging structure, which includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipation element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipation element is connected to the first semiconductor die, and the first semiconductor die is located between the circuit element and the heat dissipation element, wherein the sum of the first thickness of the first semiconductor die and the third thickness of the heat dissipation element is substantially equal to the second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die, and the heat dissipation element, wherein the surface of the heat dissipation element is substantially flush with the surface of the insulating encapsulation.

[0004] The disclosed embodiment provides a method for manufacturing a packaging structure, comprising the following steps: providing a first semiconductor die connected to a heat dissipation element; providing a second semiconductor die; encapsulating the first semiconductor die, the second semiconductor die, and the heat dissipation element in an insulating encapsulation body; and flattening the insulating encapsulation body so that the insulating encapsulation body exposes the heat dissipation element, wherein the sum of the first thickness of the first semiconductor die and the third thickness of the heat dissipation element is substantially equal to the second thickness of the second semiconductor die.

[0005] The disclosed embodiment provides a method for manufacturing a packaging structure, comprising the following steps: providing at least one first semiconductor die and at least one second semiconductor die; setting a dummy element on the surface of the at least one first semiconductor die, wherein the at least one first semiconductor die is located above the dummy element; encapsulating the at least one first semiconductor die, the at least one second semiconductor die and the dummy element in an insulating encapsulation body; planarizing the insulating encapsulation body so that the dummy element is exposed on the surface of the insulating encapsulation body; removing the dummy element to form a groove in the insulating encapsulation body; and setting a heat dissipation element on the at least one first semiconductor die and in the groove, wherein the sum of the first thickness of the at least one first semiconductor die and the third thickness of the heat dissipation element is substantially equal to the second thickness of the at least one second semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 13 and Fig.14A are schematic cross-sectional views of various stages in a method for manufacturing a package structure according to some embodiments of the present disclosure.

[0008] Fig. 14B is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0009] Fig.15 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0010] Fig.16 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0011] Fig.17 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0012] Figure 18 to Figure 19 are schematic cross-sectional views of various stages in a method for manufacturing a package structure according to some embodiments of the present disclosure.

[0013] Fig. 20 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0014] Fig.21A and Fig.21B is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0015] Fig. 22 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0016] Fig.23 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0017] Figures 24 to 33A are schematic cross-sectional views of various stages in a method for manufacturing a package structure according to some embodiments of the present disclosure.

[0018] Fig.33B is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0019] Fig.34 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0020] Fig.35 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0021] Fig.36 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0022] Fig.37 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0023] Fig.38 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0024] Fig.39 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0025] Fig.40 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0026] Fig.41 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0027] Fig.42 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0028] Fig.43 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0029] Fig.44 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0030] Fig.45is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0031] Fig.46 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0032] Fig.47 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0033] Fig.48 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure.

[0034] Fig.49 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure.

[0035] [Explanation of Symbols]

[0036] 10a, 10b, 10c, 10d, 10e, 10f, 30: Semiconductor components

[0037] 20: Second semiconductor component / semiconductor component

[0038] 20b, 110b, 210b, 320b, S1: bottom surface

[0039] 22, 33, 140, CP1, CP2: vias

[0040] 31, 110: Semiconductor substrate

[0041] 31a: Active surface

[0042] 32, 120: Internal structure

[0043] 32a, 122: interlayer dielectric layer

[0044] 32b, 124: Patterned conductive layer

[0045] 41, 310, 500: substrate

[0046] 42, 340, 800: Re-routing line structure

[0047] 42a, 342: Dielectric structure

[0048] 42b, 344, 530, 804: Metallization layer

[0049] 43, 320: Perforation

[0050] 100: first semiconductor die / semiconductor die

[0051] 110a, 210a, 220a: top surface

[0052] 130: Passivation layer

[0053] 130a, 310a, 310b, 400a, 700a, 700b, 702a, S2, S3: Surface

[0054] 210: Basal layer

[0055] 220: Adhesive layer

[0056] 360, 380: Conductive connectors

[0057] 400, 400m, 700, 702: Insulation enclosure

[0058] 510, 520: Bonding pads

[0059] 540, 550: Surface devices

[0060] 560: Conductive element

[0061] 600: Heat sink cover

[0062] 610: Thermal interface material

[0063] 620: Joint element

[0064] 802, PM1: Dielectric layer

[0065] 900: Conductive terminal

[0066] BE: Bridge Element

[0067] C1: Carrier

[0068] D1, D2, D3: Offset

[0069] DE: Dummy Element

[0070] HD1, HD2: Retaining devices

[0071] HDE: Heat Dissipation Element

[0072] O1: Opening

[0073] P1A, P1B, P1C, P1D, P1E, P1F, P2A, P2C, P2E, P2F, P3A, P3C, P3E, P4A, P4B, P5A, P5B, P6A, P6B, P7A, P7B: Package structure

[0074] R: Groove

[0075] S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S30, S31, S32, S33, S34, S35, S36, S37, S38, S40, S41, S42, S43, S44, S45, S46, S50, S51, S52, S53, S 54, S55, S60, S61, S62, S63, S64, S65, S66, S70, S71, S72, S73, S74, S75, S76, S77, S78, S79, S80, S81, S82, S83, S84, S85, S86, S87, S88, S90, S91, S92, S93, S94, S95, S96, S97, S98, S99: Steps

[0076] T1, T1': total thickness

[0077] u1: Under ball metal (UBM) pattern

[0078] UF1, UF2: bottom filler

[0079] W1, W2: Chip

[0080] Z: Stacking direction DETAILED DESCRIPTION

[0081] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components, values, operations, materials, arrangements, etc. to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements, etc. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact with each other by forming a first feature on or on the second feature, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact with each other. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0082] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0083] In addition, for ease of description, terms such as "first", "second", "third", "fourth", "fifth", etc. may be used herein to describe similar elements or features or different elements or features shown in the figures, and may be used interchangeably depending on the order of presentation or the context of description.

[0084] The present disclosure may also include other features and processes. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate to enable testing of a 3D package or 3DIC, use of a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method including intermediate verification of a known good die to improve yield and reduce costs.

[0085] Figures 1 to 13 and Fig.14A are schematic cross-sectional views of various stages in a method for manufacturing a package structure according to some embodiments of the present disclosure. Fig. 14B is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.15 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.16 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.17 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Figures 1 to 14A , Fig. 14B , Fig.15 and Fig.17In the embodiment, one or more (semiconductor) chips or tube dies are shown to represent multiple (semiconductor) chips or tube dies of a wafer, and one (semiconductor) package structure is shown to represent multiple (semiconductor) package structures obtained after the (semiconductor) manufacturing method, but the present disclosure is not limited thereto. In other embodiments, one or more (semiconductor) chips or tube dies are shown to represent multiple (semiconductor) chips or tube dies of a wafer, and one or more (semiconductor) package structures are shown to represent multiple (semiconductor) package structures obtained after the (semiconductor) manufacturing method.

[0086] Reference Figure 1 In some embodiments, according to Fig.16 In step S10, a wafer W1 including a plurality of semiconductor dies 100 arranged in an array is provided. Before performing a wafer sawing or dicing process on the wafer W1, the semiconductor dies 100 of the wafer W1 are connected to each other, such as Figure 1 In some embodiments, the wafer W1 includes a semiconductor substrate 110, an interconnect structure 120 disposed on the semiconductor substrate 110, and a passivation layer 130 covering the interconnect structure 120. Figure 1 As shown in FIG. 1 , for example, the semiconductor substrate 110 has a top surface 110 a and a bottom surface 110 b opposite to the top surface 110 a , and the interconnect structure 120 is located on the top surface 110 a of the semiconductor substrate 110 and sandwiched between the semiconductor substrate 110 and the passivation layer 130 .

[0087] In some embodiments, the semiconductor substrate 110 may be a silicon substrate including active components (e.g., transistors and / or memories (e.g., N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices, etc.)) and / or passive components (e.g., resistors, capacitors, inductors, etc.) formed therein. In some embodiments, such active components and passive components may be formed in a front-end-of-line (FEOL) process. In alternative embodiments, the semiconductor substrate 110 may be a bulk silicon substrate, such as a bulk single crystal silicon substrate, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination thereof. The present disclosure is not limited thereto.

[0088] The semiconductor substrate 110 may include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multi-layered substrates or gradient substrates may also be used. The semiconductor substrate 110 has an active surface (e.g., top surface 110a) sometimes referred to as a front side and an inactive surface (e.g., bottom surface 110b) sometimes referred to as a back side.

[0089] In some embodiments, the interconnect structure 120 may include one or more interlayer dielectric layers 122 and one or more patterned conductive layers 124 stacked alternately. For example, the interlayer dielectric layer 122 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and the interlayer dielectric layer 122 may be formed by deposition, etc. For example, the patterned conductive layer 124 may be a patterned copper layer or other suitable patterned metal layer, and the patterned conductive layer 124 may be formed by electroplating or deposition. However, the present disclosure is not limited to this. In some embodiments, the patterned conductive layer 124 may be formed by a dual damascene method. The number of interlayer dielectric layers 122 and the number of patterned conductive layers 124 may be less than or greater than Figure 1 The number shown in the figure can be specified based on the needs and / or design layout; the present disclosure is not particularly limited thereto. Throughout the description, the term "copper" is intended to include substantially pure elemental copper, copper containing inevitable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0090] In certain embodiments, such as Figure 1 As shown in , the patterned conductive layer 124 is sandwiched between the interlayer dielectric layers 122, wherein the top surface of the topmost layer of the patterned conductive layer 124 is at least partially exposed by a plurality of openings O1 formed in the topmost layer of the interlayer dielectric layer 122 to be connected to components formed later for electrical connection, and the bottom surface of the lowest layer of the patterned conductive layer 124 is at least partially exposed by a plurality of openings (not labeled) formed in the lowest layer of the interlayer dielectric layer 122 and is electrically connected to active components and / or passive components included in the semiconductor substrate 110. The shapes and numbers of the openings O1 and the openings formed in the lowest layer of the interlayer dielectric layer 122 are not limited in the present disclosure and may be specified based on needs and / or design layout.

[0091] The present disclosure is not limited thereto. In an alternative embodiment (not shown), the patterned conductive layer 124 may be sandwiched between interlayer dielectric layers 122, wherein the top surface of the topmost layer of the patterned conductive layer 124 may be completely covered by the interlayer dielectric layer 122 to prevent damage caused by subsequent processes, and the bottom surface of the lowest layer of the patterned conductive layer 124 may be at least partially exposed by openings formed in the lowest layer of the interlayer dielectric layer 122 and electrically connected to underlying active components and / or passive components. For example, through a subsequent patterning process, the top surface of the topmost layer of the patterned conductive layer 124 covered by the topmost layer of the interlayer dielectric layer 122 may be exposed by multiple openings formed in the topmost layer of the interlayer dielectric layer 122 to be electrically connected to a component formed later on the top surface of the topmost layer of the patterned conductive layer 124.

[0092] In some embodiments, Figure 1 As shown in , the passivation layer 130 is formed on the interconnect structure 120, wherein the interconnect structure 120 is covered by the passivation layer 130 and is in contact with the passivation layer 130. Figure 1 As shown in , for example, the passivation layer 130 has a substantially flat surface 130a. In certain embodiments, the surface 130a of the passivation layer 130 may be flush and may have high flatness and high planarity, which is beneficial for the layers formed later. In some embodiments, the passivation layer 130 may be a polyimide (PI) layer, a polybenzoxazole (PBO) layer, a silicon dioxide-based (non-organic) layer, or other suitable polymer (or organic) layer, and may be formed by deposition, etc. The present disclosure is not limited to this. In some embodiments, the passivation layer 130 completely covers the topmost layer of the patterned conductive layer 124 and the topmost layer of the interlayer dielectric layer 122, wherein the interconnect structure 120 is well protected by the passivation layer 130 from damage caused by subsequent processes. As Figure 1 As shown in , for example, the interconnect structure 120 is located between the top surface 110a of the semiconductor substrate 110 and the passivation layer 130. The present disclosure does not particularly limit the thickness of the passivation layer 130, as long as the surface 130a of the passivation layer 130 can maintain its high flatness and high planarity. In the present disclosure, the surface 130a of the passivation layer can be referred to as the top surface of the semiconductor die 100.

[0093] continue Figure 1 In some embodiments, according to Fig.16 In step S11, a wafer W2 including a plurality of heat dissipation elements HDE arranged in an array is also provided. Before the wafer W2 is subjected to a wafer sawing or dicing process, the heat dissipation elements HDE of the wafer W2 are connected to each other, such as Figure 1As shown in . In the present disclosure, the heat dissipation element HDE is also referred to as a heat spreader element. In some embodiments, the wafer W2 includes a base layer 210 and an adhesive layer 220 coated on the base layer 210. Figure 1 As shown in FIG. 1 , for example, the base layer 210 has a top surface 210a and a bottom surface 210b opposite to the top surface 210a, and the adhesive layer 220 is formed on the top surface 210a of the base layer 210. In the present disclosure, the material of the base layer 210 is different from the material of the adhesive layer 220. In the embodiment where the wafer W2 includes the base layer 210 and the adhesive layer 220, the base layer 210 and the adhesive layer 220 included in the wafer W2 are collectively referred to as a heat dissipation element HDE in the present disclosure.

[0094] However, the present disclosure is not limited thereto; in alternative embodiments, the adhesive layer 220 may be omitted from the wafer W2. That is, in embodiments where the wafer W2 does not include the adhesive layer 220, the base layer 210 included in the wafer W2 is individually referred to as a heat dissipation element HDE in the present disclosure.

[0095] In some embodiments, a given base layer 210 has a thermal conductivity coefficient greater than that of an insulating encapsulation formed later, and the base layer 210 may include a silicon-based layer (e.g., a silicon substrate or a silicon oxide layer), a ceramic layer, a metal film (e.g., a copper (Cu) film, an aluminum (Al) film, an indium (In) film, or a silver (Ag) film), a layer formed by a metal paste (e.g., an Ag paste, a Cu paste, a nano-Ag paste, or a nano-Cu paste), a polymer layer, a compound layer, or a layer made of any other suitable material.

[0096] In some embodiments, given that the adhesive layer 220 has a greater thermal conductivity than the insulating encapsulation formed later and is capable of adhering the base layer 210 to any layer or any wafer (e.g., wafer W1) to be disposed above the base layer 210, the adhesive layer 220 may include a silicon-based layer (e.g., a silicon oxide layer, a silicon nitride layer), a layer formed of a metal paste, a polymer layer, or a layer made of any other suitable material. For example, the adhesive layer 220 may be a die attach film (DAF), a liquid DAF, a glue layer, or an adhesive tape. In some embodiments, the adhesive layer 220 may be formed on the base layer 210 by lamination, a spin coating method, a dip coating method, or a suitable coating method. For example, the adhesive layer 220 may be dispensed on the base layer 210 as a liquid (e.g., liquid DAF) and cured, or may be a laminated film (e.g., DAF) laminated to the base layer 210. The present disclosure is not limited thereto. The top surface 220 a of the adhesive layer 220 may be flush and may have a high coplanarity.

[0097] Refer to Figure 1 and Figure 2 In some embodiments, according to Fig.16 In step S11, the wafer W1 is picked up and placed on the wafer W2, and the wafer W1 is bonded to the wafer W2. For example, Figure 2 The total thickness T1 of the structure shown in FIG. 1 is in the range from 100 μm to 2000 μm. Figure 2 As shown in FIG. 1 , the semiconductor substrate 110 is located between the interconnect structure 120 and the base layer 210, the interconnect structure 120 is located between the passivation layer 130 and the semiconductor substrate 110, and the adhesive layer 220 is located between the semiconductor substrate 110 and the base layer 210. In the present disclosure, the base layer 210 and the adhesive layer 220 (if any) are independently thermally coupled to the semiconductor substrate 110 of the wafer W1. In other words, the heat dissipation element HDE included in the wafer W2 is thermally coupled to each of the semiconductor dies 100 included in the wafer W1.

[0098] In some embodiments, Figure 1 and Figure 2As shown in , the bottom surface 110b of the semiconductor substrate 110 of the wafer W1 faces the top surface 220a of the adhesive layer 220 of the wafer W2, wherein the wafer W1 is bonded to the wafer W2 by bonding the semiconductor substrate 110 to the base layer 210 (e.g., an indirect bonding method) with the aid of the adhesive layer 220. In one embodiment, when the semiconductor substrate 110 of the wafer W1 is bonded to the base layer 210 of the wafer W2 using the adhesive layer 220 made of a material having adhesive properties (e.g., a metal paste, a polymer, etc.), the wafer W1 is bonded to the wafer W2 by adhesion. In an alternative embodiment, when the semiconductor substrate 110 of the wafer W1 is bonded to the base layer 210 of the wafer W2 using the adhesive layer 220 made of a material (e.g., a silicon-based layer), the wafer W1 is bonded to the wafer W2 by fusion bonding. That is, through the adhesive layer 220, the semiconductor substrate 110 of the wafer W1 is indirectly bonded to the base layer 210 of the wafer W2 by adhesion or fusion bonding. It should be understood that in the embodiment of the present disclosure, due to the presence of the adhesive layer 220 , the material of the base layer 210 is different from the material of the adhesive layer 220 .

[0099] However, the present disclosure is not limited thereto; in an alternative embodiment in which the adhesive layer 220 is omitted, the wafer W1 may be directly bonded to the wafer W2 by adhesive bonding or fusion bonding. That is, the bottom surface 110b of the semiconductor substrate 110 of the wafer W1 faces the top surface 210a of the base layer 210 of the wafer W2, wherein the wafer W1 is bonded to the wafer W2 by physically bonding the bottom surface 110b of the semiconductor substrate 110 to the top surface 210a of the base layer 210 (e.g., a direct bonding method). In one embodiment, when the base layer 210 made of a material having adhesive properties (e.g., a metal paste, a polymer, etc.) is used to directly bond to the semiconductor substrate 110 of the wafer W1, the wafer W1 is bonded to the wafer W2 by adhesion. In an alternative embodiment, when the base layer 210 made of a material (e.g., a silicon-based layer) is used to directly bond to the semiconductor substrate 110 of the wafer W1, the wafer W1 is bonded to the wafer W2 by fusion bonding. That is, due to the base layer 210 , the semiconductor substrate 110 of the wafer W1 is directly bonded to the base layer 210 of the wafer W2 by adhesive or fusion bonding.

[0100] Reference Figure 3 In some embodiments, a planarization step is performed on the bottom surface 210b of the base layer 210. After planarization, the base layer 210 can be considered a planarized base layer or a thinned base layer. In some embodiments, Figure 3The total thickness T1' of the planarized structure shown in FIG. 1 may be in the range of 100 μm to 1200 μm. In some embodiments, the planarization step may include a grinding process or a chemical mechanical polishing (CMP) process. After the planarization step, a cleaning step may be performed as needed, such as cleaning and removing residues generated by the planarization step. However, the present disclosure is not limited thereto, and the planarization step may be performed by any other suitable method.

[0101] In certain embodiments, to facilitate the aforementioned Figure 3 The process shown in FIG. 1 can be achieved by contacting the passivation layer 130 with an adhesive film (not shown). Figure 2 The structure shown in the figure is temporarily bonded to a support member (not shown) or temporarily bonded to a temporary carrier (not shown, such as an adhesive tape, an adhesive carrier, a suction pad, etc.). However, the present disclosure is not limited thereto. In one embodiment, the thickness of the semiconductor substrate 110 is thick enough to perform the above-mentioned Figure 3 When the process illustrated in FIG. 1 is performed without causing damage (such as cracks or broken wafers), there is no need to temporarily bond the passivation layer 130 to the support.

[0102] Reference Figure 4 In some embodiments, a plurality of vias 140 are formed on the interconnect structure 120 and on the semiconductor substrate 110, and the sidewalls of the vias 140 are surrounded by the passivation layer 130. Figure 4 As shown in FIG. 1 , each of the vias 140 penetrates the passivation layer 130 and extends into the opening O1 formed in the topmost layer of the interlayer dielectric layer 122 to physically contact the top surface of the topmost layer of the patterned conductive layer 124 exposed by the opening O1. The vias 140 are electrically connected to active components and / or passive components included in the semiconductor substrate 110 through the interconnect structure 120.

[0103] It should be understood that each of the semiconductor dies 100 includes at least a semiconductor substrate 110, an interconnect structure 120, a passivation layer 130, and a via 140. In some embodiments, each of the semiconductor dies 100 described herein may be referred to as a semiconductor chip or an integrated circuit (IC). In some embodiments, each of the semiconductor dies 100 is a logic chip, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, etc. However, the present disclosure is not limited thereto; in alternative embodiments, the semiconductor die 100 may independently include one or more digital chips, analog chips, or mixed signal chips, such as an application-specific integrated circuit (ASIC) chip, a sensor chip, a wireless and radio frequency (RF) chip, a memory chip, or a voltage regulator chip. In some alternative embodiments, the semiconductor die 100 may be independently referred to as a combination type chip or IC, such as a WiFi chip that includes both an RF chip and a digital chip.

[0104] In some embodiments, Figure 4 As shown in FIG. 1 , for each semiconductor die 100 , the via 140 physically contacting the interconnect structure 120 extends away from the surface 130 a of the passivation layer 130 . Figure 4 In each semiconductor die 100, only two vias 140 are shown, however, it should be noted that more than two vias 140 may be formed; the present disclosure is not limited thereto. In some embodiments, in a vertical projection on the top surface 110a of the semiconductor substrate 110 along the stacking direction Z of the semiconductor substrate 110, the interconnect structure 120, and the passivation layer 130, the vias 140 may be independently circular, elliptical, triangular, rectangular, etc. The shape of the vias 140 is not limited in the present disclosure. The number and shape of the vias 140 may be specified and selected based on needs, and adjusted by changing the number and shape of the openings O1.

[0105] In some embodiments, the via 140 is formed by photolithography, plating, a photoresiststripping process, or any other suitable method. For example, the plating process may include electroplating, electroless plating, etc. In one embodiment, the via 140 may be formed by: forming a mask pattern (not shown) covering the passivation layer 130, the mask pattern having a plurality of openings (not shown), the openings corresponding to the top surface of the top layer of the patterned conductive layer 124 exposed by the opening O1; patterning the passivation layer 130 to form a plurality of contact openings (not shown) in the passivation layer 130, thereby exposing the top surface of the top layer of the patterned conductive layer 124 exposed by the opening O1; forming a metal material filling the openings formed in the mask pattern, the contact openings formed in the passivation layer 130, and the openings O1 by electroplating or deposition to form a plurality of vias 140; and then removing the mask pattern. In some embodiments, the passivation layer 130 may be patterned by an etching process (e.g., a dry etching process, a wet etching process, or a combination thereof). It should be noted that the contact opening formed in the passivation layer 130 and the corresponding one of the openings O1 located below the passivation layer 130 are spatially connected to each other to form the via hole 140. In one embodiment, the mask pattern can be removed by an acceptable ashing process and / or a photoresist stripping process (e.g., using oxygen plasma, etc.). In one embodiment, the material of the via hole 140 may include a metal material, such as copper or a copper alloy, etc.

[0106] In some alternative embodiments, the via 140 may be formed by: forming a first mask pattern (not shown) covering the passivation layer 130, the first mask pattern having a plurality of openings (not shown), the openings corresponding to the top surface of the top layer of the patterned conductive layer 124 exposed by the openings O1; patterning the passivation layer 130 to form a plurality of contact openings (not shown) in the passivation layer 130, thereby exposing the top surface of the top layer of the patterned conductive layer 124 exposed by the openings O1; removing the first mask pattern; 30; forming a metal seed layer conformally on the passivation layer 130; forming a second mask pattern (not shown) covering the passivation layer 130 and the metal seed layer, the second mask pattern having a plurality of openings (not shown) exposing the contact openings and the openings O1 formed in the passivation layer 130; forming a metal material filling the openings formed in the second mask pattern, the contact openings formed in the passivation layer 130, and the openings O1 by electroplating or deposition; removing the second mask pattern; and then removing the metal seed layer not covered by the metal material to form a plurality of vias 140. In some embodiments, the metal seed layer is referred to as a metal layer, which may be a single layer or a combined layer including a plurality of sub-layers formed of different materials. In some embodiments, the metal seed layer includes titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, and the like. For example, the metal seed layer may include a titanium layer and a copper layer located on the titanium layer. The metal seed layer may be formed using, for example, sputtering, physical vapor deposition (PVD), and the like.

[0107] Reference Figure 5 In some embodiments, according to Fig.16 Step S12, Figure 4 The structure shown in FIG. 1 is subjected to a dicing (single-formation) process so that Figure 4 The structure shown in FIG. 1 is cut into individual and separate semiconductor components 10 a. In some embodiments, Figure 5 As shown in the figure, the holding device HD1 is used to fix Figure 4The structure shown in the figure prevents any damage to the semiconductor component 10a during the dicing (singulation) process. In one embodiment, the holding device HD1 is not cut during the dicing (singulation) process, but the present disclosure is not limited to this. In an alternative embodiment (not shown), the holding device HD1 may be partially cut during the dicing (singulation) process. For example, the holding device HD1 may be an adhesive tape, an adhesive carrier, or a suction pad, but the present disclosure is not limited to this. In one embodiment, the dicing (singulation) process is a wafer dicing process or a wafer singulation process, and the wafer dicing process or the wafer singulation process may include mechanical sawing or laser cutting. The present disclosure is not limited to this. At this point, the semiconductor component 10a is manufactured, wherein each of the semiconductor components 10a includes a semiconductor die 100 connected to a heat dissipation element HDE. In the present disclosure, in each of the semiconductor components 10a, the heat dissipation element HDE is thermally coupled to the semiconductor die 100. As Figure 5 As shown in , the sidewalls of the heat dissipation element HDE are aligned with the sidewalls of the semiconductor die 100 .

[0108] Reference Figure 6 In some embodiments, according to Fig.16 In step S13, a substrate 310 is provided, wherein the semiconductor component 10a ( Figure 5 The semiconductor component 10a) and at least one semiconductor component 20 shown in the figure are picked up and placed on the substrate 310, and are bonded to the substrate 310 by flip chip bonding. In some embodiments, the substrate 310 may be a wafer, such as a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, etc. In some embodiments, the semiconductor material of the substrate 310 may be: silicon, germanium; compound semiconductors including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In alternative embodiments, other substrates, such as multilayer substrates or gradient substrates, may also be used. The substrate 310 may, for example, be doped or undoped and may also include active devices and / or passive devices, such as transistors, capacitors, resistors, diodes, etc. formed in the substrate 310 and / or on the surface 310a of the substrate 310. In some embodiments, the surface 310a may be referred to as an active surface (or front side) of the substrate 310. In certain embodiments, the substrate 310 may contain substantially no active devices and / or passive devices, although the present disclosure is not limited thereto.

[0109] In some embodiments, a plurality of through-holes 320 extending from a surface 310a of the substrate 310 are formed in the substrate 310. For example, since the substrate 310 is a silicon substrate, the through-holes 320 are sometimes referred to as through-substrate-vias or through-silicon-vias. The through-holes 320 may be formed by forming grooves in the substrate 310, for example, by etching, milling, laser technology, combinations thereof, and / or the like. A thin dielectric material may be formed in the grooves, for example, by using an oxidation technique. A thin barrier layer may be conformally deposited over the surface 310a of the substrate 310 and in the openings, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), PVD, thermal oxidation, combinations thereof, and / or the like. The barrier layer may include a nitride or an oxynitride, for example, titanium nitride, titanium oxynitride, tantalum nitride, tungsten nitride, combinations thereof, and / or the like. Conductive material may be deposited over the thin barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and / or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and / or the like. Excess conductive material and the barrier layer are removed from the surface 310a of the substrate 310 by, for example, CMP. Thus, the through-hole 320 may include a conductive material and a thin barrier layer between the conductive material and the substrate 310.

[0110] In some embodiments, a redistribution wiring structure 340 is formed on the surface 310a of the substrate 310, and the redistribution wiring structure 340 is electrically connected to the substrate 310. In some embodiments, the redistribution wiring structure 340 is used to provide a wiring function and includes a dielectric structure 342 and one or more metallization layers 344 arranged in the dielectric structure 342. In some embodiments, the dielectric structure 342 includes one or more dielectric layers, so that the dielectric layer and the metallization layer 344 are formed in sequence, and one metallization layer 344 is sandwiched between two dielectric layers. Figure 6As shown in , portions of the top surface of the topmost layer of the metallization layer 344 are respectively exposed by a plurality of openings formed in the topmost dielectric layer of the dielectric structure 342, and portions of the bottom surface of the bottommost layer of the metallization layer 344 are respectively exposed by a plurality of openings formed in the bottommost dielectric layer of the dielectric structure 342. However, the present disclosure is not limited thereto. The number of metallization layers and the number of dielectric layers included in the redistribution wiring structure 340 are not limited thereto, and may be specified and selected based on needs. The material and formation of the dielectric structure 342 may be the same or similar to the material and formation of the interlayer dielectric layer 122, and the material and formation of the metallization layer 344 may be the same or similar to the material and formation of the patterned conductive layer 124, and therefore will not be repeated herein. As Figure 6 As shown in , the through-hole 320 is connected to the portion of the bottom surface of the bottom layer of the metallization layer 344 that is exposed by the opening formed in the bottommost dielectric layer of the dielectric structure 342, respectively. In other words, the redistribution wiring structure 340 is electrically connected to the through-hole 320. In alternative embodiments, the redistribution wiring structure 340 may also be electrically connected to active devices and / or passive devices embedded in the substrate 310 or formed on the surface 310a of the substrate 310.

[0111] In some embodiments, a plurality of conductive connectors 360 are formed on the redistribution wiring structure 340. Figure 6 As shown in , for example, conductive connectors 360 are formed on and connected to portions of the top surface of the top layer of metallization layer 344 that are exposed by openings formed in the top dielectric layer of dielectric structure 342, respectively. In other words, conductive connectors 360 are electrically connected to redistribution structure 340. In alternative embodiments, some of conductive connectors 360 may also be electrically connected to substrate 310 (e.g., active devices and / or passive devices embedded in substrate 310 or formed on surface 310a) and through-vias 320 through redistribution structure 340.

[0112] In some embodiments, the conductive connector 360 may include a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, etc. The material of the conductive connector 360 may include, for example, a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In one embodiment, the material of the conductive connector 360 may be, for example, solder-free. The cross-sectional view of the conductive connector 360 is not limited to the embodiments described, and may have any suitable shape based on needs.

[0113] continue Figure 6 In some embodiments, each of the semiconductor components 20 described herein may be referred to as a semiconductor chip or integrated circuit (IC) having a plurality of vias 22, wherein the vias 22 are used as conductive terminals of the semiconductor components 20 to electrically connect to external components. In some embodiments, the semiconductor components 20 are each a memory chip or device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. However, the present disclosure is not limited thereto; in alternative embodiments, the semiconductor components 20 may independently include one or more digital chips, analog chips, or mixed signal chips, such as an application-specific integrated circuit ("ASIC") chip, a sensor chip, a wireless and radio frequency (RF) chip, a logic chip, or a voltage regulator chip. In some alternative embodiments, the semiconductor components 20 may independently be referred to as a combination type chip or IC, such as a WiFi chip that includes both an RF chip and a digital chip.

[0114] In one embodiment, the semiconductor die 100 of the semiconductor component 10a and the semiconductor component 20 may be the same type of die or different types of die. In one embodiment, the semiconductor die 100 of the semiconductor component 10a and the semiconductor component 20 may be formed in a process of the same technology node, or may be formed in processes of different technology nodes. For example, the semiconductor die 100 of the semiconductor component 10a may have an advanced process node than the semiconductor component 20; or vice versa.

[0115] In some embodiments, the semiconductor die 100 of the semiconductor component 10a and the semiconductor component 20 have different sizes (eg, different heights and / or different surface areas measured along the stacking direction Z). Figure 6 As shown in FIG. 1 , the height of the semiconductor die 100 of the semiconductor component 10a is less than the height of the semiconductor component 20, and the height of the semiconductor component 10a is greater than the height of the semiconductor component 20. However, the present disclosure is not limited thereto; for another example, the height of the semiconductor die 100 of the semiconductor component 10a is less than the height of the semiconductor component 20, and the height of the semiconductor component 10a is substantially equal to the height of the semiconductor component 20.

[0116] In some embodiments, Figure 6 As shown in FIG. 1 , semiconductor device 10a is electrically connected to substrate 310 through via 140 and conductive connector 360, and semiconductor device 20 is electrically connected to substrate 310 through via 22 and conductive connector 360. In some embodiments, semiconductor device 10a and semiconductor device 20 are electrically communicated with each other through redistribution structure 340 and conductive connector 360.

[0117] In some embodiments, the bottom filler UF1 at least fills the gap between the semiconductor component 10a and the redistribution wiring structure 340 and the gap between the semiconductor component 20 and the redistribution wiring structure 340, and surrounds the sidewalls of the via 140, the sidewalls of the via 22, and the sidewalls of the conductive connector 360. In one embodiment, the bottom filler UF1 filled in the gap between the semiconductor components 10a, 20 and the redistribution wiring structure 340 is not connected to each other. In another embodiment, the bottom filler UF1 filled in the gap between the semiconductor components 10a, 20 and the redistribution wiring structure 340 is connected to each other, and the present disclosure is not limited to this. In some alternative embodiments, the sidewalls of the semiconductor component 10a and the sidewalls of the semiconductor component 20 may be covered by the bottom filler UF1. For example, the bottom filler UF1 may be any acceptable material, such as a polymer, epoxy resin, molded bottom filler, etc. In one embodiment, the bottom filler UF1 may be formed by underfill dispensing, capillary flow process, or any other suitable method.

[0118] Reference Figure 7 In some embodiments, according to Fig.16 In step S14, an insulating encapsulation body 400m is formed on the substrate 310. For example, Figure 7As shown in FIG. 4 , the semiconductor components 10a and 20 are encapsulated in an insulating encapsulation body 400m, and the redistribution wiring structure 340 exposed by the bottom filling glue UF1 is covered by the insulating encapsulation body 400m. For example, the insulating encapsulation body 400m at least fills the gap between the semiconductor components 10a and 20 and the gap between the bottom filling glue UF1 respectively located under the semiconductor components 10a and 20. Figure 7 As shown in FIG. 4 , for example, the semiconductor components 10a, 20 and the bottom filler UF1 are surrounded and covered by the insulating encapsulation 400m. That is, the semiconductor components 10a, 20 and the bottom filler UF1 are embedded in the insulating encapsulation 400m. In other words, the semiconductor components 10a, 20 are not exposed by the insulating encapsulation 400m in a touchable manner and are embedded in the insulating encapsulation 400m.

[0119] In some embodiments, the insulating enclosure 400m is a molding compound formed by a molding process. In some embodiments, the insulating enclosure 400m may, for example, include a polymer (e.g., epoxy resin, phenolic resin, silicone-containing resin or other suitable resin), a dielectric material or other suitable material. In alternative embodiments, the insulating enclosure 400m may include an acceptable insulating enclosure material. In some embodiments, the insulating enclosure 400m may also include an inorganic filler or inorganic compound (e.g., silica, clay, etc.) that can be added to the insulating enclosure 400m to optimize the coefficient of thermal expansion (CTE) of the insulating enclosure 400m. The present disclosure is not limited thereto.

[0120] Refer to Figure 7 and Figure 8 In some embodiments, according to Fig.16 In step S15, the insulating encapsulant 400m is planarized until the bottom surface of the semiconductor component 10a (e.g., the bottom surface 210b of the base layer 210) and the bottom surface 20b of the semiconductor component 20 are exposed. After the insulating encapsulant 400m is planarized, the (planarized) insulating encapsulant 400 is formed, and the bottom surface of the semiconductor component 10a (e.g., the bottom surface 210b of the base layer 210) and the bottom surface 20b of the semiconductor component 20 are exposed by the surface 400a of the insulating encapsulant 400.

[0121] During the planarization process of the insulating package 400m, the semiconductor components 10a and 20 may also be planarized independently. For example, the insulating package 400 may be formed by mechanical grinding or CMP. After the planarization process, a cleaning step may be performed as needed, such as cleaning and removing residues generated by the planarization step. However, the present disclosure is not limited thereto, and the planarization step may be performed by any other suitable method. Figure 8 As shown in FIG. 4 , the bottom surface of the semiconductor component 10a (e.g., the bottom surface 210b of the base layer 210) and the bottom surface 20b of the semiconductor component 20 are substantially flush with the surface 400a of the insulating encapsulation 400. In other words, the bottom surface of the semiconductor component 10a (e.g., the bottom surface 210b of the base layer 210), the bottom surface 20b of the semiconductor component 20, and the surface 400a of the insulating encapsulation 400 are substantially coplanar with each other. In other words, the semiconductor components 10a and 20 are exposed by the insulating encapsulation 400 in a touchable manner.

[0122] Reference Fig. 9 In some embodiments, after forming the insulating encapsulation body 400, Figure 8 The structure shown in is flipped (inverted along the stacking direction Z), and the insulating encapsulation 400 is placed on the carrier C1. In some alternative embodiments, the carrier C1 may also be coated with a peeling layer (not shown). For example, the peeling layer is disposed on the carrier C1, and the material of the peeling layer may be any material suitable for bonding and peeling the carrier C1 from an upper layer (e.g., the insulating encapsulation 400) or any wafer disposed on the carrier C1. In some embodiments, the peeling layer may include a release layer (e.g., a light-to-heat conversion (“LTHC”) layer) or an adhesive layer (e.g., an ultra-violet curable adhesive layer or a heat curable adhesive layer).

[0123] Reference Fig.10 In some embodiments, according to Fig.16 In step S16, the substrate 310 is then planarized until the bottom surface 320b of the through-hole 320 embedded in the substrate 310 is exposed. After the substrate 310 is planarized, the bottom surface 320b of the through-hole 320 is exposed by the surface 310b of the substrate 310. During the planarization process of the substrate 310, the through-hole 320 may also be planarized. For example, the substrate 310 may be planarized by mechanical grinding or CMP. After the planarization process, a cleaning step may be performed as needed, such as cleaning and removing residues generated by the planarization step. However, the present disclosure is not limited thereto, and the planarization step may be performed by any other suitable method. Fig.10 As shown in FIG. 3 , the bottom surface 320 b of the through-hole 320 is substantially flush and coplanar with the surface 310 b of the substrate 310. That is, the bottom surface 320 b of the through-hole 320 is exposed by the substrate 310 in an accessible manner.

[0124] Reference Fig.11 In some embodiments, according to Fig.16 In step S17, a plurality of conductive connecting members 380 are formed on the substrate 310, wherein the conductive connecting members 380 are connected to the through-holes 320. Fig.11 As shown in , for example, the conductive connector 380 is formed on the substrate 310 corresponding to the positioning position of the through-hole 320, and thus the conductive connector 380 is physically in contact with the bottom surface 320b of the through-hole 320, respectively. In some embodiments, some of the conductive connectors 380 are electrically connected to the semiconductor component 10a through the through-hole 320, the redistribution wiring structure 340, and the conductive connector 360. In some embodiments, some of the conductive connectors 380 are electrically connected to the semiconductor component 20 through the through-hole 320, the redistribution wiring structure 340, and the conductive connector 360. In alternative embodiments, some of the conductive connectors 380 may also be electrically connected to active devices and passive devices embedded in the substrate 310 or formed on the surface 310a of the substrate 310. The material and formation of the conductive connector 380 are the same or similar to the material and formation of the conductive connector 360, and therefore may not be repeated herein. In one embodiment, the conductive connector 380 can be the same as the conductive connector 360. In an alternative embodiment, the conductive connector 380 can be different from the conductive connector 360.

[0125] Reference Fig.12 In some embodiments, Fig.11 The entire structure shown in FIG. 4 is flipped (inverted) together with the carrier C1 and then the carrier C1 is peeled off from the insulating package 400 and the semiconductor components 10a, 20. In some embodiments, the carrier C1 is separated (detached) from the insulating package 400 and the semiconductor components 10a, 20 by a peeling process, wherein the carrier C1 is removed and the insulating package 400 and the semiconductor components 10a, 20 are exposed. Fig.12 As shown in FIG. 4 , a surface 400 a of the insulating encapsulation body 400 , a bottom surface (eg, bottom surface 210 b ) of the semiconductor device 10 a , and a bottom surface 20 b of the semiconductor device 20 are exposed.

[0126] In one embodiment, the lift-off process is a laser lift-off process. During the lift-off step, before the carrier C1 is lifted off, a holding device HD2 is used to fix the carrier C1. Fig.11 The entire structure shown in FIG. 1 , wherein the conductive connecting member 380 is held by the holding device HD2. Fig.12 As shown in , for example, the holding device HD2 can be an adhesive strip, a carrier film or a suction pad.

[0127] Reference Fig.13 In some embodiments, according to Fig.16 Step S18, sequentially performing a slicing (or singulation) process to Fig.12The entire structure shown in the figure is cut into a plurality of separate and separate package structures P1A. In one embodiment, the dicing process is a wafer dicing process, and the wafer dicing process includes mechanical blade sawing or laser cutting. The present disclosure is not limited to this. At this point, the package structure P1A is manufactured. In addition, the substrate 310 and the through-hole 320 are considered as an interposer.

[0128] Reference Fig.13 and Fig.14A In some embodiments, one semiconductor component 10a and two semiconductor components 20 are shown in the package structure P1A for illustrative purposes, but the present disclosure is not limited thereto. Based on needs and design layout, the number of semiconductor components 10a and the number of semiconductor components 20 can be independently one or more than one. Fig.13 and Fig.14A As shown in , in each semiconductor component 10a encapsulated in the insulating package 400, the heat generated from the semiconductor die 100 can be easily dissipated to the external environment through the heat dissipation element HDE thermally coupled to the semiconductor die 100, thereby helping to maintain a lower temperature in the package structure P1A. That is, based on the heat dissipation element HDE of each semiconductor component 10a included in the package structure P1A, the heat dissipation efficiency of the semiconductor component 10a can be controlled by adjusting the material of the heat dissipation element HDE, thereby ensuring the reliability of the package structure P1A. In other words, due to the presence of the heat dissipation element HDE, the overall thermal characteristics (such as heat dissipation, heat resistance) of the package structure P1A can be ensured.

[0129] In addition, for Fig.14A The package structure P1A shown in Fig.16 In the manufacturing method, the sidewalls of the heat dissipation element HDE (for example, the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220) are aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE. Fig.14A In the semiconductor device 10 a shown in FIG. 1 , the sidewalls of the heat dissipation element HDE and the sidewalls of the semiconductor die 100 are substantially coplanar with each other.

[0130] On the other hand, in alternative embodiments, the adhesive layer 220 may be omitted from the heat dissipation element HDE, see Fig. 14B The package structure P1B shown in FIG. Fig. 14B The package structure P1B shown in FIG. Fig.14A The package structure P1A shown in FIG. 1 is similar to the package structure P1B, except that the package structure P1B includes a semiconductor component 10b instead of the semiconductor component 10a, wherein the semiconductor component 10b includes a heat dissipation element having only a base layer 210. That is, in Fig. 14BIn the semiconductor device 10 b shown in FIG. 1 , the sidewalls of the heat dissipation element HDE (eg, the sidewalls of the base layer 210 ) are aligned with and substantially coplanar with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE.

[0131] Reference Fig.15 In some embodiments, according to Fig.16 In step S19, the package structure P1A is bonded to the substrate 500 through the conductive connector 380 to form a (stacked) package structure P2A. The substrate 500 may be made of semiconductor materials such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these materials, etc. may also be used. In some embodiments, the substrate 500 may be an SOI substrate, wherein the SOI substrate may include a semiconductor material (e.g., epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI) or a combination thereof) layer. In an alternative embodiment, the substrate 500 may be based on an insulating core, such as a fiberglass reinforced resin core. An exemplary core material is a fiberglass resin, such as flame retardant class 4 (FR4). Alternatives to the core material include bismaleimidetriazine (BT) resins, or alternatively, other printed circuit board (PCB) materials or films. In yet another alternative embodiment, the substrate 500 may be a build-up film, such as Ajinomoto build-up film (ABF) or other suitable laminates.

[0132] In one embodiment, substrate 500 may include active devices and / or passive devices (not shown) that may be used to produce the structural and functional requirements for the semiconductor package design, such as transistors, capacitors, resistors, combinations thereof, etc. The active devices and / or passive devices may be formed using any suitable method. However, the present disclosure is not limited thereto; in alternative embodiments, substrate 500 may substantially not include active devices and / or passive devices.

[0133] In some embodiments, the substrate 500 includes a plurality of metallization layers 530 and a plurality of through-holes (not shown) interconnected with each other, and a plurality of bonding pads 510, 520 connected to the metallization layers 530 and the through-holes. The metallization layers 530 and the through-holes together form a functional circuit system that provides wiring for the substrate 500. The metallization layers 530 and the through-holes embedded in the substrate 500 may be formed by alternating dielectric (e.g., low-k dielectric material) layers and conductive material (e.g., copper) layers and through-holes interconnecting the conductive material layers and may be formed by any suitable process (e.g., deposition, inlay, dual inlay, etc.). The bonding pads 510, 520 are used to provide the substrate 500 with electrical connections to external components. In some embodiments, the bonding pads 510, 520 are electrically connected to each other through the metallization layers 530 and the through-holes. Fig.15 As shown in FIG. 5 , for example, the conductive connectors 380 of the package structure P1A are respectively connected to the bonding pads 510 of the substrate 500. Fig.15 As shown in , in some embodiments, the package structure P1A is electrically connected to the substrate 500 through the bonding pads 510 and the conductive connectors 380 .

[0134] In some embodiments, a plurality of conductive elements 560 may be disposed on the bottom surface of the substrate 500 as desired, such as Fig.15 In some embodiments, the conductive element 560 can be used to physically connect and electrically connect the substrate 500 to other devices, packages, connection components, etc. In the present disclosure, the conductive element 560 is referred to as a conductive terminal of the substrate 500 to provide a physical connection and / or an electrical connection with an external component. Fig.15 As shown in , the conductive elements 560 and the package structure P1A are respectively located on two opposite sides of the substrate 500 , wherein some of the conductive elements 560 are electrically connected to the package structure P1A through the bonding pads 510 , 520 and the conductive connector 380 .

[0135] In some embodiments, one or more surface devices 540, 550 may be connected to the substrate 500 as needed. The surface devices 540, 550 may be used, for example, to provide additional functions or programming to the package structure P2A. In an embodiment, the surface devices 540, 550 may include surface mount devices (surfacemount devices, SMDs) or integrated passive devices (integrated passive devices, IPDs) that are expected to be connected to the package structure P2A and are used in conjunction with the package structure P2A, and the integrated passive devices include passive devices such as resistors, inductors, capacitors, jumpers, combinations of these devices, etc.

[0136] For example, if Fig.15As shown in , the surface device 540 is placed on the surface of the substrate 500 in which the package structure P1A is disposed, and the surface device 550 is placed on the surface of the substrate 500 in which the conductive element 560 is disposed. The number of surface devices 540 and the number of surface devices 550 are not limited to the described embodiment and can be selected based on needs and design layout. The present disclosure is not limited to this. In one embodiment, only the surface device 540 is formed on the substrate 500, wherein the number of surface devices 540 can be one or more than one. In an alternative embodiment, only the surface device 550 is formed on the substrate 500, wherein the number of surface devices 550 can be one or more than one. As Fig.15 As shown in FIG. , surface devices 540 , 550 are electrically connected to package structure P1A through, for example, bonding pads 510 , 520 , metallization layer 530 and vias, and conductive connectors 380 .

[0137] In some embodiments, a bottom filler UF2 is formed on the substrate 500. Fig.15 As shown in FIG. 5 , for example, the bottom filler UF2 fills the gap between the package structure P1A and the substrate 500 and surrounds the sidewalls of the conductive connector 380 . The material and formation of the bottom filler UF2 can be different from Figure 6 The materials and formation of the underfill UF1 described in are the same or similar, and therefore are not repeated herein for the sake of brevity.

[0138] At this point, the package structure P2A is manufactured. In addition, the substrate 500 is considered to be a circuit structure (eg, an organic substrate with a circuit system structure embedded therein, such as a printed circuit board (PCB)). However, the present disclosure is not limited thereto; in alternative embodiments, Fig.15 The package structure P1A included in the package structure P2A shown in FIG. Fig. 14B The package structure P1B shown in FIG.

[0139] Reference Fig.17 In some embodiments, a heat dissipation cover 600 is provided and bonded to the substrate 500 of the package structure P2A to form a package structure P3A. In some embodiments, in the package structure P3A, in addition to the function of heat dissipation, the heat dissipation cover 600 may provide physical protection to the package structure P1A included in the package structure P2A. The heat dissipation cover 600 may have a high thermal conductivity (e.g., greater than or between about 200 W / m·K and about 400 W / m·K) and may be formed using a metal, a metal alloy, etc. In some embodiments, the heat dissipation cover 600 is attached to the substrate 500 using a bonding element 620 such as an adhesive so that the package structure P1A is arranged in an inner cavity defined by the heat dissipation cover 600 and the substrate 500. However, the present disclosure is not limited thereto; in alternative embodiments, Fig.17The package structure P1A included in the package structure P3A shown may be Fig. 14B The package structure P1B shown in FIG.

[0140] In some embodiments, a thermal interface material 610 is applied between the package structure P1A and the heat dissipation cover 600, wherein the thermal interface material 610 is thermally coupled to the heat dissipation element HDE of the package structure P1A, which further helps to dissipate heat from the package structure P1A to the heat dissipation cover 600, thereby helping to maintain a lower temperature within the package structure P3A. The thermal interface material 610 may include any suitable thermally conductive material, for example, a polymer having a good thermal conductivity greater than or between about 3 W / m·K and about 10 W / m·K.

[0141] Figure 18 to Figure 19 are schematic cross-sectional views of various stages in a method for manufacturing a package structure according to some embodiments of the present disclosure. Fig. 20 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.21A and Fig.21B is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig. 22 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.23 is a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure. In some embodiments, Figures 1 to 6 The process described in Figure 18 to Figure 19 Elements similar or substantially the same as those described above will be denoted by the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0142] Reference Fig.18 In some embodiments, according to Fig. 20 In step S20, at least one semiconductor die 100 and at least one semiconductor component 20 are provided and the at least one semiconductor die 100 and the at least one semiconductor component 20 are bonded to a substrate 310 (in which a plurality of through holes 320 are embedded and a redistribution wiring structure 340 and a plurality of conductive connectors 360 are disposed above). Fig.18As shown in , for example, the semiconductor die 100 is bonded to the substrate 310 by physically connecting the vias 140 and the conductive connectors 360, and the semiconductor component 20 is bonded to the substrate 310 by physically connecting the vias 22 and the conductive connectors 360. In some embodiments, bottom filler UF1 is applied to fill the gaps between the redistribution wiring structure 340 and the semiconductor die 100 and the gaps between the redistribution wiring structure 340 and the semiconductor component 20, thereby further enhancing the bonding strength between the redistribution wiring structure 340 and the semiconductor die 100 and the bonding strength between the redistribution wiring structure 340 and the semiconductor component 20. Figures 1 to 4 The details of semiconductor die 100 are described in Figure 6 The details of the semiconductor device 20, the details of the substrate 310 and the details of the underfill UF1 are described in detail in the accompanying drawings and are therefore not repeated herein. Fig.18 As shown in , for example, when measured along the stacking direction Z, the thickness of the first semiconductor die 100 is less than the thickness of the second semiconductor component 20 .

[0143] Reference Fig.19 In some embodiments, according to Fig. 20 In step S21, a heat dissipation element HDE is provided and the heat dissipation element HDE is bonded to a corresponding one of the semiconductor dies 100 to form a semiconductor component 10c. Fig.19 As shown, for example, when measured along the stacking direction Z, the thickness of the semiconductor component 10c is greater than the thickness of the second semiconductor component 20. However, the present disclosure is not limited thereto; in alternative embodiments, the thickness of the semiconductor component 10c is substantially equal to the thickness of the second semiconductor component 20. In some embodiments, for Fig.19 In each semiconductor component 10c shown in FIG. 1 , the heat dissipation element HDE is connected to the semiconductor die 100 located thereunder, and the heat dissipation element HDE and the semiconductor die 100 located thereunder are thermally coupled to each other. Fig.19 As shown in FIG, the heat dissipation element HDE includes a base layer 210 and an adhesive layer 220 disposed on the base layer 210, wherein the adhesive layer 220 is sandwiched between the base layer 210 of the heat dissipation element HDE and the semiconductor die 100. Fig.19 The structure shown in FIG. 1 is implemented as previously described in Figures 7 to 13 The manufacturing process described in the Fig.21A The packaging structure P1C shown in FIG. 1 is also shown in FIG. 1 . Fig. 20 The manufacturing method of FIG. 1 is shown in steps S22 to S27. Due to the heat dissipation element HDE, the heat generated from the semiconductor die 100 can be easily dissipated to the external environment through the heat dissipation element HDE, thereby helping to maintain a low temperature within the package structure P1C.

[0144] That is, based on the heat dissipation element HDE of each semiconductor component 10c included in the package structure P1C, the heat dissipation efficiency of the semiconductor component 10c can be controlled by adjusting the material of the heat dissipation element HDE, thereby ensuring the reliability of the package structure P1C. In other words, due to the presence of the heat dissipation element HDE, the overall thermal characteristics (e.g., heat dissipation, heat resistance) of the package structure P1C can be ensured.

[0145] In some embodiments, due to Fig. 20 The manufacturing method for Fig.21A In each semiconductor device 10c shown in FIG. 1 , the sidewalls of the heat dissipation element HDE (e.g., the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220) may not be aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE, and the sidewalls of the base layer 210 may not be aligned with the sidewalls of the adhesive layer 220. In other words, Fig.21A For example, in the heat dissipation element HDE, there is an offset D1 between the sidewall of the base layer 210 and the sidewall of the adhesive layer 220; and in the semiconductor device 10c, there is an offset D2 between the sidewall of the adhesive layer 220 and the sidewall of the semiconductor die 100. In some embodiments, the offset D1 and the offset D2 are independently in the range from 5 μm to 5000 μm.

[0146] However, the present disclosure is not limited thereto. In one embodiment, the sidewalls of the heat dissipation element HDE (e.g., the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220) may not be aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE, while the sidewalls of the base layer 210 may be aligned with the sidewalls of the adhesive layer 220. Alternatively, in another embodiment, the sidewalls of the heat dissipation element HDE may be partially aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE (e.g., one of the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220 may be partially aligned with the sidewalls of the semiconductor die 100 located therebelow), while the sidewalls of the base layer 210 may not be aligned with the sidewalls of the adhesive layer 220. Alternatively, in yet another embodiment, similar to the semiconductor component 10a, the sidewalls of the heat dissipation element HDE (for example, the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220) may be aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE, and the sidewalls of the base layer 210 may be aligned with the sidewalls of the adhesive layer 220.

[0147] On the other hand, in an alternative embodiment of the package structure P1C, the adhesive layer 220 may be omitted from the heat dissipation element HDE, see Fig.21BIn some embodiments, the package structure P1D includes a semiconductor component 10d instead of the semiconductor component 10c, wherein the semiconductor component 10d in the package structure P1D includes a heat dissipation element HDE having only a base layer 210. In some embodiments, due to Fig. 20 The manufacturing method for Fig.21B In each semiconductor device 10d shown in FIG. 1 , the sidewalls of the heat dissipation element HDE (eg, the sidewalls of the base layer 210 ) may not be aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE. Fig.21B In the embodiment, for example, there is an offset D3 between the sidewalls of the base layer 210 and the sidewalls of the semiconductor die 100 in the semiconductor component 10d. In some embodiments, the offset D3 is in a range from 5 μm to 5000 μm. Alternatively, in one embodiment, similar to the semiconductor component 10b, the sidewalls of the heat dissipation element HDE (e.g., the sidewalls of the base layer 210) can be aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE.

[0148] In addition, Fig.21A The structure shown in FIG. 1 is implemented as previously described in Fig.15 The manufacturing process described in the Fig. 22 The (stacked) package structure P2C shown in FIG. Fig. 22 The structure shown in FIG. 1 is implemented as previously described in Fig.17 The manufacturing process described in the Fig.23 However, the present disclosure is not limited thereto; in alternative embodiments, Fig. 22 The package structure P1C or the package structure P2C shown in FIG. Fig.23 The package structure P1C included in the package structure P3C shown in FIG. Fig.21B The package structure P1D shown in FIG.

[0149] Figures 24 to 33A are schematic cross-sectional views of various stages in a method for manufacturing a package structure according to some embodiments of the present disclosure. Fig.33B is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.34 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.35 is a flow chart showing a method of manufacturing a packaging structure according to some embodiments of the present disclosure. Elements similar to or substantially the same as the above elements will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0150] Reference Fig.24 In some embodiments, Fig.18 The process described in Fig.35 After step S30), dummy elements DE (according to the steps of FIG. 1 and FIG. 2 ) are sequentially formed on each of the semiconductor dies 100. Fig.35 Step S31). The dummy element DE may include a removable layer made of glass, polymer or compound, and may be formed on the semiconductor die 100 by bonding or any other suitable technique. The present disclosure is not limited thereto. Fig.24 As shown in , for example, when measured along the stacking direction Z, the thickness of each semiconductor die having a corresponding one of the dummy elements DE is greater than the thickness of the second semiconductor component 20. However, the present disclosure is not limited thereto; in an alternative embodiment, the thickness of each semiconductor die having a corresponding one of the dummy elements DE is substantially equal to the thickness of the second semiconductor component 20.

[0151] Reference Fig.25 In some embodiments, according to Fig.35 In step S32, an insulating encapsulation body 400m is formed on the substrate 310. Figure 7 The formation and materials of the insulating encapsulation body 400m have been described in the process of FIG. 1 and are therefore not repeated herein. Fig.25 As shown in , for example, the semiconductor die 100, semiconductor component 20, and bottom filling glue UF1 on which the dummy element DE is disposed are surrounded and covered by the insulating encapsulation body 400m. That is, the semiconductor die 100, semiconductor component 20, and bottom filling glue UF1 on which the dummy element DE is disposed are embedded in the insulating encapsulation body 400m. In other words, the semiconductor die 100, semiconductor component 20, and bottom filling glue UF1 on which the dummy element DE is disposed are not exposed by the insulating encapsulation body 400m in a touchable manner and are embedded in the insulating encapsulation body 400m.

[0152] Reference Fig.25 and Fig.26 In some embodiments, according to Fig.35 In step S33, the insulating encapsulation body 400m is planarized until the bottom surface S1 of the dummy element DE and the bottom surface 20b of the semiconductor component 20 disposed on the semiconductor die 100 are exposed. After the insulating encapsulation body 400m is planarized, the (planarized) insulating encapsulation body 400 is formed, and the bottom surface S1 of the dummy element DE and the bottom surface 20b of the semiconductor component 20 are exposed by the surface 400a of the insulating encapsulation body 400. Figure 8 The formation of the insulating encapsulation body 400 has been described in the process of FIG. 1 and is therefore not repeated herein.

[0153] Reference Fig. 27In some embodiments, after forming the insulating encapsulation body 400, Fig.26 The structure shown in FIG. 4 is turned over (upside down along the stacking direction Z), and the insulating encapsulation 400 is placed on the carrier C1. Fig. 9 The materials of the carrier C1 have been described in the process of FIG. 1 and are therefore not repeated herein.

[0154] Reference Fig.28 In some embodiments, according to Fig.35 In step S34, the substrate 310 is then planarized until the bottom surface 320b of the through hole 320 embedded in the substrate 310 is exposed. Fig.10 The details of the patterning process have been described in the process of FIG. 1 and therefore will not be repeated herein. Fig.28 As shown in FIG. 3 , the bottom surface 320 b of the through-hole 320 is substantially flush and coplanar with the surface 310 b of the substrate 310. That is, the bottom surface 320 b of the through-hole 320 is exposed by the substrate 310 in an accessible manner.

[0155] Reference Fig.29 In some embodiments, according to Fig.35 In step S35, a plurality of conductive connecting members 380 are formed on the substrate 310, wherein the conductive connecting members 380 are connected to the through-holes 320. Fig.29 The formation and materials of the conductive connectors 380 have been described in the process of and are therefore not repeated herein. In some embodiments, some of the conductive connectors 380 are electrically connected to the semiconductor die 100 through the through-holes 320, the redistribution wiring structure 340, and the conductive connectors 360. In some embodiments, some of the conductive connectors 380 are electrically connected to the semiconductor component 20 through the through-holes 320, the redistribution wiring structure 340, and the conductive connectors 360. In alternative embodiments, some of the conductive connectors 380 may also be electrically connected to active devices and passive devices embedded in the substrate 310 or formed on the surface 310a of the substrate 310.

[0156] Reference Fig.30 In some embodiments, Fig.29 The entire structure shown in FIG. 1 is flipped (inverted) together with the carrier C1 and placed on the holding device HD2, and then the carrier C1 is peeled off from the insulating encapsulation 400, the dummy element DE and the semiconductor component 20. In some embodiments, the carrier C1 is separated from the insulating encapsulation 400, the dummy element DE and the semiconductor component 20 by a peeling process, wherein the carrier C1 is removed and the insulating encapsulation 400, the dummy element DE and the semiconductor component 20 are exposed. Fig.30As shown in FIG. 4 , the surface 400 a of the insulating encapsulation body 400 , the bottom surface S1 of the dummy element DE, and the bottom surface 20 b of the semiconductor device 20 are exposed. Fig.12 The details of the lift-off process and the material of the holding device HD2 have been described in the process of FIG. 1 and therefore will not be repeated herein.

[0157] Reference Fig.31 In some embodiments, according to Fig.35 Step S36, sequentially performing a dicing (or singulation) process to Fig.30 The entire structure shown in the figure is cut into a plurality of individual and separate structures on which dummy elements DE are disposed. In one embodiment, the dicing process is a wafer dicing process, which includes mechanical blade sawing or laser cutting. The present disclosure is not limited thereto. In addition, the substrate 310 and the through-hole 320 are considered as an interposer.

[0158] Reference Fig.32 In some embodiments, according to Fig.35 In step S37, the structure on which the dummy element DE is disposed is bonded to the substrate 500 (including a plurality of bonding pads 510, 520, a plurality of metallization layers 530 interconnected with each other and a plurality of through holes, a plurality of surface devices 540, 550, and a plurality of conductive elements 560) through a plurality of conductive connectors 380. Fig.15 The details of the bonding process and the formation and materials of the substrate 500 (including the bonding pads 510, 520, the interconnected metallization layers 530 and through-holes, the surface devices 540, 550 and the conductive element 560) have been described in the process of FIG. 1 and are therefore not repeated herein. In some embodiments, an underfill UF2 is formed on the substrate 500. Fig.32 As shown in FIG. 5 , for example, the bottom filler UF2 fills the gap between the structure on which the dummy element DE is disposed and the substrate 500 and surrounds the sidewall of the conductive connection member 380. The material and formation of the bottom filler UF2 can be different from Figure 6 The materials and formation of the underfill UF1 described in , are the same or similar, and therefore are not repeated herein for the sake of brevity. In addition, the substrate 500 is considered to be a circuit structure (eg, an organic substrate with a circuit system structure embedded therein, such as a printed circuit board (PCB)).

[0159] Reference Fig.33A In some embodiments, according to Fig.35In step S38, the dummy element DE is removed, and then a heat dissipation element HDE is disposed on the semiconductor die 100 to form a (stacked) package structure P2E having a package structure P1E, the package structure P1E including a semiconductor component 10e disposed on the substrate 500. For example, the removal of the dummy element DE may be performed by etching, UV de-adhesion, or thermal de-adhesion, but the present disclosure is not limited thereto. In some embodiments, the heat dissipation element HDE is disposed on the semiconductor die 100 to form a (stacked) package structure P2E having a package structure P1E. The package structure P1E includes a semiconductor component 10e disposed on the substrate 500. Fig.32 The structure shown in FIG. 1 is shown in FIG. 2 , wherein the dummy element DE is removed to form a recess R above the semiconductor die 100, and then a heat dissipation element HDE is disposed in the recess R to physically contact the semiconductor die 100 and the insulating encapsulation body 400. In other words, the recess R is defined by the semiconductor die 100 and the insulating encapsulation body 400. In some embodiments, the semiconductor device 10e includes a heat dissipation element HDE and a semiconductor die 100 located below the heat dissipation element HDE, wherein the heat dissipation element HDE is thermally coupled to the semiconductor die 100. For example, as shown in FIG. Fig.33A As shown in , the heat dissipation element HDE includes a base layer 210 and an adhesive layer 220 disposed on the base layer 210, wherein the adhesive layer 220 is sandwiched between the semiconductor die 100 of the semiconductor device 10e and the base layer 210. Figure 1 The material of the base layer 210 and the material of the adhesive layer 220 included in the heat dissipation element HDE have been described in Figures 1 to 5 The details of the semiconductor die 100 have been described in detail in the prior art and are therefore not repeated herein. Fig.33A As shown in , in each semiconductor component 10e encapsulated in the insulating package 400, the heat generated from the semiconductor die 100 can be easily dissipated to the external environment through the heat dissipation element HDE, thereby helping to maintain a lower temperature in the package structure P1E. That is, based on the heat dissipation element HDE of each semiconductor component 10e included in the package structure P1E, the heat dissipation efficiency of the semiconductor component 10e can be controlled by adjusting the material of the heat dissipation element HDE, thereby ensuring the reliability of the package structure P1E. In other words, due to the presence of the heat dissipation element HDE, the overall thermal characteristics (e.g., heat dissipation, heat resistance) of the package structure P1E can be ensured.

[0160] because Fig.35 In the cross-sectional view, the outline of the semiconductor component 10e included in the package structure P1E in the package structure P2E may be similar to Fig.14A The semiconductor device 10a or Fig.21A The outline of the semiconductor device 10c is the same as that of the semiconductor device 10c shown in FIG. Fig.33AAs shown in FIG. 1 , similar to the semiconductor device 10a, the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220 are aligned with the sidewalls of the semiconductor die 100 and are substantially coplanar. However, the present disclosure is not limited thereto. In some embodiments, similar to the semiconductor device 10c, the sidewalls of the heat dissipation element HDE (e.g., the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220) may not be aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE, and the sidewalls of the base layer 210 may not be aligned with the sidewalls of the adhesive layer 220. That is, for example, within the heat dissipation element HDE, there may be an offset between the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220 in a range from 5 μm to 5000 μm; and within the semiconductor device 10e, there may be another offset between the sidewalls of the adhesive layer 220 and the sidewalls of the semiconductor die 100 in a range from 5 μm to 5000 μm. In some embodiments, the sidewalls of the heat dissipation element HDE (e.g., the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220) may not be aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE, while the sidewalls of the base layer 210 may be aligned with the sidewalls of the adhesive layer 220. Alternatively, in another embodiment, the sidewalls of the heat dissipation element HDE may be partially aligned with the sidewalls of the semiconductor die 100 located below the heat dissipation element HDE (e.g., one of the sidewalls of the base layer 210 and the sidewalls of the adhesive layer 220 may be aligned with the sidewalls of the semiconductor die 100), while the sidewalls of the base layer 210 may not be aligned with the sidewalls of the adhesive layer 220.

[0161] On the other hand, in an alternative embodiment of the package structure P1E, the adhesive layer 220 may be omitted from the heat dissipation element HDE, see Fig.33B In some embodiments, the package structure P1F includes a semiconductor component 10f instead of a semiconductor component 10e, wherein the semiconductor component 10f of the package structure P1F includes a heat dissipation element HDE having only a base layer 210. In some embodiments, due to Fig.35 The manufacturing method for Fig.33B For each semiconductor component 10f shown in FIG. 1 , in the cross-sectional view, the outline of the semiconductor component 10f included in the package structure P1F of the package structure P2F may be the same as Fig. 14B The semiconductor device 10b shown in FIG. Fig.21B The outline of the semiconductor device 10d is the same as that of the semiconductor device 10d shown in FIG. Fig.33BAs shown, similar to the semiconductor component 10b, the sidewalls of the base layer 210 may be aligned with the sidewalls of the semiconductor die 100 located below the base layer 210. However, the present disclosure is not limited thereto. In some embodiments, similar to the semiconductor component 10d, the sidewalls of the base layer 210 may not be aligned with the sidewalls of the semiconductor die 100 located below the base layer 210. That is, for example, there may be an offset ranging from 5 μm to 5000 μm between the sidewalls of the base layer 210 and the sidewalls of the semiconductor die 100 in the semiconductor component 10f.

[0162] Reference Fig.34 In some embodiments, a heat dissipation cover 600 and a thermal interface material 610 are provided and bonded to the substrate 500 of the package structure P2E to form a package structure P3E. Fig.17 The materials and formation of the heat dissipation cover 600 and the thermal interface material 610 have been described in detail in the previous section and are therefore not repeated herein for the sake of brevity. In some embodiments, the thermal interface material 610 is located between the package structure P1E and the heat dissipation cover 600, wherein the thermal interface material 610 is thermally coupled to the heat dissipation element HDE included in the semiconductor component 10e of the package structure P1E, which further helps to dissipate heat from the package structure P1E to the heat dissipation cover 600, thereby helping to maintain a lower temperature within the package structure P3E. However, the present disclosure is not limited thereto; in alternative embodiments, Fig.34 The package structure P2E included in the package structure P3E shown in FIG. Fig.33B The package structure P2F shown in FIG.

[0163] Fig.36 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.37 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.38 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.39 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.40 Schematic cross-sectional views of packaging structures according to some embodiments of the present disclosure. Elements similar to or substantially the same as the above elements will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0164] Reference Fig.36In some embodiments, the package structure P4A includes a semiconductor component 10a, a semiconductor component 30, an insulating enclosure 700, a redistribution wiring structure 800, and a plurality of conductive terminals 900. In some embodiments, the semiconductor component 10a and the semiconductor component 30 are encapsulated in the insulating enclosure 700, wherein the surface S2 of the semiconductor component 10a and the surface S3 of the semiconductor component 30 are exposed by the surface 700b of the insulating enclosure 700. In some embodiments, the redistribution wiring structure 800 is located on the surface 700a of the insulating enclosure 700, wherein the surface 700a is opposite to the surface 700b along the stacking direction Z of the redistribution wiring structure 800 and the insulating enclosure 700. Fig.36 As shown in FIG. 1 , for example, the redistribution wiring structure 800 is electrically connected to the semiconductor component 10a and the semiconductor component 30. In the present disclosure, the redistribution wiring structure 800 provides a wiring function to the semiconductor components 10a and 30. In some embodiments, the conductive terminal 900 is located on and connected to the redistribution wiring structure 800, wherein the redistribution wiring structure 800 is located between the insulating enclosure 700 and the conductive terminal 900. Fig.36 As shown in , some of the conductive terminals 900 are electrically connected to the semiconductor component 10 a , and some of the conductive terminals 900 are electrically connected to the semiconductor component 30 .

[0165] exist Figures 1 to 5 The formation and materials of the semiconductor device 10a have been described in detail in the previous section and are therefore not repeated herein. Fig.36 As shown in , the semiconductor component 10a includes a first semiconductor die 100 and a heat dissipation element HDE disposed on the first semiconductor die 100, wherein the heat dissipation element HDE is thermally coupled to the first semiconductor die 100. Due to the heat dissipation element HDE, the heat generated from the semiconductor die 100 can be easily dissipated to the external environment through the heat dissipation element HDE, thereby helping to maintain a lower temperature within the package structure P4A. That is, based on the heat dissipation element HDE of the semiconductor component 10a included in the package structure P4A, the heat dissipation efficiency of the semiconductor component 10a can be controlled by adjusting the material of the heat dissipation element HDE, thereby ensuring the reliability of the package structure P4A. In other words, due to the presence of the heat dissipation element HDE, the overall thermal characteristics of the package structure P4A (e.g., heat dissipation, heat resistance) can be ensured. However, the present disclosure is not limited to this; in alternative embodiments, the semiconductor component 10a may be Fig.21A The semiconductor device 10c or Fig.33A Alternatively, the semiconductor component 10a may be replaced by the semiconductor component 10e shown in FIG. Fig. 14B The semiconductor device 10b shown in FIG. Fig.40 The package shown in P4B), Fig.21BThe semiconductor device 10d or Fig.33B The semiconductor device 10f shown in FIG.

[0166] In some embodiments, the semiconductor component 30 includes a semiconductor substrate 31 having an active surface 31a, an interconnect structure 32 formed on the active surface 31a, and a plurality of vias 33 electrically connected to the interconnect structure 32. In some embodiments, the semiconductor substrate 31 may be a silicon substrate including active components (e.g., transistors, etc.) and / or passive components (e.g., resistors, capacitors, inductors, etc.) formed therein. The present disclosure is not limited thereto. In one embodiment, the formation and material of the semiconductor substrate 31 may be the same as the formation and material of the semiconductor substrate 110; however, the present disclosure is not limited thereto.

[0167] In some embodiments, the interconnect structure 32 includes one or more interlayer dielectric layers 32a and one or more patterned conductive layers 32b that are alternately stacked. In some embodiments, the patterned conductive layer 32b is sandwiched between the interlayer dielectric layers 32a, wherein a portion of the top surface of the top layer of the patterned conductive layer 32b is exposed by the top layer of the interlayer dielectric layer 32a and physically connected to the via 33, and some portions of the bottom layer of the patterned conductive layer 32b are exposed by the bottom layer of the interlayer dielectric layer 32a and electrically connected to active components and / or passive components (not shown) formed in the semiconductor substrate 31. Fig.36 As shown in FIG. 1 , the bottom layer of the interlayer dielectric layer 32a is located on the active surface 31a of the semiconductor substrate 31, and the top layer of the interlayer dielectric layer 32a is at least partially in contact with the via 33. The number of interlayer dielectric layers 32a and the number of patterned conductive layers 32b can be selected based on needs and are not limited in the present disclosure. The number of interlayer dielectric layers 32a and the number of patterned conductive layers 32b can be less than or greater than Fig.36 The number shown in FIG. 1 and may be specified based on needs and / or design layout; the present disclosure is not limited thereto. In one embodiment, the formation and material of the interlayer dielectric layer 32a may be similar to Figure 1 The formation and material of the interlayer dielectric layer 122 described in the above are the same or similar, and the formation and material of the patterned conductive layer 32b can be the same as Figure 1 The formation and materials of the patterned conductive layer 124 described in the above are the same or similar, and therefore are not repeated herein. In the present disclosure, the vias 33 are used as conductive terminals of the semiconductor component 30 to electrically connect to external components. In some embodiments, although for illustrative purposes, Fig.36 Only four vias 33 are shown in FIG. 1 , but it should be understood that the number of vias 33 can be selected or specified based on needs and design layout; the present disclosure is not limited thereto. In one embodiment, the formation and material of the vias 33 can be different from Figure 1The formation and materials of the via 140 are the same as those described in , and therefore will not be repeated herein. Fig.36 As shown in , the via 33 is physically connected to and electrically connected to the internal circuit structure 32. In some embodiments, the surface of the via 140 of the semiconductor component 10a and the surface of the via 33 of the semiconductor component 30 are substantially flush and substantially coplanar with the surface 700a of the insulating package 700, wherein the surface of the via 140 of the semiconductor component 10a and the surface of the via 33 of the semiconductor component 30 are exposed by the insulating package 700 and contact the redistribution wiring structure 800.

[0168] In some embodiments, semiconductor component 30 described herein may be referred to as a semiconductor chip or integrated circuit (IC). In one embodiment, semiconductor component 30 may be the same as or similar to semiconductor die 100. In an alternative embodiment, semiconductor component 30 may be different from semiconductor die 100. In yet another embodiment, semiconductor component 30 may be the same as or similar to semiconductor component 20. In yet another alternative embodiment, semiconductor component 30 may be different from semiconductor component 20.

[0169] In some embodiments, Fig.36 As shown in , the redistribution wiring structure 800 includes a plurality of dielectric layers 802 and a plurality of metallization layers 804 alternately stacked, wherein the metallization layers 804 are sandwiched between the dielectric layers 802, wherein the top surface of the topmost layer of the metallization layer 804 is at least partially exposed by a plurality of openings (not labeled) formed in the topmost layer of the dielectric layer 802 to be connected to a component formed later for electrical connection, and the bottom surface of the lowest layer of the metallization layer 804 is at least partially exposed by a plurality of openings (not labeled) formed in the lowest layer of the dielectric layer 802 and is electrically connected to the semiconductor component 10a through the via 140, and is electrically connected to the semiconductor component 30 through the via 33. The number of metallization layers 804 and the number of dielectric layers 802 are not limited in the present disclosure, and may be specified based on needs and / or design layout. That is, the surface of the via hole 140 of the semiconductor component 10a and the surface of the via hole 33 of the semiconductor component 30 exposed by the insulating encapsulation body 700 are in physical contact with the bottom layer of the metallization layer 804 exposed by the bottom layer of the dielectric layer 802. In some embodiments, the surface of the via hole 140 of the semiconductor component 10a and the surface of the via hole 33 of the semiconductor component 30 exposed by the insulating encapsulation body 700 are partially covered by the bottom layer of the dielectric layer 802.

[0170] continue Fig.36In some embodiments, the package structure P4A may further include a plurality of under-ball metallurgy (UBM) patterns u1, wherein the UBM pattern u1 may be disposed on the exposed top surface of the topmost layer of the metallization layer 804 to be electrically connected to a plurality of conductive elements (e.g., conductive balls or conductive bumps, such as conductive terminals 900). Fig.36 As shown in , for example, the UBM pattern u1 is formed on the redistribution wiring structure 800 and is electrically connected to the redistribution wiring structure 800. For example, the material of the UBM pattern u1 may include copper, nickel, titanium, tungsten or alloys thereof, and may be formed by an electroplating process. The number of UBM patterns u1 is not limited in the present disclosure, and corresponds to the number of portions of the top surface of the top layer of the metallization layer 804 that are exposed by the top layer of the dielectric layer 802. In some embodiments, the conductive terminal 900 is electrically connected to the redistribution wiring structure 800 through the UBM pattern u1. In some embodiments, the conductive terminal 900 may be disposed on the UBM pattern u1 by a ball placement process or a reflow process. In some embodiments, the conductive terminal 900 is, for example, a solder ball or a ball grid array (BGA) ball. The number of conductive terminals 900 is not limited to the present disclosure, and may be specified and selected based on the number of UBM patterns u1.

[0171] In one embodiment, the Fig.37 It should be understood that in Fig.37 Additional treatments may occur before, during, and after the illustrated actions of the method to complete the formation of the package structure P4A. Fig.37 The method includes at least steps S40 to S46. For example, Fig.37The method shown in the embodiment starts from step S40, step S40 provides a wafer including a plurality of first semiconductor dies; step S41, bonding the wafer including the plurality of first semiconductor dies to a wafer including a plurality of heat dissipation elements; step S42, dicing the bonded structure to form a plurality of individual and separate first semiconductor components each having a first semiconductor die and a corresponding heat dissipation element disposed on the first semiconductor die, wherein the first semiconductor die is thermally coupled to a corresponding heat dissipation element; step S43, bonding at least one of the plurality of first semiconductor components and at least one second The semiconductor component is encapsulated in an insulating package; step S44, flattening the insulating package so that the first surface of the insulating package exposes the heat dissipation element included in the first semiconductor component; step S45, forming a redistribution wiring structure electrically connected to the first semiconductor component and the second semiconductor component on the second surface of the insulating package, wherein the first surface is opposite to the second surface; and step S46, arranging a plurality of conductive terminals on the redistribution wiring structure, the conductive terminals being electrically connected to the first semiconductor component and the second semiconductor component through the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the conductive terminals and the insulating package. However, the present disclosure is not limited thereto.

[0172] In an alternative embodiment, the Fig.38 It should be understood that in Fig.38 Additional processing may occur before, during, and after the illustrated actions of the method to complete the formation of package structure P4A. Fig.38 The method comprises at least steps S50 to S55. For example, Fig.38 The method shown in starts from step S50, step S50 provides at least one first semiconductor die and at least one second semiconductor component, wherein the thickness of the first semiconductor die is less than the thickness of the second semiconductor component; step S51, disposing a heat dissipation element on the first semiconductor die to form a first semiconductor component, wherein the heat dissipation element is physically connected to the first semiconductor die, and the heat dissipation element is thermally coupled to the first semiconductor die; step S52, encapsulating the first semiconductor component and the second semiconductor component in an insulating encapsulation; step S53, flattening the insulating encapsulation so that the first surface of the insulating encapsulation exposes the heat dissipation element included in the first semiconductor component; step S54, forming a redistribution wiring structure electrically connected to the first semiconductor component and the second semiconductor component on the second surface of the insulating encapsulation, wherein the first surface is opposite to the second surface; and step S55, disposing a plurality of conductive terminals on the redistribution wiring structure, the conductive terminals being electrically connected to the first semiconductor component and the second semiconductor component through the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the conductive terminals and the insulating encapsulation. However, the present disclosure is not limited to this.

[0173] In some alternative embodiments, Fig.39 It should be understood that in Fig.39 Additional processing may occur before, during, and after the illustrated actions of the method to complete the formation of package structure P4A. Fig.39 The method includes at least steps S60 to S66. For example, Fig.39 The method shown in the embodiment starts from step S60, wherein step S60 provides at least one first semiconductor die and at least one second semiconductor component, wherein the thickness of the first semiconductor die is less than the thickness of the second semiconductor component; step S61, arranges a dummy element on the first semiconductor die; step S62, encapsulates the first semiconductor die and the second semiconductor component with the dummy element arranged thereon in an insulating package; step S63, flattens the insulating package so that the dummy element is exposed on the first surface of the insulating package; step S64, forms a conductive layer electrically connected to the first semiconductor die on the second surface of the insulating package; A redistribution wiring structure for a body die and a second semiconductor component, wherein the first surface is opposite to the second surface; step S65, setting a plurality of conductive terminals on the redistribution wiring structure, the conductive terminals being electrically connected to the first semiconductor die and the second semiconductor component through the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the conductive terminals and the insulating package; and step S66, removing the dummy elements from the first semiconductor die and directly setting a heat dissipation element on the first semiconductor die to form a first semiconductor component, wherein the heat dissipation element is physically connected to the first semiconductor die, and the heat dissipation element is thermally coupled to the first semiconductor die.

[0174] In some embodiments, Fig.36 The number of semiconductor components 10a and the number of semiconductor components 30 shown in FIG. Fig.40 The number of semiconductor components 10b and the number of semiconductor components 30 shown in the figure are not limited thereto, and may be one or more than one. Figure 6 The semiconductor component 20 described in the specification is replaced. Fig.41 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.42 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.43 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.44 Schematic cross-sectional views of packaging structures according to some embodiments of the present disclosure. Elements similar to or substantially the same as the above elements will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0175] Refer to Fig.36 and Fig.41 , Fig.36 The package structure P4A shown in FIG. Fig.41 The package structure P5A shown in FIG. 1 is similar to the package structure P5A shown in FIG. 1 ; the difference is that for Fig.41 The semiconductor package P5A shown in FIG. 1 is a semiconductor package that replaces one semiconductor component 30 with two semiconductor components 20. Fig.40 and Fig.42 , Fig.40 The package structure P4B shown in FIG. Fig.42 The package structure P5B shown in FIG. 1 is similar to the package structure P5B shown in FIG. 1 ; the difference is that for Fig.42 In the semiconductor package P5B shown in FIG. 8 , two semiconductor components 20 are used instead of one semiconductor component 30 .

[0176] Refer to Fig.36 and Fig.43 , Fig.36 The package structure P4A shown in FIG. Fig.43 The package structure P6A shown in FIG. 1 is similar to the package structure P6A shown in FIG. 1 ; the difference is that for Fig.43 The semiconductor package P6A shown in FIG. 1 replaces one semiconductor component 10a with two semiconductor components 10a, and replaces one semiconductor component 30 with one semiconductor component 20. Fig.40 and Fig.44 , Fig.40 The package structure P4B shown in FIG. Fig.44 The package structure P6B shown in FIG. 1 is similar to the package structure P6B shown in FIG. 1 ; the difference is that for Fig.44 In the semiconductor package P6B shown in FIG. 8 , one semiconductor component 10 b is replaced by two semiconductor components 10 b , and one semiconductor component 30 is replaced by one semiconductor component 20 .

[0177] However, the present disclosure is not limited thereto. In alternative embodiments, Fig.21A The semiconductor device 10c or Fig.33A The semiconductor device 10e shown in FIG. Fig.41 and Fig.43 The semiconductor device 10a shown in FIG. Fig.42 and Fig.44 The semiconductor device 10b shown in FIG. 1 can be independently Fig.21B The semiconductor device 10d or Fig.33B The semiconductor device 10f shown in FIG.

[0178] Fig.45 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.46 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.47is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.48 is a flow chart illustrating a method of manufacturing a package structure according to some embodiments of the present disclosure. Fig.49 is a schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure. Fig.36 and Fig.45 , Fig.36 The package structure P4A shown in FIG. Fig.45 Similar to the package structure P7A shown in FIG. 1 ; so that elements similar or substantially the same as the above-mentioned elements will use the same reference numbers, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated in this article.

[0179] Refer to Fig.36 and Fig.45 , the difference is that for Fig.45 The package structure P7A shown in the figure further includes additional elements (e.g., dielectric layer PM1, multiple vias CP1, multiple vias CP2, insulating package 702, and bridge element BE), wherein the bridge element BE is encapsulated in the insulating package 702 and disposed between the redistribution wiring structure 800 and the insulating package 700, and the bridge element BE is electrically connected to the semiconductor component 10a and the semiconductor component 30 through the vias CP2. That is, for example, the semiconductor component 10a is electrically connected to the semiconductor component 30 through the bridge element BE.

[0180] In some embodiments, Fig.45 As shown in , the dielectric layer PM1 is formed on the insulating package 700 and physically contacts the insulating package 700, wherein the dielectric layer PM1 has a plurality of openings (not labeled), which expose the surface of the via 33 of the semiconductor component 30 and the surface of the via 140 of the semiconductor component 10a. The material of the dielectric layer PM1 may include polyimide, PBO, benzocyclobutene (BCB), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, etc. that can be patterned using photolithography and / or etching processes. In some embodiments, vias CP1 and CP2 are formed on the dielectric layer PM1 and are connected to the vias 33 and 140 through the openings of the dielectric layer PM1. The material and formation of vias CP1 and CP2 are similar to those of the semiconductor component 10a. Figure 4The material and formation of the via 140 described in are the same or similar, and thus will not be repeated herein.

[0181] In some embodiments, the bridge element BE is disposed on the via CP2 and is surrounded by the via CP1. In some embodiments, when measured in the stacking direction Z, the height of the bridge element BE is less than the height of the via CP1. Fig.45 As shown in FIG. 1 , the bridge element BE overlaps the semiconductor component 10a and the semiconductor component 30 in the stacking direction Z of the redistribution wiring structure 800 and the insulating package 700, and extends from the semiconductor component 10a to the semiconductor component 30 (or, from the semiconductor component 30 to the semiconductor component 10a) in the vertical projection on the redistribution wiring structure 800. Due to the configuration, a short electrical path between the semiconductor component 10a and the semiconductor component 30 is achieved, thereby reducing the signal loss thereof.

[0182] In some embodiments, the via CP1, the via CP2 and the bridge element BE are encapsulated in the insulating encapsulation body 702, and the dielectric layer PM1 exposed by the via CP1 and the via CP2 is covered by the insulating encapsulation body 702. Fig.45 As shown in FIG. 1 , the surface of the bridge element BE, the surface of the via CP1, and the surface 702a of the insulating enclosure 142 are substantially flush with each other and substantially coplanar with each other. In some embodiments, the redistribution structure 800 is located on the bridge element BE, the via CP1, and the insulating enclosure 702 (at the surface 702a), and is physically and electrically connected to the via CP1. The material and formation of the insulating enclosure 702 are similar to Fig.36 The material and formation of the insulating encapsulation body 700 described in the foregoing are the same or similar, and thus will not be repeated herein. That is, for example, the redistribution wiring structure 800 is electrically connected to the semiconductor device 10a and the semiconductor device 30 through the via CP1, the via 33 and the via 140.

[0183] In some embodiments, the bridging element BE includes a substrate 41, a redistribution wiring structure 42 disposed on the substrate 41 (in which a dielectric structure 42a and one or more metallization layers 42b are arranged), and a plurality of through-holes 43 embedded in the substrate 41 and electrically connected to the redistribution wiring structure 42. The formation and material of the substrate 41 are the same or similar to the formation and material of the substrate 310, the formation and material of the redistribution wiring structure 42 are the same or similar to the formation and material of the redistribution wiring structure 340, and the formation and material of the through-hole 43 are the same or similar to the formation and material of the through-hole 320, and therefore are not repeated herein for the sake of brevity.

[0184] like Fig.45As shown in FIG. 1 , the bridge element BE is electrically connected to the semiconductor component 10a and the semiconductor component 30 through the vias 33, 140, CP2 and the redistribution structure 42. In other words, the semiconductor component 10a and the semiconductor component 30 are electrically connected to each other through the bridge element BE. Fig.45 As shown in FIG. 1 , the through-hole 43 of the bridge element BE is physically and electrically connected to the bottom layer of the metallization layer 804 of the redistribution wiring structure 800. That is, for example, the redistribution wiring structure 800 may also be electrically connected to the semiconductor device 10a and the semiconductor device 30 through the bridge element BE, the via CP2, the via 33 and the via 140. In some embodiments, some of the conductive elements 900 are electrically connected to the semiconductor component 10a through some of the UBM patterns u1, the redistribution wiring structure 800 and some of the vias CP1, or through some of the UBM patterns u1, the redistribution wiring structure 800, the bridging element BE and some of the vias CP2, and some of the conductive elements 900 are electrically connected to the semiconductor component 30 through some of the UBM patterns u1, the redistribution wiring structure 800 and some of the vias CP1, or through some of the UBM patterns u1, the redistribution wiring structure 800, the bridging element BE and some of the vias CP2.

[0185] In one embodiment, the Fig.46 It should be understood that in Fig.46 Additional processing may occur before, during, and after the illustrated actions of the method to complete the formation of package structure P7A. Fig.46 The method includes at least steps S70 to S79. For example, Fig.46The method shown in the embodiment starts from step S70, in which a wafer including a plurality of first semiconductor dies is provided; step S71, the wafer including the plurality of first semiconductor dies is bonded to a wafer including a plurality of heat dissipation elements; step S72, the bonded structure is cut to form a plurality of individual and separate first semiconductor components each having a first semiconductor die and a corresponding heat dissipation element disposed on the first semiconductor die, wherein the first semiconductor die is thermally coupled to a corresponding heat dissipation element; step S73, at least one of the plurality of first semiconductor components and at least one second semiconductor component are encapsulated in a first portion of an insulating encapsulation; step S74, the first portion of the insulating encapsulation is planarized so that a first surface of the first portion of the insulating encapsulation exposes the heat dissipation elements included in the first semiconductor components; step S75, a plurality of first vias and a plurality of second vias are disposed on the first semiconductor component and the second semiconductor component; step S76, a connecting element (e.g., Fig.45 A bridging element BE shown in the figure is used to electrically connect the first semiconductor component and the second semiconductor component, wherein the connecting element is physically connected to and electrically connected to the second conductive hole connected to the first semiconductor component and the second semiconductor component, so that the first semiconductor component and the second semiconductor component are electrically connected to each other through the connecting element and the second conductive hole; step S77, encapsulating the first conductive hole, the second conductive hole and the connecting element in the second part of the insulating enclosure, wherein the surface of the first conductive hole and the surface of the connecting element are substantially flush with and substantially coplanar with the second surface of the second part of the insulating enclosure; step S78, forming a redistribution wiring structure on the second surface of the second part of the insulating enclosure to electrically connect to the first semiconductor component and the second semiconductor component through the first conductive hole and / or the connecting element connected to the second conductive hole, wherein the second part of the insulating enclosure is sandwiched between the redistribution wiring structure and the first part of the insulating enclosure; and step S79, providing a plurality of conductive terminals on the redistribution wiring structure, the conductive terminals are electrically connected to the first semiconductor component and the second semiconductor component through the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the conductive terminals and the second part of the insulating enclosure. However, the present disclosure is not limited thereto.

[0186] In an alternative embodiment, the Fig.47 It should be understood that in Fig.47 Additional processing may occur before, during, and after the illustrated actions of the method to complete the formation of package structure P7A. Fig.47 The method includes at least steps S80 to S88. For example, Fig.47The method shown in the embodiment starts from step S80, wherein step S80 provides at least one first semiconductor die and at least one second semiconductor component, wherein the thickness of the first semiconductor die is less than the thickness of the second semiconductor component; step S81, disposing a heat dissipation element on the first semiconductor die to form a first semiconductor component, wherein the heat dissipation element is physically connected to the first semiconductor die and the heat dissipation element is thermally coupled to the first semiconductor die; step S82, encapsulating the first semiconductor component and the second semiconductor component in a first portion of an insulating encapsulation body; step S83, flattening the first portion of the insulating encapsulation body so that a first surface of the first portion of the insulating encapsulation body exposes the heat dissipation element included in the first semiconductor component; step S84, disposing a plurality of first vias and a plurality of second vias on the first semiconductor component and the second semiconductor component; step S85, disposing a connecting element (e.g., Fig.45 A bridging element BE shown in the figure is used to electrically connect the first semiconductor component and the second semiconductor component, wherein the connecting element is physically connected to and electrically connected to the second conductive hole connected to the first semiconductor component and the second semiconductor component, so that the first semiconductor component and the second semiconductor component are electrically connected to each other through the connecting element and the second conductive hole; step S86, encapsulating the first conductive hole, the second conductive hole and the connecting element in the second part of the insulating enclosure, wherein the surface of the first conductive hole and the surface of the connecting element are substantially flush with and substantially coplanar with the second surface of the second part of the insulating enclosure; step S87, forming a redistribution wiring structure on the second surface of the second part of the insulating enclosure to electrically connect to the first semiconductor component and the second semiconductor component through the first conductive hole and / or the connecting element connected to the second conductive hole, wherein the second part of the insulating enclosure is sandwiched between the redistribution wiring structure and the first part of the insulating enclosure; and step S88, providing a plurality of conductive terminals on the redistribution wiring structure, the conductive terminals are electrically connected to the first semiconductor component and the second semiconductor component through the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the conductive terminals and the second part of the insulating enclosure. However, the present disclosure is not limited thereto.

[0187] In some alternative embodiments, Fig.48 It should be understood that in Fig.48 Additional processing may occur before, during, and after the illustrated actions of the method to complete the formation of package structure P7A. Fig.48 The method includes at least steps S90 to S99. For example, Fig.48The method shown starts from step S90, in which at least one first semiconductor die and at least one second semiconductor component are provided, wherein the thickness of the first semiconductor die is less than the thickness of the second semiconductor component; step S91, arranging a dummy element on the first semiconductor die; step S92, encapsulating the first semiconductor die and the second semiconductor component with the dummy element arranged thereon in a first part of an insulating encapsulation body; step S93, flattening the first part of the insulating encapsulation body so that the first surface of the first part of the insulating encapsulation body exposes the dummy element arranged on the first semiconductor die; step S94, arranging a plurality of first conductive vias and a plurality of second conductive vias on the first semiconductor die and the second semiconductor component; step S95, arranging a connecting element (e.g., Fig.45 Step S96, encapsulating the first conductive hole, the second conductive hole and the connecting element by the second part of the insulating encapsulation, wherein the surface of the first conductive hole and the surface of the connecting element are substantially flush with and substantially coplanar with the second surface of the second part of the insulating encapsulation; Step S97, forming a redistribution wiring structure on the second surface of the second part of the insulating encapsulation to connect the first conductive hole and / or the second conductive hole to the second semiconductor component. The connecting element connected to the second conductive hole is electrically connected to the first semiconductor die and the second semiconductor component, wherein the second portion of the insulating encapsulant is sandwiched between the redistribution wiring structure and the first portion of the insulating encapsulant; step S98, a plurality of conductive terminals are provided on the redistribution wiring structure, the conductive terminals are electrically connected to the first semiconductor die and the second semiconductor component through the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the conductive terminals and the second portion of the insulating encapsulant; and step S99, the dummy element is removed from the first semiconductor die and a heat dissipation element is directly provided on the first semiconductor die to form a first semiconductor component, wherein the heat dissipation element is physically connected to the first semiconductor die, and the heat dissipation element is thermally coupled to the first semiconductor die.

[0188] However, the present disclosure is not limited thereto; in some alternative embodiments, Fig.21A The semiconductor device 10c or Fig.33A The semiconductor component 10e shown in FIG. 1 replaces the semiconductor component 10a of the package structure P7A; or, the semiconductor component 10a of the package structure P7A may be Fig. 14B The semiconductor device 10b shown in FIG. Fig.49 The package structure shown in P7B) Fig.21B The semiconductor device 10d or Fig.33B The semiconductor device 10f shown in FIG.

[0189] In some alternative embodiments, in addition to Fig.36 , Figure 40 to Figure 45 ,and Fig.49 In addition to the conductive terminals 900 in the redistribution structure 800, additional semiconductor elements (not shown) may be provided on the redistribution structure 800 by replacing the bonding pads (not shown) of the UBM pattern u1. The additional semiconductor elements may include passive components or active components. The number of additional semiconductor elements is not limited in the present disclosure and may be specified based on needs and design layout. In some embodiments, the package structures P4A to P7B may be further installed with additional packages, chips / die, other electronic devices or suitable substrates (e.g., organic substrates) to form a stacked package structure, but the present disclosure is not limited thereto.

[0190] According to some embodiments, a packaging structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipation element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipation element is connected to the first semiconductor die, and the first semiconductor die is located between the circuit element and the heat dissipation element, wherein the sum of the first thickness of the first semiconductor die and the third thickness of the heat dissipation element is substantially equal to the second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die, and the heat dissipation element, wherein the surface of the heat dissipation element is substantially flush with the surface of the insulating encapsulation.

[0191] In some embodiments, in the package structure, wherein in a cross-sectional view, the sidewall of the heat dissipation element is substantially aligned with the sidewall of the first semiconductor die. In some embodiments, in the package structure, wherein the heat dissipation element includes an adhesive base layer, and the thermal conductivity of the adhesive base layer is greater than the thermal conductivity of the insulating encapsulation. In some embodiments, in the package structure, wherein in a cross-sectional view, there is an offset between the sidewall of the heat dissipation element and the sidewall of the first semiconductor die, and the offset is in a range from 5 μm to 5000 μm. In some embodiments, in the package structure, wherein the heat dissipation element includes a base layer and an adhesive layer located between the base layer and the first semiconductor die, wherein the thermal conductivity of the base layer is greater than the thermal conductivity of the insulating encapsulation, and the thermal conductivity of the adhesive layer is greater than the thermal conductivity of the insulating encapsulation. In some embodiments, in the package structure, in a cross-sectional view, there is a first offset between the sidewall of the base layer and the sidewall of the adhesive layer, and there is a second offset between the sidewall of the adhesive layer and the sidewall of the first semiconductor die, and the first offset and the second offset are independently in a range from 5 μm to 5000 μm. In some embodiments, in the package structure, the circuit element is a circuit substrate that is not in contact with the insulating encapsulation, and the package structure further includes: an interposer structure located between the first semiconductor die and the circuit element and connected to the first semiconductor die and the circuit element; and a plurality of conductive terminals located on the circuit element, the circuit element being located between the interposer structure and the plurality of conductive terminals. In some embodiments, in the package structure, the circuit element is a redistribution wiring structure, the portion of the redistribution wiring structure exposed by the first semiconductor die and the second semiconductor die is covered by the insulating encapsulation, and the package structure further includes: a plurality of conductive terminals located on the circuit element, the circuit element being located between the insulating encapsulation and the plurality of conductive terminals.In some embodiments, in the packaging structure, the circuit element is a redistribution wiring structure, the portion of the redistribution wiring structure exposed by the first semiconductor die and the second semiconductor die is covered by the insulating encapsulant, and the packaging structure also includes: a connecting element having a semiconductor substrate and a plurality of through-holes penetrating the semiconductor substrate, the connecting element being located on the first semiconductor die and the second semiconductor die, the first semiconductor die and the second semiconductor die being electrically connected through the connecting element; a plurality of conductive pillars being located on the first semiconductor die and the second semiconductor die and connected to the first semiconductor die and the second semiconductor die, and being located next to the connecting element; and a plurality of conductive terminals being located on the circuit element, the circuit element being located between the insulating encapsulant and the plurality of conductive terminals, wherein the insulating encapsulant includes a first portion encapsulating the first semiconductor die and the second semiconductor die and a second portion encapsulating the connecting element and the plurality of conductive pillars, the second portion being located between the first portion and the circuit element.

[0192] According to some embodiments, a method for manufacturing a packaging structure includes the following steps: providing a first semiconductor die connected to a heat dissipation element; providing a second semiconductor die; encapsulating the first semiconductor die, the second semiconductor die, and the heat dissipation element in an insulating encapsulation body; and flattening the insulating encapsulation body so that the insulating encapsulation body exposes the heat dissipation element, wherein the sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipation element is substantially equal to a second thickness of the second semiconductor die.

[0193] In some embodiments, in the method of manufacturing a package structure, providing the first semiconductor die connected to the heat dissipation element includes: providing a first wafer having a circuit system and a second wafer including the heat dissipation element; bonding the first wafer to the second wafer to form a stacked structure; and dicing the stacked structure to form the first semiconductor die connected to the heat dissipation element. In some embodiments, in the method of manufacturing a package structure, providing the first semiconductor die connected to the heat dissipation element includes: providing the first semiconductor die; disposing the first semiconductor die on the circuit element; and disposing the heat dissipation element on the first semiconductor die. In some embodiments, the method of manufacturing a package structure further includes: forming a redistribution wiring structure electrically connected to the first semiconductor die and the second semiconductor die on the insulating encapsulation; and disposing a plurality of conductive terminals on the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the plurality of conductive terminals and the insulating encapsulation. In some embodiments, in the method for manufacturing a packaging structure, wherein the insulating encapsulation includes a first portion encapsulating the first semiconductor die and the second semiconductor die and a second portion stacked on the first portion, before forming the redistribution wiring structure, the method further includes: providing a connecting element on the first semiconductor die and the second semiconductor die encapsulated in the first portion to electrically connect the first semiconductor die and the second semiconductor die; forming a plurality of conductive columns on the first semiconductor die and the second semiconductor die; and encapsulating the connecting element and the plurality of conductive columns in the second portion of the insulating encapsulation, the second portion being located between the first portion and the redistribution wiring structure. In some embodiments, the method for manufacturing a packaging structure also includes: providing an interposer having a plurality of through-holes therein; before encapsulating the first semiconductor die and the second semiconductor die in the insulating encapsulant, arranging the first semiconductor die and the second semiconductor die on the interposer by flip-chip bonding; after planarizing the insulating encapsulant, patterning the interposer to expose the plurality of through-holes; forming a plurality of connectors on the exposed plurality of through-holes, the interposer being sandwiched between the insulating encapsulant and the plurality of connectors; and bonding the first semiconductor die and the second semiconductor die to a circuit structure having a plurality of conductive terminals through the plurality of connectors of the interposer, the circuit substrate being sandwiched between the plurality of conductive terminals and the plurality of connectors.In some embodiments, the method for manufacturing a packaging structure also includes: providing a cover; setting the cover on the circuit substrate, wherein the first semiconductor die, the second semiconductor die and the interposer are located in a space surrounded by the cover and the circuit structure; and setting a thermal adhesive layer between the cover and a surface of the heat dissipation element that is substantially flush with a surface of the insulating enclosure.

[0194] According to some embodiments, a method for manufacturing a packaging structure includes the following steps: providing at least one first semiconductor die and at least one second semiconductor die; setting a dummy element on the surface of the at least one first semiconductor die, the at least one first semiconductor die being located above the dummy element; encapsulating the at least one first semiconductor die, the at least one second semiconductor die and the dummy element in an insulating encapsulation body; flattening the insulating encapsulation body so that the dummy element is exposed on the surface of the insulating encapsulation body; removing the dummy element to form a groove in the insulating encapsulation body; and setting a heat dissipation element on the at least one first semiconductor die and in the groove, wherein the sum of the first thickness of the at least one first semiconductor die and the third thickness of the heat dissipation element is substantially equal to the second thickness of the at least one second semiconductor die.

[0195] In some embodiments, in the method for manufacturing a packaging structure, before removing the dummy element, the method further includes: forming a redistribution wiring structure electrically connected to the at least one first semiconductor die and the at least one second semiconductor die on the insulating encapsulant; and providing a plurality of conductive terminals on the redistribution wiring structure, wherein the redistribution wiring structure is sandwiched between the plurality of conductive terminals and the insulating encapsulant. In some embodiments, in the method for manufacturing a packaging structure, wherein the insulating encapsulant includes a first portion encapsulating the at least one first semiconductor die and the at least one second semiconductor die and a second portion stacked on the first portion, before forming the redistribution wiring structure, the method further includes: providing a connecting element on the at least one first semiconductor die and the at least one second semiconductor die encapsulated in the first portion to electrically connect the at least one first semiconductor die with the at least one second semiconductor die; forming a plurality of conductive pillars on the at least one first semiconductor die and the at least one second semiconductor die; and encapsulating the connecting element and the plurality of conductive pillars in the second portion of the insulating encapsulant, the second portion being located between the first portion and the redistribution wiring structure. In some embodiments, the method for manufacturing a packaging structure also includes: providing an interposer having a plurality of through-holes therein; before setting the dummy element on the at least one first semiconductor die, setting the at least one first semiconductor die and the at least one second semiconductor die on the interposer by flip-chip bonding; after planarizing the insulating encapsulant, patterning the interposer to expose the plurality of through-holes; forming a plurality of connectors on the exposed plurality of through-holes, the interposer being sandwiched between the insulating encapsulant and the plurality of connectors; and bonding the first semiconductor die and the second semiconductor die to a circuit structure having a plurality of conductive terminals through the plurality of connectors of the interposer, the circuit substrate being sandwiched between the plurality of conductive terminals and the plurality of connectors.

[0196] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, comprising: Circuit components; A first semiconductor die and a second semiconductor die are located on the circuit element; a heat sink element connected to the first semiconductor die, the first semiconductor die being located between the circuit element and the heat sink element, wherein a sum of a first thickness of the first semiconductor die and a third thickness of the heat sink element is substantially equal to a second thickness of the second semiconductor die; as well as An insulating encapsulation body encapsulates the first semiconductor die, the second semiconductor die, and the heat dissipation element, wherein a surface of the heat dissipation element is substantially flush with a surface of the insulating encapsulation body. 2 . The package structure of claim 1 , wherein in a cross-sectional view, a sidewall of the heat dissipation element is substantially aligned with a sidewall of the first semiconductor die. 3 . The packaging structure according to claim 1 , wherein the heat dissipation element comprises an adhesive base layer, and a thermal conductivity of the adhesive base layer is greater than a thermal conductivity of the insulating encapsulation body. 4 . The package structure of claim 3 , wherein in a cross-sectional view, there is an offset between a sidewall of the heat dissipation element and a sidewall of the first semiconductor die, and the offset is in a range from 5 μm to 5000 μm.

5. The packaging structure according to claim 1, wherein the heat dissipation element comprises a base layer and an adhesive layer located between the base layer and the first semiconductor die, wherein the thermal conductivity of the base layer is greater than the thermal conductivity of the insulating encapsulant, and the thermal conductivity of the adhesive layer is greater than the thermal conductivity of the insulating encapsulant.

6. The packaging structure according to claim 5, wherein in a cross-sectional view, there is a first offset between the sidewall of the base layer and the sidewall of the adhesive layer, and there is a second offset between the sidewall of the adhesive layer and the sidewall of the first semiconductor die, and the first offset and the second offset are independently in the range from 5 μm to 5000 μm.

7. The package structure according to claim 1, wherein the circuit element is a circuit substrate that is not in contact with the insulating package, and the package structure further comprises: an interposer structure located between and connected to the first semiconductor die and the circuit element; as well as A plurality of conductive terminals are located on the circuit element, and the circuit element is located between the interposer structure and the plurality of conductive terminals.

8. The package structure according to claim 1, wherein the circuit element is a redistribution wiring structure, a portion of the redistribution wiring structure exposed by the first semiconductor die and the second semiconductor die is covered by the insulating encapsulant, and the package structure further comprises: A plurality of conductive terminals are located on the circuit element, and the circuit element is located between the insulating enclosure and the plurality of conductive terminals.

9. The package structure according to claim 1, wherein the circuit element is a redistribution wiring structure, a portion of the redistribution wiring structure exposed by the first semiconductor die and the second semiconductor die is covered by the insulating encapsulant, and the package structure further comprises: A connecting element, comprising a semiconductor substrate and a plurality of through holes penetrating the semiconductor substrate, wherein the connecting element is located on the first semiconductor die and the second semiconductor die, and the first semiconductor die is electrically connected to the second semiconductor die through the connecting element; a plurality of conductive pillars located on and connected to the first semiconductor die and the second semiconductor die and located beside the connecting element; as well as A plurality of conductive terminals are located on the circuit element, and the circuit element is located between the insulating enclosure and the plurality of conductive terminals. The insulating encapsulation body includes a first portion encapsulating the first semiconductor die and the second semiconductor die and a second portion encapsulating the connecting element and the plurality of conductive pillars, wherein the second portion is located between the first portion and the circuit element.

10. A method for manufacturing a packaging structure, comprising: providing a first semiconductor die having a heat sink element attached thereto; providing a second semiconductor die; encapsulating the first semiconductor die, the second semiconductor die and the heat dissipation element in an insulating encapsulation; as well as The insulating encapsulation is planarized so that the insulating encapsulation exposes the heat dissipation element, wherein a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipation element is substantially equal to a second thickness of the second semiconductor die.

11. The method of claim 10, wherein providing the first semiconductor die having the heat sink element attached thereto comprises: Providing a first chip having a circuit system and a second chip including the heat dissipation element; bonding the first wafer to the second wafer to form a stacked structure; as well as The stacked structure is cut into pieces to form the first semiconductor die connected with the heat dissipation element.

12. The method of claim 10, wherein providing the first semiconductor die having the heat sink element attached thereto comprises: providing the first semiconductor die; disposing the first semiconductor die on a circuit element; as well as The heat dissipation element is disposed on the first semiconductor die.

13. The method according to claim 10, further comprising: forming a redistribution wiring structure electrically connected to the first semiconductor die and the second semiconductor die on the insulating encapsulation; as well as A plurality of conductive terminals are disposed on the redistribution line structure, wherein the redistribution line structure is sandwiched between the plurality of conductive terminals and the insulating enclosure.

14. The method of claim 13, wherein the insulating encapsulation comprises a first portion encapsulating the first semiconductor die and the second semiconductor die and a second portion stacked on the first portion, Before forming the redistribution line structure, the method further includes: Disposing a connection element on the first semiconductor die and the second semiconductor die encapsulated in the first portion to electrically connect the first semiconductor die and the second semiconductor die; forming a plurality of conductive pillars on the first semiconductor die and the second semiconductor die; as well as The connecting element and the plurality of conductive posts are enclosed in the second portion of the insulating enclosure, wherein the second portion is located between the first portion and the redistribution wiring structure.

15. The method according to claim 10, further comprising: providing an interposer having a plurality of perforations therein; before encapsulating the first semiconductor die and the second semiconductor die in the insulating encapsulant, disposing the first semiconductor die and the second semiconductor die on the interposer by flip chip bonding; After planarizing the insulating encapsulation, patterning the interposer to reveal the plurality of through-holes; forming a plurality of connectors on the exposed plurality of through holes, wherein the intermediary body is sandwiched between the insulating enclosure and the plurality of connectors; as well as The first semiconductor die and the second semiconductor die are bonded to a circuit structure having a plurality of conductive terminals through the plurality of connectors of the interposer, and the circuit substrate is sandwiched between the plurality of conductive terminals and the plurality of connectors.

16. The method according to claim 15, wherein: Also includes: Provide a cover; Disposing the cover on the circuit substrate, the first semiconductor die, the second semiconductor die and the interposer are located in a space surrounded by the cover and the circuit structure; as well as A thermal adhesive layer is provided between the cover and a surface of the heat dissipating element that is substantially flush with a surface of the insulating enclosure.

17. A method for manufacturing a packaging structure, comprising: providing at least one first semiconductor die and at least one second semiconductor die; providing a dummy element on a surface of the at least one first semiconductor die, the at least one first semiconductor die being located above the dummy element; encapsulating the at least one first semiconductor die, the at least one second semiconductor die, and the dummy element in an insulating encapsulation; planarizing the insulating enclosure so that the dummy element is exposed on the surface of the insulating enclosure; removing the dummy element to form a groove in the insulating enclosure; as well as A heat dissipation element is disposed on the at least one first semiconductor die and in the recess, wherein a sum of a first thickness of the at least one first semiconductor die and a third thickness of the heat dissipation element is substantially equal to a second thickness of the at least one second semiconductor die.

18. The method according to claim 17, before removing the dummy element, further comprising: forming a redistribution wiring structure electrically connected to the at least one first semiconductor die and the at least one second semiconductor die on the insulating encapsulation; as well as A plurality of conductive terminals are disposed on the redistribution line structure, wherein the redistribution line structure is sandwiched between the plurality of conductive terminals and the insulating enclosure.

19. The method of claim 18, wherein the insulating encapsulation comprises a first portion encapsulating the at least one first semiconductor die and the at least one second semiconductor die and a second portion stacked on the first portion, Before forming the redistribution line structure, the method further includes: Disposing connection elements on the at least one first semiconductor die and the at least one second semiconductor die encapsulated in the first portion to electrically connect the at least one first semiconductor die with the at least one second semiconductor die; forming a plurality of conductive pillars on the at least one first semiconductor die and the at least one second semiconductor die; as well as The connecting element and the plurality of conductive posts are enclosed in the second portion of the insulating enclosure, wherein the second portion is located between the first portion and the redistribution wiring structure.

20. The method of claim 17, further comprising: providing an interposer having a plurality of perforations therein; Before disposing the dummy element on the at least one first semiconductor die, disposing the at least one first semiconductor die and the at least one second semiconductor die on the interposer by flip chip bonding; After planarizing the insulating encapsulation, patterning the interposer to reveal the plurality of through-holes; forming a plurality of connectors on the exposed plurality of through holes, wherein the intermediary body is sandwiched between the insulating enclosure and the plurality of connectors; as well as The first semiconductor die and the second semiconductor die are bonded to a circuit structure having a plurality of conductive terminals through the plurality of connectors of the interposer, and the circuit substrate is sandwiched between the plurality of conductive terminals and the plurality of connectors.

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