A semiconductor device and a method of manufacturing the same

Abstract

A semiconductor device includes: a gate structure, source / drain electrodes, a first via hole disposed above the gate structure and the source / drain electrodes, and a first metal line having a higher vertical position than the first via hole in a cross-sectional view. The first via hole is electrically connected to the gate structure and the source / drain electrodes. Both the first metal line and the first via hole extend along a first direction. In a second direction different from the first direction, the metal line is separated from the first via hole by a first distance. The first metal line includes a protruding portion that protrudes outward in the second direction. Embodiments of the present invention also provide a method for manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Background Art

[0002] In deep sub-micron integrated circuit technology, embedded static random access memory (SRAM) devices have become popular memory cells for high-speed communication, image processing, and system-on-chip (SOC) products. The number of embedded SRAMs in microprocessors and SOCs is increasing continuously to meet the performance requirements of each new generation of technology. As silicon technology continues to scale from one generation to the next, parasitic effects may increasingly affect the performance of SRAM devices. For example, as the size of semiconductor components continues to shrink, parasitic resistance may become a greater factor, which may reduce the minimum operating voltage (Vmin) of SRAM cells. This can result in sub-standard SRAM performance and even device failure.

[0003] Therefore, although existing SRAM devices are generally sufficient for their intended purposes, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device, comprising: a gate structure; a source / drain; a first via disposed above the gate structure and the source / drain, wherein the first via is electrically connected to the gate structure and the source / drain; and a first metal line having a higher vertical position than the first via in a cross-sectional view; wherein: both the first metal line and the first via extend in a first direction; in a second direction different from the first direction, the metal line is separated from the first via by a first distance; and the first metal line includes a protruding portion protruding outward in the second direction.

[0005] Another embodiment of the present invention provides a semiconductor device, comprising: a first metal line extending in a first direction in a top view, wherein the first metal line includes a protrusion region; a second metal line extending in the first direction in the top view, wherein the second metal line defines a recessed region, wherein the protrusion region points to the recessed region in a second direction different from the first direction; a third metal line extending in the first direction in the top view and disposed between the first metal line and the second metal line, wherein the geometric profile of the third metal line in the top view is different from that of the first metal line and the second metal line; a first via hole, a second via hole, a third via hole, and a fourth via hole, all extending in the first direction in the top view; wherein: the first via hole and the second via hole are disposed between the first metal line and the third metal line; the third via hole and the fourth via hole are disposed between the second metal line and the third metal line; the first via hole and the second via hole are disposed on opposite sides of the protrusion region; and the third via hole and the fourth via hole are at least partially disposed within the recessed region.

[0006] Yet another embodiment of the present invention provides a method of manufacturing a semiconductor device, comprising: receiving an integrated circuit (IC) layout design including a plurality of metal lines of an interconnect structure, wherein the metal lines each extend in a first direction in a top view; and at least partially modifying the received integrated circuit layout design by at least partially magnifying portions of at least a subset of the metal lines in a second direction different from the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to standard practice in the industry, the various components are not drawn to scale. In fact, for clarity, the dimensions of the various components may be increased or decreased arbitrarily. It should also be emphasized that the accompanying drawings only show typical embodiments of the present invention and should not be regarded as limiting the scope of the present invention, since the present invention can be equally well applied to other embodiments.

[0008] Figure 1 A circuit schematic diagram of a 1-bit SRAM cell according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A three-dimensional perspective view of a FinFET device according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A top view layout of a part of an SRAM cell array according to an embodiment of the present disclosure is shown.

[0011] Figure 4Shows a top - view layout of another part of the SRAM cell array according to an embodiment of the present disclosure.

[0012] Figure 5 Shows a top - view layout of yet another part of the SRAM cell array according to an embodiment of the present disclosure.

[0013] Figure 6 Shows a cross - sectional side view of a part of the SRAM cell array according to an embodiment of the present disclosure.

[0014] Figure 7 Shows a cross - sectional side view of another part of the SRAM cell array according to an embodiment of the present disclosure.

[0015] Figure 8 Shows a graph of voltage versus resistance according to an embodiment of the present disclosure.

[0016] Figure 9 Shows an integrated circuit manufacturing system according to an embodiment of the present disclosure.

[0017] Figure 10 Is a flowchart showing a method of manufacturing an SRAN device according to an embodiment of the present disclosure. Detailed Description

[0018] The following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component, such that the first component and the second component are not in direct contact. Additionally, the present invention may repeat reference numerals and / or characters in various embodiments. The repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0019] Furthermore, spatial relative terms, such as "below", "beneath", "lower", "above", "upper", etc., are used to facilitate the description of the relationship between one component and another in the drawings. In addition to the orientation shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0020] In addition, when a value or a range of values is described using terms such as "about" or "approximate", such term is intended to cover values within a reasonable range including the recited value, such as within a range of + / - 10% of the recited value or other values understood by those skilled in the art. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0021] The present disclosure is directed to, but not limited to, static random access memory (SRAM) devices. An SRAM device is a semiconductor memory that uses bistable latch circuits (e.g., flip - flops) to store binary bits of information. Figure 1 An exemplary circuit schematic of a single - port SRAM cell (e.g., a 1 - bit SRAM cell) 5 is shown. The single - port SRAM cell 5 includes pull - up transistors PU1, PU2; and pull - down transistors PD1, PD2; and transmission gate transistors PG1, PG2. As shown in the circuit diagram, the transistors PU1 and PU2 are p - type transistors, such as the p - type FinFETs discussed above, while the transistors PG1, PG2, PD1, and PD2 are the n - type FinFETs discussed above. Since the SRAM cell 5 includes six transistors in the illustrated embodiment, it may also be referred to as a 6T SRAM cell.

[0022] The drains of the pull - up transistor PU1 and the pull - down transistor PD1 are connected together, and the drains of the pull - up transistor PU2 and the pull - down transistor PD2 are connected together. The transistors PU1 and PD1 are cross - connected with the transistors PU2 and PD2 to form a first data latch. The gates of the transistors PU2 and PD2 are connected together and are connected to the drains of the transistors PU1 and PD1 to form a first storage node SN1, and the gates of the transistors PU1 and PD1 are connected together and are connected to the drains of the transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull - up transistors PU1 and PU2 are connected to a power supply voltage Vcc (also referred to as Vdd), and the sources of the pull - down transistors PD1 and PD2 are connected to a voltage Vss, which may be electrically grounded in some embodiments.

[0023] The first storage node SN1 of the first data latch is connected to a bit line BL through a transmission gate transistor PG1, and the complementary first storage node SNB1 is connected to a complementary bit line BLB through a transmission gate transistor PG2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes that are typically at opposite logic levels (logic high or logic low). The gates of the transmission gate transistors PG1 and PG2 are connected to a word line WL.

[0024] SRAM devices such as SRAM cell 5 can be implemented using "planar" transistor devices and / or by leveraging FinFET devices. In this regard, a FinFET device is a fin field-effect transistor device that has recently become increasingly popular in the semiconductor industry. Compared to traditional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (such as "planar" transistor devices), FinFET devices have several advantages. These advantages may include better chip area efficiency, higher carrier mobility, and a manufacturing process that is compatible with the manufacturing process of planar devices. Therefore, it is desirable to design an integrated circuit (IC) chip that uses FinFET devices for a portion or the entire IC chip.

[0025] A FinFET device can be a complementary metal-oxide-semiconductor (CMOS) device, including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. It should be understood that FinFET devices can be used as examples to discuss some of the aspects disclosed below, but it should be understood that this application is not limited to FinFET devices, except as specifically claimed.

[0026] Referring Figure 2 , a perspective view of an exemplary FinFET device 10 is shown. The FinFET device structure 10 includes an N-type FinFET device structure (NMOS) 15 and a P-type FinFET device structure (PMOS) 25. The FinFET device structure 10 includes a substrate 102. The substrate 102 can be made of silicon or other semiconductor materials. Optionally or additionally, the substrate 102 can include other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor, such as silicon germanium, silicon carbide germanium, gallium phosphide arsenide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 can include an epitaxial layer overlying a bulk semiconductor.

[0027] The FinFET device structure 10 further includes one or more fin structures 104 (e.g., Si fins) that extend from the substrate 102 in the Z direction and are surrounded by spacers 105 in the Y direction. The fin structures 104 are elongated in the X direction and may optionally include germanium (Ge). The fin structures 104 can be formed by using suitable processes such as lithography and etching processes. In some embodiments, the fin structures 104 are etched from the substrate 102 using a dry etching or plasma process. In some other embodiments, the fin structures 104 can be formed by a multiple-patterning lithography process (e.g., a double-patterning lithography (DPL) process). DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows for increased component (e.g., fin) density. The fin structures 104 further include epitaxial growth material 12, which (along with portions of the fin structures 104) can be used as the source / drain of the FinFET device structure 10.

[0028] An isolation structure 108, such as a shallow trench isolation (STI) structure, is formed to surround the fin structures 104. As Figure 2 shown, in some embodiments, the lower portion of the fin structures 104 is surrounded by the isolation structure 108, and the upper portion of the fin structures 104 protrudes from the isolation structure 108. In other words, a portion of the fin structures 104 is embedded in the isolation structure 108. The isolation structure 108 prevents electrical interference or crosstalk.

[0029] The FinFET device structure 10 further includes a gate stack structure that includes a gate electrode 110 and a gate dielectric layer (not shown) below the gate electrode 110. The gate electrode 110 can include polysilicon or metal. Metals include tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials. The gate electrode 110 can be formed in a back-gate process (or gate replacement process). Hard mask layers 112 and 114 can be used to define the gate electrode 110. A dielectric layer 115 can also be formed on the sidewalls of the gate electrode 110 and above the hard mask layers 112 and 114. In at least one embodiment, the dielectric layer 115 is in direct contact with the gate electrode 110.

[0030] The gate dielectric layer (not shown) can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-k), or a combination thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, etc., or a combination thereof.

[0031] In some embodiments, the gate stack structure includes additional layers, such as an interface layer, a capping layer, a diffusion / barrier layer, or other suitable layers. In some embodiments, the gate stack structure is formed over the central portion of the fin structure 104. In some other embodiments, multiple gate stack structures are formed over the fin structure 104. In some other embodiments, the gate stack structure includes a dummy gate stack and is replaced by a metal gate (MG) after performing a high thermal budget process.

[0032] The gate stack structure is formed by a deposition process, a lithography process, and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metalorganic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods, and / or combinations thereof. The lithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Optionally, the lithography process can be implemented or replaced by other suitable methods, such as maskless lithography, electron beam writing, and ion beam writing.

[0033] Figure 3 A top view of a portion of an SRAM cell array 200 implemented using FinFETs according to an embodiment of the present disclosure is shown. Figure 3 The top view is defined by the X-axis (only spanning the Figure 2 X-direction of Figure 2 ), and the Y-axis (only spanning the Figure 3 Y-direction of Figure 3 ). Note that the X-axis is the

[0034] The SRAM cell array 200 includes a plurality of SRAM cells, e.g., SRAM cells such as Figure 1 SRAM cell 5 (e.g., a 6T SRAM cell). The SRAM cell array 200 includes an N-doped region 202 (or N-well) and a P-doped region 204 (or P-well). In the N-doped region 202 and the P-doped region 204, the SRAM cell array 200 includes a plurality of fin lines 210, each fin line extending in an elongated manner in the X-direction. The fin lines 210 can be implemented using Figure 2 the fin structure 104 of Figure 2 The SRAM cell array 200 further includes a plurality of gate structures 220, which can be implemented by Figure 2In the top view, the gate structure 220 is shown as extending in the Y direction perpendicular to the X direction, where the fin line 210 extends in the X direction. The fin line 210 and the gate structure 220 form a transistor. For example, in an embodiment, the pull-up (PU) transistor of the SRAM cell 5 is formed by a transistor in the N-doped region, and the pull-down (PD) transistor and the pass gate (PG) transistor are formed by transistors in the P-doped region.

[0035] Figure 4 Another top view of another portion of the SRAM cell array 200 (e.g., Figure 3 the SRAM cell array of, which is composed of Figure 1 the 6T SRAM cells shown) is shown. Note that the top view may correspond to an ideal top view of the SRAM cell array 200. For example, Figure 4 the various components shown may have straight edges or be shaped as rectangles or polygons. In an actual manufactured device, Figure 4 the components in may have more rounded, curved, or other non-straight edges. In some embodiments, Figure 4 the top view of may correspond to the top view of the pattern on one or more photomasks used to form the SRAM cell array 200, because the pattern on the photolithography mask does have more straight edges and is more similar to a rectangle or polygon than the pattern on an actual manufactured device.

[0036] Figure 4 A portion of the SRAM cell array 200 shown includes multiple wires, such as the metal lines 310 - 313 and 320 - 332 of the metal-0 interconnect layer (also referred to as the M0 layer) of a multilayer interconnect (MLI) structure. In this regard, the MLI structure may be formed above the substrate and may include multiple patterned dielectric layers and conductive layers that provide interconnections (e.g., wiring) between various microelectronic components of a semiconductor device (e.g., the SRAM cell array 200). For example, the MLI structure may include multiple conductive components, such as contacts, vias, or metal lines. The metal lines may be disposed in multiple metal layers stacked perpendicular to each other, and the vias are used to electrically interconnect the metal lines from different layers together. The contacts and vias may also provide electrical connections to transistor components (such as gates, sources, and / or drains). The conductive components may comprise conductive materials such as aluminum, aluminum / silicon / copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof. Optionally, the conductive components may include copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof.

[0037] The MLI structure may further include an interlayer dielectric (ILD) surrounding the conductive component. The ILD can provide electrical isolation for the conductive component. In some embodiments, the ILD may include a low-k dielectric material (e.g., a dielectric material having a dielectric constant less than that of silicon dioxide (about 4)). As a non-limiting example, the low-k dielectric material may include a porous organosilicate film such as SiOCH, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon carbonitride (SiCN), silicon oxynitride (SiOCN), spin-on organic polymer dielectrics, spin-on silicon-based polymer dielectrics, or combinations thereof.

[0038] As Figure 4 shown, the metal lines 310-313 and 320-332 each extend in an elongated manner in the X direction. In some embodiments, the metal lines 310-313 are each a bit line (BL) or an anti-phase line (BLB) of the SRAM cell array 200 (see Figure 1 ). For example, the metal lines 310 and 313 may each be a BL, and the metal lines 311-312 may each be a BLB. Optionally, the metal lines 310 and 313 may each be a BLB, and the metal lines 311-312 may each be a BL. For simplicity, the metal lines 310-313 will hereinafter be interchangeably referred to as BL 310-313 (even if some of them are BLBs).

[0039] In some embodiments of the SRAM cell array 200, in a top view, the BLs 310-313 each continuously extend through a plurality of SRAM cells. For example, in a top view, each of the BLs 310-313 may extend in the X direction through the entire SRAM cell array 200. As electrical conductors, ideally, the BLs 310-313 should have substantially zero resistance. However, in real-world devices, each of the BLs 310-313 may generate a parasitic resistance that is a function of its dimensions (e.g., both the length in the X direction and the width in the Y direction). For example, as the width of the BL (e.g., the lateral dimension measured along the Y direction) decreases, the parasitic resistance may increase. In older technologies greater than the 5-nanometer technology generation, since the dimensions of the BLs may be large enough, this parasitic resistance can be negligible.

[0040] However, as the device scaling trend continues to reduce the size of microelectronic components (e.g., including the size of BLs 310 - 313), the resistance may increase to a level that is no longer negligible, which may significantly degrade the performance of semiconductor devices. For example, according to Ohm's law, the voltage drop across the length of a resistor is equal to the current flowing through the resistor multiplied by the resistance of the resistor. This relationship between voltage and resistance can be expressed by the mathematical formula V = I * R, where V represents voltage, I represents current, and R represents resistance. In the current case, each of the BLs 310 - 313 can be modeled as a resistor (due to its parasitic resistance). Thus, each BL in the BLs 310 - 313 can experience a voltage drop along its length (in the X direction) during the operation of the SRAM cell array 200. This voltage drop may degrade certain SRAM operating parameters or criteria, such as the minimum operating voltage (hereinafter referred to as Vmin). In some cases, the decrease in Vmin can be in the range of about 5 millivolts (mV) to about 200 mV. If Vmin is not met, the SRAM cells may experience read failures, write failures, access failures, and / or retention failures. To exacerbate the problem, the device scaling process may also be accompanied by a need to scale down the SRAM supply voltage (e.g., Vdd). Since Vmin can be related to the supply voltage, the scaling down of the supply voltage can further reduce the error margin (or the amount of decrease) that Vmin may experience.

[0041] The present disclosure alleviates the Vmin decrease problem by selectively increasing the BLs 310 - 313, thereby reducing their resistance. As a result, the BLs 310 - 313 each have a top - view profile that is not completely linear but serrated. For example, each of the BLs 310 - 313 includes one or more protrusions that protrude laterally in the Y direction. In contrast, such lateral protrusions do not exist in the metal lines 320 - 332. The serrated shape of the BLs 310 - 313 (or alternatively, the presence of their lateral protrusions) is one of the unique physical characteristics of the SRAM cell array 200 of the present disclosure and will be discussed in more detail below..

[0042] Still referring to Figure 4 , the metal lines 324 and 328 also each extend in an elongated manner in the X direction. In some embodiments, the metal lines 324 and 328 are each the Vcc of the SRAM cell array 200 (see Figure 1 ). The metal lines 324 and 328 can also be narrower in the Y direction than each of the BLs 310 - 313. As Figure 4As shown, BL 310-313 may have a minimum lateral dimension of 350 in the Y direction (measured at its thinnest part), and the metal lines 324 and 328 may each have a minimum lateral dimension of 351 in the Y direction. The lateral dimension 350 is substantially greater than the lateral dimension 351, for example at least 50% greater in some embodiments. The difference between the dimensions 350 and 351 may be due to the fact that they are configured to allow for different voltages or currents. The wider BL 310-313 results in a reduced resistance, which enables them to handle greater voltages or currents.

[0043] Although BL 310-313 and the metal lines 324 and 328 are continuous, they continue to extend in the X direction beyond Figure 4 the range shown (since Figure 4 it is only a partial view of a part of the SRAM cell array), and due to the fact that the metal lines 320-323, 325-327, and 329-332 are separated from each other in the X direction, the metal lines 320-323, 325-327, and 329-332 are discontinuous metal "islands". In some embodiments, the metal lines 320-323, 325-327, and 329-33 are metallization components for the WL or Vss of the SRAM cell array 200 (see Figure 1 ). In other words, the metal lines 320-323, 325-327, and 329-332 are electrically connected to the WL or Vss, where the WL or Vss can be implemented as metal lines in a separate metal layer (e.g., a metal 1 layer above a metal 0 layer) of the MLI structure.

[0044] The SRAM cell array 200 also includes a plurality of conductive vias, such as Figure 4 the vias 370-377 shown in Figure 3 (hereinafter also referred to as vias). Each of the vias 370-377 extends in an elongated manner in the X direction and can be configured to electrically connect a gate structure (e.g., Figure 5 one of the gate structures 220 in Figure 6 ) to a source / drain. This is shown more clearly in Figure 5 . In this regard, Figure 4 is a partial top view schematic of a part of a semiconductor device (e.g., a part of the SRAM cell array 200) that includes some vias, such as vias 370 and 372. Note that compared with Figure 5 , the X direction and the Y direction in Figure 6 are rotated 90 degrees respectively. Figure 5 is a partial cross-sectional side view taken along the cutting line A-A' extending in the X-direction in Figure 6The cross-sectional view therein is obtained by taking a cross-section along the XZ plane defined by the X direction (horizontal) and the Z direction (vertical).

[0045] As Figures 5 to 6 shown, each gate structure 220 is formed to extend in an elongated manner in the Y direction and is formed above the fin structure 210 in the Z direction (see Figure 6 ). The gate structure 220 also partially wraps around the fin structure 210 in the manner shown in Figure 2 , although since this is a cross-sectional view, this aspect may not be easily visible in Figure 6 . In other words, Figure 6 shows a part of the cross-section in which the gate structure 220 is located above the fin structure 210. Each gate structure 220 may include a high-k gate dielectric and a metal gate electrode. In other words, each gate structure 220 may be an HKMG structure.

[0046] A gate via 380 is formed above one gate structure 220 in the Z direction, and a gate via 382 is formed above another gate structure 220 in the Z direction. Each of the gate vias 380 and 382 contains a conductive material (e.g., a metal or a metal compound) and provides electrical connectivity to their respective gate structures 220. At the same time, source / drain vias 390 - 397 are each formed on a part of the fin structure 210 along the Z direction, e.g., above the source / drain part of the fin structure 210. Each of the source / drain vias 390 - 397 also contains a conductive material (e.g., a metal or a metal compound) and provides electrical connectivity to their respective source / drains. The source / drain vias 390 - 397 may also be referred to as source / drain contacts or diffusion contacts. Note that since Figure 6 's cross-section is taken along the cut line A - A' (on a part of the source / drain via 390), the source / drain via 390 is visible in the cross-sectional view of Figure 6 , however, the remaining vias 391 - 397 are not easily visible in Figure 6 . In the illustrated embodiment, in a top view, the via 370 is larger than the gate via 380 because the via 370 is connected to both the gate structure 220 and the source / drain via 390, while the gate via 380 only needs to be connected to the gate structure 220.

[0047] As Figure 6As shown, in the Z direction, a via 370 is formed above the gate via 380 and the source / drain via 390. Since one end of the via 370 is formed above the gate via 380 and is electrically connected to the gate via 380, and the other end of the via 370 is formed above the source / drain via 390 and is electrically connected to the source / drain via 390, the via 370 horizontally spans in the X direction and electrically connects the gate via 380 and the source / drain via 390 together. It should be understood that although Figures 5 to 6 the gate via 380 and the via 370 are shown and labeled as two separate components, this may not necessarily be the case. For example, in some embodiments, the vias for the gate via 380 and the via 370 can be formed simultaneously (or using the same process), and then a conductive material is formed to fill these vias simultaneously. In these embodiments, the gate via 380 and the via 370 can include the same material and can be regarded as the same structure (e.g., the same via), and there may be no distinct interface between the gate via 380 and the via 370. However, in other embodiments, the gate via 380 and the via 370 can indeed be formed separately and / or can include different materials. In any case, since the gate via 380 and the source / drain via 390 respectively provide electrical connectivity to the gate structure 220 and the source / drain (e.g., a part of the fin structure 210), the via 370 can establish an electrical connection between the gate and the source / drain of the transistor.

[0048] Similarly, as Figure 6 shown, an electrical isolation structure 400 can be formed around the via 370 and the gate via 380 and the source / drain via 390 to provide electrical isolation from other microelectronic components. In some embodiments, the electrical isolation structure 400 can include an interlayer dielectric (ILD) structure, which can contain a low-k material as a non-limiting example.

[0049] Figure 7 Another partial schematic cross-sectional side view of a part of the semiconductor device (e.g., a part of the SRAM cell array 200) is shown to further illustrate the position of the via relative to the metal line. Figure 7 The cross-sectional view in Figure 4 is obtained by taking a cross-section along the cutting line B-B' in the Y direction. In other words, Figure 7 the cross-sectional view in Figure 7 is taken in a plane defined by the Y direction (horizontal) and the Z direction (vertical). Thus, Figure 6 the cross-sectional view of

[0050] is perpendicular or orthogonal to the cross-sectional view of Figure 7As shown, via holes 370 and 372 are respectively disposed above source / drain via holes 390 and 391 in the Z direction (and are electrically connected to the source / drain via holes 390 and 391). The metal 0 layer has a position that rises more vertically than via holes 370 and 372 in the Z direction. For example, BLs 310 - 311 and metal line 324 are disposed on via holes 370 and 372 (e.g., more vertically raised), but are not electrically connected to via holes 370 and 372. This is because the SRAM design rules can specify that the via holes should be electrically isolated from BLs 310 - 311 to prevent undesired bridging (e.g., electrical short circuit) between them. As shown in the figure. As Figure 4 and Figure 7 shown, BL 310 is separated from via hole 370 by a distance 450 in the Y direction, and BL 311 is separated from via hole 372 by a distance 460 in the Y direction. The value of distance 450 and the value of distance 460 may be substantially equal to each other in some embodiments, or they may be different from each other in other embodiments.

[0051] Referring again to Figure 4 , one of the unique and novel physical features of the present disclosure is that the top - view profiles of BLs 310 - 313 are substantially different from those of metal lines 320 - 332. For example, the edges of the boundaries of each of BLs 310 - 313 are non - linear, such that each of them includes a plurality of lateral protrusions in the Y direction. In contrast, metal lines 320 - 332 substantially do not have lateral protrusions. In other words, although metal lines 320 - 332 ideally (or on a photolithography mask) have a substantially linear top - view profile, BLs 310 - 313 have a serrated top - view profile.

[0052] For example, as Figure 4 shown, BL 310 may include protrusions 500A and 500B, while BL 311 may include protrusion 501. Protrusions 500A and 500B protrude laterally towards BL 311 (or towards metal line 324), and protrusion 501 protrudes laterally towards BL 310 (or towards metal line 324). Although only one protrusion 501 for BL 311 is shown in Figure 4 , it can be understood that BL 311 may include a plurality of protrusions similar to protrusion 501. Similar to how protrusions 500A and 500B are arranged relative to each other, these additional protrusions may be arranged relative to protrusion 501. For space considerations, these additional protrusions are not specifically shown in Figure 4 (because Figure 4 shows a partial top - view of the SRAM cell array 200).

[0053] In some embodiments, BL 310 and BL 311 may be mirror images of each other (e.g., flipped 180 degrees with respect to the metal line 324), but they are also offset from each other in the X direction. In other words, the protrusion 501 of BL 311 may be substantially the same as the protrusion 500A, but is further "downward" shifted in the X direction. BL 311 may have another protrusion that is substantially the same as the protrusion 500B, but this protrusion is further "downward" positioned in the X direction from the protrusion 501 and is thus Figure 4 invisible. It should be understood that both BL 310 and BL 311 may have multiple other protrusions that periodically repeat themselves, similar to the way the protrusions 500A and 500B are shown Figure 4 in how they are spaced apart from each other.

[0054] Another way to view the protrusions 500A - 500B and 501 is to say that BL 310 - 311 has convex and / or concave regions (or convex polygons and / or concave polygons), although these convex and / or concave regions do not need to be curved or rounded (e.g., they may or may not have substantially straight or linear edges or boundaries). For example, as Figure 4 shown, since the protrusion 501 of BL 311 protrudes outward (towards the metal line 324) in the -Y direction, the protrusion 501 of BL 311 can be regarded as a convex region of BL 311. The protrusion 501 of BL 311 protrudes Figure 4 outward as a rectangular protrusion. Another way to express the protrusion 501 is to say that Figure 4 a part of BL 311 shown has a rotated "T-shaped" top view profile. For example, when BL311 is rotated counterclockwise by 90 degrees, Figure 4 the top view of a part of BL 311 in

[0055] may be similar to the letter "T". Conversely, the protrusions 500A and 500B of BL310 and the remaining part of BL 310 that does not protrude outward together define a concave region 520. The concave region 520 may also be referred to as a groove, such as a rectangular groove. Since BL 310 - 311 are each continuous in the X direction, it can be said that BL 310 - 311 may each have multiple convex regions (or multiple lateral protrusions) interspersed with multiple concave regions (or multiple lateral grooves), and vice versa.

[0056] One reason for configuring BL 310-313 to have such an irregular top-view shape as described above is to reduce the resistance of BL 310-313. In previous and older semiconductor technology nodes (e.g., nodes greater than 5 nanometers), device sizes were larger, and thus, device parasitic effects (e.g., parasitic resistance) were not as big of a problem. For example, the BL corresponding to BL 310 in an older technology generation may have had a substantially larger size in the Y direction, or in other words, be "wider / thicker" than BL 310. Since resistance is negatively correlated with the width of a metal wire, the resistance of the BL for SRAM devices in the earlier technology may have been small enough that it did not have an adverse effect on device performance and could thus be ignored.

[0057] However, in newer technology nodes such as the 5-nanometer node or beyond (e.g., the 3-nanometer node), device sizes are scaled down to the extent that device parasitic effects may substantially degrade device performance. For example, the lateral dimension 350 of BL 310 can be small enough to increase the parasitic resistance of BL 310 to the extent that the voltage drop across the length (in the X direction) of BL 310 can no longer be ignored. The fact that BL310-313 extends continuously across many cells of the SRAM cell array 200 in the X direction exacerbates this situation. Since the longer BL 310-313 is, the greater the parasitic resistance is, the more distant cells at the far end of the SRAM cell array will experience the largest unintentional (and undesired) voltage drop because they experience the largest parasitic resistance. For example, the voltage drop across the entire length of BL 310-313 may deteriorate Vmin of the SRAM cell. Vmin may be the lowest voltage at which an SRAM cell can be read. However, the voltage drop due to the parasitic resistance across the entire length of BL 310 may cause Vmin to be too high, which may cause the transistors of the SRAM cell not to conduct (and thus the SRAM cannot be read).

[0058] The present disclosure achieves a reduction in the resistance of BL 310-313 by selectively increasing BL 310-311 in the Y direction when appropriate. For example, the protrusions 500A-500B and 501 can be regarded as a lateral magnification of BL310-311. These protrusions 500A-500B and 501 project laterally into the space between BL 310-311 and the metal wire 324 without being electrically shorted to the metal wire 324 or the vias 370-373. For example, since the vias 372 and 373 are disposed on opposite sides of the protrusion 501, the protrusion 501 projects into the region between the vias 372 and 373 without physically contacting the metal wire 324 or the vias 372 and 373. Similarly, in a top view, the protrusion 500A projects into the region between the via 370 and another via ( Figure 4 invisible inFigure 4 invisible), and in the top view, the protrusion 500B protrudes into the region between the through-hole 371 and another through-hole "below" the through-hole 371 (in Figure 4 invisible), without physically contacting the metal wire 324 or the through-holes 370-371. The through-holes 370 and 371 are at least partially located within the concave region 520 defined in part by the protrusions 500A-500B. Since the protrusion 501 is provided between the through-holes 370-371, but no part of the BL 310 is provided between the through-holes 370-371, the distance separating the through-holes 370-371 in the X direction is smaller than the distance separating the VDR through-holes 372-373 in the X direction

[0059] According to the present disclosure, a set of design rules are implemented regarding the dimensions and / or positions of the lateral protrusions 500A - 500B and 501 such that they can reduce the resistance of BL 310 - 311 without creating a dangerous electrical bridging problem. For example, each of the protrusions 500A - 500B has a dimension 420 measured in the Y direction, and the protrusion 501 has a dimension 430 measured in the Y direction. In some embodiments, in the Y direction, the dimension 430 varies within a range between 0% and 100% of the width of BL 311. In some embodiments, the dimensions 420 and 430 are equal to each other. In other words, the amount of protrusion exhibited by BL 311 is substantially equal to the amount of indentation defined by BL 310. According to one design rule, 0 < dimension 420 (or dimension 430) < N * distance 450. In some embodiments, N ranges between 0 and 2. Another design rule stipulates that a distance 470 should be maintained in the X direction between a via (e.g., via 370) and the nearest protrusion of the BL (e.g., protrusion 500A). In some embodiments, the distance 470 is substantially equal to the distance 450. Thus, the design rule 0 < dimension 420 (or dimension 430) < N * distance 470 can also hold. In some embodiments, the distance 450 and / or the distance 470 are configured to meet the minimum pitch design rule for a given technology node. For example, the distance 450 can be configured to be long enough such that BL 310 does not have a significant risk of electrical short - circuiting with the via 370 in the Y direction, and the distance 470 can be configured to be long enough such that BL 310 is electrically short - circuited with the Y - shaped via 370. The protrusion portion 500A of BL 310 does not have a significant risk of electrical short - circuiting with the via 370 in the X direction. Another design rule stipulates that a distance 480 should be maintained in the Y direction between the protrusions 500A - 500B and the metal line 324. In some embodiments, the distance 480 is also configured to meet the minimum pitch design rule for a given technology node. For example, the distance 480 can be configured to be long enough such that the protrusion portion 500A or 500B of BL310 does not have a significant risk of electrical short - circuiting with the metal line 324 in the Y direction. In some embodiments, the distance 480 = N * distance 450, where N ranges between 0 and 3. These design rules help ensure that the protrusions 500A - 500B and 501 can extend as far as possible in the Y direction without unduly increasing the risk of electrical short - circuiting with the nearby vias 370 - 373 or with the metal line 324.

[0060] In some embodiments, newer lithography methods such as extreme ultraviolet (EUV) lithography can be used to define the shape of BLs 310-313 (e.g., the dimensions, positions, and profiles of their lateral protrusions) with sufficient precision. Details regarding EUV lithography are discussed in U.S. Patent Application No. 15 / 851,829, filed on Dec. 22, 2017, entitled “Lithography Mask Having a Black Border Region and Method of Manufacturing the Same,” the entire disclosure of which is incorporated herein by reference. By using EUV lithography, the present disclosure can selectively expand the BLs 310-313 in place without the risk of electrical bridging to nearby components.

[0061] It should be understood that although the present disclosure herein has used BLs as exemplary metal lines where selective expansion can achieve reduced resistance (thereby improving parameters such as Vmin), the concepts discussed above can be applied to metal lines of other types of SRAM devices. For example, word lines (WLs) can be implemented as metal lines in a metal 1 layer located above the metal 0 layer in the Z direction. The WLs can be selectively expanded in a manner similar to selectively expanding the BLs 310-313 (e.g., lateral protrusions), and thus the WLs in the SRAM device can also achieve reduced resistance, thereby improving the device performance of the SRAM.

[0062] Figure 8 FIG. 600 is a graph showing how Vmin varies according to the resistance. In graph 600, the X-axis represents the resistance value of the BLs 310-313, and the Y-axis represents the value of Vmin, e.g., as a percentage of Vdd. Graph 600 shows a curve 620, which may include a plurality of data points, such as data points 640, 641, and 642. Each data point 640-642 corresponds to a data sample collected from an actually manufactured SRAM device, where the resistance values are different from each other. As Figure 8 shown, as the resistance decreases (e.g., from data point 642 to data point 641), the corresponding Vmin also decreases, which translates to an improvement in the SRAM device performance. This reduction in the resistance of the BL can be achieved by implementing various aspects of the present disclosure discussed above. Experimental data shows that by selectively expanding the BLs 310-313, the total area of the BL can be increased by approximately 15%-25%. The increase in the area of the BL can lead to a reduction in the resistance of the BL, which results in a reduction in Vmin of more than at least 1% of Vdd.

[0063] Figure 9FIG. 700 shows an integrated circuit manufacturing system according to an embodiment of the present disclosure. The manufacturing system 700 includes a plurality of entities 702, 704, 706, 708, 710, 712, 714, 716…, N connected via a communication network 718. The network 718 can be a single network or can be various different networks (such as an intranet and the Internet) and may simultaneously include wired and wireless communication channels.

[0064] In one embodiment, entity 702 represents a service system for manufacturing collaboration; entity 704 represents a user, such as a product engineer monitoring a product of interest; entity 706 represents an engineer, such as a process engineer controlling a process and related recipes, or an equipment engineer monitoring or adjusting the conditions and settings of a processing tool; entity 708 represents a metrology tool for IC testing and measurement; entity 710 represents a semiconductor processing tool, such as an EUV tool for implementing a lithography process to define the irregularly shaped metal wires of an SRAM device; entity 712 represents a virtual metrology module associated with the processing tool 710; entity 714 represents an improved process control module associated with the processing tool 710 and additional other processing tools; and entity 716 represents a sampling module associated with the processing tool 710.

[0065] Each entity can interact with other entities and can provide integrated circuit manufacturing, process control, and / or computing capabilities to other entities, and / or receive such capabilities from other entities. Each entity can also include one or more computer systems for implementing computing and performing automation. For example, the improved process control module of entity 714 can include a plurality of computer hardwares encoded with software instructions. The computer hardwares can include a hard disk drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), and input / output devices (e.g., a mouse and a keyboard). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0066] The integrated circuit manufacturing system 700 enables interaction between entities for the purpose of integrated circuit (IC) manufacturing and improved process control of IC manufacturing. In an embodiment, the improved process control includes adjusting the process conditions, settings, and / or recipes of a processing tool applicable to a relevant wafer according to metrology results.

[0067] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0068] One of the capabilities provided by the IC manufacturing system 700 enables collaboration and information access in areas such as design, engineering and processing, metrology, and improving process control. Another capability provided by the IC manufacturing system 700 integrates systems between facilities (such as between metrology tools and processing tools). This integration enables the facilities to coordinate their activities. For example, integrating metrology tools and processing tools can enable manufacturing information to be more effectively incorporated into the manufacturing process or APC module, and in-situ measurement of wafer data can be achieved through metrology tools integrated in the relevant processing tools.

[0069] Figure 10 is a flowchart showing a method 900 according to an embodiment of the present disclosure. Method 900 includes step 910 of receiving an integrated circuit (IC) layout design including multiple metal lines of an interconnect structure. For example, the IC layout design can be received from a fabless IC design house. In some embodiments, the IC layout design can be a computer file in Graphic Data System (GDS) format. In a top view, each metal line extends in a first direction. In some embodiments, the received IC layout design includes an IC layout design for a static random access memory (SRAM) device, the SRAM including multiple bit lines and multiple anti-phase lines. In some embodiments, the received IC layout design includes multiple vias disposed between the multiple metal lines in a top view.

[0070] Method 900 includes step 920 of modifying the received IC layout design by at least partially magnifying a portion of at least a subset of the metal lines in a second direction different from the first direction.

[0071] Method 900 includes step 930 of facilitating the manufacture of semiconductor devices based on the modified IC layout design. In some embodiments, facilitating the manufacture includes performing an extreme ultraviolet (EUV) process to form a subset of the metal lines. In some embodiments, modifying the received IC layout design includes magnifying the bit lines. In some embodiments, magnifying includes magnifying the portion into the space between the metal lines not occupied by any vias.

[0072] It should be understood that additional processes can be performed before, during, or after steps 910 - 930 of method 900. For example, method 900 can include forming active regions, fin structures, gate structures, source / drain regions, interconnect structures, and packaging, dicing, and testing processes. For simplicity, other additional steps are not discussed in detail here.

[0073] Based on the above discussion, it can be seen that the present disclosure describes a solution that addresses the problem of performance degradation caused by the increasing effect of parasitic resistance due to the shrinking of device dimensions. For example, as the dimensions of SRAM devices shrink, the BL (as a metal wire in a metal interconnect layer) may see its resistance increase to an extent that has a non-negligible impact on the voltage drop. As a result, voltage performance such as Vmin may degrade. The present disclosure solves this problem by selectively expanding the BL in appropriate places, such as by modifying the IC layout so that the BL can have a lateral protrusion (or a zigzag top-view shape). The lateral protrusion can be arranged in the top view in a manner that protrudes between certain vias. Design rules are also implemented to configure the size and / or position of the lateral protrusion. The presence of the zigzag top-view profile or the lateral protrusion of the BL may be a unique physical characteristic of SRAM devices that undergo the above manufacturing process. They may also be unique physical characteristics of the lithography mask used to pattern the BL.

[0074] Based on the above discussion, it can be seen that the present disclosure provides advantages over conventional SRAM devices. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and specific advantages are not required for all embodiments. One advantage is the improvement in Vmin due to the reduced resistance. Since the resistance of a metal wire such as the BL is negatively correlated with the area of the metal wire, the selective expansion of a metal wire such as the BL effectively increases the area of the metal wire. Therefore, the resistance of the metal wire can be reduced, which in turn reduces the voltage drop across the length of the metal wire and improves the Vmin performance of the SRAM. Another advantage is that the present disclosure does not overly increase the risk of electrical bridging. For example, the lateral protrusions of the BL are carefully set according to various design rules so as to be sufficiently separated from nearby conductive components such as vias or other metal wires. Therefore, even though the total area of the BL is expanded, the bridging risk can still be negligible. Other advantages include compatibility with existing SRAM designs and manufacturing, so the present disclosure does not require additional processing and is thus easy to implement and inexpensive.

[0075] The improved lithography processes, methods, and materials described above can be used in many applications, including but not limited to fin field-effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacings between components, and the above disclosure is well-suited for these spacings. Additionally, spacers, also known as mandrels, used to form the fins of FinFETs can be processed according to the above disclosure. It should also be understood that although SRAM is used as an example to discuss the present disclosure, the concepts discussed herein can also be applied to other non-SRAM devices.

[0076] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure, source / drain, a first via disposed above the gate structure and the source / drain, and a first metal line having a higher vertical position than the first via in a cross-sectional view. The first via is electrically connected to both the gate structure and the source / drain. The first metal line and the first via extend in a first direction respectively. In a second direction different from the first direction, the metal line and the via are separated by a first distance. The first metal line includes a protruding portion protruding outward in the second direction.

[0077] Another aspect of the present disclosure relates to a semiconductor device. The first metal line extends in a first direction in a top view. The first metal line includes a protruding region. The second metal line extends in the first direction in a top view. The second metal line defines a recessed region. The protruding region points to the recessed region in a second direction different from the first direction. The third metal line extends in the first direction in a top view and is disposed between the first metal line and the second metal line. The geometric profile of the third metal line in the top view is different from that of the first metal line and the second metal line. The first via, the second via, the third via, and the fourth via all extend in the first direction in a top view. The first via and the second via are disposed between the first metal line and the third metal line. The third via and the fourth via are disposed between the second metal line and the third metal line. The first via and the second via are disposed on opposite sides of the protruding region. The third via and the fourth via are at least partially disposed within the recessed region.

[0078] Yet another aspect of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes receiving an integrated circuit (IC) layout design that includes multiple metal lines of an interconnect structure. The metal lines each extend in a first direction in a top view. The method further includes at least partially modifying the received IC layout design by at least partially magnifying portions of at least a subset of the metal lines in a second direction different from the first direction.

[0079] Embodiments of the present invention provide a semiconductor device, including: a gate structure; source / drain; a first via disposed above the gate structure and the source / drain, wherein the first via is electrically connected to the gate structure and the source / drain; and a first metal line having a higher vertical position than the first via in a cross-sectional view; wherein: the first metal line and the first via both extend in a first direction; in a second direction different from the first direction, the metal line and the first via are separated by a first distance; and the first metal line includes a protruding portion protruding outward in the second direction.

[0080] In the above semiconductor device, the protrusion has a first dimension measured in the second direction; and the first dimension is greater than 0 but less than N times the first distance, where N ranges between 0 and 2.

[0081] In the above semiconductor device, the first metal line is a metal line of the metal 0 layer of the interconnect structure.

[0082] In the above semiconductor device, the semiconductor device includes a FinFET fabricated according to a 5-nanometer technology node or a technology node less than 5 nanometers.

[0083] In the above semiconductor device, it further includes: a second via hole extending in the first direction; and a second metal line and a third metal line each extending in the first direction; wherein: in a cross-sectional view, the first metal line, the second metal line, and the third metal line respectively have a higher vertical position than the first via hole and the second via hole; in a top view, the third metal line is disposed between the first metal line and the second metal line; in a top view, the first via hole is disposed between the first metal line and the third metal line; and in a top view, the second via hole is disposed between the second metal line and the third metal line.

[0084] In the above semiconductor device, the first metal line is a bit line (BL) of a static random access memory (SRAM) device; and the second metal line is an anti-phase line (BLB) of a static random access memory (SRAM) device.

[0085] In the above semiconductor device, the third metal line is Vcc of a static random access memory (SRAM) device; and in the second direction, the dimension of the third metal line is smaller than the dimension of the first metal line or the dimension of the second metal line.

[0086] In the above semiconductor device, it further includes: a third via hole extending in the first direction; wherein: in a top view, the third via hole is disposed between the first metal line and the third metal line; and in a top view, the protrusion of the first metal line is disposed between the first via hole and the third via hole.

[0087] In the above semiconductor device, it further includes: a fourth via hole extending in the first direction; wherein: in a top view, the fourth via hole is disposed between the second metal line and the third metal line; the second metal line includes a first protrusion and a second protrusion, the first protrusion and the second protrusion each protrude outward toward the third metal line in the second direction; and both the second via hole and the fourth via hole are disposed between the first protrusion and the second protrusion of the second metal line.

[0088] In the above semiconductor device, the distance by which the first through hole and the third through hole are separated in the first direction is greater than the distance by which the second through hole and the fourth through hole are separated in the first direction.

[0089] Another embodiment of the present invention provides a semiconductor device, comprising: a first metal line extending in a first direction in a top view, wherein the first metal line includes a protruding region; a second metal line extending in the first direction in the top view, wherein the second metal line defines a recessed region, wherein the protruding region points to the recessed region in a second direction different from the first direction; a third metal line extending in the first direction in the top view and disposed between the first metal line and the second metal line, wherein the geometric profile of the third metal line in the top view is different from that of the first metal line and the second metal line; a first through hole, a second through hole, a third through hole, and a fourth through hole, all extending in the first direction in the top view; wherein: the first through hole and the second through hole are disposed between the first metal line and the third metal line; the third through hole and the fourth through hole are disposed between the second metal line and the third metal line; the first through hole and the second through hole are disposed on opposite sides of the protruding region; and the third through hole and the fourth through hole are at least partially disposed within the recessed region.

[0090] In the above semiconductor device, the third metal line substantially does not have a protruding region or a recessed region.

[0091] In the above semiconductor device, the lateral dimension of the third metal line in the second direction is smaller than the lateral dimensions of the first metal line and the second metal line.

[0092] In the above semiconductor device, the semiconductor device includes a static random access memory (SRAM) device; one of the first metal line and the second metal line corresponds to a bit line (BL) of the static random access memory device; and the other of the first metal line and the second metal line corresponds to an anti-phase line (BLB) of the static random access memory device.

[0093] In the above semiconductor device, in a cross-sectional view, the first through hole, the second through hole, the third through hole, and the fourth through hole are all located at a vertical height lower than that of the first metal line, the second metal line, and the third metal line; and each of the first through hole, the second through hole, the third through hole, and the fourth through hole is electrically connected to a corresponding gate through hole and a corresponding source / drain through hole.

[0094] Another embodiment of the present invention provides a method of manufacturing a semiconductor device, comprising: receiving an integrated circuit (IC) layout design, the integrated circuit layout design including a plurality of metal lines of an interconnect structure, wherein the metal lines each extend in a first direction in a top view; and at least partially modifying the received integrated circuit layout design by magnifying at least a subset of portions of the metal lines in a second direction different from the first direction.

[0095] In the above method, receiving the integrated circuit layout design includes: receiving an integrated circuit layout design of a static random access memory (SRAM) device including a plurality of bit lines; and modifying the received integrated circuit layout design includes magnifying the bit lines.

[0096] In the above method, the received integrated circuit layout design includes a plurality of vias disposed between the plurality of metal lines in a top view; and the magnifying includes magnifying a portion into a space between the metal lines that is not occupied by any via.

[0097] In the above method, it further includes: facilitating the manufacturing of the semiconductor device according to the modified integrated circuit layout design.

[0098] In the above method, the step of facilitating the manufacturing includes implementing an extreme ultraviolet (EUV) process to form a subset of the metal lines.

[0099] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: Gate structure; Source / drain; A first via hole, disposed above the gate structure and the source / drain, wherein the first via hole is electrically connected to the gate structure and the source / drain; and A first metal line having a higher vertical position than the first via hole in a cross-sectional view; Wherein: The semiconductor device includes a FinFET fabricated according to a technology node of 5 nanometers or less than 5 nanometers; Both the first metal line and the first via hole extend in a first direction; In a second direction different from the first direction, the first metal line is separated from the first via hole by a first distance; and The first metal line includes a protruding portion protruding outward in the second direction, wherein the protruding portion is not in physical contact with any via hole.

2. The semiconductor device according to claim 1, wherein: The protruding portion has a first dimension measured in the second direction; and The first dimension is greater than 0 but less than N times the first distance, where N ranges between 0 and 2.

3. The semiconductor device according to claim 1, wherein, The first metal line is a metal line of a metal 0 layer of an interconnect structure.

4. The semiconductor device according to claim 1, wherein, The gate structure includes a high-k gate dielectric and a metal gate electrode.

5. The semiconductor device according to claim 1, further comprising: A second via hole extending in the first direction; And A second metal line and a third metal line each extending in the first direction; Wherein: In a cross-sectional view, the first metal line, the second metal line, and the third metal line respectively have a higher vertical position than the first via hole and the second via hole; In a top view, the third metal line is disposed between the first metal line and the second metal line; In a top view, the first via hole is disposed between the first metal line and the third metal line; and In a top view, the second via hole is disposed between the second metal line and the third metal line.

6. The semiconductor device according to claim 5, wherein: The first metal line is a bit line (BL) of a static random access memory (SRAM) device; and The second metal line is an anti-phase line (BLB) of a static random access memory (SRAM) device.

7. The semiconductor device according to claim 5, wherein: The third metal line is a Vcc of a static random access memory (SRAM) device; and In the second direction, the size of the third metal line is smaller than the size of the first metal line or the size of the second metal line.

8. The semiconductor device according to claim 5, further comprising: A third via hole extending in the first direction; Wherein: In a top view, the third via hole is disposed between the first metal line and the third metal line; and In a top view, the protruding portion of the first metal line is disposed between the first via hole and the third via hole.

9. The semiconductor device according to claim 8 further comprises: A fourth via hole extending in the first direction; Wherein: In a top view, the fourth via hole is disposed between the second metal line and the third metal line; The second metal line includes a first protruding portion and a second protruding portion, and the first protruding portion and the second protruding portion each protrude outward toward the third metal line in the second direction; and Both the second via hole and the fourth via hole are disposed between the first protruding portion and the second protruding portion of the second metal line.

10. The semiconductor device according to claim 9, wherein, The distance by which the first through-hole and the third through-hole are separated in the first direction is greater than the distance by which the second through-hole and the fourth through-hole are separated in the first direction.

11. A semiconductor device comprising: A first metal line extending in a first direction in a top view, wherein the first metal line includes a protruding region; A second metal line extending in the first direction in a top view, wherein the second metal line defines a recessed region, and wherein the protruding region points towards the recessed region in a second direction different from the first direction; A third metal line extending in the first direction in a top view and disposed between the first metal line and the second metal line, wherein the geometric profile of the third metal line in the top view is different from that of the first metal line and the second metal line; A first through-hole, a second through-hole, a third through-hole, and a fourth through-hole, all extending in the first direction in a top view; Wherein: The first through-hole and the second through-hole are disposed between the first metal line and the third metal line; The third through-hole and the fourth through-hole are disposed between the second metal line and the third metal line; The first through-hole and the second through-hole are disposed on opposite sides of the protruding region; and The third through-hole and the fourth through-hole are at least partially disposed within the recessed region.

12. The semiconductor device according to claim 11, wherein, The third metal line does not have a protruding region or a recessed region.

13. The semiconductor device according to claim 11, wherein, The lateral dimension of the third metal line in the second direction is smaller than the lateral dimensions of the first metal line and the second metal line.

14. The semiconductor device according to claim 11, wherein: The semiconductor device includes a static random access memory (SRAM) device; One of the first metal line and the second metal line corresponds to a bit line (BL) of the static random access memory device; And The other of the first metal line and the second metal line corresponds to an anti-phase line (BLB) of the static random access memory device.

15. The semiconductor device according to claim 11, wherein: In a cross-sectional view, the first through-hole, the second through-hole, the third through-hole, and the fourth through-hole are all located at a vertical height lower than that of the first metal line, the second metal line, and the third metal line; and Each of the first through-hole, the second through-hole, the third through-hole, and the fourth through-hole is electrically connected to a corresponding gate through-hole and a corresponding source / drain through-hole.

16. A method of manufacturing a semiconductor device, comprising: Receiving an integrated circuit (IC) layout design, the integrated circuit layout design including multiple metal lines and multiple through-holes of an interconnect structure, wherein the metal lines each extend in a first direction in a top view, and wherein, in the top view, the through-holes are disposed between the metal lines; and At least partially modifying the received integrated circuit layout design by magnifying at least a subset of portions of the metal lines in a second direction different from the first direction to form protrusions, wherein all the protrusions protrude into the region between the through-holes without physically contacting the through-holes.

17. The method according to claim 16, wherein: Receiving an integrated circuit layout design includes: receiving an integrated circuit layout design of a static random access memory (SRAM) device including multiple bit lines; and Modifying the received integrated circuit layout design includes magnifying the bit lines.

18. The method according to claim 16, wherein: The plurality of metal lines includes a first metal line and a second metal line; and The amplifying includes amplifying an end portion of the first metal line and a non-end portion of the second metal line.

19. The method according to claim 16, further comprising: The integrated circuit layout design according to the modification facilitates the fabrication of the semiconductor device.

20. The method according to claim 19, wherein The step of facilitating the fabrication includes implementing an extreme ultraviolet (EUV) process to form a subset of the metal lines.

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