Semiconductor integrated circuits and electronic instruments

Abstract

The present disclosure relates to a semiconductor integrated circuit and an electronic instrument that can further improve performance. The shape of the wiring that forms a transmission network in which the same signal is transmitted is set according to the distance from the driver. The wiring width is formed to decrease as the distance from the driver increases. The transmission network is formed by: a trunk line with a larger wiring width; a driver connected to the trunk line; and a branch line branching from the trunk line, the branch line having a smaller wiring width. The wiring shape of the trunk line is set so that the wiring width of each part of the second wiring branch decreases as the distance from the part connected to the driver increases. This feature can be applied to clock wiring of a semiconductor integrated circuit, for example.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit and an electronic device, and more particularly, to a semiconductor integrated circuit and an electronic device capable of further improving performance. Background Art

[0002] Generally, in a semiconductor integrated circuit, wirings constituting a wiring network (hereinafter referred to as the same net) through which the same signal is transmitted have wiring shapes designed to have the same wiring width. In addition, conventionally, wirings attempting various optimizations have been proposed.

[0003] For example, Patent Document 1 proposes a wiring layout that is optimized by considering wiring intervals to minimize wiring delays. In addition, Patent Document 2 proposes a clock wiring method that is used to reduce clock skew by adjusting the lengths of adjacent wirings and the unevenness of wiring capacity caused by the crossing of interlayer wirings.

[0004] Citation List

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2002-313921

[0007] Patent Document 2: Japanese Patent Application Publication No. 2001-228931 Summary of the invention

[0008] Problems to be solved by the present invention

[0009] By the way, even in the same net, the current density changes in one wiring, so the performance may deteriorate in the wiring shape with the same wiring width. For example, when the same wiring width is designed to be larger, the performance in terms of power consumption, speed, etc. is reduced due to unnecessary wiring capacity.

[0010] Note that since the wiring layout proposed in the above-mentioned Patent Document 1 is not a technology related to the same net, and the clock wiring method proposed in Patent Document 2 is not a technology related to the wiring shape, such problems cannot be solved.

[0011] Therefore, it is necessary to avoid the performance degradation occurring in the conventional wiring shape, optimize the wiring shape in the same net, and improve the performance of the semiconductor integrated circuit.

[0012] The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to be able to further improve the performance.

[0013] Solution to the problem

[0014] A semiconductor integrated circuit according to one aspect of the present disclosure includes: wirings forming a transmission network through which the same signal is transmitted; and a driver that supplies the signal to the wirings, wherein the wirings have a wiring shape set according to a distance from the driver or a frequency of the signal.

[0015] An electronic device according to one aspect of the present disclosure includes: a semiconductor integrated circuit, which includes: wiring forming a transmission network through which the same signal is transmitted; and a driver that provides the signal to the wiring, wherein the wiring has a wiring shape set according to the distance from the driver or the frequency of the signal.

[0016] In one aspect of the present disclosure, wirings forming a transmission network through which the same signal is transmitted have a wiring shape set according to a distance from a driver that supplies a signal to the wirings or a frequency of the signal.

[0017] Effects of the Invention

[0018] According to an aspect of the present disclosure, the performance may be further improved.

[0019] Note that the effects described here are not necessarily limited and may be any effects described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] [ Figure 1 ] is a diagram showing a circuit diagram of clock wiring to which the present technology is applied.

[0021] [[ Figure 2 ] is a layout diagram showing a conventional wiring shape.

[0022] [ Figure 3 ] is a layout diagram showing the wiring shape according to the first embodiment.

[0023] [ Figure 4 ]yes Figure 3 A magnified view of a portion of .

[0024] [ Figure 5 ] is a layout diagram showing another wiring shape according to the first embodiment.

[0025] [ Figure 6 ]yes Figure 5 A magnified view of a portion of .

[0026] [ Figure 7 ] is shown Figure 3 A diagram showing a specific configuration example of a wiring shape.

[0027] [ Figure 8 ] is shown Figure 7 A diagram showing a modified example of the wiring shape shown.

[0028] [ Fig. 9 ] is a diagram for explaining the wiring shape when the first embodiment is applied to long-distance wiring.

[0029] [ Fig.10 ] is shown Fig. 9 A diagram showing a specific configuration example of a wiring shape.

[0030] [ Fig.11 ] is a layout diagram showing the wiring shape according to the second embodiment.

[0031] [ Fig.12 ]yes Fig.11 A magnified view of a portion of .

[0032] [ Fig.13 ] is a layout diagram showing another wiring shape according to the second embodiment.

[0033] [ Fig.14 ]yes Fig.13 A magnified view of a portion of .

[0034] [ Fig.15 ] is shown Fig.13 A diagram showing a specific configuration example of a wiring shape.

[0035] [ Fig.16 ] is a diagram for explaining the wiring shape when the second embodiment is applied to long-distance wiring.

[0036] [ Fig.17 ] is shown Fig.16 A diagram showing a specific configuration example of a wiring shape.

[0037] [ Fig.18 ] is a layout diagram of the power supply wiring.

[0038] [ Fig.19 ] is a diagram used to describe impedance matching.

[0039] [ Fig. 20 ] is a diagram for describing the occurrence of current concentration.

[0040] [ Fig.21 ] is a block diagram showing a configuration example of an electronic device including a semiconductor integrated circuit. DETAILED DESCRIPTION

[0041] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the accompanying drawings.

[0042] <First Embodiment of Wiring Shape>

[0043] Will refer to Figures 1 to 10 A first embodiment of a wiring shape used in a semiconductor integrated circuit to which the present technology is applied is described.

[0044] Figure 1 A circuit diagram showing clock wiring to which the present technology is applied.

[0045] exist Figure 1 In the clock wiring 11 shown, signal lines of the same network are designed so that a clock signal output from a clock generation circuit (not shown) is supplied to a driver 13 via buffers 12-1 and 12-2, and is supplied from the driver 13 to a plurality of receivers 14. Figure 1 In the example shown, the wiring shape of the clock wiring 11 is designed so that the signal line branches from the output terminal of the driver 13 and is connected to the input terminals of nine receivers 14-1 to 14-9. Then, the driving elements 15-1 to 15-9 driven by the clock signal are connected to the receivers 14-1 to 14-9, respectively.

[0046] In such a clock wiring 11, a special wiring shape is usually used, such as Figure 2 and Figure 3 The so-called fishbone wiring shape shown.

[0047] Figure 2 is based on Figure 1 The circuit diagram shown shows a layout diagram of a conventional wiring shape.

[0048] Figure 2 The clock wiring 21 shown has a fishbone wiring shape, in which a trunk line 22 as a signal line with a large wiring width is connected to the output terminal of the driver 13, and branch lines 23 as a plurality of signal lines with a small wiring width are connected to the trunk line 22 so as to branch from the trunk line 22. Figure 2 In the example shown, five branch lines 23 - 1 to 23 - 5 are connected to the trunk line 22 .

[0049] In addition, in the clock wiring 21, the branch lines 23-1 to 23-5 are provided with Figure 1 The receivers 14-1 to 14-9 are connected to the connection terminals 24-1 to 24-9. In addition, connection terminals 25-1 and 25-2 are provided between the buffer 12 and the driver 13.

[0050] Then, conventionally, in such a clock wiring 21, the trunk line 22 and the branch line 23 are designed so that the wiring width is constant.

[0051] Figure 3 Shown based on Figure 1 The circuit diagram shown is a layout diagram showing the wiring shape to which this technology is applied.

[0052] Figure 3The clock wiring 31 shown has a fishbone wiring shape, in which five branch lines 33-1 and 33-5 having a small wiring width are connected to a trunk line 32 having a large wiring width so as to branch from the trunk line 32, similar to Figure 2 Clock routing 21. Note that Figure 3 The clock wiring 31 has a layout in which a trunk line 32 is arranged along the vertical direction of the semiconductor integrated circuit.

[0053] In addition, in the clock wiring 31, the branch lines 33-1 to 33-5 are provided with Figure 1 The receivers 14-1 to 14-9 are connected to the connection terminals 34-1 to 34-9. In addition, connection terminals 35-1 and 35-2 are provided between the buffer 12 and the driver 13.

[0054] Then, in the clock wiring 31, the output terminal of the driver 13 is connected to the center of the trunk 32, and the trunk 32 has a wiring shape set so that the wiring width becomes smaller according to the distance from the connection portion of the driver 13 to the upper and lower sides in the vertical direction of the trunk 32. That is, since the current density of the signal transmitted via the trunk 32 decreases as the distance from the driver 13 increases, the wiring shape of the trunk 32 is set so that the wiring width corresponds to the decrease in the current density.

[0055] Note that since the reduction in current density varies depending not only on the number of receivers, etc., and the distance from the driver 13 , it is preferable to form the trunk line 32 with a narrowed wiring width so as to optimize the current density according to the signal transmitted via the trunk line 32 .

[0056] Figure 4 Zoom in and show Figure 3 The area surrounded by the dotted line.

[0057] Figure 4 The branch lines 33-1 and 33-2 shown in the figure have a set wiring shape so that the wiring width becomes smaller according to the distance from the branch part with the trunk line 32 to the right in the horizontal direction, that is, as the distance from the driver 13 increases, similar to the trunk line 32. Of course, although not shown, the branch lines 33-1 and 33-2 extending to the left from the trunk line 32 also have a set wiring shape so that the wiring width becomes smaller according to the distance from the branch part, and the same applies to the branch lines 33-3 to 33-5.

[0058] In this way, in the clock wiring 31, the trunk line 32 and the branch line 33 have a designed wiring shape so that the wiring width becomes smaller as the distance from the driver 13 increases. Then, in the clock wiring 31, the wiring performance can be improved by optimizing the wiring width of the trunk line 32 and the branch line 33. Therefore, the clock wiring 31 can, for example, reduce unnecessary wiring capacity and avoid performance degradation in terms of power consumption, speed, etc. In addition, in the case where the receiver 14 that receives the signal is a complementary metal oxide semiconductor (CMOS), it is preferred to narrow the wiring width of the trunk line 32 and the branch line 33, thereby suppressing reflection at the ends of the trunk line 32 and the branch line 33.

[0059] Therefore, the performance of the semiconductor integrated circuit including the clock wiring 31 can be improved. For example, the size of the driver 13 can be reduced according to the reduction of the wiring capacity in the clock wiring 31, so that the power can be further reduced. In particular, in the case where the clock wiring 31 adopts a herringbone wiring shape, this effect can be well obtained.

[0060] Figure 5 Shown based on Figure 1 The circuit diagram shown in FIG. 1 shows a layout diagram of the wiring shape to which the present technology is applied, similar to Figure 3 .also, Figure 6 Zoom in and show Figure 5 The area surrounded by the dotted line in Figure 4 .

[0061] Figure 5 and Figure 6 The clock wiring 41 shown has a layout in which a trunk line 42 connected to the driver 13 is arranged along the horizontal direction of the semiconductor integrated circuit.

[0062] Then, if Figure 5 As shown, in the clock wiring 41, similar to Figure 3 The clock wiring 31 and the trunk line 42 connected to the driver 13 have a set wiring shape so that the wiring width becomes smaller according to the distance from the connection part of the driver 13 to the left and right in the horizontal direction. Figure 6 As shown, the branch line 43 branched from the main line 42 has a set wiring shape so that the wiring width becomes smaller according to the distance from the branch part having the main line 42 to the lower side in the vertical direction, that is, as the distance from the driver 13 increases.

[0063] In the clock wiring 41 having such a wiring shape, similar to Figure 3 The clock wiring 31 can achieve better performance by optimizing the wiring width of the trunk line 42 and the branch line 43.

[0064] Figure 7 Show reference Figure 3Specific wiring shape of the described clock wiring 31.

[0065] In Figure 7 the clock wiring 31 shown, the driver 13 is arranged at the center of gravity of the plurality of receivers 14 ( Figure 1 ). Then, the driver 13 is connected to the main line 32 having a large wiring width via the through electrodes 51-1 to 51-3. In addition, the branch lines 33-1 to 33-4 having a small wiring width are respectively connected to the main line 32 via the through electrodes 52-1 to 52-4. Further, in the clock wiring 31, a plurality of VDD lines and a plurality of GND lines are arranged in parallel at regular intervals with respect to the branch lines 33. In addition, the wiring shape of the clock wiring 31 is symmetric about the center line of the main line 32.

[0066] Then, as described above, since the current density decreases as the main line 32 approaches the distal end, the wiring shape of the main line 32 is set such that the wiring width gradually becomes smaller, so that the resistance increases toward the distal end side according to the change in the current density. Further, the main line 32 is formed such that the wiring width becomes smaller at a constant distance, for example, at a predetermined constant width, from the connection portion of the driver 13.

[0067] For example, the wiring shape of the main line 32 is set such that for each branch portion where the branch lines 33-1 to 33-3 branch upward (similarly, downward (not shown)) from the connection portion of the driver 13, the wiring width becomes smaller so as to be symmetric with respect to the center line. That is, the main line 32 is formed such that the wiring width changes from the wiring width D1 to the wiring width D2 (<D1) at the branch portion where the branch line 33-3 branches, from the wiring width D2 to the wiring width D3 (<D2) at the branch portion where the branch line 33-2 branches, and from the wiring width D3 to the wiring width D4 (<D3) at the branch portion where the branch line 33-1 branches. Note that in the present embodiment, the wiring width D is formed to be symmetric with respect to the center line and will be described below as the width on one side with respect to the center line (that is, the actual wiring width is twice D), similar to Figure 7 .

[0068] Specifically, a configuration example of driving the clock wiring 31 by the driver 13, where the total capacitance of the clock wiring 31 including the wiring capacitance and the gate capacitance is 10 pF, the rate is controlled by the signal EM, the required wiring width on the driver 13 side is 5 μm, the total capacitance (wiring capacitance and gate capacitance) connected to the receiver 14 is 0.1 pF, and the required wiring width on the receiver 14 side is 0.5 μm. In such a configuration example, the driving charge decreases as the main line approaches the distal end. Therefore, as Figure 7As shown, in the case where ten branch lines 33 branch on one side of the trunk line 32 in a fishbone wiring shape, it is preferable to set the wiring shape so that the wiring width of the trunk line 32 becomes smaller by 0.5 μm for each branch portion. Therefore, the redundant wiring capacity in the clock wiring 31 can be eliminated.

[0069] In this way, the conditions for appropriately eliminating the redundant wiring capacity of the clock wiring 31 vary depending on layout conditions such as wiring capacity or gate capacity, required wiring width, the number of branch lines 33, circuit conditions, etc. Therefore, it is necessary to appropriately design the wiring shape according to these conditions so that the wiring width of the trunk line 32 is narrowed.

[0070] Figure 8 Show Figure 7 A modification example of the wiring shape of the clock wiring 31 is shown.

[0071] exist Figure 8 In the clock wiring 31A shown, the wiring shapes of the branch lines 33A-1 to 33A-4 branched from the main line 32 are set so that the wiring width becomes smaller according to the distance from the main line 32, that is, as the distance from the driver 13 increases. For example, a plurality of branch lines 33A forming the clock wiring 31A are formed so that the wiring width uniformly becomes smaller from the center line at a predetermined constant width for every constant distance from the main line 32 to the branch portion.

[0072] For example, Figure 8 As shown, branch lines 33A-1 to 33A-4 are formed so that the wiring width becomes smaller at each constant distance in the order of length L1 from the center line of the trunk line 32, length L2 after length L1, and length L3 (L1=L2=L3) after length L1.

[0073] In this way, in the clock wiring 31A, better performance can be obtained by optimizing the wiring widths of the trunk line 32 and the branch line 33A.

[0074] Will refer to Fig. 9 and Fig.10 The following describes the wiring shape in which the present technology is applied to long-distance wiring.

[0075] Fig. 9 A shows a circuit diagram of long distance wiring. Fig. 9 As shown in A, the output terminal of the driver 13 is connected to the input terminal of the receiver 14, and the distance between the driver 13 and the receiver 14 is greater than or equal to a predetermined distance in a single wiring without providing a branch between the driver 13 and the receiver 14.

[0076] Fig. 9 B and Fig. 9 C shows that based on Fig. 9The circuit diagram shown in A is a layout diagram showing the wiring shape to which the present technology is applied. Fig. 9 The clock wiring 61 of B has a layout in which the long distance wiring 62 is arranged along the vertical direction of the semiconductor integrated circuit, and Fig. 9 The clock wiring 71 of C has a layout in which a long distance wiring 72 is arranged along the horizontal direction of the semiconductor integrated circuit.

[0077] like Fig. 9 As shown in FIG. 1B , in the clock wiring 61, the long distance wiring 62 has a set wiring shape so that the wiring width becomes smaller according to the distance from the connection part of the driver 13 to the upper and lower sides in the vertical direction, and is connected to the receiver 14. That is, since the current density of the signal transmitted via the long distance wiring 62 decreases as the distance from the driver 13 increases, the long distance wiring 62 is formed so that the wiring width becomes smaller according to the decrease in the current density.

[0078] Similarly, if Fig. 9 As shown in C, in the clock wiring 71, the long distance wiring 72 has a set wiring shape so that the wiring width becomes smaller according to the distance from the connection part of the driver 13 to the left and right in the horizontal direction, and is connected to the receiver 14. That is, since the current density of the signal transmitted via the long distance wiring 72 decreases as the distance from the driver 13 increases, the long distance wiring 72 is formed so that the wiring width becomes smaller according to the decrease in current density.

[0079] The clock wirings 61 and 71 having such a wiring shape are long-distance wirings 62 and 72 having a predetermined distance or longer, specifically, large-scale wirings of about 100 μm to 15 mm, and have a wiring shape set according to the current density. In this way, regardless of the number of receivers 14, the distance from the driver 13 to the receiver 14, etc., better performance can be obtained by optimizing the wiring width in the wiring where a difference in current density occurs.

[0080] Fig.10 Show Fig. 9 B shows the specific wiring shape of the clock wiring 61.

[0081] like Fig.10 As shown, the driver 13 is connected to one end of the long distance wiring 62 via a through electrode 63 - 1 , and the receiver 14 is connected to the other end of the long distance wiring 62 via a through electrode 63 - 2 .

[0082] Then, in the clock wiring 61, as the long distance wiring 62 approaches the receiver 14, the current density decreases, and therefore, the wiring shape of the long distance wiring 62 is set so that the wiring width becomes smaller in accordance with the change in the current density. For example, the wiring shape of the long distance wiring 62 is set so that the wiring width becomes smaller so as to be symmetrical with respect to the center line from the connection portion of the driver 13 toward the upper side. That is, the wiring shape of the long distance wiring 62 is set so that the wiring width changes from the wiring width D1 to the wiring width D2 (<D1) according to the distance from the driver 13, and changes from the wiring width D2 to the wiring width D3 (<D2).

[0083] Specifically, in the case of a wiring shape in which the wiring width becomes smaller according to the distance from the connection portion of the driver 13, it is preferable to reduce the wiring width of the long-distance wiring 62 at a pitch of 10 μm to 100 μm, and set the wiring shape so that the wiring width is the minimum width at the connection portion of the receiver 14. Alternatively, in the case where the length of the long-distance wiring 62 is about 100 μm to 15 mm, the wiring shape can be optimized by calculating the wiring width required at the connection portion of the receiver 14 as the far end, and gradually reducing the wiring width from the driver 13 side to have a uniformly divided value so that the wiring width at the connection portion of the receiver 14 is the calculated wiring width.

[0084] By adopting the above wiring shape, the wiring capacity is reduced, so that the amount of current can be reduced, the power consumption can be reduced, and the electromagnetic interference (EMI) characteristics can be improved.

[0085] In addition, the wiring capacity can be reduced, so that the load capacity can be reduced, the speed can be increased, and the driving ability of the driver 13 can be reduced. Therefore, the power can be increased and the area can be reduced. Therefore, the reduced area can be used for other wiring, so that the wiring characteristics can be improved.

[0086] In addition, by adopting the above wiring shape, the resistance value on the far end side increases, so that the occurrence of reflection in the signal can be reduced. In addition, the area of ​​the upper wiring and the through electrode is reduced, so that the antenna characteristics can also be improved. In particular, for high-frequency clocks where signal reflection is prone to occur, fine processes with problems with electromigration (EM), large-scale wiring, etc., better characteristics can be obtained.

[0087] <Second Embodiment of Wiring Shape>

[0088] Will refer to Figures 11 to 17 A second embodiment of a wiring shape used in a semiconductor integrated circuit to which the present technology is applied is described.

[0089] Fig.11 Shown based on Figure 1The circuit diagram shown in FIG. 1 shows a layout diagram of the wiring shape to which the present technology is applied. Fig.12 Zoom in and show Fig.11 The area surrounded by the dotted line.

[0090] Fig.11 and Fig.12 The clock wiring 81 shown has a fishbone wiring shape, in which five branch lines 83-1 and 83-5 having a small wiring width are connected to a trunk line 82 having a large wiring width so as to branch from the trunk line 82, similar to Figure 2 Clock routing 21. Note that Fig.11 The clock wiring 81 has a layout in which a trunk line 82 is arranged along the vertical direction of the semiconductor integrated circuit.

[0091] In addition, in the clock wiring 81, the branch lines 33-1 to 33-5 are provided with Figure 1 The receivers 14-1 to 14-9 are connected to the connection terminals 84-1 to 84-9. In addition, connection terminals 85-1 and 85-2 are provided between the buffer 12 and the driver 13.

[0092] Then, in the clock wiring 81 , when the output terminal of the driver 13 is connected to the center of the trunk 82 and the transmission signal has a high frequency, the wiring shape of the trunk 82 is set to a mesh shape in which a plurality of slits are formed according to the frequency of the signal transmitted by the trunk 82 .

[0093] Generally, as the frequency of the signal transmitted by the trunk line 82 becomes higher, the ratio of the skin resistance component increases due to direct current (DC) resistance. Therefore, in the clock wiring 81 that transmits a high-frequency signal, a plurality of slits are formed on the trunk line 82 so as to become thinner according to the frequency, thereby reducing the skin resistance component of the mesh shape as the surface area of ​​the trunk line 82 increases.

[0094] Therefore, in the clock wiring 81, by forming a plurality of slits to set the wiring shape to a mesh shape, the skin resistance can be reduced and the attenuation of the signal can be suppressed. Therefore, the performance of the semiconductor integrated circuit including the clock wiring 81 can be improved.

[0095] Fig.13 Shown based on Figure 1 The circuit diagram shown in FIG. 1 shows a layout diagram of the wiring shape to which the present technology is applied, similar to Fig.11 .also, Fig.14 Zoom in and show Fig.13 The area surrounded by the dotted line in Fig.12 .

[0096] Fig.13 and Fig.14The clock wiring 91 shown has a layout in which a trunk line 92 connected to the driver 13 is arranged along the horizontal direction of the semiconductor integrated circuit.

[0097] Then, if Fig.13 As shown, in the clock wiring 91, similar to Fig.11 The wiring shape of the clock wiring 81 and the trunk line 92 connected to the driver 13 is set to a mesh shape, in which a plurality of slits are formed according to the frequency of the signal transmitted by the trunk line 92.

[0098] In the clock wiring 91 having such a wiring shape, similar to Fig.11 The clock wiring 81 can achieve better performance by forming the trunk 92 into an optimal mesh according to the frequency of the signal.

[0099] Fig.15 Show reference Fig.11 A specific wiring shape of the clock wiring 81 is described.

[0100] exist Fig.15 In the clock wiring 81 shown, the driver 13 is connected to the trunk line 82 having a large wiring width via the through electrodes 86-1 to 86-3. In addition, the branch lines 83-1 to 83-4 having a small wiring width are connected to the trunk line 82 via the through electrodes 87-1 to 87-4, respectively. In addition, in the clock wiring 81, a plurality of VDD lines and a plurality of GND lines are arranged in parallel with the branch line 33. In addition, the wiring shape of the clock wiring 81 is left-right symmetrical with respect to the center line of the trunk line 82.

[0101] Then, as described above, slits having a width w and a height h are formed at a plurality of locations of the trunk line 82, and the wiring shape of the trunk line 82 is set to a mesh shape by these slits. For example, as the frequency of the signal transmitted by the clock wiring 81 becomes higher, the width w and the height h of the slit are formed to smaller sizes, so that the trunk line 82 is formed into a finer mesh shape.

[0102] Will refer to Fig.16 and Fig.17 The following describes the wiring shape in which the present technology is applied to long-distance wiring.

[0103] Fig.16 A circuit diagram showing long distance wiring, such as Fig.16 As shown in A, the output terminal of the driver 13 is connected to the input terminal of the receiver 14 in a single wiring without providing a branch between the driver 13 and the receiver 14.

[0104] Fig.16 B and Fig.16 C shows that based on Fig.16 The circuit diagram shown in A is a layout diagram showing the wiring shape to which the present technology is applied. Fig.16 The clock wiring 101 of B has a layout in which the long distance wiring 102 is arranged along the vertical direction of the semiconductor integrated circuit, and Fig.16 The clock wiring 111 of C has a layout in which a long distance wiring 112 is arranged along the horizontal direction of the semiconductor integrated circuit.

[0105] like Fig.16 As shown in B, in the clock wiring 101, the long distance wiring 102 directed in the vertical direction has a set wiring shape so that a plurality of slits are formed according to the frequency of the signal transmitted through the clock wiring 101, and is connected to the receiver 14. That is, in the case where the signal has a high frequency, the long distance wiring 102 is formed to have a finer mesh, thereby increasing the surface area by forming the slits.

[0106] Similarly, if Fig.17 As shown in C, in the clock wiring 111, the long distance wiring 112 directed in the horizontal direction has a set wiring shape so that a plurality of slits are formed according to the frequency of the signal transmitted through the clock wiring 111, and is connected to the receiver 14. That is, in the case where the signal has a high frequency, the long distance wiring 112 is formed to have a finer mesh, thereby increasing the surface area by forming the slits.

[0107] The clock wirings 101 and 111 having such a wiring shape use long-distance wirings 102 and 112 having a predetermined distance or longer, specifically, large-scale wirings of about 100 μm to 15 mm, and have a wiring shape set according to the frequency of the signal. In this way, regardless of the number of receivers 14, the distance from the driver 13 to the receiver 14, etc., the slit can be optimized according to the frequency of the transmission signal to obtain better performance.

[0108] Fig.17 Show Fig.16 B shows the specific wiring shape of the clock wiring 101.

[0109] like Fig.17 As shown, the driver 13 is connected to one end of the long distance wiring 102 via a through electrode 103 - 1 , and the receiver 14 is connected to the other end of the long distance wiring 102 via a through electrode 103 - 2 .

[0110] Then, in the clock wiring 101, slits with a width of w and a height of h are formed at multiple locations of the long-distance wiring 102, and the wiring shape of the long-distance wiring 102 is set to a mesh shape by these slits. Therefore, the surface area of ​​the long-distance wiring 102 can be increased, so that the signal attenuation caused by the skin resistance can be reduced.

[0111] For example, in the clock wiring 101, as the frequency of the signal transmitted by the long-distance wiring 102 becomes higher, the width w and the height h of the slit are reduced, thereby setting the wiring shape of the long-distance wiring 102 to a finer mesh.

[0112] By adopting the above wiring shape, the skin resistance is reduced, so that the attenuation of the signal can be suppressed and the speed can be increased. In addition, the wiring capacity can be reduced and the power consumption can be reduced.

[0113] <Wiring Shape of Power Wiring>

[0114] Will refer to Fig.18 Describe the power supply wiring to which this technology is applied.

[0115] Fig.18 A layout diagram showing power supply wiring.

[0116] Fig.18 The illustrated power supply wiring 121 includes a current supply source 122 and a GND supply source 123 , a VDD rail 124 is connected to the current supply source 122 , and a GND rail 125 is connected to the GND supply source 123 .

[0117] In addition, a VDD trunk line 124 and a GND trunk line 125 having a large wiring width are arranged in the vertical direction of the semiconductor integrated circuit, and a plurality of VDD lines and a plurality of GND lines having a small wiring width are arranged in the horizontal direction of the semiconductor integrated circuit. Then, in the power supply wiring 121, the VDD trunk line 124 is connected to each of the seven VDD lines via through electrodes 126-1 to 126-7, and the GND trunk line 125 is connected to each of the six GND lines via through electrodes 127-1 to 127-6.

[0118] In addition, Fig.18 In the example shown, a plurality of power consumption sources (eg, transistors) represented by dotted shading are connected between the VDD line and the GND line at desired locations.

[0119] In such a power supply wiring 121, the VDD trunk line 124 has a wiring shape set so that the wiring width becomes larger as the distance from the current supply source 122 increases. That is, the VDD trunk line 124 is formed so that the wiring width changes from the wiring width D11 to the wiring width D12 (>D11), from the wiring width D12 to the wiring width D13 (>D12), and from the wiring width D13 to the wiring width D14 (>D13) per a constant distance from the current supply source 122.

[0120] In addition, for example, the VDD rail line 124 is formed to have a larger wiring width for each of a plurality of power consumption sources each time a power consumption source is connected. Fig.18In the example shown, the power consumption sources are arranged so as to be dense at a position away from the current supply source 122, and the wiring shape of the VDD trunk line 124 is set so that the wiring width is larger toward this position.

[0121] Similarly, in the power supply wiring 121, the GND trunk line 125 has a wiring shape set so that the wiring width becomes larger as the distance from the GND supply source 123 increases. That is, the GND trunk line 125 is formed so that the wiring width changes from the wiring width D21 to the wiring width D22 (>D21), from the wiring width D22 to the wiring width D23 (>D22), and from the wiring width D23 to the wiring width D24 (>D23) per constant distance from the GND supply source 123.

[0122] In addition, for example, the GND trunk line 125 is formed to have a larger wiring width for each of a plurality of power consumption sources each time a power consumption source is connected. Fig.18 In the example shown, the power consumption sources are arranged so as to be dense at a position away from the GND supply source 123, and the wiring shape of the GND trunk line 125 is set so that the wiring width is larger toward this position.

[0123] Therefore, the power supply wiring 121 can achieve a uniform voltage drop (IR Drop) in the longitudinal direction of the current supply source 122 and the GND supply source 123 and can improve resistance to arrangement variation of a plurality of power consumption sources.

[0124] By adopting the above-described wiring shape, the voltage drop can be made uniform, so that jitter generated in the signal waveform can be improved or signal timing can be improved, and thus better characteristics can be obtained.

[0125] <Impedance Matching>

[0126] Will refer to Fig.19 Describe impedance matching.

[0127] Fig.19 A shows a circuit diagram of wiring for performing impedance matching.

[0128] like Fig.19 As shown in A in FIG. 1 , in the wiring 131 , the output terminal of the driver 13 is grounded via a terminal resistor 132 .

[0129] like Fig.19 As shown in FIG. 1B, the driver 13 is connected to one end of a signal line 133, which is a target for obtaining impedance, via a through electrode 134-1, and a terminal resistor 132 is connected to the other end of the signal line 133 via a through electrode 134-2. Fig.19As shown in B, the signal line 133 is arranged along the vertical direction of the semiconductor integrated circuit, and a plurality of VDD lines and a plurality of GND lines are arranged along the horizontal direction of the semiconductor integrated circuit.

[0130] Then, the signal line 133 has a set wiring shape so that the wiring width becomes larger from the driver 13 toward the terminal resistor 132, thereby matching the impedance. That is, the signal line 133 is formed so that the wiring width changes from the wiring width D1 to the wiring width D2 (>D1) and from the wiring width D2 to the wiring width D3 (>D2) at every constant distance from the driver 13.

[0131] Therefore, in the wiring 131, impedance matching can be performed through the signal line 133 so that the output impedance of the driver 13 and the input impedance of the terminal resistor 132 are equal to each other.

[0132] By adopting the above-described wiring shape, electromagnetic radiation can be suppressed and reflection of signals can be reduced, so that reliability can be improved, and better characteristics can be obtained as a result.

[0133] <Example of current concentration>

[0134] Will refer to Fig. 20 An example in which current concentration occurs is described.

[0135] In such Fig. 20 In the wiring 141 shown in A, if the current density on the driver 13 side and the receiver 14-1 to 14-5 side are compared with each other, the current density on the driver 13 side is higher than the current density on the receiver 14-1 to 14-5 side. Therefore, it is preferable that the wiring resistances 142-1 to 142-5 from the driver 13 side to the receiver 14-5 are set to have the maximum current density on the driver 13 side.

[0136] Therefore, if Fig. 20 As shown in B, in the wiring 141, the signal line 143 has a wiring shape in which the wiring width becomes larger on the driver 13 side having a high current density and becomes smaller on the receiver 14-5 side having a low current density. That is, the signal line 143 is formed so that for each connection portion connected to the receiver 14, the wiring width changes from the driver 13 from the wiring width D1 to the wiring width D2 (<D1), from the wiring width D2 to the wiring width D3 (<D2), from the wiring width D3 to the wiring width D4 (<D3), and from the wiring width D4 to the wiring width D5 (<D5).

[0137] By adopting such a wiring shape, redundant wiring capacity in the wiring 141 can be reduced.

[0138] As described above, in the semiconductor integrated circuit to which the wiring shape of each of the above-described embodiments is applied, the wiring width of the signal line is formed to gradually become smaller, so that the resistance increases toward the distal side, so that reflection of the signal, electromagnetic radiation, etc. can be reduced. In addition, in the semiconductor integrated circuit, the wiring width of the power supply wiring is formed to gradually become larger toward the distal side, so that the amount of voltage drop can be controlled, a more uniform voltage drop can be achieved, and the resistance can be improved.

[0139] In addition, the semiconductor integrated circuit to which the wiring shapes of the above-described embodiments are applied can be applied to designs for high speed or designs for low power consumption to achieve further improvement in performance. For example, the semiconductor integrated circuit may be more effective for designs requiring high-speed (1 GHz or higher) clocks or large-scale (1 pF or higher) wiring.

[0140] In addition, in the future, as the miniaturization of semiconductor integrated circuits progresses, wiring becomes thinner and film thinning progresses, so there is concern about adverse effects such as EM, high resistance, etc., but by applying the wiring shape of each of the above-mentioned embodiments, these adverse effects can be suppressed. Similarly, due to the progress of miniaturization, there is concern about adverse effects of changes, and in particular, assuming that reference is emphasized Fig.18 The uniformity of the voltage drop in the power dissipation sources (eg transistors), therefore, being able to make the voltage drop uniform as described above is very effective.

[0141] In particular, for example, in the case where the wiring width needs to be increased due to severe EM or the like, in the case where multiple wirings should be used, etc., by applying the present technology, it is possible to reduce unnecessary wiring area, thereby significantly reducing power consumption. In addition, by applying the present technology to high-frequency wirings such as 1 GHz or more, wirings that are farther away (e.g., more than 3 mm) from the receiver 14 side, etc., it is possible to minimize the wiring width of the wiring on the far side, thereby significantly achieving the effect of suppressing reflection or noise.

[0142] <Configuration Example of Electronic Equipment>

[0143] The wiring shape of each embodiment as described above can be adopted in semiconductor integrated circuits such as imaging elements, signal processing circuits, etc., and can be applied to various electronic devices, for example, imaging systems such as digital still cameras, digital video cameras, etc., mobile phones with imaging functions, or another device with imaging functions.

[0144] Fig.21 is a block diagram showing a configuration example of an imaging device installed in an electronic device.

[0145] like Fig.21As shown, the imaging device 201 includes an optical system 202, an imaging element 203, a signal processing circuit 204, a monitor 205, and a memory 206, and can capture still images and moving images.

[0146] The optical system 202 includes one or more lenses, guides image light (incident light) from a subject to the imaging element 203 , and forms an image on a light receiving surface (sensor unit) of the imaging element 203 .

[0147] The semiconductor integrated circuit that has adopted the above wiring shape is applied to the imaging element 203. In the imaging element 203, electrons are accumulated for a certain period of time according to the image formed on the light receiving surface by the optical system 202. Then, a signal corresponding to the electrons accumulated in the imaging element 203 is supplied to the signal processing circuit 204.

[0148] The semiconductor integrated circuit having the above-described wiring shape is applied to the signal processing circuit 204, and the signal processing circuit 204 performs various signal processing on the pixel signal output from the imaging element 203. The image (image data) obtained by the signal processing performed by the signal processing circuit 204 is supplied to the monitor 205 and displayed on the monitor 205, or supplied to the memory 206 and stored (recorded) in the memory 206.

[0149] In the imaging device 201 configured as described above, for example, by applying a semiconductor integrated circuit adopting the above-described wiring shape, power consumption can be reduced or reliability can be improved.

[0150] <Configuration combination example>

[0151] Note that the present technology may also have the following configurations. (1)

[0153] A semiconductor integrated circuit comprising:

[0154] wiring forming a transmission network through which the same signals are transmitted; and

[0155] The driver that provides the signal to the wiring,

[0156] The wiring has a wiring shape set according to the distance from the driver or the frequency of the signal. (2)

[0158] According to the semiconductor integrated circuit of (1) above,

[0159] The wiring has a set wiring shape such that the wiring width becomes smaller as the distance from the driver increases. (3)

[0161] According to the semiconductor integrated circuit of (1) or (2) above,

[0162] Among them, in the case where a receiver that receives a signal is a complementary metal oxide semiconductor (CMOS), the wiring width of the wiring becomes small to suppress reflection of the signal at the end of the wiring. (4)

[0164] According to the semiconductor integrated circuit of any one of (1) to (3) above,

[0165] The wiring has a set wiring shape so that the wiring width is consistent with the current density of the signal. (5)

[0167] According to the semiconductor integrated circuit of any one of (1) to (4) above,

[0168] wherein the transmission network is formed of a first wiring connected to the driver and having a large wiring width and a plurality of second wirings branched from the first wiring and having a small wiring width, and

[0169] The first wiring has a wiring shape set so that a wiring width of each branch portion of the second wiring becomes smaller as a distance from a connection portion of the driver increases. (6)

[0171] According to the semiconductor integrated circuit of (5) above,

[0172] Among them, the first wiring has a central portion connected to the driver and has a wiring width that becomes smaller so that the resistance increases toward the distal end side. (7)

[0174] According to the semiconductor integrated circuit of (5) or (6) above,

[0175] Here, the first wiring is formed so that the wiring width becomes smaller by a predetermined constant width every constant distance from the connection portion of the driver. (8)

[0177] The semiconductor integrated circuit according to any one of (5) to (7) above,

[0178] The second wiring is formed so that the wiring width becomes smaller by a predetermined constant width every constant distance from the branch portion originating from the first wiring. (9)

[0180] According to the semiconductor integrated circuit of (1) or (2) above,

[0181] Among them, the wiring is a long-distance wiring that connects the driver to the receiver in a single line and has a predetermined distance or longer. (10)

[0183] According to the semiconductor integrated circuit of any one of (1) to (9) above,

[0184] However, when the signal has a high frequency, the wiring has a wiring shape set in a mesh shape by forming a plurality of slits. (11)

[0186] According to the semiconductor integrated circuit of (10) above,

[0187] Among them, the wiring is formed in a mesh shape so that the slits become thinner as the frequency of the signal increases. (12)

[0189] According to the semiconductor integrated circuit of (10) or (11) above,

[0190] Among them, the wiring is a long-distance wiring that connects the driver to the receiver and has a predetermined distance or longer. (13)

[0192] According to the semiconductor integrated circuit of any one of (1) to (12) above,

[0193] The wiring is a power supply wiring for supplying power from a current supply source to a plurality of power consumption sources, and has a wiring shape set so that the wiring width increases as the distance from the current supply source increases. (14)

[0195] According to the semiconductor integrated circuit of (13) above,

[0196] Wherein, each time a power consumption source is connected, the wiring is formed to have a larger wiring width for each of the plurality of power consumption sources. (15)

[0198] According to any one of the semiconductor integrated circuits (1) to (14) above,

[0199] Here, the wiring has a set wiring shape so that the wiring width from the driver to the terminal resistor becomes large, thereby matching the impedance. (16)

[0201] According to the semiconductor integrated circuit of (15) above,

[0202] Here, the wiring width of the wiring increases by a predetermined constant width at every constant distance from the driver. (17)

[0204] An electronic device, comprising:

[0205] Semiconductor integrated circuits, including:

[0206] wiring forming a transmission network through which the same signals are transmitted; and

[0207] The driver that provides the signal to the wiring,

[0208] The wiring has a wiring shape set according to the distance from the driver or the frequency of the signal.

[0209] Note that the present embodiment is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present disclosure. In addition, the effects described in this specification are merely examples and are not limited, and other effects can be provided.

[0210] Reference designator list

[0211] 11 Clock Routing

[0212] 12 Buffer

[0213] 13 Driver

[0214] 14 Receiver

[0215] 15. Driving element

[0216] 31 Clock Routing

[0217] 32 Trunk

[0218] 33 Branch Line

[0219] 34 and 35 connection terminals

[0220] 41 Clock Routing

[0221] 42 Main Line

[0222] 43 branch line

[0223] 44 and 45 connection terminals

[0224] 51 and 52 through electrodes

[0225] 61 Clock Routing

[0226] 62 Long distance wiring

[0227] 63 Through electrode

[0228] 71 Clock Routing

[0229] 72 Long Distance Wiring

[0230] 81 Clock Routing

[0231] 82 Main Line

[0232] 83 branch line

[0233] 84 and 85 connection terminals

[0234] 86 and 87 through electrodes

[0235] 91 Clock Routing

[0236] 92 Main Line

[0237] 93 branch line

[0238] 94 and 95 connection terminals

[0239] 101 Clock Routing

[0240] 102 Long Distance Wiring

[0241] 103 Through electrode

[0242] 111 Clock Routing

[0243] 112 Long Distance Wiring

[0244] 121 Power supply wiring

[0245] 122 Current supply source

[0246] 123 GND Supply source

[0247] 124 VDD Mains

[0248] 125 GND Main Line

[0249] 126 and 127 through electrodes

[0250] 131 Wiring

[0251] 132 Terminal resistor

[0252] 133 Signal line

[0253] 134 Through-electrode

[0254] 141 Wiring

[0255] 142 Wiring resistor

[0256] 143 Wiring.

Claims

1. A semiconductor integrated circuit comprising: wiring forming a transmission network through which the same signals are transmitted; as well as providing the signal to a driver of the wiring, wherein the wiring has a wiring shape set according to a distance from the driver or a frequency of the signal, wherein, when the signal has a high frequency, the wiring has a wiring shape set in a mesh shape by forming a plurality of slits, The wiring is formed in a mesh shape so that the slit becomes thinner as the frequency of the signal increases.

2. The semiconductor integrated circuit according to claim 1, in, The wiring has a wiring shape set so that a wiring width becomes smaller as the distance from the driver increases.

3. The semiconductor integrated circuit according to claim 2, in, In the case where a receiver that receives the signal is a complementary metal oxide semiconductor, the wiring width of the wiring becomes small to suppress reflection of the signal at an end portion of the wiring.

4. The semiconductor integrated circuit according to claim 2, in, The wiring has a wiring shape set so that the wiring width is consistent with the current density of the signal.

5. The semiconductor integrated circuit according to claim 2, in, The transmission network is formed of a first wiring connected to the driver and having a large wiring width and a plurality of second wirings branched from the first wiring and having a small wiring width, and The first wiring has a wiring shape set so that a wiring width of each branch portion of the second wiring becomes smaller as a distance from a connection portion of the driver increases.

6. The semiconductor integrated circuit according to claim 5, in, The first wiring has a central portion connected to the driver, and has a wiring width that becomes smaller so that resistance increases toward a distal end side.

7. The semiconductor integrated circuit according to claim 5, in, The first wiring is formed so that the wiring width becomes smaller by a predetermined constant width every constant distance from the connection portion of the driver.

8. The semiconductor integrated circuit according to claim 5, in, The second wiring is formed so that the wiring width becomes smaller by a predetermined constant width every constant distance from a branch portion originating from the first wiring.

9. The semiconductor integrated circuit according to claim 2, in, The wiring is a long-distance wiring that singly connects the driver to a receiver that receives the signal and has a predetermined distance or longer.

10. The semiconductor integrated circuit according to claim 3, in, The wiring is a long-distance wiring that singly connects the driver to the receiver and has a predetermined distance or longer.

11. An electronic device, comprising: Semiconductor integrated circuits, including: wiring forming a transmission network through which the same signals are transmitted; and providing the signal to a driver of the wiring, wherein the wiring has a wiring shape set according to the distance from the driver or the frequency of the signal, wherein, when the signal has a high frequency, the wiring has a wiring shape set in a mesh shape by forming a plurality of slits, The wiring is formed in a mesh shape so that the slit becomes thinner as the frequency of the signal increases.

Images