Synchronous rectification control circuit compatible with CCM and DCM working modes

Abstract

The present invention discloses a synchronous rectification control circuit compatible with CCM and DCM working modes, comprising a CCM control module, a first negative voltage comparator, a second negative voltage comparator and a logic control module, wherein the CCM control module is connected to the output end of the second negative voltage comparator, the first input end of the first negative voltage comparator and the second input end of the second negative voltage comparator serve as the input end of the synchronous rectification control circuit, the output end of the first negative voltage comparator is connected to the first input end of a first AND gate, the output end of the first AND gate is connected to the first input end of the logic control module, the output end of the second negative voltage comparator is connected to the first input end of a first OR gate, the output end of the first OR gate is connected to the first input end of a second AND gate, the output end of the CCM control module and the output end of the second negative voltage comparator are respectively connected to the first input end and the second input end of a modulation module, and the output end of the second AND gate is connected to the second input end of the logic control module.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and in particular to a synchronous rectification control circuit compatible with CCM and DCM working modes. Background Art

[0002] In recent years, with the rapid development of electronic technology, the size of large-scale integrated circuits has been continuously reduced, and the power consumption has been continuously reduced. The circuit operating voltage required is getting lower and lower, and the operating current is getting higher and higher. The loss of the output rectifier tube is an important part of the switching power supply loss. The traditional rectifier diode has a high conduction voltage drop. Even if a low-voltage drop Schottky diode is used, a voltage drop of more than 0.4V will be generated, resulting in large conduction losses and low power efficiency.

[0003] In view of this, it is necessary to provide a synchronous rectification control circuit that is compatible with CCM and DCM operating modes to effectively reduce rectification conduction losses and improve the efficiency of realizing synchronous rectification. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a synchronous rectification control circuit compatible with CCM and DCM working modes to effectively reduce rectification conduction losses and improve the efficiency of realizing synchronous rectification.

[0005] To solve the above technical problems, the present invention adopts the following technical solution: a synchronous rectification control circuit compatible with CCM and DCM working modes, a CCM control module, a first negative voltage comparator, a second negative voltage comparator and a logic control module, the CCM control module is connected to the output end of the second negative voltage comparator, the first input end of the first negative voltage comparator and the second input end of the second negative voltage comparator serve as the input end of the synchronous rectification control circuit, the output end of the first negative voltage comparator is connected to the first input end of a first AND gate, the output end of the first AND gate is connected to the first input end of the logic control module, the output end of the second negative voltage comparator is connected to the first input end of a first OR gate, the output end of the first OR gate is connected to the first input end of a second AND gate, the output end of the CCM control module and the output end of the second negative voltage comparator are respectively connected to the first input end and the second input end of a modulation module, the output end of the modulation module is connected to the second input end of the second AND gate, and the output end of the second AND gate is connected to the second input end of the logic control module.

[0006] A further technical solution is: the synchronous rectification control circuit also includes an LDO power supply module and a voltage and current bias module, and the voltage and current bias module is connected to the LDO power supply module to generate a reference voltage and a bias current.

[0007] Its further technical solution is: the CCM control module includes a conduction signal modulation unit, the conduction signal modulation unit includes a third negative voltage comparator, a first NMOS tube, a second NMOS tube, a first PMOS tube and a fifth PMOS tube, the drain of the first NMOS tube is connected to a first current source, and its gate is connected to the output end of an NOR gate, the output end of the modulation module is connected to the first input end of the NOR gate through a first delay device, the output end of the modulation module is connected to the second input end of the NOR gate, the source of the first NMOS tube is connected to the second input end of the third negative voltage comparator, the output end of the third negative voltage comparator is used as the output end of the CCM control module, and its first input end is connected to the second The drain of the first NMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is grounded, and the gate thereof is connected to the output end of an inverting amplifier, the input end of the inverting amplifier is connected to the output end of the second negative voltage comparator, a second capacitor is connected in parallel between the source and the drain of the second NMOS tube, the source of the first PMOS tube is connected to a second current source, the drain thereof is connected to the drain of the second NMOS tube, and the gate thereof is connected to the output end of the inverting amplifier, the source of the fifth PMOS tube is connected to the source of the first NMOS tube, and the drain thereof is connected to the output end of a second operational amplifier, a first capacitor is connected between the source and the drain of the fifth PMOS tube, and the inverting input end of the second operational amplifier is connected to the drain of the fifth PMOS tube.

[0008] Its further technical solution is: the CCM control module also includes an abnormal shielding unit, which is connected to the conduction signal modulation unit, including a D trigger, a pulse modulator, a second delay, a third NMOS tube and a second PMOS tube, the gate of the fifth PMOS tube is connected to the reset input terminal of the D trigger through the second delay, the clock input terminal of the D trigger is connected to the output terminal of the second negative voltage comparator, the first input terminal of the D trigger is connected to the output terminal of the modulation module, the first output terminal of the D trigger is connected to the gate of the fifth PMOS tube through the pulse modulator, the gate of the second PMOS tube is connected to the gate of the fifth PMOS tube, its source is connected to the non-inverting input terminal of the second operational amplifier, and its drain is connected to the drain of the third NMOS tube. A grounding capacitor is connected in parallel between the source of the second PMOS tube and the non-inverting input terminal of the second operational amplifier, the gate of the third NMOS tube is connected to the gate of the fifth PMOS tube, and its source is grounded, and a fourth capacitor is connected between the drain and source of the third NMOS tube.

[0009] Its further technical solution is: the CCM control module also includes an abnormal shielding unit, which is connected to the conduction signal modulation unit, including a D trigger, a pulse modulator, a second delay, a third delay, a first operational amplifier, a third PMOS tube, a fourth PMOS tube and a fourth NMOS tube, the gate of the fifth PMOS tube is connected to the reset input terminal of the D trigger via the second delay, the clock input terminal of the D trigger is connected to the output terminal of the second negative voltage comparator, the first input terminal of the D trigger is connected to the output terminal of the modulation module, the first output terminal of the D trigger is connected to the gate of the third PMOS tube via the pulse modulator, the drain of the third PMOS tube is connected to the in-phase input terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the fourth PMOS The source of the transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the non-inverting input terminal of the second operational amplifier, and the gate thereof is connected to the gate of the fifth PMOS transistor. A grounded capacitor is connected in parallel between the drain of the fourth PMOS transistor and the non-inverting input terminal of the second operational amplifier. The inverting input terminal of the first operational amplifier is connected to its output terminal. The source of the third PMOS transistor is connected to the source of the fourth NMOS transistor, and a fifth capacitor with one end grounded is connected in parallel between the source of the third PMOS tube and the source of the fourth NMOS tube. The drain of the fourth NMOS tube is connected to a third current source, and the gate thereof is connected to the output terminal of a third AND gate. The output terminal of the second negative voltage comparator is connected to the first input terminal of the third AND gate, and the output terminal of the second negative voltage comparator is connected to the second input terminal of the third AND gate via the third delay device.

[0010] Its further technical solution is: when the synchronous rectification control circuit is used for a flyback switching power supply, the output voltage of the flyback switching power supply is used as the power supply voltage of the synchronous rectification control circuit, the input end of the synchronous rectification control circuit is connected to the drain of the synchronous rectification MOS tube of the flyback switching power supply, the output end of the logic control module is connected to the gate of the synchronous rectification MOS tube, and the source of the synchronous rectification MOS tube is grounded.

[0011] The beneficial technical effect of the present invention is that the synchronous rectification control circuit compatible with CCM and DCM working modes of the present invention adjusts the signal output through the first negative voltage comparator in conjunction with the first AND gate and the second negative voltage comparator in conjunction with the first OR gate and the second AND gate, combined with the CCM control module and the modulation module to expand the maximum conduction time of the signal to achieve extremely small dead time control, and then uses the logic control module for logic control, effectively reducing the rectification conduction loss, achieving high efficiency of synchronous rectification, and also realizing synchronous rectification under the current continuous conduction mode CCM. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is an application topological structure diagram of the synchronous rectification control circuit of the present invention which is compatible with CCM and DCM working modes.

[0013] Figure 2 It is a signal timing diagram of the synchronous rectification control circuit compatible with CCM and DCM working modes of the present invention working in current discontinuous DCM.

[0014] Figure 3 It is a signal timing diagram of a synchronous rectification control circuit compatible with CCM and DCM working modes of the present invention working in current discontinuous CCM.

[0015] Figure 4 It is a circuit schematic diagram of a specific embodiment of a CCM control module of a synchronous rectification control circuit compatible with CCM and DCM working modes of the present invention.

[0016] Figure 5 It is a circuit schematic diagram of another specific embodiment of a CCM control module of a synchronous rectification control circuit compatible with CCM and DCM working modes of the present invention. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to more clearly understand the objectives, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0018] Reference Figures 1 to 5 , Figure 1 The topological structure diagram of the synchronous rectification control circuit 10 compatible with CCM and DCM working modes of the present invention is applied to a flyback switching power supply, wherein the flyback switching power supply includes a transformer T, an input terminal V in , voltage output terminal V out , input capacitor C in , primary MOS tube M N , sampling resistor R sense , synchronous rectifier MOS tube M0 and output capacitor C out , the input terminal V in The positive electrode is connected to one end of the primary of the transformer T, and the negative electrode is grounded. The other end of the primary of the transformer T is connected to the primary MOS tube M N The drain of the primary MOS tube M N The source of the sense After grounding, the primary MOS tube M N The gate is used to receive the primary control signal Duty, the input capacitor C in The two ends of the in The positive and negative electrodes of the transformer T are connected, and one end of the secondary of the transformer T is connected to the voltage output terminal V outThe positive electrode of the synchronous rectifier MOS tube M0 is connected to the positive electrode of the synchronous rectifier MOS tube M0, and the other end is connected to the drain of the synchronous rectifier MOS tube M0. out The negative electrode of the output capacitor C out The synchronous rectification control circuit 10 compatible with CCM and DCM working modes includes a CCM control module CCM_CONTROL, a first negative voltage comparator CM1, a second negative voltage comparator CM2 and a logic control module LOGIC. The CCM control module CCM_CONTROL is connected to the output end of the second negative voltage comparator CM2 to adjust and control the maximum on-time signal T ONMAX , to adjust the maximum conduction time of the synchronous rectification MOS tube M0, the first input end of the first negative voltage comparator CM1 and the second input end of the second negative voltage comparator CM2 are used as the input end of the synchronous rectification control circuit 10, the output end of the first negative voltage comparator CM1 is connected to the first input end of a first AND gate AND1, the output end of the first AND gate AND1 is connected to the first input end of the logic control module LOGIC, the output end of the second negative voltage comparator CM2 is connected to the first input end of a first OR gate OR1, the output end of the first OR gate OR1 is connected to the first input end of a second AND gate AND2, the output end of the CCM control module CCM_CONTROL and the output end of the second negative voltage comparator CM2 are respectively connected to the first input end and the second input end of a modulation module 12, the output end of the modulation module 12 is connected to the second input end of the second AND gate AND2, and the output end of the second AND gate AND2 is connected to the second input end of the logic control module LOGIC. The output voltage of the flyback switching power supply is used as the power supply voltage Vdd of the synchronous rectification control circuit 10. The input end of the synchronous rectification control circuit 10 is connected to the drain of the synchronous rectification MOS tube M0 of the flyback switching power supply. The first input end of the first negative voltage comparator CM1 and the second input end of the second negative voltage comparator CM2 are connected to the drain of the synchronous rectification MOS tube M0. The output end of the logic control module LOGIC is connected to the gate of the synchronous rectification MOS tube M0. The source of the synchronous rectification MOS tube M0 is grounded.

[0019] The second input terminal of the first OR gate OR1 receives the minimum on-time signal T ONMIN The second input terminal of the first AND gate AND1 receives the minimum off time signal T OFFMIN The second input terminal of the second AND gate AND2 receives the maximum continuous conduction time signal TC ONMAXThe synchronous rectification control circuit 10 compatible with CCM and DCM working modes adjusts the signal output by using the first negative voltage comparator CM1, the first AND gate AND1, the second negative voltage comparator CM2, the first OR gate OR1, and the second AND gate AND2, combined with the CCM control module CCM_CONTROL and the modulation module 12 to expand the maximum on-time of the signal to achieve extremely small dead time control, and then uses the logic control module LOGIC for logic control, effectively reducing the rectification conduction loss, achieving high efficiency of synchronous rectification, and also realizing synchronous rectification under the current continuous conduction mode CCM. Among them, the maximum on-time signal T ONMAX is the output signal of the CCM control module CCM_CONTROL, which is used to control the maximum conduction time of the synchronous rectifier MOS tube M0, and is consistent with the output signal T of the second negative voltage comparator CM2. B The maximum continuous conduction time signal TC is obtained by modulation through a modulation module 12 ONMAX , in order to adjust the maximum continuous conduction time of the synchronous rectifier MOS tube M0, effectively adjusting the dead time T DEAD When the maximum on-time signal T ONMAX When the high level drops to the low level, the maximum continuous conduction time signal TC ONMAX The high level of the second negative voltage comparator CM2 drops to a low level. At this time, if the output signal T B The high level drops to the low level, then the maximum continuous conduction time signal TC ONMAX The low level will rise to a high level, and the maximum continuous conduction time signal TC ONMAX The time it takes to become a low level is the dead time T DEAD The minimum on-time signal T ONMIN It is used to limit the synchronous rectification MOS tube M0 to be turned on for at least a corresponding time before it can be turned off. The minimum turn-off time signal T OFFMIN It is used to limit the synchronous rectification MOS tube M0 to be closed and turned on at least for a corresponding time. The minimum conduction time signal T ONMIN and the minimum off time signal T OFFMIN All are controlled by internal chip settings. Preferably, in this embodiment, the minimum on-time signal T ONMIN When the level drops from high level to low level, the shutdown restriction of the synchronous rectifier MOS tube M0 is released, and the minimum shutdown time signal T OFFMIN When the low level rises to the high level, the conduction restriction of the synchronous rectifier MOS tube M0 is released, and the maximum continuous conduction time signal TC ONMAX When the level drops from a high level, the restriction on the shutdown of the synchronous rectification MOS tube M0 is released.

[0020] Specifically, in this embodiment, the synchronous rectification control circuit 10 further includes an LDO power supply module LDO1 and a voltage and current bias module 11. The input terminal of the LDO power supply module LDO1 is connected to the voltage output terminal V out The voltage and current bias module 11 is connected to the output end of the LDO power supply module LDO1 to use the output voltage of the flyback switching power supply as the power supply voltage Vdd of the synchronous rectification control circuit 10 to generate a reference voltage V ref and bias current I bias .

[0021] Reference Figure 2 , Figure 2 The signal timing diagram of the synchronous rectification control circuit 10 working in the current discontinuous conduction mode DCM is shown. When working, the primary MOS tube M N Turn off, secondary current I S Linearly decrease, the drain voltage V of the synchronous rectifier MOS tube M0 D Rapidly decreases when V D When the voltage is lower than -80mV, the output signal T of the first negative voltage comparator CM1 A From low to high, and after an internal transmission delay △T, the synchronous rectifier MOS tube M0 is turned on. At this time, the gate voltage V G The value of is Vdd. Due to the existence of the turn-on delay, the drain voltage V D The signal is maintained for a short period of -V F After the level rises, V F is the conduction value of the body diode of the synchronous rectifier MOS tube M0. When the drain voltage V D When it rises to -30mV, the gate voltage V of the synchronous rectifier MOS tube M0 is controlled by the logic control module LOGIC G The drain voltage V D The output signal T of the first negative voltage comparator CM1 can be maintained at slightly lower than -30mV for a long time. A After a low pulse, it is high, and the output signal T of the second negative voltage comparator CM2 is B The drain voltage V of the synchronous rectifier MOS tube M0 is D After falling below -4mV, it remains high. S When the drain voltage V of the synchronous rectifier MOS tube M0 decreases continuously and approaches 0, D The output signal T of the first negative voltage comparator CM1 will be higher than -4mV. A and the output signal T of the second negative voltage comparator CM2 BThen it turns low, and the gate voltage V G The synchronous rectifier MOS tube M0 is turned off. During the entire DCM mode operation, the maximum on-time signal T output by the CCM control module CCM_CONTROL is ONMAX Always high, and the maximum continuous conduction time signal TC ONMAX It is always high and has no control effect. Among them, -80mV, -30mV and -4mV are the preferred values ​​of reference voltage. In DCM mode, the dead time T DEAD is the output signal T of the first negative voltage comparator CM1 A and the output signal T of the second negative voltage comparator CM2 B When both drop from high level to low level, the secondary current I S The time period ends when the value drops to 0.

[0022] Reference Figure 3 , Figure 3 The signal timing diagram of the synchronous rectification control circuit 10 working in the current continuous conduction mode CCM is shown. When working, the primary MOS tube M N Turn off, secondary current I S Linearly decrease, the drain voltage V of the synchronous rectifier MOS tube M0 D Rapidly decreases when V D When the voltage is lower than -80mV, the output signal T of the first negative voltage comparator CM1 A From low to high, and after an internal transmission delay △T, the synchronous rectifier MOS tube M0 is turned on. At this time, the gate voltage V G The value of is Vdd. Due to the existence of the turn-on delay, the drain voltage V D The signal is maintained for a short period of -V F After the level rises, V F is the conduction value of the body diode of the synchronous rectifier MOS tube M0. When the drain voltage V D When it rises to -30mV, the gate voltage V of the synchronous rectifier MOS tube M0 is controlled by the logic control module LOGIC G The drain voltage V D The output signal T of the first negative voltage comparator CM1 can be maintained at slightly lower than -30mV for a long time. A After a low pulse, the output signal T of the second negative voltage comparator CM2 is high. B The drain voltage V of the synchronous rectifier MOS tube M0 is D After falling below -4mV, it remains high, and the maximum continuous conduction time signal TC ONMAX The maximum on-time is set by the initial The maximum on-time signal T output by the CCM control module CCM_CONTROL is followed ONMAX Flips to low and immediately pulls down the gate voltage V of the synchronous rectifier MOS tube M0 G To 0, turn off the synchronous rectifier MOS tube M0, and then after the initial dead time After that, the primary MOS tube M N conduction, secondary current I S Turn off, the drain voltage V D Rapidly rises and is greater than -4mV, the output signal T of the first negative voltage comparator CM1 A The output signal T of the second negative voltage comparator CM2 B Both turn low, the maximum continuous on-time signal TC ONMAX Pull high to complete the primary MOS tube M of this cycle N The CCM control module CCM_CONTROL in the CCM working mode plays the role of adaptively increasing the maximum on-time of the signal. When the system is working stably, the demagnetization time is fixed and the maximum on-time of the signal is Increase the dead time Where N represents the primary MOS tube M N The number of cycles of the state change, that is, the primary MOS tube M N From off to on is a cycle. -80mV, -30mV and -4mV are the preferred values ​​for reference voltage. Dead time The maximum continuous conduction time signal TC ONMAX Low level time.

[0023] Reference Figure 4 , Figure 4The circuit schematic diagram of a specific embodiment of the CCM control module is shown. The CCM control module 11 includes a conduction signal modulation unit BLOCKA, which includes a third negative voltage comparator CM3, a first NMOS tube MN1, a second NMOS tube MN2, a first PMOS tube MP1 and a fifth PMOS tube MP5. The drain of the first NMOS tube MN1 is connected to a first current source I1, and its gate is connected to the output end of a NOR gate NOR1. The output end of the modulation module 12 is connected to the first input end of the NOR gate NOR1 through a first delay device Delay1, and the output end of the modulation module 12 is connected to the second input end of the NOR gate NOR1. The source of the first NMOS tube MN1 is connected to the second input end of the third negative voltage comparator CM3. The output end of the third negative voltage comparator CM3 serves as the output end of the CCM control module CCM_CONTROL to output the maximum conduction time signal T ONMAX The first input terminal of the third negative voltage comparator CM3 is connected to the drain of the second NMOS tube MN2, the source of the second NMOS tube MN2 is grounded, and the gate thereof is connected to the output terminal of an inverting amplifier INV1, the input terminal of the inverting amplifier INV1 is connected to the output terminal of the second negative voltage comparator CM2, a second capacitor C2 is connected in parallel between the source and the drain of the second NMOS tube MN2, the source of the first PMOS tube MP1 is connected to a second current source I2, the drain of the first PMOS tube MP1 is connected to the drain of the second NMOS tube MN2, and the gate thereof is connected to the output terminal of the inverting amplifier INV1, the source of the fifth PMOS tube MP5 is connected to the source of the first NMOS tube MN1, and the drain of the fifth PMOS tube MP5 is connected to the output terminal of a second operational amplifier OP2, a first capacitor C1 is connected between the source and the drain of the fifth PMOS tube MP5, and the inverting input terminal of the second operational amplifier OP2 is connected to the drain of the fifth PMOS tube MP5.

[0024] The CCM control module CCM_CONTROL also includes an abnormal shielding unit BLOCKB, which is connected to the conduction signal modulation unit BLOCKA, including a D flip-flop DFF1, a pulse modulator Pulse1, a second delay device Delay2, a third NMOS tube MN3 and a second PMOS tube MP2, the gate of the fifth PMOS tube MP5 is connected to the reset input terminal of the D flip-flop DFF1 through the second delay device, the clock input terminal of the D flip-flop DFF1 is connected to the output terminal of the second negative voltage comparator CM2, the first input terminal of the D flip-flop DFF1 is connected to the output terminal of the modulation module 12, and the D The first output end of the trigger DFF1 is connected to the gate of the fifth PMOS tube MP5 via the pulse modulator Pulse1, the gate of the second PMOS MP2 is connected to the gate of the fifth PMOS tube MP5, its source is connected to the non-inverting input end of the second operational amplifier OP2, and its drain is connected to the drain of the third NMOS tube MN3, a grounding capacitor C3 is connected in parallel between the source of the second PMOS tube MP2 and the non-inverting input end of the second operational amplifier OP2, the gate of the third NMOS tube MN3 is connected to the gate of the fifth PMOS tube MP5, and its source is grounded, and a fourth capacitor C4 is connected between the drain and source of the third NMOS tube MN3.

[0025] When working, it is assumed that the input signal of the non-inverting input terminal of the second operational amplifier OP2 is V REF1 , the input signal of the first input terminal of the third negative voltage comparator CM3 is Where n represents the maximum continuous conduction time signal TC ONMAX The number of times the high level drops to the low level, initially, That is, the input signal of the first input terminal of the third negative voltage comparator CM3 and the input signal of the in-phase input terminal of the second operational amplifier OP2 are both initially set to be the reference voltage. n represents the number of times the output signal of the second negative voltage comparator CM2 drops from a high level to a low level. In the CCM mode, during the conduction period of the first synchronous rectifier MOS tube M0, the input signal of the second input terminal of the third negative voltage comparator CM3 is initially It can be expressed by formula (1):

[0026]

[0027] At this time, the output signal of the CCM control module CCM_CONTROL It can be expressed by formula (2):

[0028]

[0029] Combination Figure 3 , maximum continuous conduction signal TC ONMAX The falling edge of the output signal T of the second negative voltage comparator CM2 B The time difference between the falling edges of Then, during the conduction period of the first synchronous rectifier MOS tube M0, the charging time of the first current source I1 on the first capacitor C1 is It can be expressed by formula (3):

[0030]

[0031] Wherein, Td1 represents the delay time of the first delay device Delay1, is the first dead time, Indicates the first charging time. At this time, the input signal of the second input terminal of the third negative voltage comparator CM3 is It can be expressed by formula (4):

[0032]

[0033] Then, during the conduction period of the second synchronous rectifier MOS tube M0, the output signal of the CCM control module CCM_CONTROL It can be expressed by formula (5):

[0034]

[0035] When the system is working stably, the secondary demagnetization time remains constant, and the output signal T of the second negative voltage comparator CM2 is B The duration of the high level remains unchanged, so the dead time at this time can be obtained It can be expressed by formula (6):

[0036]

[0037] in, is the second dead time, Td1 represents the delay time of the first delay device Delay1, is the first dead time, Indicates the first charging time. Assume Then, during the conduction period of the second synchronous rectifier MOS tube M0, the charging time of the first current source I1 on the first capacitor C1 is It can be expressed by formula (7):

[0038]

[0039] Wherein, Td1 represents the delay time of the first delay device Delay1, is the first dead time, Indicates the first charging time. is the second dead time, Indicates the second charging time. At this time, the input signal of the second input terminal of the third negative voltage comparator CM3 is It can be expressed by formula (8):

[0040]

[0041] During the conduction cycle of the third synchronous rectifier MOS tube M0, the output signal of the CCM control module CCM_CONTROL is It can be expressed by formula (9):

[0042]

[0043] When the system is working stably, the secondary demagnetization time remains constant, and the output signal T of the second negative voltage comparator CM2 is B The duration of the high level remains unchanged, so the dead time at this time can be obtained It can be expressed by formula (10):

[0044]

[0045] in, is the third dead time, Td1 represents the delay time of the first delay device Delay1, During the conduction period of the third synchronous rectifier MOS tube M0, the charging time of the first current source I1 on the first capacitor C1 is It can be expressed by formula (11):

[0046]

[0047] Wherein, Td1 represents the delay time of the first delay device Delay1, is the first dead time, Indicates the first charging time. This is the third dead time.

[0048] At this time, the input signal of the second input terminal of the third negative voltage comparator CM3 is It can be expressed by formula (12):

[0049]

[0050] in, Indicates the first charging time, Indicates the second charging time. Indicates the third charging time.

[0051] During the conduction cycle of the fourth synchronous rectifier MOS tube M0, the output signal of the CCM control module CCM_CONTROL is It can be expressed by formula (13):

[0052]

[0053] When the system is working stably, the secondary demagnetization time remains constant, and the output signal T of the second negative voltage comparator CM2 is B The duration of the high level remains unchanged, so the dead time at this time can be obtained It can be expressed by formula (14):

[0054]

[0055] in, is the fourth dead time, Td1 represents the delay time of the first delay device Delay1, This is the first dead time.

[0056] By analogy, the n+1th dead time It can be expressed by formula (15):

[0057]

[0058] Among them, (1-K1) n-1 represents (1-K1) raised to the power of n-1. Then the n+1th dead time is It can be expressed by formula (16):

[0059]

[0060] Assume that the maximum continuous conduction time signal TC ONMAX The delay from the falling edge of to the shutdown of the synchronous rectifier MOS tube M0 is T OFF1 , primary MOS tube M N Open the output signal T to the second negative pressure comparator CM2 B The delay of the falling edge is T OFF2 , then the turn-off delay of the common synchronous rectifier chip can be expressed by formula (17):

[0061] T OFF =T OFF1 +T OFF2 (17)

[0062] The delay time Td1 of the first delay device Delay1 of the CCM control module CCM_CONTROL of the present invention is controlled OFF , the synchronous rectifier MOS tube M0 can be turned off and the primary MOS tube M NThe conduction is synchronized to achieve high efficiency and high performance.

[0063] Under abnormal conditions, the output signal T of the second negative voltage comparator CM2 is B The falling edge of the signal is earlier than the preset maximum continuous conduction time signal TC. ONMAX The falling edge of the clock signal may be in DCM mode or CCM mode.

[0064] Combination Figure 4 , maximum continuous conduction time signal TC ONMAX is high level, the output signal T of the second negative voltage comparator CM2 B The falling edge of trigger triggers the first output terminal of D flip-flop DFF1 to flip from low level to high level, and then generates a low pulse. This low pulse controls the D flip-flop DFF1 to reset after the delay time Td2 of the second delay device Delay2. At the same time, the low pulse connects the third capacitor C3 and the fourth capacitor C4. After the charges on the third capacitor C3 and the fourth capacitor C4 are balanced, the input signal of the non-inverting input terminal of the second operational amplifier OP2 It can be expressed by formula (18):

[0065]

[0066] Then we know that V REF1 Primary decay times, the maximum on-time signal T ONMAX It also decays, and each abnormal detection will make V REF1 attenuation times until the maximum continuous conduction time signal TC ONMAX The falling edge of the output signal T of the second negative voltage comparator CM2 is earlier than B The falling edge of the synchronous rectification control circuit 10 is detected and enters the operating range of the conduction signal modulation unit BLOCKA. At this time, the synchronous rectification control circuit 10 can work efficiently in both CCM mode and DCM mode.

[0067] Reference Figure 5 , Figure 5 The circuit schematic diagram of another specific embodiment of the CCM control module is shown. The abnormal shielding unit BLOCKB of the CCM control module 11 is connected to Figure 4The embodiments shown are different, and their conduction signal modulation units BLOCKA are the same. In this embodiment, the abnormal shielding unit BLOCKB includes a D flip-flop DFF1, a pulse modulator Pulse1, a second delay device Delay2, a third delay device Delay3, a first operational amplifier OP1, a third PMOS tube MP3, a fourth PMOS tube MP4 and a fourth NMOS tube MN4. The gate of the fifth PMOS tube MP5 is connected to the reset input terminal of the D flip-flop DFF1 via the second delay device Delay2, the clock input terminal of the D flip-flop DFF1 is connected to the output terminal of the second negative voltage comparator CM2, the first input terminal of the D flip-flop DFF1 is connected to the output terminal of the modulation module 12, the first output terminal of the D flip-flop DFF1 is connected to the gate terminal of the third PMOS tube MP3 via the pulse modulator Pulse1, the drain of the third PMOS tube MP3 is connected to the non-inverting input terminal of the first operational amplifier OP1, and the output terminal of the first operational amplifier OP1 is connected to the output terminal of the modulation module 12. The first operational amplifier OP1 is connected to the output terminal thereof, the inverting input terminal thereof is connected to the output terminal thereof, the source of the third PMOS tube MP3 is connected to the source of the fourth NMOS tube MN4, and a fifth capacitor C5 with one end grounded is connected in parallel between the source of the third PMOS tube MP3 and the source of the fourth NMOS tube MN4, the drain of the fourth NMOS tube MN4 is connected to a third current source I3, and the gate thereof is connected to the output terminal of a third AND gate AND3, the output terminal of the second negative voltage comparator CM2 is connected to the first input terminal of the third AND gate AND3, and the output terminal of the second negative voltage comparator CM2 is connected to the second input terminal of the third AND gate AND3 via the third delay device Delay3.

[0068] Combination Figure 5 , maximum continuous conduction time signal TC ONMAX is high level, the output signal T of the second negative voltage comparator CM2 B The falling edge of trigger triggers the first output terminal of the D flip-flop DFF1 to flip from a low level to a high level, and then generates a low pulse. At this time, the third current source I3 charges the fifth capacitor C5, and the charging time is the secondary demagnetization time minus the delay time Td1 of the first delay device Delay1, which is the output signal T of the second negative voltage comparator CM2. B =The duration of the high level minus the delay time Td1 of the first delay device Delay1, then the charging time T of the fifth capacitor C5 is CHC5It can be expressed by formula (19):

[0069] T CHC5 =T BH -Td1 (19)

[0070] Among them, T BH represents the output signal T of the second negative voltage comparator CM2 B The voltage V on the fifth capacitor C5 is C5 It can be expressed by formula (20):

[0071]

[0072] And the voltage V on the fifth capacitor C5 C5 is transmitted to the non-inverting input terminal of the second operational amplifier OP2, then V REF1 =V C5 , let I3=I2, C5=C2; then the maximum on-time signal T of the next cycle ONMAX It can be expressed by formula (21):

[0073] T ONMAX =T BH -Td1 (21)

[0074] At this time, the operating range of the conduction signal modulation unit BLOCKA is entered in one step, so that the synchronous rectification control circuit 10 can work efficiently in the CCM mode or the DCM mode more quickly, and the system efficiency is better.

[0075] In summary, the synchronous rectification control circuit compatible with CCM and DCM working modes of the present invention adjusts the signal output through the first negative voltage comparator cooperates with the first AND gate and the second negative voltage comparator cooperates with the first OR gate and the second AND gate, combines the CCM control module and the modulation module to expand the maximum conduction time of the signal to achieve extremely small dead time control, and then uses the logic control module to perform logic control, effectively reducing the rectification conduction loss, achieving high efficiency of synchronous rectification, and also realizing synchronous rectification under the current continuous conduction mode CCM.

[0076] The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Those skilled in the art can make various equivalent changes and improvements based on the above embodiments, and all equivalent changes or modifications made within the scope of the claims should fall within the protection scope of the present invention.

Claims

1. A synchronous rectification control circuit compatible with CCM and DCM working modes, characterized in that: It includes a CCM control module, a first negative voltage comparator, a second negative voltage comparator and a logic control module, wherein the CCM control module is connected to the output end of the second negative voltage comparator, the first input end of the first negative voltage comparator and the second input end of the second negative voltage comparator serve as the input end of the synchronous rectification control circuit, the output end of the first negative voltage comparator is connected to the first input end of a first AND gate, the output end of the first AND gate is connected to the first input end of the logic control module, the output end of the second negative voltage comparator is connected to the first input end of a first OR gate, the output end of the first OR gate is connected to the first input end of a second AND gate, the output end of the CCM control module and the output end of the second negative voltage comparator are respectively connected to the first input end and the second input end of a modulation module, the output end of the modulation module is connected to the second input end of the second AND gate, and the output end of the second AND gate is connected to the second input end of the logic control module; The synchronous rectification control circuit further includes an LDO power supply module and a voltage and current bias module, wherein the voltage and current bias module is connected to the LDO power supply module to generate a reference voltage and a bias current; The CCM control module includes a conduction signal modulation unit, which includes a third negative voltage comparator, a first NMOS tube, a second NMOS tube, a first PMOS tube and a fifth PMOS tube. The drain of the first NMOS tube is connected to a first current source, and the gate thereof is connected to the output end of an NOR gate. The output end of the modulation module is connected to the first input end of the NOR gate through a first delay device, and the output end of the modulation module is connected to the second input end of the NOR gate. The source of the first NMOS tube is connected to the second input end of the third negative voltage comparator. The output end of the third negative voltage comparator serves as the output end of the CCM control module, and the first input end thereof is connected to the second NMOS tube. The source of the second NMOS tube is grounded, and the gate thereof is connected to the output end of an inverting amplifier. The input end of the inverting amplifier is connected to the output end of the second negative voltage comparator. A second capacitor is connected in parallel between the source and the drain of the second NMOS tube. The source of the first PMOS tube is connected to a second current source, and the drain thereof is connected to the drain of the second NMOS tube. The gate thereof is connected to the output end of the inverting amplifier. The source of the fifth PMOS tube is connected to the source of the first NMOS tube, and the drain thereof is connected to the output end of a second operational amplifier. A first capacitor is connected between the source and the drain of the fifth PMOS tube. The inverting input end of the second operational amplifier is connected to the drain of the fifth PMOS tube. The CCM control module also includes an abnormal shielding unit, which is connected to the conduction signal modulation unit and includes a D trigger, a pulse modulator, a second delayer, a third NMOS tube and a second PMOS tube. The gate of the fifth PMOS tube is connected to the reset input terminal of the D trigger via the second delayer, the clock input terminal of the D trigger is connected to the output terminal of the second negative voltage comparator, the first input terminal of the D trigger is connected to the output terminal of the modulation module, the first output terminal of the D trigger is connected to the gate of the fifth PMOS tube via the pulse modulator, the gate of the second PMOS tube is connected to the gate of the fifth PMOS tube, the source of the second PMOS tube is connected to the in-phase input terminal of the second operational amplifier, the drain of the second PMOS tube is connected to the drain of the third NMOS tube, a grounding capacitor is connected in parallel between the source of the second PMOS tube and the in-phase input terminal of the second operational amplifier, the gate of the third NMOS tube is connected to the gate of the fifth PMOS tube, the source of the third NMOS tube is grounded, and a fourth capacitor is connected between the drain and source of the third NMOS tube.

2. The synchronous rectification control circuit compatible with CCM and DCM working modes as claimed in claim 1, characterized in that: When the synchronous rectification control circuit is used for a flyback switching power supply, the output voltage of the flyback switching power supply is used as the power supply voltage of the synchronous rectification control circuit, the input end of the synchronous rectification control circuit is connected to the drain of the synchronous rectification MOS tube of the flyback switching power supply, the output end of the logic control module is connected to the gate of the synchronous rectification MOS tube, and the source of the synchronous rectification MOS tube is grounded.

3. A synchronous rectification control circuit compatible with CCM and DCM working modes, characterized in that: It includes a CCM control module, a first negative voltage comparator, a second negative voltage comparator and a logic control module, wherein the CCM control module is connected to the output end of the second negative voltage comparator, the first input end of the first negative voltage comparator and the second input end of the second negative voltage comparator serve as the input end of the synchronous rectification control circuit, the output end of the first negative voltage comparator is connected to the first input end of a first AND gate, the output end of the first AND gate is connected to the first input end of the logic control module, the output end of the second negative voltage comparator is connected to the first input end of a first OR gate, the output end of the first OR gate is connected to the first input end of a second AND gate, the output end of the CCM control module and the output end of the second negative voltage comparator are respectively connected to the first input end and the second input end of a modulation module, the output end of the modulation module is connected to the second input end of the second AND gate, and the output end of the second AND gate is connected to the second input end of the logic control module; The synchronous rectification control circuit further includes an LDO power supply module and a voltage and current bias module, wherein the voltage and current bias module is connected to the LDO power supply module to generate a reference voltage and a bias current; The CCM control module includes a conduction signal modulation unit, which includes a third negative voltage comparator, a first NMOS tube, a second NMOS tube, a first PMOS tube and a fifth PMOS tube. The drain of the first NMOS tube is connected to a first current source, and the gate thereof is connected to the output end of an NOR gate. The output end of the modulation module is connected to the first input end of the NOR gate through a first delay device, and the output end of the modulation module is connected to the second input end of the NOR gate. The source of the first NMOS tube is connected to the second input end of the third negative voltage comparator. The output end of the third negative voltage comparator serves as the output end of the CCM control module, and the first input end thereof is connected to the second NMOS tube. The source of the second NMOS tube is grounded, and the gate thereof is connected to the output end of an inverting amplifier. The input end of the inverting amplifier is connected to the output end of the second negative voltage comparator. A second capacitor is connected in parallel between the source and the drain of the second NMOS tube. The source of the first PMOS tube is connected to a second current source, and the drain thereof is connected to the drain of the second NMOS tube. The gate thereof is connected to the output end of the inverting amplifier. The source of the fifth PMOS tube is connected to the source of the first NMOS tube, and the drain thereof is connected to the output end of a second operational amplifier. A first capacitor is connected between the source and the drain of the fifth PMOS tube. The inverting input end of the second operational amplifier is connected to the drain of the fifth PMOS tube. The CCM control module also includes an abnormal shielding unit, which is connected to the conduction signal modulation unit and includes a D trigger, a pulse modulator, a second delay, a third delay, a first operational amplifier, a third PMOS tube, a fourth PMOS tube and a fourth NMOS tube. The gate of the fifth PMOS tube is connected to the reset input terminal of the D trigger via the second delay, the clock input terminal of the D trigger is connected to the output terminal of the second negative voltage comparator, the first input terminal of the D trigger is connected to the output terminal of the modulation module, the first output terminal of the D trigger is connected to the gate of the third PMOS tube via the pulse modulator, the drain of the third PMOS tube is connected to the in-phase input terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the source terminal of the fourth PMOS tube. The drain of the fourth PMOS tube is connected to the non-inverting input terminal of the second operational amplifier, and the gate thereof is connected to the gate of the fifth PMOS tube. A grounded capacitor is connected in parallel between the drain of the fourth PMOS tube and the non-inverting input terminal of the second operational amplifier. The inverting input terminal of the first operational amplifier is connected to its output terminal. The source of the third PMOS tube is connected to the source of the fourth NMOS tube, and a fifth capacitor with one end grounded is connected in parallel between the source of the third PMOS tube and the source of the fourth NMOS tube. The drain of the fourth NMOS tube is connected to a third current source, and the gate thereof is connected to the output terminal of a third AND gate. The output terminal of the second negative voltage comparator is connected to the first input terminal of the third AND gate, and the output terminal of the second negative voltage comparator is connected to the second input terminal of the third AND gate via the third delay device.

4. The synchronous rectification control circuit compatible with CCM and DCM working modes as claimed in claim 3, characterized in that: When the synchronous rectification control circuit is used for a flyback switching power supply, the output voltage of the flyback switching power supply is used as the power supply voltage of the synchronous rectification control circuit, the input end of the synchronous rectification control circuit is connected to the drain of the synchronous rectification MOS tube of the flyback switching power supply, the output end of the logic control module is connected to the gate of the synchronous rectification MOS tube, and the source of the synchronous rectification MOS tube is grounded.

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