Method for manufacturing semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first major surface of a semiconductor substrate. Forming a metal-containing photoresist layer over the first major surface of the semiconductor substrate. Removing the first protective layer and selectively exposing the metal-containing photoresist layer to actinic radiation. Forming a second protective layer over an edge portion of the first major surface of the semiconductor substrate. Developing the selectively exposed photoresist layer to form a patterned photoresist layer, and removing the second protective layer.

Description

Technical Field

[0001] The present disclosure generally relates to methods of fabricating semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs, each of which has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of IC processing and manufacturing, and for these advances to be achieved, similar developments in IC processing and manufacturing are needed. In the process of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) is generally increasing, while geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) is decreasing. This reduction process generally provides benefits by improving production efficiency and reducing associated costs. This reduction also increases the complexity of IC processing and manufacturing, and for these advances to be achieved, similar developments in IC processing and manufacturing are needed. In one example, advanced photolithography patterning techniques are implemented to form various patterns, such as gate electrodes and metal lines, on a semiconductor wafer. Photolithography patterning techniques include coating a resist material on the surface of a semiconductor wafer.

[0003] Existing resist coating methods (e.g., spin coating) form resist materials on all areas of the wafer including the wafer edge, and even on the back side of the wafer. During the coating process and subsequent processes (e.g., development), the resist materials on the edge and back side of the wafer can cause various problems and troubles related to contamination, such as contaminating the applicator chuck or track. The accumulation of resist materials on the edge of the wafer can interfere with the patterning stability on the edge of the wafer and cause erroneous level readings during the lithography process. For example, the presence of resist materials on the bevel and back side not only increases the probability of high hot spots, but also may contaminate subsequent process tools. In other instances, existing coating processes have high resist residues at the edge and bevel of the wafer, which may cause resist stripping and lead to poor yields. Various methods are used or proposed to solve these problems, such as edge bead rinse, back side rinse, and additional coating. However, edge bead rinse and back side rinse produce undesirable ridges, which are potential sources of defects in subsequent processes. In other cases, additional coatings can also cause contamination of the wafer and lithography system, or have additional efficiency and effectiveness issues for production throughput. Therefore, it is desirable to provide a system and method of utilizing the same that does not suffer from the above-mentioned disadvantages. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate; forming a metal-containing photoresist layer over the first main surface of the semiconductor substrate; removing the first protective layer; selectively exposing the metal-containing photoresist layer to actinic radiation; forming a second protective layer over the edge portion of the first main surface of the semiconductor substrate; developing the selectively exposed metal-containing photoresist layer to form a patterned photoresist layer; and removing the second protective layer.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate; forming a photoresist layer over the first main surface of the semiconductor substrate; removing the first protective layer; selectively exposing the photoresist layer to actinic radiation; forming a second protective layer over the edge portion of the first main surface of the semiconductor substrate; and performing a first heating on the selectively exposed photoresist layer and the second protective layer in a heating chamber; wherein, during the first heating of the selectively exposed photoresist layer and the second protective layer, one or more parameters are controlled, wherein the parameters are selected from the following items: an air flow entering the heating chamber, an exhaust flow leaving the heating chamber, a temperature of a gas flowing into the heating chamber, and a relative humidity in the heating chamber.

[0006] According to another embodiment of the present disclosure, a semiconductor manufacturing device is provided, comprising: a heating chamber; a semiconductor substrate support in the heating chamber; an air flow inlet in the heating chamber; an air flow outlet in the heating chamber; a gas heater; and a controller programmed to perform the following items: control the air flow entering the heating chamber through the air flow inlet, control the exhaust flow leaving the heating chamber through the air flow outlet, control the temperature of the gas flowing into the heating chamber, and control the relative humidity in the heating chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following specific embodiments when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for integrated circuit fabrication according to some embodiments of the present disclosure.

[0009] Figure 2Ais a cross-sectional view of a wafer constructed according to some embodiments of the present disclosure.

[0010] Figure 2B According to some embodiments of the present disclosure Figure 2A A top view of the wafer in FIG.

[0011] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view of a wafer at a manufacturing stage constructed according to various embodiments of the present disclosure.

[0012] Figure 4 According to some embodiments of the present disclosure, Figure 1 Schematic cross-sectional view of a wafer and coating apparatus used in the method.

[0013] Figure 5 Various embodiments according to the present disclosure are shown. Figure 3A , Figure 3B and Figure 3C The chemical structure of the acid-labile group (ALG) in the protective layer.

[0014] Figure 6 Various embodiments according to the present disclosure are shown. Figure 3A , Figure 3B and Figure 3C Chemical structure of thermal acid generator (TAG) in the protective layer.

[0015] Figure 7 According to some embodiments of the present disclosure, Figure 1 Schematic cross-sectional view of a wafer and coating apparatus used in the method.

[0016] Figure 8 According to some embodiments of the present disclosure, Figure 1 Schematic cross-sectional view of a wafer and coating apparatus used in the method.

[0017] Fig. 9 According to some embodiments of the present disclosure Figure 8 Schematic diagram of the barrier agent used in the coating apparatus.

[0018] Fig.10 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0019] Fig.11 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0020] Fig.12 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0021] Fig.13AAn apparatus including a heating chamber according to an embodiment of the present disclosure is shown. Fig. 13B and Fig. 13C A controller according to an embodiment of the present disclosure is shown.

[0022] Fig.14 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0023] Fig.15 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0024] Fig.16 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0025] Fig.17A and Fig. 17B The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0026] Fig.18 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0027] Fig.19 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0028] Fig. 20 The process stages are shown in sequential operation according to an embodiment of the present disclosure.

[0029] Fig.21 A process flow according to an embodiment of the present disclosure is shown.

[0030] Fig. 22 A process flow according to an embodiment of the present disclosure is shown.

[0031] Fig.23 A photoresist pattern formed according to an embodiment of the present disclosure is shown.

[0032] Fig.24 A process flow according to an embodiment of the present disclosure is shown. Specific embodiments

[0033] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0034] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0035] Figure 1 A flow chart of a method 100 for integrated circuit fabrication is shown in accordance with some embodiments. Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 3C , Figure 4 , Figure 7 , Figure 8 and Figure 10-Figure 14 Cross-sectional and top views of wafer 200 at various stages of fabrication are shown in accordance with some embodiments. Method 100, wafer 200, and systems used in the method are collectively described with reference to these and other figures.

[0036] Method 100 includes an operation 102 of coating an edge portion of wafer 200. In an embodiment, wafer 200 is a semiconductor wafer, such as a silicon wafer. In some embodiments, wafer 200 includes other elemental semiconductors, such as germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or combinations thereof. In some embodiments, a semiconductor material layer is epitaxially grown on wafer 200.

[0037] like Figure 2AAs shown, the wafer 200 has a front side 200A and an opposite back side 200B. In some embodiments, one or more integrated circuits are partially formed, formed, or to be formed on the front side 200A of the wafer 200. Therefore, the front side 200A of the wafer 200 includes a patterned material layer, or a material layer to be patterned. For example, in some embodiments, the front side 200A includes various isolation features (e.g., shallow trench isolation features), various doping features (e.g., doped wells or doped source and drain features), various devices (e.g., transistors, diodes, imaging sensors, or resistors), various conductive features (e.g., contacts, metal lines, and / or vias of interconnect structures), packaging material layers (e.g., bonding pads and / or passivation layers), or combinations thereof. On a manufactured semiconductor wafer, all of the above material layers and patterns may be present on the front side 200A of the semiconductor wafer 200. In some embodiments, the semiconductor wafer 200 is being manufactured, and a subset of the above material layers are formed on the front side 200A.

[0038] Wafer 200 includes a circuit area 202 and an edge portion 204 surrounding the circuit area 202. The circuit area 202 is an area of ​​the wafer 200 in which integrated circuits are formed on the top surface 200A of the wafer. The circuit area 202 includes a plurality of integrated circuits that will be cut to form a plurality of integrated circuit chips at the back end of manufacturing. The circuit area 202 also includes scribing lines between the integrated circuit chips. Various test patterns may be formed in the scribing lines for various testing, monitoring and manufacturing purposes. The edge portion 204 of the wafer 200 is an area without circuits and is not patterned during manufacturing. The edge portion 204 includes a portion at the edge of the front side 200A, and may further include a border surface and edge portion of the back side 200B of the wafer. In operation 102, the edge portion 204 is coated with a protective layer (or first protective layer) 206, such as Figure 3A As shown, it limits the edge portion 204 from directly depositing and forming resist material thereon. According to various embodiments, coating of the edge portion 204 of the wafer 200 is performed by a suitable coating operation.

[0039] The edge portion 204 is selectively coated to form a protective layer 206 on the edge portion 204 of the wafer 200. The protective layer 206 is formed to prevent various problems caused by the resist layer coated on the edge portion of the wafer. These problems include peeling, leveling, and contamination, especially metal contamination generated by EUV resist. In some embodiments, the selective coating process includes spraying to form the protective layer 206 on the edge portion 204 of the wafer 200. The spraying process can use a spraying device 400, such as Figure 4As shown. The spraying device 400 includes a wafer stage 402, which is designed to fix the wafer 200 for spraying. The wafer stage 402 is operable to rotate around an axis 404 so that the wafer 200 fixed thereon also rotates. The spraying device 400 also includes a spray head 406 for spraying a protective layer chemical solution, such as a polymer-containing solution from a chemical supply source 408 connected to the spray head. The spray head 406 is configured to align the edge portion 206 of the wafer 200 and is capable of spraying the chemical solution thereto. Operation 102 includes spraying the chemical solution on the edge portion 204 of the wafer 200 and rotating the wafer 200 at the same time, thereby spin-coating the chemical solution on the edge portion 204. In some embodiments, the thickness of the protective layer 206 ranges from about 50nm to about 100nm.

[0040] In some embodiments, the chemical solution to be coated on the edge portion 204 of the wafer 200 includes a chemical mixture of an acid-labile group (ALG), a solubility control unit, and a thermal acid generator (TAG). The chemical solution also includes a suitable solvent, such as an organic solvent or an aqueous solvent. A thermal process with a suitable baking temperature will trigger the TAG to release acid; the generated acid further reacts with the ALG; this allows the formation of a polymer material layer as a protective layer. In this example, the solubility control unit chemically combines with the ALG (triggered by the generated acid) to form a cross-linked polymer material layer. In other examples, the chemical solution includes other monomers. In some embodiments, the ALG is initially chemically bonded to the monomer. The generated acid reacts with the ALG, resulting in the ALG cleaved from the monomer and the monomer combining with the solubility control unit to form a polymer. The chemical solution is sensitive to thermal processes, but does not contain a photosensitive composition and is different from a photoresist.

[0041] In some embodiments, the ALG includes t-butoxycarbonyl (tBOC). Figure 5 Other examples of ALG 500 according to other embodiments are provided. By convention, carbon and hydrogen are not labeled in the above formula. In some embodiments, TAG is selected from NH4 + C4F9SO3 - and NH4 + CF3SO3 - . Figure 6 Other examples of TAG 600 according to other embodiments are provided. By convention, carbon and hydrogen are not labeled in the above formula. In some embodiments, the solubility control unit is selected from lactones, esters, ethers, ketones, and combinations thereof.

[0042] ALG, solubility control unit and TAG in the chemical solution are mixed in a certain ratio. The total weight W0 of ALG and solubility control unit in the chemical solution is used as a reference. The weight of ALG is in the range of about 30% to about 70% relative to the total weight W0. The weight of solubility control unit is in the range of about 70% to about 30% relative to the total weight W0. The weight of TAG is in the range of 3% to 20% relative to the total weight W0.

[0043] The solubility control unit controls the solubility of the protective layer in a specific removal chemical. Therefore, the protective layer can be selectively removed by a specific removal chemical, while the resist layer can remain. In other words, the specific removal chemical can dissolve the chemical groups of the protective layer 206 corresponding to the solubility control unit, and thus can dissolve the protective layer. Since the resist layer has no solubility control unit, the resist layer is retained in the removal chemical. In some embodiments, the specific removal chemical is a chemical solution (or removal solution) having a mixture of propylene glycol methyl ether (PGME) and propylene glycol methyl ether acetate (PGMEA). In some embodiments, the removal solution includes 70% PGME and 30% PGMEA, also known as OK73.

[0044] In some embodiments, operation 102 further includes a curing operation to cure the protective chemical solution to form the protective layer 206, such as curing at an elevated temperature or by ultraviolet irradiation, so that the applied chemical solution is cross-linked to form a polymer material as the protective layer 206 at the edge portion 204, as described above. In some embodiments, the curing process is a thermal baking process with a sufficiently high baking temperature to trigger the TAG to release acid. With this in mind, the TAG is selected so that the baking temperature in the thermal curing process is close to the temperature T of the post-exposure bake. PEB , for example T PEB + / -20°C, for example in the range between about 130°C and about 170°C. The thermal curing process may have a duration of about 60 seconds. In some embodiments, the thermal curing process is performed at a temperature between about 40°C and about 120°C for about 10 seconds to about 10 minutes.

[0045] In some embodiments, the selective coating mechanism includes a stopper 702 having a special design, such as Figure 7 As shown. The blocker 702 is designed with a shape, size and configuration for preventing the circuit area 202 of the wafer 200 from being coated by the protective chemical solution. In some embodiments, the blocker 702 has a circular shape, the size of which matches and covers the circuit area 202 of the wafer 200. In some embodiments, the blocker 802 used for this purpose has a different shape (including sidewalls) to effectively prevent the circuit area 202 of the wafer 200 from being coated by the protective chemical solution, such as Figure 8 shown. Fig. 9 is a schematic diagram of the barrier 802. The barrier 802 includes a circular plate 902 and a side wall 904 connected together. During the selective coating process, the barrier 802 is positioned so that the circuit area 202 of the wafer is substantially covered from the top and the side so that the protective chemical solution cannot be distributed to the circuit area 202. Specifically, the radius of the circular plate 902 is equal to or close to the radius R of the circuit area 202 of the wafer 200.

[0046] In some embodiments, the protection layer 206 has a width of about 1 mm to about 5 mm along the edge of the wafer 200 .

[0047] Return to reference Figure 1 After forming the protective layer 206 on the edge portion 204 of the wafer 200 through operation 102, the method 100 proceeds to operation 104 of coating a photoresist layer 208 on the wafer 200, as shown in FIG. Figure 3A Specifically, the resist layer 208 is coated on the front 200A of the wafer 200 in the circuit area 202, and the resist layer 208 is constrained from the edge portion 204. Alternatively, due to surface tension and composition differences between the wafer, the protective layer and the photoresist material, the edge of the photoresist layer 208 may have a different geometry, such as a rounded edge, as shown in FIG. Figure 3B In other embodiments, the photoresist layer 208 may be diffused to the edge portion 204 and disposed on the protective layer 206, such as Figure 3C shown.

[0048] In some embodiments, the thickness of the protection layer 206 is 0.5 to 3 times the thickness of the photoresist layer 208 .

[0049] In some embodiments, the photoresist layer 208 is sensitive to radiation used in a photolithography exposure operation and has resistance to etching or implantation. In some embodiments, the photoresist layer 208 is formed by a spin coating process. In some embodiments, the photoresist layer 208 is further subjected to a pre-exposure baking process at a temperature range of about 40° C. to about 120° C. In some embodiments, the photoresist layer 208 is sensitive to actinic radiation, such as I-line light, deep ultraviolet (DUV) light (e.g., 248 nm radiation from a krypton fluoride (KrF) excimer laser, or 193 nm radiation from an argon fluoride (ArF) excimer laser), extreme ultraviolet (EUV) light (e.g., 13.5 nm light), an electron beam (e-beam), and an ion beam.

[0050] The photoresist layer 208 may include a photosensitive chemical, a polymer material, and a solvent. In some embodiments, the resist layer 208 uses a chemically amplified (CA) photoresist material. In some embodiments, the CA photoresist material is a positive photoresist and includes a polymer material that becomes soluble in a developer after the polymer material reacts with an acid. In another embodiment, the CA photoresist material is a negative photoresist and includes a polymer material that becomes insoluble in a developer (e.g., an alkaline solution) after the polymer reacts with an acid. In yet another embodiment, the CA photoresist material includes a polymer material that changes its polarity after the polymer reacts with an acid so that the exposed portion or the unexposed portion will be removed during the development operation, depending on the type of developer (organic solvent or aqueous solvent). In some embodiments, the CA photoresist includes a photoacid generator (PAG) as a photosensitive chemical. In some embodiments, the photoresist includes other additives, such as a sensitizer. The polymer material in the CA resist material may further include an acid-labile group. As described above, in some embodiments, the protective layer 206 is a cross-linked polymer so that it does not dissolve during resist coating.

[0051] Whether a resist is positive or negative may depend on the type of developer used to develop the resist. For example, some positive photoresists provide positive patterns (i.e., the exposed areas are removed by the developer) when the developer is a water-based developer, such as a tetramethylammonium hydroxide (TMAH) solution. On the other hand, when the developer is an organic solvent, the same photoresist provides a negative pattern (i.e., the unexposed areas are removed by the developer). In addition, in some negative photoresists developed with TMAH solutions, the unexposed areas of the photoresist are removed by TMAH, and the exposed areas of the photoresist (crosslinked upon exposure to actinic radiation) remain on the substrate after development.

[0052] In some embodiments, the photoresist according to the present disclosure includes one or more photosensitive compounds (PAC) in a polymer and a solvent. In some embodiments, the polymer includes a hydrocarbon structure (e.g., an alicyclic hydrocarbon structure) containing one or more groups that will decompose (e.g., an acid-labile group) or otherwise react (as further described below) when mixed with an acid, base, or free radical produced by the PAC. In some embodiments, the hydrocarbon structure includes repeating units that form the backbone of the polymer. The repeating units may include acrylates, methacrylates, crotonates, vinyl esters, maleic diesters, fumaric diesters, itaconic diesters, (meth) acrylonitrile, (meth) acrylamide, styrene, vinyl ethers, combinations thereof, and the like.

[0053] In some embodiments, the specific structure of the repeating unit for the hydrocarbon structure includes one or more of the following: methyl acrylate, ethyl acrylate, n-propyl acrylate, isopropyl acrylate, n-butyl acrylate, isobutyl acrylate, tert-butyl acrylate, n-hexyl acrylate, 2-ethylhexyl acrylate, acetoxyethyl acrylate, phenyl acrylate, 2-hydroxyethyl acrylate, 2-methoxyethyl acrylate, 2-ethoxyethyl acrylate, 2-(2-methoxyethoxy)ethyl acrylate, cyclohexyl acrylate, benzyl acrylate, 2-alkyl-2-adamantyl(meth)acrylate or dialkyl(1-adamantyl)methyl(meth)acrylate, methyl Methyl acrylate, ethyl methacrylate, n-propyl methacrylate, isopropyl methacrylate, n-butyl methacrylate, isobutyl methacrylate, tert-butyl methacrylate, n-hexyl methacrylate, 2-ethylhexyl methacrylate, acetoxyethyl methacrylate, phenyl methacrylate, 2-hydroxyethyl methacrylate, 2-methoxyethyl methacrylate, 2-ethoxyethyl methacrylate, 2-(2-methoxyethoxy)ethyl methacrylate, cyclohexyl methacrylate, benzyl methacrylate, 3-chloro-2-hydroxypropyl methacrylate, 3-acetoxy-2-hydroxypropyl methacrylate, 3-chloroacetoxy-2-hydroxypropylmethacrylate, butyl crotonate, hexyl crotonate, and the like. Examples of vinyl esters include vinyl acetate, vinyl propionate, vinyl butyrate, vinyl methoxyacetate, vinyl benzoate, dimethyl maleate, diethyl maleate, dibutyl maleate, dimethyl fumarate, diethyl fumarate, dibutyl fumarate, dimethyl itaconate, diethyl itaconate, dibutyl itaconate, acrylamide, methacrylamide, ethyl acrylamide, propyl acrylamide, n-butyl acrylamide, tert-butyl acrylamide, cyclohexyl acrylamide, 2-methoxyethyl acrylamide, dimethyl acrylamide, diethyl acrylamide , phenyl acrylamide, benzyl acrylamide, methacrylamide, methyl methacrylamide, ethyl methacrylamide, propyl methacrylamide, n-butyl methacrylate, tert-butyl methacrylate, cyclohexyl methacrylate, 2-methoxyethyl methacrylate, dimethyl methacrylate, diethyl methacrylate, phenyl methacrylate, benzyl methacrylate, methyl vinyl ether, butyl vinyl ether, hexyl vinyl ether, methoxyethyl vinyl ether, dimethylaminoethyl vinyl ether, etc.Examples of styrenes include styrene, methylstyrene, dimethylstyrene, trimethylstyrene, ethylstyrene, isopropylstyrene, butylstyrene, methoxystyrene, butoxystyrene, acetoxystyrene, chlorostyrene, dichlorostyrene, bromostyrene, vinyl methyl benzoate, α-methylstyrene, maleimide, vinylpyridine, vinylpyrrolidone, vinylcarbazole, combinations thereof, and the like.

[0054] In some embodiments, the repeating unit of the hydrocarbon structure also has a monocyclic or polycyclic hydrocarbon structure substituted therein, or the monocyclic or polycyclic hydrocarbon structure is a repeating unit to form an alicyclic hydrocarbon structure. In some embodiments, specific examples of monocyclic structures include: bicycloalkanes, tricycloalkanes, tetracycloalkanes, cyclopentane, cyclohexane, etc. In some embodiments, specific examples of polycyclic structures include: adamantane, norbornane, isobornane, tricyclodecane, tetracyclododecane, etc.

[0055] The decomposition group (also referred to as a leaving group or (in some embodiments where the PAC is a photoacid generator) an acid labile group) is attached to the hydrocarbon structure so that it will react with the acid / base / radicals generated by the PAC during exposure. In some embodiments, the decomposition group is: a carboxylic acid group, a fluorinated alcohol group, a phenolic alcohol group, a sulfonic acid group, a sulfonamide group, a sulfonylimido group, a (alkylsulfonyl)(alkylcarbonyl)methylene group, a (alkylsulfonyl)(alkylcarbonyl)imido group, a bis(alkylcarbonyl)methylene group, a bis(alkylcarbonyl)imido group, a bis(alkylsulfonyl)methylene group, a bis(alkylsulfonyl)imino group, a tri(alkylcarbonyl)methylene group, a tri(alkylsulfonyl)methylene group, a combination thereof, and the like. In some embodiments, specific groups for fluorinated alcohol groups include fluorinated hydroxyalkyl groups, such as hexafluoroisopropanol groups. Specific groups for carboxylic acid groups include acrylic acid groups, methacrylic acid groups, and the like.

[0056] In some embodiments, the polymer further comprises other groups attached to the hydrocarbon structure that help improve various properties of the polymerizable resin. For example, the inclusion of a lactone group in the hydrocarbon structure helps reduce the amount of line edge roughness after the photoresist has been developed, thereby helping to reduce the number of defects that occur during development. In some embodiments, the lactone group comprises a ring having five to seven members, but any suitable lactone structure may alternatively be used for the lactone group.

[0057] In some embodiments, the polymer includes groups that can help increase the adhesion of the photoresist layer to the underlying structure (e.g., substrate). Polar groups can be used to assist in increasing adhesion. Suitable polar groups include hydroxyl, cyano, etc., but any suitable polar group may be used instead.

[0058] Alternatively, in some embodiments, the polymer includes one or more alicyclic hydrocarbon structures that do not include groups that will decompose. In some embodiments, the hydrocarbon structure that does not include groups that will decompose includes structures such as: 1-adamantyl (meth) acrylate, tricyclodecanyl (meth) acrylate, cyclohexyl (methacrylate), combinations thereof, and the like.

[0059] In addition, some embodiments of the photoresist include one or more photoactive compounds (PACs). PACs are photosensitive components, such as photoacid generators, photobase generators, free radical generators, etc. PACs can be positive-acting or negative-acting. In some embodiments where the PAC is a photoacid generator, the PAC includes halogenated triazines, onium salts, diazonium salts, aromatic diazonium salts, phosphonium salts, sulfonium salts, iodonium salts, imide sulfonates, oxime sulfonates, diazodisulfones, disulfones, o-nitrobenzylsulfonates, sulfonates, halogenated sulfonyloxy dicarboximides, diazodisulfones, α-cyanooxyamine-sulfonates, imidesulfonates, ketodiazosulfones, sulfonyldiazoesters, 1,2-di(arylsulfonyl)hydrazines, nitrobenzyl esters, and s-triazine derivatives, combinations thereof, and the like.

[0060] Specific examples of the photoacid generator include α-(trifluoromethylsulfonyloxy)-bicyclo[2.2.1]hept-5-ene-2, 3-dicarb-o-ximide (MDT), N-hydroxy-naphthalimide (DDSN), benzoin tosylate, t-butylphenyl-α-(p-toluenesulfonyloxy)-acetate and t-butyl-α-(p-toluenesulfonyloxy)-acetate, triarylsulfonium and diaryliodonium hexafluoroantimonates. hexafluoroantimonates), hexafluoroarsenates, trifluoromethanesulfonates, iodonium perfluorooctanesulfonate, N-camphorsulfonyloxynaphthalimide, N-pentafluorophenylsulfonyloxynaphthalimide, ionic iodonium sulfonates (e.g., diaryl iodonium (alkyl or aryl) sulfonates and bis (di-tert-butylphenyl) iodonium camphorsulfonate), perfluoroalkanesulfonates (e.g., fluoroalkanesulfonates) (e.g., perfluoropentanesulfonate, perfluorooctanesulfonate, perfluoromethanesulfonate), aryl (e.g., phenyl or benzyl) trifluoromethanesulfonates (e.g., triphenylsulfonium trifluoromethanesulfonate or bis(tert-butylphenyl)iodonium trifluoromethanesulfonate), pyrogallol derivatives (e.g., trimesylate of pyrogallol), trifluoromethanesulfonates of hydroxyimides, α,α'-bissulfonyl-diazomethane, sulfonates of nitro-substituted benzyl alcohols, naphthoquinone-4-diazide, alkyl disulfones, and the like.

[0061] In some embodiments where the PAC is a free radical generator, the PAC includes: n-phenylglycine; aromatic ketones including benzophenone, N,N'-tetramethyl-4,4'-diaminobenzophenone, N,N'-tetraethyl-4,4'-diaminobenzophenone, 4-methoxy-4'-dimethylaminobenzophenone, 3,3'-dimethyl-4-methoxybenzophenone, p,p'-bis(dimethylamino)benzophenone, p,p'-bis(diethylamino)-benzophenone; anthraquinone, 2-ethylanthraquinone; naphthoquinone (napthoquinone) hthaquinone; and phenanthraquinone; benzoins, including benzoin, benzoin methyl ether, benzoin isopropyl ether, benzoin n-butyl ether, benzoin phenyl ether, methyl benzoin and ethyl benzoin; benzyl derivatives, including dibenzyl, benzyldiphenyldisulfide and benzyldimethylketal; acridine derivatives, including 9-phenylacridine and 1,7-bis(9 -acridinyl) heptane; thioxanthones, including 2-chlorothioxanthone, 2-methylthioxanthone, 2,4-diethylthioxanthone, 2,4-dimethylthioxanthone and 2-isopropylthioxanthone; acetophenones, including 1,1-dichloroacetophenone, pt-butyldichloro-acetophenone, 2,2-diethoxyacetophenone, 2,2-dimethoxy-2-phenylacetophenone and 2,2-dichloro-4-phenoxyacetophenone; 2,4,5-triarylimidazole dimers, Including 2-(o-chlorophenyl)-4,5-diphenylimidazole dimer, 2-(o-chlorophenyl)-4,5-di-(m-methoxyphenyl)imidazole dimer, 2-(o-fluorophenyl)-4,5-diphenylimidazole dimer, 2-(o-methoxyphenyl)-4,5-diphenylimidazole dimer, 2-(p-methoxyphenyl)-4,5-diphenylimidazole dimer, 2,4-di(p-methoxyphenyl)-5-phenylimidazole dimer, 2-(2,4-dimethoxyphenyl)-4,5-diphenylimidazole dimer and 2-(p-methylmercaptophenyl)-4,5-diphenylimidazole dimer; combinations thereof, etc.

[0062] In some embodiments where the PAC is a photobase generator, the PAC includes: quaternary ammonium dithiocarbamates, alpha aminoketones, oxime-carbamate-containing molecules such as dibenzophenoneoxime hexamethylene diurethan, ammonium tetraorganylborate salts, and N-(2-nitrobenzyloxycarbonyl) cyclic amines, combinations thereof, and the like.

[0063] As will be appreciated by one of ordinary skill in the art, the compounds listed herein are intended only as examples of PACs and are not intended to limit the embodiments to only those PACs specifically described. Rather, any suitable PAC may be used, and all such PACs are fully intended to be included within the scope of the present embodiments. In some embodiments, the photoresist composition comprises from about 1 wt.% to about 10 wt.% of a photosensitive compound (PAC), based on the total weight of the PAC and the polymer.

[0064] In some embodiments, a crosslinking agent is added to the photoresist. The crosslinking agent reacts with a group in one of the hydrocarbon structures of the polymer and also reacts with a second group in a different hydrocarbon structure to crosslink and bond the two hydrocarbon structures together. This bonding and crosslinking increases the molecular weight of the polymer product of the crosslinking reaction and increases the overall link density of the photoresist. This increase in density and link density helps improve the resist pattern.

[0065] In some embodiments, the cross-linking agent has the following structure:

[0066]

[0067] Wherein C is carbon, n is in the range of 1 to 15; A and B independently include hydrogen atoms, hydroxyl groups, halides, aromatic carbon rings, or linear or cyclic alkyl, alkoxy / fluorine, alkyl / fluoroalkoxy chains with carbon numbers between 1 and 12, and each carbon C contains A and B; the first terminal carbon C of the first end of the carbon C chain includes X, and the second terminal carbon C of the second end of the carbon chain includes Y, wherein X and Y independently include amine groups, thiol groups, hydroxyl groups, isopropanol groups, or isopropylamine groups, but when n=1, X and Y are bonded to the same carbon C. Specific examples of materials that can be used as crosslinking agents include:

[0068]

[0069]

[0070] Alternatively, instead of or in addition to adding a crosslinking agent to the photoresist composition, a coupling agent is added in some embodiments, wherein the coupling agent is added in addition to the crosslinking agent. The coupling agent promotes the crosslinking reaction by reacting with the groups on the hydrocarbon structure in the polymer before the crosslinking agent, thereby reducing the reaction energy of the crosslinking reaction and increasing the reaction rate. The bonded coupling agent then reacts with the crosslinking agent, thereby coupling the crosslinking agent to the polymer.

[0071] Alternatively, in some embodiments where a coupling agent is added to a photoresist without a crosslinking agent, the coupling agent is used to couple a group from one of the hydrocarbon structures in the polymer with a second group from a different hydrocarbon structure in order to crosslink and bond the two polymers together. However, in such embodiments, unlike the crosslinking agent, the coupling agent does not remain as part of the polymer and merely facilitates direct bonding of one hydrocarbon structure to another hydrocarbon structure.

[0072] In some embodiments, the coupling agent has the following structure:

[0073]

[0074] Wherein R is a carbon atom, a nitrogen atom, a sulfur atom or an oxygen atom; M includes a chlorine atom, a bromine atom, an iodine atom, --NO2; --SO3-; --H--; --CN; --NCO, --OCN; --CO2-; --OH; --OR*; --OC(O)CR*; --SR; --SO2N(R*)2; --SO2R*; SOR; --OC(O)R*; --C(O)OR*; --C(O)R*; --Si(OR*)3; --Si(R*)3; an epoxy group, etc.; R* is a substituted or unsubstituted C1-C12 alkyl, C1-C12 aryl, C1-C12 aralkyl, etc. Specific examples of materials used as coupling agents in some embodiments include:

[0075]

[0076] Some embodiments of the photoresist are metal-containing photoresists. In some embodiments, the metal-containing photoresist forms a metal-containing photoresist layer. In some embodiments, the metal in the metal-containing photoresist includes one or more of Cs, Ba, La, Ce, In, Sn, or Ag.

[0077] In some embodiments, the metal-containing photoresist includes metal oxide nanoparticles. In some embodiments, the metal oxide nanoparticles are selected from the group consisting of titanium dioxide, zinc oxide, zirconium dioxide, nickel oxide, cobalt oxide, manganese oxide, copper oxide, iron oxide, strontium titanate, tungsten oxide, vanadium oxide, chromium oxide, tin oxide, hafnium oxide, indium oxide, cadmium oxide, molybdenum oxide, tantalum oxide, niobium oxide, aluminum oxide, and combinations thereof. As used herein, nanoparticles are particles having an average particle size between about 1 nm and about 10 nm. In some embodiments, the average particle size of the metal oxide nanoparticles is between about 2 nm and about 5 nm. In some embodiments, based on the total weight of the photoresist composition, the amount of metal oxide nanoparticles in the photoresist composition is in the range of about 1 wt.% to about 10 wt.%. In some embodiments, a metal oxide nanoparticle concentration below about 1 wt.% provides an overly thin photoresist layer, and a metal oxide nanoparticle concentration above about 10 wt.% provides an overly sticky photoresist composition, and it will be difficult to provide a uniform thickness of photoresist coating on the substrate.

[0078] In some embodiments, the metal oxide nanoparticles are complexed with carboxylic acid or sulfonic acid ligands. For example, in some embodiments, zirconium oxide or hafnium oxide nanoparticles are complexed with methacrylic acid to form hafnium methacrylate (HfMAA) or zirconium methacrylate (ZrMAA). In some embodiments, HfMAA or ZrMAA is dissolved in a coating solvent, such as propylene glycol methyl ether acetate (PGMEA), in a weight range of about 5 wt.% to about 10 wt.%. In some embodiments, the metal concentration in the metal-containing photoresist layer is 10 wt.% to 80 wt.% based on the total weight of the metal-containing photoresist layer after solvent drying. In some embodiments, the metal concentration in the metal-containing photoresist layer is 20 wt.% to 50 wt.% based on the total weight of the metal-containing photoresist layer after solvent drying.

[0079] In some embodiments, the photoresist layer is a three-layer photoresist. The three-layer photoresist includes a bottom layer (also called a lower layer), an intermediate layer, and a top layer (the top layer may also be called a photosensitive layer). In some embodiments, the bottom layer includes C x H y O z Materials, intermediate layers include SiC x H y O z material, and the top layer includes C x H y O z In some embodiments, the bottom layer of C x H y O z Materials and top layer Cx H y O z In some embodiments, the top layer is patterned with a photolithography process, which may include one or more exposure, baking, developing and rinsing processes (not necessarily performed in this order). The top layer is patterned into a photoresist mask by the photolithography process, and the photoresist mask may have one or more grooves or openings, and the one or more grooves or openings expose the intermediate layer below it. In some embodiments, the intermediate layer is then etched using the photoresist mask to form a patterned intermediate layer, and then the patterned intermediate layer is used to etch the bottom layer to form a patterned bottom layer. Then, the patterned bottom layer is used to pattern the following layers. In the embodiment where the photoresist layer is a three-layer photoresist, the metal-containing material is located in any one of the bottom layer, the intermediate layer, and the top layer, or all of these layers.

[0080] refer to Figure 1 and Fig.10 , the method 100 proceeds to operation 106 of removing the protective layer 206 from the wafer by a specific removal solution that selectively removes the protective layer 206, such as 70% propylene glycol monomethyl ether and 30% propylene glycol monomethyl ether acetate (OK73) in some embodiments. As a result, the edge portion 204 of the wafer 200 is free of the resist layer 208. In addition, because the removal solution is designed to selectively remove the protective layer 206, the resist layer 208 remains after removing the protective layer 206. The layer 206 is removed before applying the exposure process to the resist layer because the protective layer 206 may introduce contaminants into the lithography system and subsequently the wafer to be exposed in the lithography system.

[0081] In some embodiments, a cleaning solution is applied to the wafer 200 to remove contaminants, such as metal from a metal-containing photoresist. The cleaning solution is applied to the back side of the wafer and / or the side edge of the wafer. The wafer is cleaned because the wafer transfer process (e.g., when the wafer 200 is transferred from one semiconductor manufacturing tool to another semiconductor manufacturing tool) may involve physical contact with the back side or side edge of the wafer 200. For example, when the wafer 200 is removed from the semiconductor manufacturing tool (e.g., EUV lithography equipment in one embodiment), various components of the semiconductor manufacturing tool may contact the bottom (e.g., back side) or side portion of the wafer 200. Through this contact, metal may remain on the semiconductor manufacturing tool. If it is assumed that the subsequent process performed by the semiconductor manufacturing tool does not contain metal, the metal remaining on the semiconductor manufacturing tool may be a contaminant.

[0082] In addition, if metal is not completely removed from wafer 200, metal may contaminate the new semiconductor manufacturing tool when the wafer is loaded into the new semiconductor manufacturing tool. This may be exacerbated by various heating processes, which promote the escape of metal-containing materials from wafer 200 or photoresist layer 208. Subsequently, new (now contaminated) semiconductor manufacturing tools may be needed to perform semiconductor manufacturing processes in a metal-free environment, in which case the presence of metal is undesirable. For these reasons, cleaning solutions are used to clean the metal. In order to enhance the efficiency of cleaning, the cleaning solution is configured to be the back side and side edge of wafer 200 as the main target, but the front side of wafer 200 may also be optionally cleaned.

[0083] The material composition of the cleaning solution is configured to enhance the removal of metal from the wafer 200. In some embodiments, the cleaning solution includes two cleaning solutions having different compositions, a first cleaning solution and a second cleaning solution. The first cleaning solution is an aqueous solution or an organic solution including a first solvent. In some embodiments, the cleaning solution includes a first solvent having a Hansen solubility parameter of 25>δ d >13,25>δ p >3, and 30>δ h >4. The unit of Hansen solubility parameter is (joule / cm 3 ) 1 / 2 Or equivalent to MPa 1 / 2 , and is based on the idea that a molecule is defined as similar to another molecule if it bonds to itself in a similar way. d is the energy of the dispersion force between molecules. p is the energy of the dipole intermolecular forces between molecules. h is the energy of hydrogen bonds between molecules. The three parameters δ d ,δ p and δ h Think of it as the coordinates of a point in three dimensions (called Hansen space). The closer two molecules are in Hansen space, the more likely they are to dissolve in each other.

[0084] Solvents with the desired Hansen solubility parameters include: propylene glycol methyl ether, propylene glycol ethyl ether, gamma-butyrolactone, cyclohexanone, ethyl lactate, dimethyl sulfoxide, acetone, ethylene glycol, methanol, ethanol, propanol, propylene glycol, n-butanol, water, 4-methyl-2-pentanone, hydrogen peroxide, isopropanol, dimethylformamide, acetonitrile, acetic acid, toluene, tetrahydrofuran, and butyldiglycol.

[0085] In some embodiments, the first cleaning solution comprises 0.1 wt.% to 5 wt.% of one or more surfactants based on the total weight of the first cleaning solution. In some embodiments, the surfactant is selected from the group consisting of alkylbenzene sulfonates, lignin sulfonates, fatty alcohol ethoxylates, and alkylphenol ethoxylates.In some embodiments, the surfactant is selected from the group consisting of sodium stearate, 4-(5-dodecyl)benzenesulfonic acid, ammonium lauryl sulfate, sodium lauryl sulfate, sodium laureth sulfate, sodium myreth sulfate, dioctylsodium sulfosuccinate, perfluorooctanesulfonate, perfluorobutanesulfonate, alkyl-aryl ether phosphate, alkyl ether phosphate, sodium lauroyl sarcosinate, perfluoronononanoate, perfluorooctanoate, octenidine dihydrochloride, cetrimonium bromide, cetylpyridinium chloride, benzalkonium chloride, benzethonium chloride, dimethyldioctadecylammonium chloride chloride), dioctadecyldimethylammonium bromide, 3-[(3-cholamidopropyl)dimethylammonio]-1-propanesulfonate, cocamidopropyl hydroxysultaine, cocamidopropylbetaine, phospholipidsphosphatidylserine, phosphatidylethanolamine, phosphatidylcholine, sphingomyelin, octaethylene glycol monodecyl ether, pentaethylene glycol monodecyl ether, polyethoxylated tallow amine amine), cocamide monoethanolamine, cocamide diethanolamine, glyceryl monostearate, glyceryl monolaurate, sorbitan monolaurate, sorbitan monostearate, sorbitan tristearate, and combinations thereof.

[0086] In some embodiments, the surfactant is one or more of ionic surfactants, polyethylene oxide and polypropylene oxide, nonionic surfactants, and combinations thereof.

[0087] In method 100, various operations (such as spin coating, baking, removing protective layers and developing) are implemented in a cluster tool called a track (or cleaning track). The track includes multiple stages designed to fix wafers for chemical treatment or thermal treatment, respectively referred to as chemical stages and hot stages. Each chemical stage is operable to rotate the fixed wafer and distribute chemicals to the wafer through a nozzle when the wafer rotates. The chemical stage can be used for spin coating, development, cleaning and removal (such as resist stripping). The hot stage is designed to fix the wafer and heat the fixed wafer, such as a hot plate. The hot stage can be used for various baking, such as post-exposure baking. The wafer can be transferred to different stages in the track for various chemical treatments and thermal treatments. In some embodiments of method 100, operations 104 and 106 are implemented on the same chemical stage (referred to as the first chemical stage in the following description) of the track to improve efficiency. Specifically, when the wafer is transferred to the first chemical station, the first nozzle (or nozzle or nozzle head) is positioned to dispense the first chemical substance (i.e., a solution of the resist material) to the wafer 200 fixed on the first chemical station for anti-reagent coating, and then the second nozzle head is positioned to dispense the second chemical substance (i.e., a removal solution, OK73 in some embodiments) to the wafer 200 retained on the first chemical station to remove the first protective layer 206.

[0088] refer to Figure 1 and Fig.11 , method 100 proceeds to operation 108: selectively exposing resist layer 208 to actinic radiation 1110 in a lithography system. Radiation 1110 may be I-line, DUV radiation, EUV radiation, electron beam, or other suitable radiation. Operation 108 may be performed in air, liquid (immersion lithography), or vacuum (e.g., for EUV lithography and electron beam lithography). In some embodiments, radiation beam 1110 is patterned with mask 1112, such as a transmission mask or a reflection mask, which may include resolution enhancement techniques such as phase shifting, off-axis illumination (OAI), and / or optical proximity correction (OPC). In some other embodiments, the radiation beam is directly adjusted with a predetermined pattern (e.g., IC layout) without the use of a mask (e.g., using a digital pattern generator or direct write mode). In an illustrative embodiment, the radiation beam is directed to a transmission mask 1112, which includes a transparent substrate (e.g., fused silica) 1114, a patterned opaque layer (e.g., chrome) 1116.

[0089] After operation 108, a latent pattern is formed on the photoresist layer 208. The latent pattern of the resist layer refers to the exposure pattern on the resist layer, which eventually becomes a physical resist pattern, such as by a development process. The latent pattern of the resist layer 208 includes an unexposed portion 208a and an exposed portion 208b. In an embodiment using a CA photoresist material with a PAG, an acid is generated in the exposed portion 208b during the exposure process. In the latent pattern, the exposed portion 208b of the resist layer 208 is physically or chemically changed. In some examples, the exposed portion 208b is deprotected, causing a polarity change for dual-sexual imaging (development). In other examples, the exposed portion 208b changes in polymerization, such as depolymerization in a positive resist or cross-linking in a negative resist.

[0090] refer to Figure 1 and Fig.12 , the method 100 then proceeds to operation 110: after the exposure process of operation 108 and before subsequent operations such as post-exposure baking and development, a second protective layer 1202 is coated on the edge portion 204 of the wafer 200. Therefore, the edge portion 204 of the wafer 200 is protected from any contamination during subsequent operations. In terms of composition and formation, the second protective layer 1202 is substantially similar to the first protective layer 206. For example, a chemical solution is first coated on the edge portion 204 of the wafer 200 by spin coating, and then cured to form a polymer material as the second protective layer 1202. The chemical solution includes a chemical mixture of ALG, a solubility control unit and TAG. The chemical solution also includes a suitable solvent, such as an organic solvent or an aqueous solvent. A thermal process with an appropriate baking temperature will trigger the TAG to release acid; the generated acid further reacts with the ALG; this leads to the formation of a polymer material.

[0091] refer to Figure 1 , Fig.13A , Fig. 13B and Fig. 13C , the method 100 then proceeds to operation 112: performing a post-exposure bake (PEB) process on the photoresist-coated wafer 200. During the PEB process, more acid is generated, and the exposed portion of the resist material 208 undergoes a chemical change (e.g., more hydrophilic or more hydrophobic). In a specific embodiment, the PEB process can be performed in a heated chamber at a temperature in a range between about 90° C. and about 130° C. for 60 seconds to about 120 seconds.

[0092] In some embodiments, the semiconductor manufacturing apparatus includes a heating chamber 1350 and a semiconductor substrate support 1345 in the heating chamber. A schematic diagram of the heating chamber 1350 is shown in FIG. Fig.13A. In some embodiments, post-exposure baking or other baking operations include curing of the protective layer, and performing a photoresist drying operation in the heating chamber 1350. The heating chamber 1350 includes an airflow inlet 1360 located in the chamber, and an airflow outlet 1370. In some embodiments, the airflow inlet 1360 includes multiple inlet ports, or there are multiple airflow inlets. In some embodiments, the airflow outlet 1370 includes multiple outlet ports, or there are multiple airflow outlets. In some embodiments, it is desirable to have a stable laminar airflow through the chamber. In some embodiments, the airflow inlet 1360 is at the bottom or side of the chamber 205, and the airflow outlet 1370 is at the top of the chamber 205. In other embodiments, the airflow inlet 1360 is at the top of the chamber 205, and the airflow outlet 1370 is at the bottom or side of the chamber 205. The size, shape, or number of the inlet port or outlet port depends on the chamber design, and the size, shape, or number of the inlet port or outlet port is selected to provide a stable laminar airflow in the chamber.

[0093] In some embodiments, the apparatus includes a gas humidifier / dehumidifier 1355 for adjusting the relative humidity in the heating chamber 1350. A gas supply 1375 is connected to the gas flow inlet 1360 via a gas conduit 1380. A gas heater 1365 is provided in accordance with the gas flow inlet 1360 to heat the gas flowing into the chamber. The apparatus also includes a controller 1300 programmed to: control the gas flow entering the heating chamber 1350 through the gas flow inlet 1360, control the exhaust flow leaving the heating chamber through the gas flow outlet 1370, control the gas heater 1365 to adjust the temperature of the gas flow entering the heating chamber 1350, and control the humidifier / dehumidifier 1355 to adjust the relative humidity in the heating chamber. In some embodiments, the semiconductor substrate support 1345 includes a heating element. In some embodiments, the semiconductor substrate support 1345 is a hot plate. In some embodiments, one or more temperature sensors 1335 or humidity sensors 1340 are positioned inside the chamber 1350 to monitor the chamber temperature and relative humidity, respectively. Sensors 1335, 1340 are connected to controller 1300 and feedback control can be used to adjust relative humidity and chamber temperature. Airflow inlet 1360, airflow outlet 370, humidifier / dehumidifier 1355, sensors 1335, 1340, wafer stage 1345, and Fig.13A The locations of other components of the device shown are for illustrative purposes only, and the various components may be arranged in any feasible or suitable location or arrangement.

[0094] In some embodiments, one or more parameters are controlled during the PEB process, wherein the parameters are selected from: the gas flow entering the heating chamber, the exhaust flow leaving the heating chamber, the temperature of the gas flowing into the heating chamber, and the relative humidity within the heating chamber cavity. In some embodiments, the inlet temperature of the gas flowing into the heating chamber is in the range of about 80°C to about 190°C. In other embodiments, the inlet temperature of the gas flowing into the heating chamber is in the range of about 90°C to about 170°C. In other embodiments, the inlet temperature of the gas flowing into the heating chamber is in the range of about 100°C to about 150°C. At low temperatures below the range, insufficient acid may be produced, resulting in reduced pattern clarity. At high temperatures above the range, increased resist degassing within the heating chamber may result, as well as the concomitant release of metal contaminants.

[0095] In some embodiments, during the PEB process, the flow rate of the gas flowing into the heating chamber is in the range of about 5 L / min to about 40 L / min. In other embodiments, the flow rate of the gas flowing into the heating chamber is in the range of about 10 L / min to about 30 L / min.

[0096] In some embodiments, during the PEB process, the flow rate of the exhaust gas leaving the heating chamber is in the range of about 10 L / min to about 50 L / min. In other embodiments, the flow rate of the exhaust gas leaving the heating chamber is in the range of about 20 L / min to about 40 L / min.

[0097] At intake and exhaust flow rates below the disclosed ranges, insufficient removal of resist outgassing products (e.g., metal contaminants) may result. At flow rates above the disclosed ranges, turbulence may result and increased outflow of metal contaminants from the photoresist layer may result.

[0098] In some embodiments, during the PEB process, the relative humidity in the heated chamber is in a range from about 1% to about 50%. In some embodiments, during the PEB process, the relative humidity in the heated chamber is in a range from about 10% to about 45%. At relative humidities above the disclosed ranges, resist outgassing condensation may result, leaving metal contaminants on surfaces inside the chamber. At relative humidities below the disclosed ranges, there may be no substantial improvement in resist outgassing condensation.

[0099] In some embodiments, the post-exposure bake (PEB) process is performed for less than about 5 minutes. In some embodiments, the PEB process is performed for about 10 seconds to about 5 minutes. In other embodiments, the duration of the PEB process is about 20 seconds to about 4 minutes, and in other embodiments, about 30 seconds to about 3 minutes.

[0100] In some embodiments, the gas flowing into the heating chamber includes one or more of purge air, nitrogen, argon, neon, and helium.

[0101] In some embodiments, the controller 1300 is programmed to control the gas flow entering the heating chamber through the gas flow inlet 1360 at a flow rate of about 5 L / min to about 40 L / min. In other embodiments, the controller 1300 is programmed to control the gas flow flowing into the heating chamber 1350 at a flow rate of about 10 L / min to about 30 L / min. In some embodiments, the controller 1300 is programmed to control the inlet temperature of the gas flowing into the heating chamber 1350 at about 80°C to about 190°C. In other embodiments, the controller 1300 is programmed to control the inlet temperature of the gas flowing into the heating chamber 1355 at about 100°C to about 150°C. In other embodiments, the controller 1300 is programmed to control the inlet temperature of the gas flowing into the heating chamber 1350 at about 120°C to about 170°C. In some embodiments, the controller 1300 is programmed to control the flow rate of the exhaust gas leaving the heating chamber 1350 during the PEB process within a range of about 10 L / min to about 50 L / min. In other embodiments, the controller 1300 is programmed to control the flow rate of the exhaust gas leaving the heating chamber within a range of about 20 L / min to about 40 L / min. In some embodiments, the controller 1300 is programmed to control the relative humidity in the heating chamber within a range of about 1% to about 50% relative humidity during the PEB process. In some embodiments, the controller 1300 is programmed to control the relative humidity in the heating chamber within a range of about 10% to about 45% relative humidity during the PEB process.

[0102] In some embodiments, at a low inlet gas flow rate of less than about 5L / min or a low exhaust flow rate of less than about 10L / min, the photoresist degassing is not fully removed from the heating chamber. In some embodiments, at a high inlet gas flow rate greater than 40L / min or a high exhaust flow rate greater than 50L / min, the airflow is turbulent and less efficient in removing the photoresist degassing. Under turbulent airflow at high inlet gas flow rate or high exhaust flow rate, dead zones may be formed in which resist degassing contaminants may settle and not be taken out of the heating chamber by the airflow. In some embodiments, laminar airflow is desirable in the heating chamber.

[0103] like Fig.13AAs shown, in some embodiments, a substrate 1395 such as a silicon wafer is placed on a wafer stage (semiconductor substrate support) 1345. A target layer 1390 to be patterned is arranged on the wafer 1395, and a photoresist layer 1385 is arranged on the target layer 1390. In some embodiments, the wafer stage 1345 includes a heating element controlled by a controller 1300 for heating a substrate coated with photoresist during PEB or other baking operations. In some embodiments, the wafer coated with photoresist is heated by introducing a heated gas through a gas inlet 1360. In some embodiments, the controller 1300 controls the flow rate and temperature of the heated gas. The photoresist degassing is carried to the gas outlet 1370 by the heated inlet gas to be removed from the heating chamber, thereby preventing the degassing contaminants from contaminating the chamber. In some embodiments, the gas outlet 1370 includes a pump or other mechanical device to exhaust the gas.

[0104] like Fig.13A As shown, resist outgassing increases at higher bake temperatures, while resist outgassing decreases at lower bake temperatures. In addition, at higher exhaust and inlet gas flow rates, turbulence increases, resulting in less efficient removal of outgassing from the chamber. On the other hand, at lower exhaust and inlet gas flow rates, the gas flow may not be sufficient to remove photoresist outgassing.

[0105] Fig. 13B and Fig. 13C A controller for controlling a post-exposure bake operation or other bake operation during the method of the present disclosure is shown. In some embodiments, the computer system 1300 is used as a controller for controlling the bake operation. All or part of the processes, methods, and / or operations of the aforementioned embodiments may be implemented using computer hardware and computer programs executed thereon. Fig. 13B In the embodiment, the computer system 1300 is provided with a computer 1301 including a disc read-only memory (eg, CD-ROM or DVD-ROM) drive 1305 and a disk drive 1306 , a keyboard 1302 , a mouse 1303 , and a monitor 1304 .

[0106] Fig. 13C 1300 is a diagram showing the internal configuration of the computer system 1300. Fig. 13CIn addition to the optical drive 1305 and the magnetic disk drive 1306, the computer 1301 is also provided with one or more processors (e.g., microprocessing unit (MPU)), ROM 1312 (in which programs such as a boot program are stored), random access memory (RAM) 1313 (connected to the MPU 1211 and temporarily storing therein commands of application programs and providing a temporary storage area), hard disk 1314 (in which application programs, system programs, and data are stored), and bus 1315 (connecting the MPU 1311, ROM 1312, etc.). Note that the computer 1301 may include a network card (not shown) for providing connection to a LAN.

[0107] The program for causing the computer system 1300 to perform the functions of the device for baking the coated substrate in any of the aforementioned embodiments may be stored in the optical disk 1321 or the disk 1322 inserted in the optical disk drive 1305 and the disk drive 1306, and transferred to the hard disk 1314. Alternatively, the program may be transferred to the computer 1301 via a network (not shown) and stored in the hard disk 1314. When executed, the program is loaded into the RAM 1313. The program may be loaded from the optical disk 1321 or the disk 1322, or directly loaded from the network. The program does not necessarily include, for example, an operating system (OS) or a third-party program that causes the computer 1301 to perform the baking operation in the aforementioned embodiments. The program may only include a command portion that calls the appropriate function (module) in a controlled mode and obtains the desired result.

[0108] refer to Figure 1 and Fig.14 , the method 100 then proceeds to operation 114: developing the exposed resist layer 208 using a developer. Through the development operation, a patterned resist layer is formed. In some embodiments, the resist layer 208 undergoes a polarity change after operation 106, and a bisexual development process can be implemented. In some examples, the resist layer 208 changes from a non-polar state (hydrophobic state) to a polar state (hydrophilic state), and then the exposed portion 208b will be removed by an aqueous solvent (positive imaging) (e.g., tetramethylammonium hydroxide (TMAH)), or alternatively, the unexposed portion 208a will be removed by an organic solvent (negative imaging) (e.g., butyl acetate). In some other examples, the resist layer 208 changes from a polar state to a non-polar state, and then the exposed portion 208b will be removed by an organic solvent (positive tone imaging), or the unexposed portion 208a will be removed by an aqueous solvent (negative imaging).

[0109] In some embodiments, Fig.14As shown, the exposed portion 208b is removed in the development process. In addition, in this embodiment, the patterned resist layer is represented by a double-line pattern. However, the following discussion is also applicable to a resist pattern represented by a groove.

[0110] refer to Figure 1 and Fig.15 , the method 100 then proceeds to operation 116: removing the second protective layer 1202 from the wafer with a removal solution. Operation 116 is substantially similar to operation 106. For example, the removal solution is designed to selectively remove the second protective layer 1202 (i.e., the same composition as the first protective layer 206), and the resist layer 208 remains after removing the second protective layer 1202. The second protective layer 1202 is removed after the development process at operation 114. In some embodiments, for efficiency and production throughput, operations 114 and 116 are performed sequentially on the same chemical station (referred to as the second chemical station) of the track. When the wafer 200 is transferred to the second chemical station, the first nozzle is positioned to dispense the developer to the wafer 200 fixed on the second chemical platform for development, and then the second nozzle is positioned to dispense the second chemical, such as the removal solution. In some embodiments, OK73 is applied to the wafer 200 in the second chemical station to remove the second protective layer 1202.

[0111] In some embodiments, the method 100 then proceeds to operation 118 of performing additional process operations to fabricate the semiconductor device. In some embodiments, the fabrication process includes an ion implantation process applied to the wafer 200 using the patterned resist layer as an implantation mask to form various doped features in the wafer 200 .

[0112] refer to Figure 16-Figure 20 Additional semiconductor processes according to embodiments of the present disclosure are described. Fig.16 A portion of a substrate (e.g., a wafer) coated with photoresist is shown. To simplify the process description, the center portion of the wafer is shown, excluding Figure 16-Figure 20 The edge portion of the wafer. Fig.16A semiconductor substrate 310 is shown on which a layer 360 to be patterned is disposed. In some embodiments, the layer 360 to be patterned is a hard mask layer; a metallization layer; or a dielectric layer, such as a passivation layer, disposed on the metallization layer. In embodiments in which the layer 360 to be patterned is a metallization layer, the layer 360 to be patterned is formed from a conductive material using a metallization process and a metal deposition technique, including chemical vapor deposition, atomic layer deposition, and physical vapor deposition (sputtering). Similarly, if the layer 360 to be patterned is a dielectric layer, the layer 360 to be patterned is formed by a dielectric layer formation technique, including thermal oxidation, chemical vapor deposition, atomic layer deposition, and physical vapor deposition. As described herein, a photoresist layer 315 is disposed on the layer to be patterned. In some embodiments, an optional protective upper layer 320, such as a polysiloxane layer, is disposed on the photoresist layer 315.

[0113] Fig.17A and Fig. 17B Selective exposure of the photoresist layer is shown to form exposed areas 350 and unexposed areas 352. In some embodiments, exposure to radiation is performed by placing the photoresist-coated substrate in a photolithography tool. The photolithography tool includes a photomask 330 / 365, an optical device, an exposure radiation source that provides radiation 345 / 397 for exposure, and a movable stage for supporting and moving the substrate under the exposure radiation.

[0114] In some embodiments, a radiation source (not shown) provides radiation 345 / 397 (e.g., ultraviolet light) to the photoresist layer 315 to cause a reaction of the PAC, which in turn reacts with the polymer to chemically change those areas of the photoresist layer where the radiation 345 / 397 is incident. In some embodiments, the radiation is electromagnetic radiation, such as g-line (wavelength of about 436 nm), i-line (wavelength of about 365 nm), ultraviolet, far ultraviolet, extreme ultraviolet, electron beam, etc. In some embodiments, the radiation source is selected from the group consisting of: a mercury vapor lamp, a xenon lamp, a carbon arc lamp, a KrF excimer laser (wavelength of 248 nm), an ArF excimer laser (wavelength of 193 nm), a F2 excimer laser (wavelength of 157 nm), or a CO2 laser-excited Sn plasma (extreme ultraviolet, wavelength of 13.5 nm).

[0115] In some embodiments, optics (not shown) are used in the lithography tool to expand, reflect, or otherwise control the radiation 345 / 397 before or after it is patterned by the photomask 330 / 365. In some embodiments, the optics include one or more lenses, mirrors, filters, and combinations thereof to control the radiation 345 / 397 along its path.

[0116] In an embodiment, the patterned radiation 345 / 397 is extreme ultraviolet light having a wavelength of 13.5 nm, the PAC is a photoacid generator, the groups to be decomposed are carboxylic acid groups on a hydrocarbon structure, and a crosslinking agent is used. The patterned radiation 345 / 397 is incident on the photoacid generator, and the photoacid generator absorbs the incident patterned radiation 345 / 397. The absorption triggers the photoacid generator to generate protons (e.g., H + Atom). When the proton strikes the carboxylic acid group on the hydrocarbon structure, the proton reacts with the carboxylic acid group, thereby chemically changing the carboxylic acid group and generally changing the properties of the polymer. In some embodiments, the carboxylic acid group then reacts with a crosslinking agent to crosslink with other polymers in the exposed areas of the photoresist layer 315.

[0117] In some embodiments, exposure of photoresist layer 315 uses immersion lithography techniques. In this technique, an immersion medium (not shown) is placed between the final optical device and the photoresist layer, and exposure radiation 345 passes through the immersion medium.

[0118] In some embodiments, the thickness of optional upper layer 320 is thin enough so that upper layer 320 does not adversely affect exposure of photoresist layer 315 to radiation 345 / 397 .

[0119] After the photoresist layer 315 has been exposed to exposure radiation 345 / 397, a post-exposure bake (PEB) is performed as described herein to remove contaminants and promote the generation, distribution and reaction of acids / bases / radicals generated due to the incident radiation 345 / 397 on the PAC during exposure. As described herein, the gas is flowed over the photoresist layer at a specific, controlled flow rate, temperature and relative humidity.

[0120] Development is then performed using a solvent, such as Fig.18 As shown. In some embodiments where positive development is desired, a positive developer (e.g., an alkaline aqueous solution) is used to remove the areas 350 of the photoresist exposed to radiation. In some embodiments, the positive developer 357 includes one or more selected from the following: tetramethylammonium hydroxide (TMAH), tetrabutylammonium hydroxide, sodium hydroxide, potassium hydroxide, sodium carbonate, sodium bicarbonate, sodium silicate, sodium metasilicate, ammonia, monomethylamine, dimethylamine, trimethylamine, monoethylamine, diethylamine, triethylamine, monoisopropylamine, diisopropylamine, triisopropylamine, monobutylamine, dibutylamine, monoethanolamine, diethanolamine, triethanolamine, dimethylaminoethanol, diethylaminoethanol, ammonia, caustic soda, caustic potash, sodium metasilicate, potassium metasilicate, sodium carbonate, tetraethylammonium hydroxide, combinations of these, and the like.

[0121] In some embodiments where negative tone development is required, an organic solvent or a critical fluid is used to remove the unexposed areas 352 of the photoresist. In some embodiments, the negative tone developer 357 includes one or more selected from the following: hexane, heptane, octane, toluene, xylene, methylene chloride, chloroform, carbon tetrachloride, trichloroethylene, and similar hydrocarbon solvents; critical carbon dioxide, methanol, ethanol, propanol, butanol, and similar alcohol solvents; diethyl ether, dipropyl ether, dibutyl ether, ethyl vinyl ether, dioxane, propylene oxide, tetrahydrofuran, cellosolve, methyl cellosolve, butyl cellosolve, methyl carbitol, diethylene glycol monoethyl ether, and similar ether solvents; acetone, methyl ethyl ketone, methyl isobutyl ketone, isophorone, cyclohexanone, and similar ketone solvents; methyl acetate, ethyl acetate, propyl acetate, butyl acetate, and similar ester solvents; pyridine, formamide, and N,N-dimethylformamide, etc.

[0122] In some embodiments, the developer 357 is applied to the upper layer 320 and the photoresist layer 315 using a spin coating process. In the spin coating process, the developer 357 is applied to the upper layer 320 and the photoresist layer 315 from above by a dispenser 362 while the coating substrate is being rotated, such as Fig.18 As shown. The developer 357 is selected so that it removes both the optional upper layer 320 and the appropriate areas of the photoresist layer 315. In the case of a positive resist, the exposed areas 350 of the photoresist layer are removed, and in the case of a negative resist, the unexposed areas 352 of the photoresist layer are removed. In some embodiments, the developer 357 is supplied at a rate between about 5 ml / min and about 800 ml / min while the coated substrate 10 is rotated at a speed between about 100 rpm and about 2000 rpm. In some embodiments, the developer is at a temperature between about 10° C. and about 80° C. In some embodiments, the development operation lasts from about 30 seconds to about 10 minutes.

[0123] Although a spin coating operation is a suitable method for developing the photoresist layer 315 after exposure, it is intended to be illustrative rather than limiting the embodiments. Instead, any suitable developing operation may be used alternatively, including an immersion process, a dip coating process, and a spray coating method. All of these development operations are included within the scope of the embodiments.

[0124] In some embodiments, during the development process, the developer 357 dissolves the radiation unexposed areas 352 of the cross-linked negative resist, exposing the surface of the layer to be patterned, such as Fig.19 As shown, well-defined exposed photoresist areas 355 are left.

[0125] After the development operation, the remaining developer is removed from the patterned photoresist covered substrate. In some embodiments, a spin dry process is used to remove the remaining developer, but any suitable removal technique may be used. After the photoresist layer 315 is developed and the remaining developer is removed, additional processes are performed with the patterned photoresist layer 350 in place. For example, in some embodiments, an etching operation using dry etching or wet etching is performed to transfer the pattern 355 of the photoresist layer 352 to the layer to be patterned 360, thereby forming a Fig. 20 Recess 355' is shown. The layer 360 to be patterned has a different etch resistance than the photoresist layer 315. In some embodiments, the etchant is more selective to the layer 310 to be patterned than to the photoresist layer 315.

[0126] In some embodiments, the layer to be patterned 360 and the photoresist layer 315 contain at least one anti-etching molecule. In some embodiments, the anti-etching molecule includes a molecule having a low Onishi number structure, a double bond, a triple bond, silicon, silicon nitride, titanium, titanium nitride, aluminum, aluminum oxide, silicon oxynitride, a combination thereof, and the like.

[0127] In some embodiments, the etching operation includes dry (plasma) etching, wet etching, and / or other etching methods. For example, the dry etching operation can implement an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. The patterned resist layer can be partially or completely consumed during the etching of the hard mask layer. In an embodiment, any remaining portion of the patterned resist layer can be stripped, thereby leaving a patterned hard mask layer on the wafer.

[0128] Other embodiments include other operations before, during, or after the above operations. In an embodiment, the method includes forming a fin field effect transistor (FinFET) structure. In an embodiment, a plurality of active fins are formed on a semiconductor substrate. Such an embodiment also includes: etching the substrate through the opening of the patterned hard mask to form a trench in the substrate; filling the trench with a dielectric material; performing a chemical mechanical polishing (CMP) process to form a shallow trench isolation (STI) feature; and epitaxially growing or recessing the STI feature to form a fin-shaped active area. In another embodiment, the method includes other operations to form a plurality of gate electrodes on the semiconductor substrate. The method may further include forming gate spacers, doped source / drain regions, contacts for gate / source / drain features, and the like. In another embodiment, the target pattern will be formed as a metal line in a multilayer interconnect structure. For example, the metal line may be formed in an interlayer dielectric (ILD) layer of the substrate, which has been etched to form a plurality of trenches. The trenches may be filled with a conductive material, such as a metal; and a process such as chemical mechanical planarization (CMP) may be used to polish the conductive material to expose the patterned ILD layer, thereby forming metal lines in the ILD layer. The above are non-limiting examples of devices / structures that may be manufactured and / or improved using the methods described herein.

[0129] exist Fig.21 , a method S2100 for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. In operation S2105, a first protective layer is spin-coated over an edge portion of a semiconductor substrate. In operation S2110, the edge-coated wafer undergoes a soft bake operation to cure / dry the first protective layer at a temperature of about 40° C. to about 120° C. Then, in operation S2115, a photoresist (e.g., a metal-containing photoresist) is arranged over the semiconductor substrate to form a photoresist layer. The photoresist layer is then heated in a resist bake operation S2120 to dry the photoresist layer at a temperature of about 40° C. to about 120° C. After drying the photoresist layer, in operation S2125, the first protective layer and a portion of the photoresist overlying the first protective layer are removed in an edge bead removal (EBR) operation. Then, in operation S2130, the photoresist layer is selectively exposed to actinic radiation to form a latent pattern therein. Then in operation S2135, a second protective layer is disposed over the edge portion of the semiconductor substrate. The second protective layer and the photoresist layer then undergo a post-exposure baking operation S2140. During the post-exposure baking operation S2140, the temperature, gas flow rate, and relative humidity parameters are controlled as disclosed herein. The photoresist layer is then developed to form a pattern in operation S2145, and the second protective layer and the resist edge beads are removed in operation S2150. The semiconductor substrate then undergoes additional manufacturing operations to form a semiconductor device.

[0130] exist Fig. 22 Another method 2200 for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown in FIG. In operation S2205, a first protective layer is spin-coated over an edge portion of a semiconductor substrate. In operation S2210, the edge-coated wafer undergoes a soft bake to cure / dry the first protective layer at a temperature of about 40° C. to about 120° C. Then, in operation S2215, a photoresist (e.g., a metal-containing photoresist) is disposed over the semiconductor substrate to form a first photoresist layer. In operation S2220, the first photoresist layer is heated to dry the first photoresist layer at a temperature of about 40° C. to about 120° C. After drying the first photoresist layer, in operation S2225, the first protective layer and a portion of the photoresist layer overlying the first protective layer are removed in an edge bead removal (EBR) operation. In operation S2230, the first photoresist layer is then selectively exposed to actinic radiation to form a first latent pattern therein. A plurality of potential pattern features extend in a first direction and are arranged along a second direction intersecting the first direction. In some embodiments, the first direction and the second direction are substantially orthogonal. Then in operation S2235, a second protective layer is disposed over an edge portion of the semiconductor substrate. Subsequently, in operation S2240, the second protective layer and the first photoresist layer undergo post-exposure baking. During the post-exposure baking, temperature, gas flow rate, and relative humidity parameters are controlled as disclosed herein. Next, in operation S2245, a second photoresist (e.g., a metal-containing photoresist) is disposed over the first photoresist layer to form a second photoresist layer. In operation S2250, the second photoresist layer is heated to dry the second photoresist layer at a temperature of about 40° C. to about 120° C. After drying the second photoresist layer, in operation S2255, the second protective layer and a portion of the second photoresist layer overlying the second protective layer are removed in an edge bead removal (EBR) operation. Then, in operation S2260, the second photoresist layer is selectively exposed to actinic radiation to form a second latent pattern therein. A plurality of second latent pattern features extend in a second direction and are arranged along a first direction that intersects the second direction. Then, in operation S2265, a third protective layer is disposed over an edge portion of the semiconductor substrate. In operation S2270, the third protective layer and the second photoresist layer undergo a post-exposure bake. During the post-exposure bake, temperature, gas flow rate, and relative humidity parameters are controlled as disclosed herein. Then, in operation S2275, the first and second photoresist layers are subsequently developed to form a pattern, and the third protective layer is removed in operation S2280. The resulting photoresist pattern is Fig.23, which shows a latent pattern formed by a first exposure, a latent pattern formed by a second exposure, and a resulting pattern formed by a development operation. The semiconductor substrate then undergoes additional manufacturing operations to form a semiconductor device.

[0131] exist Fig.24 Another embodiment of the method 2400 according to the present disclosure is shown in FIG. In this embodiment, in operation S2405, a first protective layer is formed over an edge portion of a first main surface of a semiconductor substrate. Then in operation S2410, the first protective layer is heated to cure / dry the first protective layer. Next, in operation S2415, a metal-containing layer is formed over the first main surface of the semiconductor substrate. Then in operation S2420, the first protective layer and the metal-containing layer are heated. In some embodiments, the first protective layer and the metal-containing layer are heated while controlling the intake and exhaust flow rates, the inlet gas temperature, and the relative humidity, as disclosed herein with respect to various embodiments. Subsequently, in operation S2425, the first protective layer and the metal-containing layer are removed from over an edge portion of the semiconductor substrate. In some embodiments, the heating of the protective layer and the metal-containing layer is performed at a temperature of about 100° C. to about 200° C. for about 10 seconds to about 5 minutes. In some embodiments, the method includes performing a second heating of the protective layer at a temperature of about 40° C. to about 120° C. before forming the metal-containing layer. In some embodiments, the metal-containing layer includes one or more metals selected from the group consisting of Ti, Al, Hf, Sn, Si, Zr, Ta, W, Cu, Co, La, and Mn. In some embodiments, the one or more metals are included in a metal compound or alloy. In some embodiments, the metal compound or alloy is one or more selected from the group consisting of TiO2, Al2O3, TaN, SiO2, ZrSiO, and HfSiO.

[0132] The present disclosure provides a method for photolithography. The disclosed method includes coating the wafer edge so that the resist material is constrained to be coated on the front side of the wafer within the circuit area, so that the wafer edge is free of resist material or is not directly coated with resist during the photolithography patterning method. Therefore, the wafer is protected by a (first / second) protective layer to eliminate various concerns during the photolithography process, including metal contamination. Control of the post-exposure baking operation (including control of gas flow rate, temperature and relative humidity) provides improved contaminant removal of contaminants generated by photoresist outgassing.

[0133] The disclosed method may include other operations before, during, or after the above operations. In an embodiment, the wafer is a semiconductor substrate, and the method proceeds to form a fin field effect transistor (FinFET) structure. In some embodiments, the method includes forming a plurality of active fins in a semiconductor substrate of the wafer. In a further improvement of this embodiment, the method further includes: etching the substrate through an opening of a patterned hard mask to form a trench in the substrate; filling the trench with a dielectric material; performing a chemical mechanical polishing (CMP) process to form a shallow trench isolation (STI) feature; and epitaxially growing or recessing the STI feature to form a fin-shaped active area. In another embodiment, the disclosed method includes other operations for forming a plurality of gate electrodes on a semiconductor substrate or wafer. The disclosed method may further form gate spacers, doped source / drain regions, contacts for gate / source / drain features, and the like. In another embodiment, the target pattern will be formed as a metal line in a multilayer interconnect structure. For example, the metal line may be formed in an interlayer dielectric (ILD) layer of a substrate, which has been etched by an operation to form a plurality of trenches. The disclosed method includes filling the trenches with a conductive material, such as a metal; and polishing the conductive material using a process such as chemical mechanical planarization (CMP) to expose the patterned ILD layer, thereby forming metal lines in the ILD layer. The above are non-limiting examples of devices / structures that can be manufactured and / or improved using the disclosed methods according to various aspects of the present disclosure.

[0134] As described above, the semiconductor wafer may be an intermediate structure fabricated during processing of an IC or a portion thereof, which may include logic circuits, memory structures, passive components (e.g., resistors, capacitors, and inductors), and active components such as diodes, field effect transistors (FETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, fin FETs (FinFETs), other three-dimensional (3D) FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. In some embodiments, contaminants generated by photoresist degassing are controlled to be less than about 100×10 11 Atom / cm 2 In other embodiments, contaminants generated by photoresist outgassing are controlled to less than about 1×10 11 Atom / cm 2 In some embodiments, the defect rate is reduced by more than 30% compared to a semiconductor device manufacturing method that does not employ the disclosed method.

[0135] Embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all of which are necessarily discussed herein, and all embodiments do not require specific advantages. By utilizing the disclosed method, the accumulation of resist material on the edge of the wafer and associated problems (such as contamination and resist stripping) are eliminated, and contamination caused by photoresist degassing is substantially suppressed. In other examples, the implementation of the disclosed method is economical and efficient, thereby reducing manufacturing costs and increasing manufacturing yields. In addition, wafer edge modification does not introduce additional contamination.

[0136] Embodiments of the present disclosure reduce contamination of semiconductor substrates and subsequently formed devices. Embodiments of the present disclosure reduce contamination of semiconductor manufacturing tools. In some embodiments, the reduction in contamination results in improved device yield and reduced manufacturing tool downtime.

[0137] Embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all of which are necessarily discussed herein, and all embodiments do not require specific advantages. By utilizing the disclosed method, the accumulation of resist materials on the edge of the wafer and associated problems (such as contamination and resist stripping) are eliminated. In other examples, the disclosed method for forming a protected wafer edge is easy to implement, thereby reducing manufacturing costs and increasing manufacturing yields. In addition, wafer edge modification does not introduce additional contamination. In other examples, various operations are implemented together on the same wafer stage of the track to improve processing efficiency and reduce manufacturing costs.

[0138] Embodiments of the present disclosure include a method for manufacturing a semiconductor device, including forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. Forming a metal-containing photoresist layer over the first main surface of the semiconductor substrate. Removing the first protective layer, and selectively exposing the metal-containing photoresist layer to actinic radiation. Forming a second protective layer over an edge portion of the first main surface of the semiconductor substrate. Developing the selectively exposed photoresist layer to form a patterned photoresist layer, and removing the second protective layer. In an embodiment, the method includes: first heating the selectively exposed metal-containing photoresist layer and the second protective layer, the first heating being performed at a temperature of 100° C. to 200° C. for 10 seconds to 5 minutes. In an embodiment, during the first heating, the semiconductor substrate is placed on the heated surface. In an embodiment, during the first heating, a gas at a temperature of 100° C. to 190° C. flows through the selectively exposed metal-containing photoresist layer and the second protective layer. In an embodiment, during the first heating, a gas at a temperature of 100° C. to 150° C. flows through the metal-containing photoresist layer and the second protective layer. In an embodiment, the method includes: before forming the metal-containing photoresist layer, performing a second heating on the first protective layer at a temperature of 40° C. to 120° C. In an embodiment, the method includes: performing a third heating on the first protective layer and the metal-containing photoresist layer before removing the first protective layer. In an embodiment, the metal-containing photoresist layer includes one or more of Cs, Ba, La, Ce, In, Sn, or Ag. In an embodiment, based on the total weight of the metal-containing photoresist layer, the metal concentration in the metal-containing photoresist layer is in the range of 10wt.% to 80wt.%. In an embodiment, the first protective layer and the second protective layer include organic materials.

[0139] In another embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer and the second protective layer are first heated in a heating chamber. During the first heating of the selectively exposed photoresist layer and the second protective layer, one or more parameters are controlled, wherein the parameters are selected from the following items: an air flow entering the heating chamber, an exhaust flow leaving the heating chamber, a temperature of the gas flowing into the heating chamber, and a relative humidity in the heating chamber. In an embodiment, the method includes: developing the selectively exposed photoresist layer to form a patterned photoresist layer. In an embodiment, the photoresist layer includes 10 wt.% to 80 wt.% of a metal based on the total weight of the photoresist layer. In an embodiment, the inlet temperature of the gas flowing into the heating chamber is 100°C to 190°C. In an embodiment, during the first heating period, the flow rate of the gas flowing into the heating chamber is in the range of 5L / min to 40L / min. In an embodiment, during the first heating period, the flow rate of the exhaust gas leaving the heating chamber is in the range of 10L / min to 50L / min. In an embodiment, during the first heating period, the relative humidity in the heating chamber is in the range of 1% to 50%. In an embodiment, the method includes: before forming the photoresist layer, performing a second heating on the first protective layer at a temperature of 40°C to 120°C. In an embodiment, the method includes: before removing the first protective layer, performing a third heating on the first protective layer and the photoresist layer.

[0140] Another embodiment of the present disclosure is a semiconductor manufacturing device, comprising: a heating chamber; a semiconductor substrate support, an airflow inlet and an airflow outlet in the heating chamber; and a gas heater. The controller is programmed to control the airflow entering the heating chamber through the airflow inlet, control the exhaust flow leaving the heating chamber through the airflow outlet, control the temperature of the gas flowing into the heating chamber, and control the relative humidity in the heating chamber. In an embodiment, the semiconductor substrate support includes a heating element. In an embodiment, the controller is programmed to control the airflow entering the heating chamber through the airflow inlet within a flow rate range of 5L / min to 40L / min. In an embodiment, the controller is programmed to control the exhaust gas leaving the heating chamber through the airflow outlet within a flow rate range of 10L / min to 50L / min. In an embodiment, the controller is programmed to control the temperature of the gas flowing into the heating chamber within a temperature range of 100°C to 190°C. In an embodiment, the controller is programmed to control the temperature of the gas flowing into the heating chamber within a temperature range of 100°C to 150°C. In an embodiment, the controller is programmed to control the relative humidity in the heating chamber within a relative humidity range of 1% to 50%.

[0141] Another embodiment of the present disclosure is a method, including forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing layer is formed over the first main surface of the semiconductor substrate. The first protective layer and the metal-containing layer are first heated. The first protective layer and the metal-containing layer are removed from the edge portion of the semiconductor substrate. In an embodiment, the first heating of the first protective layer and the metal-containing layer is performed at a temperature of 100° C. to 200° C. for 10 seconds to 5 minutes. In an embodiment, before forming the metal-containing layer, a second heating is performed on the first protective layer at a temperature of 40° C. to 120° C. In an embodiment, the metal-containing layer includes one or more metals selected from the group consisting of the following items: Ti, Al, Hf, Sn, Si, Zr, Ta, W, Cu, Co, La, and Mn. In an embodiment, the one or more metals are included in a metal compound or alloy. In an embodiment, the metal compound or alloy is one or more selected from the group consisting of the following items: TiO2, Al2O3, TaN, SiO2, ZrSiO, and HfSiO.

[0142] Another embodiment of the present disclosure is a method of manufacturing a semiconductor device, including forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. Forming a first metal-containing photoresist layer over the first main surface of the semiconductor substrate. Removing the first protective layer, and selectively exposing the first metal-containing photoresist layer to actinic radiation to form a first plurality of latent pattern features extending along a first direction and arranged along a second direction. Forming a second protective layer over an edge portion of the first main surface of the semiconductor substrate. The selectively exposed first photoresist layer is developed to form a patterned photoresist layer, the patterned photoresist layer including a first plurality of pattern features extending along the first direction and arranged along the second direction. Forming a second metal-containing photoresist layer over the first plurality of pattern features. Removing the second protective layer, and selectively exposing the second metal-containing photoresist layer to actinic radiation to form a second plurality of latent pattern features extending along the second direction and arranged along the first direction. Forming a third protective layer over an edge portion of the first main surface of the semiconductor substrate. The selectively exposed second photoresist layer is developed to form a patterned photoresist layer including a second plurality of pattern features. In an embodiment, the method includes: removing the third protective layer. In an embodiment, the method includes: first heating the selectively exposed first metal-containing photoresist layer and the second protective layer, the first heating being performed at a temperature of 100° C. to 150° C. for 10 seconds to 5 minutes. In an embodiment, the method includes: second heating the selectively exposed second metal-containing photoresist layer and the third protective layer, the second heating being performed at a temperature of 100° C. to 150° C. for 10 seconds to 5 minutes. In an embodiment, during the first heating or the second heating, the semiconductor substrate is placed on the heated surface. In an embodiment, a gas at a temperature of 100° C. to 150° C. flows through the selectively exposed first metal-containing photoresist layer and the second protective layer during the first heating, or flows through the selectively exposed second metal-containing photoresist layer and the third protective layer during the second heating. In an embodiment, the method includes: before forming the first metal-containing photoresist layer, performing a third heating on the first protective layer at a temperature of 40°C to 120°C. In an embodiment, the method includes: before removing the second protective layer, performing a fourth heating on the second metal-containing photoresist layer at a temperature of 40°C to 120°C. In an embodiment, the first metal-containing photoresist layer and the second metal-containing photoresist layer include one or more of Cs, Ba, La, Ce, In, Sn or Ag. In an embodiment, the metal concentration in the first metal-containing photoresist layer and the second metal-containing photoresist layer is in the range of 10wt.% to 80wt.% based on the total weight of the first metal-containing photoresist layer or the second metal-containing photoresist layer, respectively. In an embodiment, the first protective layer, the second protective layer and the third protective layer include organic materials.In an embodiment, the method includes etching the exposed portion of the semiconductor substrate, thereby extending the second plurality of pattern features in the first photoresist layer and the second photoresist layer into the semiconductor substrate.

[0143] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0144] Example 1 is a method for manufacturing a semiconductor device, comprising: forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate; forming a metal-containing photoresist layer over the first main surface of the semiconductor substrate; removing the first protective layer; selectively exposing the metal-containing photoresist layer to actinic radiation; forming a second protective layer over the edge portion of the first main surface of the semiconductor substrate; developing the selectively exposed metal-containing photoresist layer to form a patterned photoresist layer; and removing the second protective layer.

[0145] Example 2 is the method described in Example 1, further comprising: performing a first heating on the selectively exposed metal-containing photoresist layer and the second protective layer, the first heating being performed at a temperature of 100° C. to 200° C. for 10 seconds to 5 minutes.

[0146] Example 3 is the method of Example 2, wherein during the first heating, the semiconductor substrate is placed on a heated surface.

[0147] Example 4 is the method of Example 3, wherein during the first heating, a gas having a temperature of 100° C. to 190° C. flows through the selectively exposed metal-containing photoresist layer and the second protective layer.

[0148] Example 5 is the method of Example 1, further comprising: before forming the metal-containing photoresist layer, performing a second heating on the first protective layer at a temperature of 40° C. to 120° C.

[0149] Example 6 is the method of Example 1, further comprising: performing a third heating on the first protective layer and the metal-containing photoresist layer before removing the first protective layer.

[0150] Example 7 is the method of Example 1, wherein the metal-containing photoresist layer includes one or more of Cs, Ba, La, Ce, In, Sn, or Ag.

[0151] Example 8 is the method of Example 1, wherein a metal concentration in the metal-containing photoresist layer is in a range of 10 wt. % to 80 wt. % based on a total weight of the metal-containing photoresist layer.

[0152] Example 9 is the method of Example 1, wherein the first protective layer and the second protective layer include organic materials.

[0153] Example 10 is a method for manufacturing a semiconductor device, comprising: forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate; forming a photoresist layer over the first main surface of the semiconductor substrate; removing the first protective layer; selectively exposing the photoresist layer to actinic radiation; forming a second protective layer over the edge portion of the first main surface of the semiconductor substrate; and performing a first heating on the selectively exposed photoresist layer and the second protective layer in a heating chamber; wherein, during the first heating of the selectively exposed photoresist layer and the second protective layer, one or more parameters are controlled, wherein the parameters are selected from the following items: an air flow entering the heating chamber, an exhaust flow leaving the heating chamber, a temperature of a gas flowing into the heating chamber, and a relative humidity in the heating chamber.

[0154] Example 11 is the method of Example 10, further comprising: developing the selectively exposed photoresist layer to form a patterned photoresist layer.

[0155] Example 12 is the method of Example 10, wherein the photoresist layer includes 10 wt. % to 80 wt. % of the metal based on the total weight of the photoresist layer.

[0156] Example 13 is the method of Example 10, wherein an inlet temperature of the gas flowing into the heating chamber is 100°C to 190°C.

[0157] Example 14 is the method of Example 10, wherein during the first heating period, a flow rate of the gas flowing into the heating chamber is in a range of 5 L / min to 40 L / min.

[0158] Example 15 is the method of Example 10, wherein during the first heating period, a flow rate of exhaust gas exiting the heating chamber is in a range of 10 L / min to 50 L / min.

[0159] Example 16 is the method of Example 10, wherein during the first heating period, the relative humidity within the heating chamber is in a range of 1% to 50%.

[0160] Example 17 is the method of Example 10, further comprising: before forming the photoresist layer, performing a second heating on the first protective layer at a temperature of 40° C. to 120° C.

[0161] Example 18 is the method of Example 10, further comprising: before removing the first protective layer, performing a third heating on the first protective layer and the photoresist layer.

[0162] Example 19 is a semiconductor manufacturing device, comprising: a heating chamber; a semiconductor substrate support in the heating chamber; an air flow inlet in the heating chamber; an air flow outlet in the heating chamber; a gas heater; and a controller programmed to perform the following items: control the air flow entering the heating chamber through the air flow inlet, control the exhaust flow leaving the heating chamber through the air flow outlet, control the temperature of the gas flowing into the heating chamber, and control the relative humidity within the heating chamber.

[0163] Example 20 is the semiconductor manufacturing apparatus of Example 19, wherein the semiconductor substrate support comprises a heating element.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first protective layer over an edge portion of the first main surface of the semiconductor substrate; forming a first metal-containing photoresist layer over the first major surface of the semiconductor substrate; removing the first protective layer; selectively exposing the first metal-containing photoresist layer to actinic radiation to form a plurality of first latent pattern features extending in a first direction and arranged along a second direction; forming a second protective layer over the edge portion of the first main surface of the semiconductor substrate; developing the selectively exposed first metal-containing photoresist layer to form a patterned photoresist layer including a plurality of first pattern features extending in the first direction and arranged along the second direction; forming a second metal-containing photoresist layer over the plurality of first pattern features; removing the second protective layer; selectively exposing the second metal-containing photoresist layer to actinic radiation to form a plurality of second latent pattern features extending in the second direction and arranged along the first direction; forming a third protective layer over the edge portion of the first main surface of the semiconductor substrate; developing the selectively exposed second metal-containing photoresist layer to form a patterned photoresist layer including a plurality of second pattern features extending in the second direction and arranged along the first direction; and The third protective layer is removed.

2. The method according to claim 1, further comprising: The selectively exposed first metal-containing photoresist layer and the second protective layer are first heated at a temperature of 100° C. to 200° C. for 10 seconds to 5 minutes.

3. The method according to claim 2, wherein: During the first heating, the semiconductor substrate is placed on a heated surface.

4. The method according to claim 3, wherein: During the first heating period, a gas having a temperature of 100° C. to 190° C. flows through the selectively exposed first metal-containing photoresist layer and the second protective layer.

5. The method according to claim 1, further comprising: Before forming the first metal-containing photoresist layer, the first protective layer is subjected to a second heating at a temperature of 40° C. to 120° C.

6. The method according to claim 1, further comprising: The first protective layer and the first metal-containing photoresist layer are subjected to a third heating before removing the first protective layer.

7. The method according to claim 1, wherein: The first metal-containing photoresist layer includes one or more of Cs, Ba, La, Ce, In, Sn, or Ag.

8. The method according to claim 1, wherein: The metal concentration in the first metal-containing photoresist layer is in a range of 10 wt. % to 80 wt. % based on the total weight of the first metal-containing photoresist layer.

9. The method according to claim 1, wherein: The first protective layer and the second protective layer include an organic material.

10. A method for manufacturing a semiconductor device, comprising: forming a first protective layer over an edge portion of the first main surface of the semiconductor substrate; forming a first photoresist layer over the first major surface of the semiconductor substrate; removing the first protective layer; selectively exposing the first photoresist layer to actinic radiation to form a plurality of first latent pattern features extending in a first direction and arranged along a second direction; forming a second protective layer over the edge portion of the first main surface of the semiconductor substrate; developing the selectively exposed first photoresist layer to form a patterned photoresist layer including a plurality of first pattern features extending in the first direction and arranged along the second direction; forming a second photoresist layer over the plurality of first pattern features; removing the second protective layer; selectively exposing the second photoresist layer to actinic radiation to form a plurality of second latent pattern features extending in the second direction and arranged along the first direction; forming a third protective layer over the edge portion of the first main surface of the semiconductor substrate; developing the selectively exposed second photoresist layer to form a patterned photoresist layer including a plurality of second pattern features extending in the second direction and arranged along the first direction; as well as removing the third protective layer, Wherein, the method further comprises: Performing a first heating on the selectively exposed first photoresist layer and the second protective layer in a heating chamber; During the first heating of the selectively exposed first photoresist layer and the second protective layer, one or more parameters are controlled, wherein the parameters are selected from the following items: the air flow entering the heating chamber, the exhaust flow leaving the heating chamber, the temperature of the gas flowing into the heating chamber, and the relative humidity in the heating chamber.

11. The method according to claim 10, wherein: The first photoresist layer includes 10 wt. % to 80 wt. % of the metal based on the total weight of the first photoresist layer.

12. The method according to claim 10, wherein: The inlet temperature of the gas flowing into the heating chamber is 100°C to 190°C.

13. The method according to claim 10, wherein: During the first heating period, a flow rate of the gas flowing into the heating chamber is in a range of 5 L / min to 40 L / min.

14. The method according to claim 10, wherein: During the first heating period, the flow rate of the exhaust gas leaving the heating chamber is in the range of 10 L / min to 50 L / min.

15. The method according to claim 10, wherein: During the first heating period, the relative humidity within the heating chamber is in a range of 1% to 50%.

16. The method according to claim 10, further comprising: Before forming the first photoresist layer, the first protective layer is subjected to a second heating at a temperature of 40° C. to 120° C.

17. The method according to claim 10, further comprising: Before removing the first protective layer, the first protective layer and the first photoresist layer are subjected to a third heating.

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