Processor performance testing method and device

Abstract

The embodiment of the present invention provides a processor performance test method and device, which relates to the technical field of electronic device testing, wherein the method comprises: creating at least two threads running on a processor; controlling the created threads to perform parallel sorting processing on data in an unordered data group respectively, until the cumulative time for each thread to perform the sorting processing is not less than a preset time; counting the total number of times each thread completes the sorting processing; and calculating a performance value used to represent the performance of the processor according to the total number of times to obtain a test result. The solution provided by the embodiment of the present invention can be used to test the performance of the processor in an electronic device.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment testing, and in particular to a processor performance testing method and device. Background Art

[0002] Electronic devices are composed of a variety of different components. For example, electronic computers contain data storage devices, electronic screens, processors, etc. The performance of each component will affect the performance of the electronic device, especially the processor used for data processing, which will directly affect the speed at which the electronic device processes data, thereby affecting the performance of the electronic device.

[0003] There are many different processors in the prior art, and the performance of different processors is different. If the performance of an electronic device is to be tested, the performance of the processor in the electronic device needs to be tested. Summary of the invention

[0004] The purpose of the embodiment of the present invention is to provide a processor performance testing method and device to test the performance of the processor in the electronic device. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present invention provides a processor performance testing method, the method comprising:

[0006] Create at least two threads to run on the processor;

[0007] Control the created threads to perform parallel sorting processing on the data in the disordered data group respectively, until the cumulative time length of the sorting processing by each thread is not less than the preset time length;

[0008] Count the total number of times each thread completes the sorting process;

[0009] A performance value representing the performance of the processor is calculated according to the total number of times to obtain a test result.

[0010] In one embodiment of the present invention, the control creates threads that perform parallel sorting processing on the data in the unordered data group until the cumulative time for each thread to perform the sorting processing is not less than a preset time, including:

[0011] For each created thread, the thread is controlled to perform sorting processing in the following way:

[0012] Randomly generate an unordered data set;

[0013] Controlling the thread to sort the data in the generated unordered data group until the thread completes the sorting process;

[0014] Determine whether the accumulated duration of the thread since the generation of the first unordered data group reaches the preset duration;

[0015] If not, return to execute the step of randomly generating an unordered data group.

[0016] In one embodiment of the present invention, the step of creating at least two threads running on a processor includes:

[0017] Determine the maximum number of threads that can be created on a processor;

[0018] The maximum number of threads is created to run on the processor.

[0019] In one embodiment of the present invention, the step of calculating a performance value representing the performance of the processor according to the total number of times to obtain a test result includes:

[0020] determining an intrinsic property of the processor;

[0021] Obtaining a first impact value of the total number of times on the performance of the processor, and obtaining a second impact value of the determined inherent attribute on the performance of the processor;

[0022] Based on the obtained first impact value and second impact value, the performance value is calculated to obtain a test result.

[0023] In one embodiment of the present invention, the method further comprises:

[0024] Count the number of times each thread completes the sorting process;

[0025] Determine the amount of processor resources occupied by a core running each thread in the process of controlling the running of the thread, wherein the core is a physical core or a logical core;

[0026] For each core, obtain a first sub-influence value of the sub-number of threads running on the core on the performance of the core, and obtain a second sub-influence value of the amount of resources of the core on the performance of the core;

[0027] Based on the obtained first sub-impact value and the second sub-impact value, a sub-performance value for representing the performance of each core in the processor is calculated.

[0028] In one embodiment of the present invention, for each thread, the sorting process is implemented by one of the following algorithms:

[0029] Insertion sort algorithm, heap sort algorithm, radix sort algorithm, quick sort algorithm, bubble sort algorithm, Shell sort algorithm, selection sort algorithm, bottom-up merge sort algorithm, top-down merge sort algorithm.

[0030] In a second aspect, an embodiment of the present invention provides a processor performance testing device, the device comprising:

[0031] A thread creation module, used for creating at least two threads running on the processor;

[0032] A sorting processing module, used to control the created threads to perform parallel sorting processing on the data in the disordered data group, until the cumulative time for each thread to perform the sorting processing is not less than a preset time;

[0033] The times statistics module is used to count the total number of times each thread completes the sorting process;

[0034] The performance determination module is used to calculate a performance value representing the performance of the processor according to the total number of times to obtain a test result.

[0035] In one embodiment of the present invention, the sorting processing module includes:

[0036] For each created thread, the thread is controlled to be sorted through the sorting processing submodule;

[0037] The sorting processing submodule is specifically used for:

[0038] Randomly generate an unordered data set;

[0039] Controlling the thread to sort the data in the generated unordered data group until the thread completes the sorting process;

[0040] Determine whether the accumulated duration of the thread since the generation of the first unordered data group reaches the preset duration;

[0041] If not, return to execute the step of randomly generating an unordered data group.

[0042] In one embodiment of the present invention, the thread creation module is specifically used to:

[0043] Determine the maximum number of threads that can be created on a processor;

[0044] The maximum number of threads is created to run on the processor.

[0045] In one embodiment of the present invention, the performance determination module is specifically used to:

[0046] determining an intrinsic property of the processor;

[0047] Obtaining a first impact value of the total number of times on the performance of the processor, and obtaining a second impact value of the determined inherent attribute on the performance of the processor;

[0048] Based on the obtained first impact value and second impact value, the performance value is calculated to obtain a test result.

[0049] In one embodiment of the present invention, the device further comprises:

[0050] The sub-number statistics module is used to count the number of sub-numbers of sorting processes completed by each thread;

[0051] A resource amount determination module, used to determine the amount of processor resources occupied by a core running each thread in the process of controlling the running of the thread, wherein the core is a physical core or a logical core;

[0052] A sub-influence value obtaining module, used for obtaining, for each core, a first sub-influence value of the sub-number of threads running on the core on the performance of the core, and obtaining a second sub-influence value of the amount of resources of the core on the performance of the core;

[0053] The sub-performance value calculation module is used to calculate a sub-performance value for representing the performance of each core in the processor based on the obtained first sub-impact value and the second sub-impact value.

[0054] In one embodiment of the present invention, for each thread, the sorting process is implemented by one of the following algorithms:

[0055] Insertion sort algorithm, heap sort algorithm, radix sort algorithm, quick sort algorithm, bubble sort algorithm, Shell sort algorithm, selection sort algorithm, bottom-up merge sort algorithm, top-down merge sort algorithm.

[0056] In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0057] Memory, used to store computer programs;

[0058] The processor is used to implement any method step described in the first aspect when executing a program stored in the memory.

[0059] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any method step described in the first aspect is implemented.

[0060] In a fifth aspect, an embodiment of the present invention further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the method steps described in the first aspect.

[0061] Beneficial effects of the embodiments of the present invention:

[0062] When the solution provided by the embodiment of the present invention is applied to test the performance of a processor, at least two threads may be created in the processor. Each thread is controlled to perform parallel sorting processing on the data in the disordered data group, until the cumulative time for each thread to perform the sorting processing is not less than the preset time. The total number of times each thread completes the sorting processing is counted, and based on the total number of times obtained by counting, a performance value used to represent the performance of the processor is calculated to obtain a test result.

[0063] As can be seen from the above, since the processor is mainly a device for data processing, the faster the processor processes data, the better the performance of the processor. Therefore, when the scheme provided by the embodiment of the present invention is applied to test the performance of the processor, the sorting process is used as a representative of the data processing, and the total number of times the threads in the processor complete the sorting process is counted. The more the above total number of times, it means that the processor can perform a larger number of sorting processes within a certain time, indicating that the faster the processor performs data processing, the better the performance of the processor. On the contrary, the fewer the above total number of times, it means that the processor can only perform a smaller number of sorting processes within a certain time, indicating that the slower the processor performs data processing, the worse the performance of the processor. Therefore, the scheme provided by the embodiment of the present invention can be used to calculate the performance value used to represent the performance of the processor and obtain the test result. In addition, the above sorting process is a data processing flow with simpler logic and higher maturity, so the probability of failure during repeated execution is lower, which is more suitable for determining the performance of the processor in the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0065] Figure 1 A schematic diagram of a flow chart of a first processor performance testing method provided by an embodiment of the present invention;

[0066] Figure 2A A schematic diagram of a flow chart of a second processor performance testing method provided by an embodiment of the present invention;

[0067] Figure 2B A schematic diagram of a flow chart of a third processor performance testing method provided by an embodiment of the present invention;

[0068] Figure 3 A schematic diagram of the structure of a first processor performance testing device provided by an embodiment of the present invention;

[0069] Figure 4A A schematic diagram of the structure of a second processor performance testing device provided by an embodiment of the present invention;

[0070] Figure 4B A schematic diagram of the structure of a third processor performance testing device provided by an embodiment of the present invention;

[0071] Figure 5 The present invention is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0073] In order to determine the performance of a processor, an embodiment of the present invention provides a method and device for testing the performance of a processor.

[0074] In one embodiment of the present invention, a processor performance testing method is provided, the method comprising:

[0075] Create at least two threads that run on the processor.

[0076] The created threads are controlled to perform parallel sorting processing on the data in the disordered data group respectively, until the accumulated time length for the sorting processing by each thread is not less than the preset time length.

[0077] Count the total number of times each thread completes the sorting process.

[0078] According to the total number of times, a performance value representing the performance of the processor is calculated to obtain a test result.

[0079] As can be seen from the above, since the processor is mainly a device for data processing, the faster the processor processes data, the better the performance of the processor. Therefore, when the scheme provided by the embodiment of the present invention is applied to test the performance of the processor, the sorting process is used as a representative of the data processing, and the total number of times the threads in the processor complete the sorting process is counted. The more the above total number of times, it means that the processor can perform a larger number of sorting processes within a certain time length, indicating that the faster the processor performs data processing, the better the performance of the processor. On the contrary, the fewer the above total number of times, it means that the processor can only perform a smaller number of sorting processes within a certain time length, indicating that the slower the processor performs data processing, the worse the performance of the processor. Therefore, the scheme provided by the embodiment of the present invention can be used to calculate the performance value used to represent the performance of the processor and obtain the test result. In addition, the above sorting process is a data processing flow with simpler logic and higher maturity, so the probability of failure during repeated execution is lower, which is more suitable for determining the performance of the processor in the electronic device.

[0080] The processor performance testing method and device provided by the embodiment of the present invention are described below through specific embodiments.

[0081] See also Figure 1 , an embodiment of the present invention provides a flow chart of a first processor performance testing method, and the above method can be implemented through the following steps S101-S104.

[0082] S101: Create at least two threads running on a processor.

[0083] The above-mentioned processors may be all processors or part of processors included in the electronic device.

[0084] The above-mentioned thread is the smallest unit for data processing in the processor, and each thread can independently perform different data processing.

[0085] Specifically, the number of threads created above may be a fixed preset number, such as 2, 4, etc.

[0086] However, since the number of processors included in different electronic devices is different, the number of physical cores included in different processors is also different, and some processors also support hyperthreading, that is, support logical core expansion. Therefore, the number of physical cores or logical cores included in different electronic devices is different. Since each physical core or logical core can run a thread at the same time, the number of threads that can be run in parallel by the electronic device is limited. The number of created threads can match the inherent number of physical cores or logical cores of the electronic device, which is less than or equal to the number of threads that can be run in parallel by the electronic device.

[0087] For example, if the electronic device includes two processors, each of which is a dual-core processor, that is, each processor includes two physical cores, that is, the electronic device includes four physical cores, and if each physical core supports two logical core expansions, then the electronic device includes a total of eight logical cores, and the electronic device can run eight threads in parallel. The number of threads created above can be less than or equal to eight, such as six, four, etc.

[0088] Furthermore, the number of threads input by the user may be received as the number of created threads.

[0089] In one embodiment of the present invention, a thread may be created by inheriting the Thread class, implementing the Runnable interface, implementing the Callable interface, or using a thread pool.

[0090] In another embodiment of the present invention, the above step S101 can be implemented through steps S101A-S101B, which will not be described in detail here.

[0091] S102: Control the created threads to perform parallel sorting processing on the data in the unordered data group respectively, until the accumulated time duration of the sorting processing by each thread is not less than a preset time duration.

[0092] In one embodiment of the present invention, a sorting algorithm may be applied to sort the data in each disordered data group. Specifically, different threads may use the same sorting algorithm to sort the data in the disordered data group, or may use different sorting algorithms to sort the data in the disordered data group.

[0093] For each thread, the sorting algorithm may be one of the following algorithms:

[0094] Insertion sort algorithm, heap sort algorithm, radix sort algorithm, quick sort algorithm, bubble sort algorithm, shell sort algorithm, selection sort algorithm, bottom-up merge sort algorithm or top-down merge sort algorithm.

[0095] The above-mentioned various sorting algorithms are all common algorithms in the prior art, and the embodiments of the present invention will not be described in detail. Of course, the embodiments of the present invention can also perform sorting processing through other sorting algorithms.

[0096] In addition, the thread can also be controlled to repeatedly traverse the unordered data group, and find the data arranged in order in order of data size, so as to complete the sorting process of the unordered data group.

[0097] For each thread, the sorting process performed by the thread can be referred to as a task executed by the thread.

[0098] The above-mentioned unordered data group may be a data group of preset length, the above-mentioned unordered data group may be randomly generated during the execution of the above-mentioned step S102, or may be a preset unordered data group.

[0099] When randomly generating a random data group, the length of the data group received from the user input may be used as the length of the generated random data group.

[0100] Specifically, the unordered data groups processed by different threads may be the same or different. The data contained in the unordered data groups may be integer data, floating point data, character data or other types of data.

[0101] In addition, the duration received from the user input may be used as the preset duration. For example, the preset duration may be 3s, 5s, 10s, etc.

[0102] The above-mentioned accumulated duration may be the duration that has passed since the thread performs the first sorting process.

[0103] In addition, in one embodiment of the present invention, the created threads can be controlled by the main thread to perform sorting processing, and the created threads can be called child threads. The main thread can send a start signal to each child thread at the same time, so that each child thread starts sorting processing in parallel after receiving the start signal.

[0104] Specifically, the start signal may be represented in the form of a semaphore. For example, a semaphore with a value of 1 may be used as the start signal. If the child thread receives a semaphore with a value of 1, it starts sorting. Otherwise, it continues to wait for the start signal.

[0105] After the electronic device receives the processor performance test instruction input by the user, the above step S101 can be executed to create the above thread. After the above thread is created, the sorting process can be started. Therefore, the main thread can send the above start signal to each sub-thread after the electronic device receives the processor performance test instruction input by the user and after a preset waiting time. The above preset waiting time can be used to create the above thread. For example, the above processor performance test instruction can be an instruction input by the user by clicking the processor performance test button, and the above preset waiting time can be 3s, 5s, etc.

[0106] In another embodiment of the present invention, for each created thread, the thread can be controlled to be sorted through steps A to C, which will not be described in detail here.

[0107] S103: Count the total number of times each thread completes the sorting process.

[0108] The thread completes the sorting process, which means that the thread arranges the data in the disordered data group into an ordered data group arranged in a preset order. The preset order may be from large to small or from small to large.

[0109] In one embodiment of the present invention, the number of sorting processes completed by each thread may be counted respectively, and the counted numbers may be added together to obtain the above total number.

[0110] Specifically, a counter may be set for each thread, and each counter is reset to zero before controlling each thread to perform sorting. For each thread, a count is performed in the counter of the thread each time the thread completes a sorting process. After executing step S102, the counter value of the counter of the thread is the number of sorting processes completed by the thread. The total number of times may be obtained by summing the counter values ​​of each counter.

[0111] S104: Calculate a performance value representing the performance of the processor according to the total number of times to obtain a test result.

[0112] Specifically, since the processor is mainly used for data processing, the faster the processor processes data, the better the performance of the processor. Sorting processing is a type of data processing. The larger the total number, the more times the processor completes the sorting processing, the faster the processor processes data, and the better the performance of the processor. Therefore, it can be considered that the larger the value of the performance value calculated based on the total number, the better the performance of the processor. Therefore, the test result of the performance of the processor can be obtained based on the performance value.

[0113] In one embodiment of the present invention, the total number of times may be directly used as the performance value, or the total number of times may be multiplied by a first parameter to obtain the performance value.

[0114] The number of sorting processes completed by the processor per unit time may also be calculated as the performance value.

[0115] Specifically, when the unit time is 1 second, the calculation result obtained by dividing the total number of times by the preset time length can be used as the performance value. The larger the performance value is, the better the performance of the processor is. In addition, the calculation result can be multiplied by the second parameter to obtain the performance value. In addition, the unit time can also be 2 seconds, 5 seconds, etc.

[0116] Furthermore, a corresponding relationship between the total number of times and the performance value may also be set, so when the total number of times is obtained by statistics, the performance value corresponding to the total number of times may be determined according to the corresponding relationship, wherein the corresponding relationship may be a linear relationship or a nonlinear relationship.

[0117] In another embodiment of the present invention, since the inherent properties of the processor can also reflect the performance of the processor, the above step S104 can also be implemented through the following steps D-F.

[0118] Step D: Determine the intrinsic properties of the above processor.

[0119] The inherent attributes of the processor may include at least one of the following information: the number of physical cores, the number of logical cores, the core frequency, the cache capacity, etc.

[0120] Since theoretically, the more physical cores, the more logical cores, the higher the core frequency, and the higher the cache capacity of a processor, the better the performance of the processor, the above basic information can also be used to calculate a performance value representing the performance of the above processor.

[0121] In one embodiment of the present invention, information of a processor recorded by an electronic device may be accessed, and one or more items of the above information may be used as inherent attributes of the above processor.

[0122] Step E: Obtain a first impact value of the total number of times on the performance of the processor, and obtain a second impact value of the determined inherent attribute on the performance of the processor.

[0123] Wherein, a corresponding relationship between the value of each inherent attribute and the second influence value may be set for each inherent attribute.

[0124] (1) For the number of physical cores, different numbers of physical cores correspond to different second impact values. Theoretically, it can be considered that the larger the number of physical cores, the larger the second impact value. The corresponding relationship between the number of physical cores and the second impact value can be a linear relationship or a nonlinear relationship.

[0125] For example, the second impact value corresponding to 2 physical cores is 100, the second impact value corresponding to 4 physical cores is 300, the second impact value corresponding to 6 physical cores is 600, etc., then the corresponding relationship between the above physical core numbers and the second impact values ​​is a nonlinear relationship.

[0126] In addition, due to the influence of actual conditions, a larger number of physical cores may not necessarily lead to better processor performance. For example, when the number of physical cores is large, the operation of multiple physical cores together may cause the processor to overheat, which in turn leads to a decrease in processor performance. Therefore, the corresponding relationship between the number of physical cores and the second impact value may not necessarily be: the larger the number of physical cores, the larger the second impact value. When the number of physical cores exceeds a certain number of physical cores, the larger the number of physical cores, the smaller the second impact value.

[0127] For example, the second impact value corresponding to 6 physical cores is 600, the second impact value corresponding to 10 physical cores is 500, and so on.

[0128] (ii) With respect to the number of logical cores, different numbers of logical cores correspond to different performance sub-values. Theoretically, it can be considered that the larger the number of logical cores, the larger the above-mentioned second impact value. The corresponding relationship between the above-mentioned number of logical cores and the second impact value can be a linear relationship or a nonlinear relationship.

[0129] For example, the second impact value corresponding to 2 logical cores is 100, the second impact value corresponding to 4 logical cores is 200, and the second impact value corresponding to 8 logical cores is 400. Then the corresponding relationship between the above logical core numbers and the second impact values ​​is a linear relationship.

[0130] In addition, since the logical core is a virtual core expanded when the physical core supports hyperthreading, and since the physical computing resources such as the number of physical cores, core frequency and cache capacity in the processor are fixed, too many logical cores may result in insufficient physical computing resources to support the normal operation of a large number of logical cores. Therefore, when there are too many logical cores, the performance of the above processor may decline. Therefore, the corresponding relationship between the number of logical cores and the second impact value may not necessarily be: the larger the number of logical cores, the larger the second impact value. When the number of logical cores exceeds a certain number of logical cores, the larger the number of logical cores, the smaller the second impact value.

[0131] For example, the second impact value corresponding to 8 logical cores is 400, the second impact value corresponding to 10 logical cores is 300, and so on.

[0132] (III) For core frequency, different core frequency intervals correspond to different performance sub-values. Theoretically, it can be considered that the higher the core frequency, the greater the above-mentioned second impact value. Among them, the corresponding relationship between the above-mentioned core frequency and the second impact value can be a linear relationship or a nonlinear relationship.

[0133] For example, the second impact value corresponding to the core frequency 1000MHz-2000MHz is 200, the second impact value corresponding to the core frequency 2000MHz-3000MHz is 400, the second impact value corresponding to the core frequency 3000MHz-4000MHz is 600, etc., then the corresponding relationship between the above core frequency and the second impact value is a linear relationship.

[0134] In addition, due to the influence of actual conditions, a higher core frequency may not necessarily lead to better processor performance. For example, when the core frequency is high, the physical core may cause the processor to overheat when running, which in turn leads to a decrease in processor performance. Therefore, the corresponding relationship between the core frequency and the second impact value may not necessarily be: the higher the core frequency, the greater the second impact value. When the core frequency exceeds a certain core frequency, the higher the core frequency, the smaller the second impact value.

[0135] For example, the second impact value corresponding to the core frequency of 3000MHz-4000MHz is 600, the second impact value corresponding to the core frequency of 4000MHz-5000MHz is 400, and so on.

[0136] (IV) Regarding cache capacity, it can be considered in theory that the larger the cache capacity is, the larger the second impact value is. The corresponding relationship between the cache capacity and the second impact value can be a linear relationship or a nonlinear relationship.

[0137] In addition, since the processor may include multiple levels of cache, different cache capacity ranges of different levels of cache have different corresponding second impact values. For example, for the first-level cache, the second impact value corresponding to the cache capacity of 100KB-150KB is 100, and for the second-level cache, the second impact value corresponding to the cache capacity of 1000KB-2000KB is 100, and so on.

[0138] In one embodiment of the present invention, the second impact value corresponding to the actual value of each inherent attribute of the processor may be determined according to the correspondence between the preset inherent attribute values ​​and the second impact value.

[0139] In addition, various parts of the processor may affect each other and jointly affect the performance of the processor.

[0140] For example, although the processor has a large number of logical cores, the cache capacity is small. When multiple logical cores are running together, due to the small cache capacity, sufficient cache cannot be provided for each logical core, affecting the operation of the logical cores and causing the performance of the processor to decline.

[0141] Or, although the processor has a large cache capacity, but the number of physical cores is small, it is difficult for the physical cores to fully use all caches during operation, that is, it always contains some free cache. Although the cache capacity is large, the impact on the performance of the processor is limited.

[0142] Therefore, in the case of the second impact value of the inherent attribute on the performance of the processor, multiple inherent attributes may be comprehensively referenced to jointly determine the second impact value of the inherent attribute on the performance of the processor.

[0143] In addition, regarding the total number of times, the embodiment of obtaining the first impact value according to the above total number of times is similar to the embodiment of obtaining the performance value according to the above total number of times, and will not be described in detail here.

[0144] In another embodiment of the present invention, the first influence value obtained according to the total number of times and the second influence value corresponding to the inherent attribute may be statistically processed to obtain the performance value.

[0145] Specifically, the statistical method for performing statistics may be calculating a sum, calculating a weighted sum, calculating an average, calculating a weighted average, etc., or other statistical methods may be used.

[0146] As can be seen from the above, since the inherent properties of the above processors can theoretically reflect the performance of the processors themselves, in addition to the total number of times obtained by actually running the above processors, the performance value of the above processors can also be calculated based on the above inherent properties.

[0147] In yet another embodiment of the present invention, the performance value may be displayed after being calculated, so that a user may determine the performance of the processor according to the performance value.

[0148] In addition, the inherent properties of the processors, the ranking algorithm used in calculating the performance values ​​of the processors, etc. may also be displayed.

[0149] Furthermore, the performance of the processor can be judged and displayed according to the performance value. For example, the performance of the processor can be represented by three levels: high, medium and low. When the calculated performance value is 0-500, the performance of the processor is low, when the performance value is 500-2000, the performance of the processor is medium, and when the performance value is greater than 2000, the performance of the processor is high.

[0150] As can be seen from the above, since the processor is mainly a device for data processing, the faster the processor processes data, the better the performance of the processor. Therefore, when the scheme provided by the embodiment of the present invention is applied to test the performance of the processor, the sorting process is used as a representative of the data processing, and the total number of times the threads in the processor complete the sorting process is counted. The more the above total number of times, it means that the processor can perform a larger number of sorting processes within a certain time, indicating that the faster the processor performs data processing, the better the performance of the processor. On the contrary, the fewer the above total number of times, it means that the processor can only perform a smaller number of sorting processes within a certain time, indicating that the slower the processor performs data processing, the worse the performance of the processor. Therefore, the scheme provided by the embodiment of the present invention can be used to calculate the performance value used to represent the performance of the processor and obtain the test result. In addition, the above sorting process is a data processing flow with simpler logic and higher maturity, so the probability of failure during repeated execution is lower, which is more suitable for determining the performance of the processor in the electronic device.

[0151] In one embodiment of the present invention, for each created thread, the following steps A to C can be used to control the thread to perform sorting processing.

[0152] Step A: Randomly generate an unordered data set.

[0153] Specifically, the randomly generated unordered data group may be a data group of a preset length.

[0154] Step B: Control the thread to sort the data in the generated unordered data group until the thread completes the sorting process.

[0155] Specifically, completing the above-mentioned sorting process refers to arranging the data in the above-mentioned disordered data group into a data group arranged in a preset order, wherein the above-mentioned preset order is: an order from large to small or an order from small to large.

[0156] Step C: Determine whether the accumulated time of the thread since the generation of the first unordered data group reaches the preset time. If the determination result is no, return to execute the above step A. If the determination result is yes, the sorting process of the thread ends.

[0157] Specifically, in the embodiment of the present invention, a timer can be set for each thread, and each timer is reset to zero before the first execution of step A. When the first execution of step A begins, the timer is started and timing begins, and the timer value of the timer is used as the accumulated duration. Therefore, it can be determined whether the accumulated duration reaches the preset duration by judging whether the timer value of the timer reaches the preset duration.

[0158] If the accumulated time reaches the preset time, it can be considered that the thread has performed the sorting process for the preset time, and the sorting process of the thread ends. Otherwise, the thread needs to continue the sorting process, but since the sorting of the generated unordered data group has been completed, when the thread continues to perform the next sorting process, the step A can be re-executed to generate a new unordered data group for the thread to continue the next sorting process.

[0159] When the sorting process is performed for each thread through the above steps A to C, since the thread can complete the sorting process once each time the steps A to C are executed, the number of times the thread loops through the steps A to C can be counted as the number of times the thread completes the sorting process.

[0160] Due to the different structures of different processors, the number of threads that can run simultaneously is different. If the same number of threads are created for different processors to determine their performance, for some processors, the number of threads created may not reach the maximum number of threads that can run simultaneously. For example, processor 1 can run 8 threads simultaneously, and processor 2 can run 16 threads simultaneously. If 4 threads are created for each to determine their performance, for processor 1 and processor 2, both have more computing resources remaining, so they can complete the sorting process more quickly, and the calculated performance values ​​may be similar. But in fact, processor 1 can run 16 processes simultaneously, and processor 2 can only run 8 processes simultaneously. Therefore, it can be considered that the performance of processor 1 is better than that of processor 2, and the calculated performance value cannot accurately reflect the difference between the performance of processor 1 and processor 2.

[0161] To solve this problem, see Figure 2A The embodiment of the present invention provides a flow chart of a second processor performance testing method, which is similar to the above Figure 1 Compared with the embodiment shown, the above step S101 can be implemented by the following steps S101A-S101B.

[0162] S101A: Determine the maximum number of threads that can be created on the processor.

[0163] Specifically, when the processor does not support hyperthreading, that is, does not support logical core expansion, the number of processors included in the electronic device can be determined, and the number of physical cores included in each processor can be determined, thereby determining the total number of physical cores included in the electronic device. Since each physical core can be used to run a thread at the same time, the total number of physical cores can be used as the maximum number of threads that the processor can create.

[0164] In the case where the processor supports hyperthreading, that is, supports logical core expansion, in addition to determining the number of processors included in the electronic device and the number of physical cores included in each processor, the number of logical cores that each physical core can support can also be determined, thereby determining the total number of logical cores that the electronic device can support. Since each logical core can be used to run a thread at the same time, the total number of logical cores can be used as the maximum number of threads that the processor can create.

[0165] In addition, since in one embodiment of the present invention, a main thread can be provided for controlling other threads to perform sorting processing, when the main thread is included in the thread, the total number of physical cores or the total number of logical cores minus the number of main threads can be used as the maximum number of threads that the processor can create.

[0166] S101B: Create the maximum number of threads running on the processor.

[0167] Specifically, the created threads may be run separately based on different physical cores or different logical cores in the processor.

[0168] As can be seen from the above, since the number of created threads is equal to the maximum number of threads that can be created on the processor, it is equivalent to that each physical core or logical core of the processor is used by the created threads, and the computing resources of the above processor are almost all occupied. Therefore, when the performance of the processor is determined by applying the embodiment of the present invention, the maximum performance of the processor can be determined, so that the performance of the processor of the electronic device obtained is more accurate.

[0169] See also Figure 2B , is a flow chart of a third processor performance testing method provided by an embodiment of the present invention, which is similar to the aforementioned Figure 1 Compared with the embodiment shown, the above method further includes the following steps S105 to S108.

[0170] S105: Count the number of times each thread completes the sorting process.

[0171] Specifically, when a counter is set for each thread, after executing step S102, the counter value of the counter corresponding to each thread may be determined as the sub-number of times the thread completes the sorting process.

[0172] For each thread, when the sorting process is implemented through the above steps A to C, the number of times the above steps A to C are executed in a loop can be used as the subnumber of times the sorting process is completed by the thread.

[0173] S106: Determine the amount of processor resources occupied by the core running each thread in the process of controlling the running of the thread.

[0174] The above cores are physical cores or logical cores.

[0175] Specifically, when the processor does not support hyperthreading, the core running the thread is a physical core; when the processor supports hyperthreading and extends the logical core, the core running the thread is a logical core.

[0176] The amount of processor resources occupied by the core may include: cache capacity, core frequency, etc. occupied by the core.

[0177] Since the amount of each resource occupied by the core may change during the operation of the core, in one embodiment of the present invention, the maximum value, minimum value or average value of each resource occupied by each core can be monitored during the operation of each thread as the amount of resources occupied by the core.

[0178] S107: For each core, obtain a first sub-influence value of the sub-number of threads running on the core on the performance of the core, and obtain a second sub-influence value of the amount of resources of the core on the performance of the core.

[0179] In one embodiment of the present invention, the method for obtaining the first sub-influence value of the sub-number corresponding to the thread running on the core on the performance of the core is similar to the method for calculating the performance value representing the performance of the processor according to the total number in step S104 shown above. It is just that the total number is replaced by the sub-number, and the calculated performance value is replaced by the first sub-influence value, which will not be described in detail here.

[0180] In addition, when multiple cores are running together, the amount of resources occupied by each core is part of the fixed attribute of the processor. The method for obtaining the second sub-influence value of the amount of resources of the core on the performance of the core is similar to the method of step D-step E shown above, except that the inherent attribute is replaced with the amount of resources, and the obtained second influence value of the inherent attribute on the performance of the processor is replaced with the second sub-influence value of the amount of resources on the performance of the core, which will not be repeated here.

[0181] S108: Calculate a sub-performance value for representing the performance of each core in the processor based on the obtained first sub-impact value and the second sub-impact value.

[0182] In one embodiment of the present invention, the first sub-impact value obtained according to the above sub-number and the second sub-impact value corresponding to the resource amount may be statistically processed to obtain the above sub-performance value.

[0183] Specifically, the statistical method for performing statistics may be calculating a sum, calculating a weighted sum, calculating an average, calculating a weighted average, etc., or other statistical methods may be used.

[0184] In addition, the calculated sub-performance values ​​of the performance of each core may be displayed, so that the user can determine the performance of each core. Furthermore, the resource amount of each core may be displayed.

[0185] It can be seen from the above that the scheme provided by the embodiment of the present invention can calculate the sub-performance value of each logical core or physical core respectively, so as to determine the performance of each logical core or physical core, implement the performance test of each logical core or physical core respectively, and determine the multi-core performance of the processor.

[0186] Corresponding to the above processor performance test method, see Figure 3 The embodiment of the present invention also provides a structural diagram of a first processor performance testing device, the device comprising:

[0187] A thread creation module 301, used to create at least two threads running on the processor;

[0188] The sorting processing module 302 is used to control the created threads to perform parallel sorting processing on the data in the unordered data group, until the accumulated time of the sorting processing of each thread is not less than a preset time;

[0189] A times counting module 303 is used to count the total times each thread completes the sorting process;

[0190] The performance determination module 304 is used to calculate a performance value representing the performance of the processor according to the total number of times to obtain a test result.

[0191] As can be seen from the above, since the processor is mainly a device for data processing, the faster the processor processes data, the better the performance of the processor. Therefore, when the scheme provided by the embodiment of the present invention is applied to test the performance of the processor, the sorting process is used as a representative of the data processing, and the total number of times the threads in the processor complete the sorting process is counted. The more the above total number of times, it means that the processor can perform a larger number of sorting processes within a certain time length, indicating that the faster the processor performs data processing, the better the performance of the processor. On the contrary, the fewer the above total number of times, it means that the processor can only perform a smaller number of sorting processes within a certain time length, indicating that the slower the processor performs data processing, the worse the performance of the processor. Therefore, the scheme provided by the embodiment of the present invention can be used to calculate the performance value used to represent the performance of the processor and obtain the test result. In addition, the above sorting process is a data processing flow with simpler logic and higher maturity, so the probability of failure during repeated execution is lower, which is more suitable for determining the performance of the processor in the electronic device.

[0192] See also Figure 4A, is a schematic diagram of the structure of a second processor performance test device provided by an embodiment of the present invention, which is similar to the aforementioned Figure 3 Compared with the embodiment shown, the above-mentioned sorting processing module 302 includes:

[0193] For each created thread, the thread is controlled to be sorted by the sorting processing submodule 302A;

[0194] The sorting processing submodule 302A is specifically used for:

[0195] Randomly generate an unordered data set;

[0196] Controlling the thread to sort the data in the generated unordered data group until the thread completes the sorting process;

[0197] Determine whether the accumulated duration of the thread since the generation of the first unordered data group reaches the preset duration;

[0198] If not, return to execute the step of randomly generating an unordered data group.

[0199] In one embodiment of the present invention, the thread creation module 301 is specifically used for:

[0200] Determine the maximum number of threads that can be created on a processor;

[0201] The maximum number of threads is created to run on the processor.

[0202] As can be seen from the above, since the number of created threads is equal to the maximum number of threads that can be created on the processor, it is equivalent to that each physical core or logical core of the processor is used by the created threads, and the computing resources of the above processor are almost all occupied. Therefore, when the performance of the processor is determined by applying the embodiment of the present invention, the maximum performance of the processor can be determined, so that the performance of the processor of the electronic device obtained is more accurate.

[0203] In one embodiment of the present invention, the performance determination module 304 is specifically configured to:

[0204] determining an intrinsic property of the processor;

[0205] Obtaining a first impact value of the total number of times on the performance of the processor, and obtaining a second impact value of the determined inherent attribute on the performance of the processor;

[0206] Based on the obtained first impact value and second impact value, the performance value is calculated to obtain a test result.

[0207] As can be seen from the above, since the inherent properties of the above processors can theoretically reflect the performance of the processors themselves, in addition to the total number of times obtained by actually running the above processors, the performance value of the above processors can also be calculated based on the above inherent properties.

[0208] See also Figure 4B , is a schematic diagram of the structure of a third processor performance test device provided by an embodiment of the present invention, which is similar to the aforementioned Figure 3 Compared with the embodiment shown, the above device also includes:

[0209] The sub-number counting module 305 is used to count the number of sub-numbers of sorting processes completed by each thread;

[0210] A resource amount determination module 306 is used to determine the amount of processor resources occupied by a core running each thread in the process of controlling the running of the thread, wherein the core is a physical core or a logical core;

[0211] The sub-impact value obtaining module 307 is used to obtain, for each core, a first sub-impact value of the sub-number of threads running on the core on the performance of the core, and obtain a second sub-impact value of the amount of resources of the core on the performance of the core;

[0212] The sub-performance value calculation module 308 is used to calculate a sub-performance value representing the performance of each core in the processor based on the obtained first sub-impact value and the second sub-impact value.

[0213] It can be seen from the above that the scheme provided by the embodiment of the present invention can calculate the sub-performance value of each logical core or physical core respectively, so as to determine the performance of each logical core or physical core, implement the performance test of each logical core or physical core respectively, and determine the multi-core performance of the processor.

[0214] In one embodiment of the present invention, for each thread, the sorting process is implemented by one of the following algorithms:

[0215] Insertion sort algorithm, heap sort algorithm, radix sort algorithm, quick sort algorithm, bubble sort algorithm, Shell sort algorithm, selection sort algorithm, bottom-up merge sort algorithm, top-down merge sort algorithm.

[0216] The embodiment of the present invention further provides an electronic device, such as Figure 5 As shown, it includes a processor 501, a communication interface 502, a memory 503 and a communication bus 504, wherein the processor 501, the communication interface 502, and the memory 503 communicate with each other through the communication bus 504.

[0217] Memory 503, used for storing computer programs;

[0218] The processor 501 is used to implement any method step described in the above-mentioned processor performance testing method when executing the program stored in the memory 503.

[0219] When the electronic device provided by the embodiment of the present invention is used to test the performance of the processor, since the processor is mainly a device for data processing, the faster the processor performs data processing, the better the performance of the processor. Therefore, when the scheme provided by the embodiment of the present invention is used to test the performance of the processor, the sorting process is used as a representative of data processing, and the total number of times the threads in the processor complete the sorting process is counted. The more the above total number of times, it means that the processor can perform more sorting processes within a certain time, indicating that the faster the speed of the processor performing data processing, the better the performance of the processor. On the contrary, the fewer the above total number of times, it means that the processor can only perform fewer sorting processes within a certain time, indicating that the slower the speed of the processor performing data processing, the worse the performance of the processor. Therefore, the scheme provided by the embodiment of the present invention can calculate the performance value used to represent the performance of the processor and obtain the test result. In addition, the above sorting process is a data processing flow with simpler logic and higher maturity, so the probability of failure during repeated execution is low, which is more suitable for determining the performance of the processor in the electronic device.

[0220] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0221] The communication interface is used for communication between the above electronic device and other devices.

[0222] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0223] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0224] In another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned processor performance testing methods are implemented.

[0225] When the computer program stored in the computer-readable storage medium provided by the present embodiment is used to test the performance of the processor, since the processor is mainly a device for data processing, the faster the processor performs data processing, the better the performance of the processor. Therefore, when the scheme provided by the embodiment of the present invention is used to test the performance of the processor, the sorting process is used as a representative of data processing, and the total number of times the threads in the processor complete the sorting process is counted. The more the above total number of times, it means that the processor can perform a larger number of sorting processes within a certain time length, indicating that the faster the processor performs data processing, the better the performance of the processor. On the contrary, the fewer the above total number of times, it means that the processor can only perform a smaller number of sorting processes within a certain time length, indicating that the slower the processor performs data processing, the worse the performance of the processor. Therefore, the scheme provided by the embodiment of the present invention can calculate the performance value used to represent the performance of the processor and obtain the test result. In addition, the above sorting process is a data processing flow with simpler logic and higher maturity, so the probability of failure during repeated execution is low, which is more suitable for determining the performance of the processor in the electronic device.

[0226] In another embodiment of the present invention, a computer program product including instructions is provided, which, when executed on a computer, enables the computer to execute any processor performance testing method in the above embodiments.

[0227] When executing the computer program product provided by this embodiment to test the performance of the processor, since the processor is mainly a device for data processing, the faster the processor performs data processing, the better the performance of the processor. Therefore, when applying the solution provided by the embodiment of the present invention to test the performance of the processor, the sorting process is used as a representative of data processing, and the total number of times the threads in the processor complete the sorting process is counted. The more the above total number of times, it means that the processor can perform a large number of sorting processes within a certain time length, indicating that the faster the speed of the processor performing data processing, the better the performance of the processor. On the contrary, the fewer the above total number of times, it means that the processor can only perform a small number of sorting processes within a certain time length, indicating that the slower the speed of the processor performing data processing, the worse the performance of the processor. Therefore, the solution provided by the embodiment of the present invention can calculate the performance value used to represent the performance of the processor and obtain the test result. In addition, the above sorting process is a data processing flow with simpler logic and higher maturity, so the probability of failure during repeated execution is low, which is more suitable for determining the performance of the processor in the electronic device.

[0228] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0229] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0230] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for devices, electronic devices, computer-readable storage media, and computer program products, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0231] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A processor performance testing method, characterized in that: Applied to electronic equipment, the method comprises: Creating at least two threads that run on a processor in the electronic device; For each created thread, the thread is controlled to perform sorting processing in the following way: Randomly generate an unordered data set; Controlling the thread to sort the data in the generated unordered data group until the thread completes the sorting process; Determine whether the cumulative duration of the thread from the generation of the first unordered data group reaches a preset duration; If not, return to the step of randomly generating an unordered data group; Count the total number of times each thread completes the sorting process; Calculate a performance value representing the performance of the processor according to the total number of times to obtain a test result; Count the number of times each thread completes the sorting process; Determine the amount of processor resources occupied by a core running each thread in the process of controlling the running of the thread, wherein the core is a physical core or a logical core; For each core, obtain a first sub-influence value of the sub-number of threads running on the core on the performance of the core, and obtain a second sub-influence value of the amount of resources of the core on the performance of the core; Based on the obtained first sub-impact value and the second sub-impact value, a sub-performance value for representing the performance of each core in the processor is calculated.

2. The method according to claim 1, characterized in that The step of creating at least two threads running on the processor includes: Determine the maximum number of threads that can be created on a processor; The maximum number of threads is created to run on the processor.

3. The method according to claim 1, characterized in that The step of calculating, according to the total number of times, a performance value used to represent the performance of the processor to obtain a test result includes: determining an intrinsic property of the processor; Obtaining a first impact value of the total number of times on the performance of the processor, and obtaining a second impact value of the determined inherent attribute on the performance of the processor; Based on the obtained first impact value and second impact value, the performance value is calculated to obtain a test result.

4. The method according to any one of claims 1 to 3, characterized in that For each thread, the sorting process is implemented by one of the following algorithms: Insertion sort algorithm, heap sort algorithm, radix sort algorithm, quick sort algorithm, bubble sort algorithm, Shell sort algorithm, selection sort algorithm, bottom-up merge sort algorithm, top-down merge sort algorithm.

5. A processor performance testing device, characterized in that: Applied to electronic equipment, the device comprises: A thread creation module, used to create at least two threads running on a processor in the electronic device; A sorting processing module is used to control the thread to perform sorting processing for each created thread through a sorting processing submodule; the sorting processing submodule is specifically used to: randomly generate an unordered data group; control the thread to sort the data in the generated unordered data group until the thread completes the sorting processing; determine whether the cumulative time of the thread from generating the first unordered data group reaches a preset time; if not, return to execute the step of randomly generating an unordered data group; The times statistics module is used to count the total number of times each thread completes the sorting process; A performance determination module, used to calculate a performance value representing the performance of the processor according to the total number of times, and obtain a test result; The sub-number statistics module is used to count the number of sub-numbers of sorting processes completed by each thread; A resource amount determination module, used to determine the amount of processor resources occupied by a core running each thread in the process of controlling the running of the thread, wherein the core is a physical core or a logical core; A sub-influence value obtaining module, used for obtaining, for each core, a first sub-influence value of the sub-number of threads running on the core on the performance of the core, and obtaining a second sub-influence value of the amount of resources of the core on the performance of the core; The sub-performance value calculation module is used to calculate a sub-performance value for representing the performance of each core in the processor based on the obtained first sub-impact value and the second sub-impact value.

6. The device according to claim 5, characterized in that The thread creation module is specifically used for: Determine the maximum number of threads that can be created on a processor; The maximum number of threads is created to run on the processor.

7. The device according to claim 5, characterized in that The performance determination module is specifically used for: determining an intrinsic property of the processor; Obtaining a first impact value of the total number of times on the performance of the processor, and obtaining a second impact value of the determined inherent attribute on the performance of the processor; Based on the obtained first impact value and second impact value, the performance value is calculated to obtain a test result.

8. The device according to any one of claims 5 to 7, characterized in that: For each thread, the sorting process is implemented by one of the following algorithms: Insertion sort algorithm, heap sort algorithm, radix sort algorithm, quick sort algorithm, bubble sort algorithm, Shell sort algorithm, selection sort algorithm, bottom-up merge sort algorithm, top-down merge sort algorithm.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing the method steps described in any one of claims 1 to 4 when executing a program stored in a memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1 to 4 are implemented.

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