Scan Driver

Abstract

The present application provides a scan driver. The scan driver includes scan stages, and the nth scan stage in the scan stages includes a first driving circuit, a second driving circuit, and an output circuit. The first driving circuit controls the voltage of a first driving node based on an input signal and the voltage of a second driving node. The second driving circuit controls the voltage of the second driving node based on a second clock signal and a first voltage. The output circuit outputs a first clock signal as a scan signal and a carry signal based on the voltage of the first driving node, and outputs a second voltage as a scan signal and a carry signal based on the voltage of the second driving node. The first driving circuit includes a first transistor, and the first transistor includes a gate electrode electrically connected to the second driving node, one electrode electrically connected to an input line providing the input signal, and another electrode electrically connected to the first driving node.

Description

Technical Field

[0001] The present disclosure relates to a scan driver. Background Art

[0002] A display device may include a data driver, a scan driver, and pixel units. The data driver is configured to provide data signals to data lines, the scan driver is configured to provide scan signals to scan lines, and the pixel units include pixels located in regions defined by the scan lines and the data lines.

[0003] Each pixel of the display device may emit light with a luminance corresponding to a data signal input through a data line. The display device may display a frame image having a combination of light-emitting pixels.

[0004] Pixels may be electrically connected to each data line. Accordingly, a scan driver may be required that can provide a scan signal for selecting pixels to which data signals are to be provided.

[0005] To this end, the scan driver may include scan stages sequentially electrically connected to each other. To operate the scan stages, each scan stage may include oxide thin-film transistors.

[0006] It is to be understood that this Background Art section is partly intended to provide useful background for understanding the technology. However, this Background Art section may also include ideas, concepts, or knowledge of things that were not known or understood by persons of ordinary skill in the relevant art before the effective filing date of the corresponding application for the subject matter disclosed herein. Summary of the Invention

[0007] An object of the present disclosure is to provide a simpler scan stage circuit.

[0008] A scan driver according to an embodiment may include a plurality of scan stages. The n-th scan stage among the plurality of scan stages may include a first driving circuit, a second driving circuit, and an output circuit. The first driving circuit controls the voltage of a first driving node based on an input signal and the voltage of a second driving node, where the input signal is a scan start signal or a carry signal from a previous stage. The second driving circuit controls the voltage of the second driving node based on a second clock signal and a first voltage. The output circuit outputs a first clock signal as a scan signal and a carry signal based on the voltage of the first driving node, and outputs a second voltage as a scan signal and a carry signal based on the voltage of the second driving node. The first driving circuit may include a first transistor including a gate electrode electrically connected to the second driving node, one electrode electrically connected to an input line providing the input signal, and another electrode electrically connected to the first driving node. Here, n may be a natural number equal to or greater than 1.

[0009] Each of the plurality of scan stages may be electrically connected to two of a first clock line that provides a first clock signal, a second clock line that provides a second clock signal, a third clock line that provides a third clock signal, and a fourth clock line that provides a fourth clock signal.

[0010] The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal may be set with the same period. The second clock signal may have a phase difference delayed by 1 / 2 period with respect to the first clock signal. The third clock signal may have a phase difference delayed by 1 / 4 period with respect to the first clock signal. And the fourth clock signal may have a phase difference delayed by 1 / 2 period with respect to the third clock signal.

[0011] The m-th scan stage among the plurality of scan stages may be electrically connected to the first clock line and the second clock line, and the (m + 1)-th scan stage among the plurality of scan stages may be electrically connected to the third clock line and the fourth clock line. Here, m is a natural number equal to or greater than 1.

[0012] The first transistor may include a first sub-transistor and a second sub-transistor. The first sub-transistor has a gate electrode electrically connected to a second driving node and one electrode electrically connected to an input line. The second sub-transistor has a gate electrode electrically connected to the second driving node, one electrode electrically connected to the other electrode of the first sub-transistor, and the other electrode electrically connected to a first driving node.

[0013] The first driving circuit may include a second transistor that has a gate electrode connected to the first driving node, one electrode connected to a first power line that provides a first voltage, and the other electrode connected to the other electrode of the first sub-transistor.

[0014] The input line electrically connected to one electrode of the first transistor included in the first scan stage among the plurality of scan stages may be a scan start line that provides a scan start signal, and the input line electrically connected to one electrode of the first transistor included in the r-th scan stage among the plurality of scan stages may be the (r - 1)-th carry line that provides a carry signal output from the (r - 1)-th scan stage among the plurality of scan stages. Here, r may be a natural number equal to or greater than 2.

[0015] The scan start signal may include a first scan start signal and a second scan start signal. The input line electrically connected to one electrode of the first transistor included in the first scan stage among the plurality of scan stages may be the first scan start line for providing the first scan start signal. The input line electrically connected to one electrode of the first transistor included in the second scan stage among the plurality of scan stages may be the second scan start line for providing the second scan start signal. And the input line electrically connected to one electrode of the first transistor included in the s-th scan stage among the plurality of scan stages may be the (s - 2)-th carry line for providing the carry signal output from the (s - 2)-th scan stage among the plurality of scan stages. Here, s is a natural number equal to or greater than 3.

[0016] The second driving circuit included in the n-th scan stage may include a third transistor and a fourth transistor. Among them, the third transistor has a gate electrode electrically connected to the first driving node, one electrode electrically connected to the second clock line for providing the second clock signal, and the other electrode electrically connected to the second driving node. The fourth transistor has a gate electrode electrically connected to the second clock line, one electrode electrically connected to the first power line, and the other electrode electrically connected to the second driving node.

[0017] The third transistor may include a third sub-transistor and a fourth sub-transistor. Among them, the third sub-transistor has a gate electrode electrically connected to the first driving node and one electrode electrically connected to the second clock line. The fourth sub-transistor has a gate electrode electrically connected to the first driving node, one electrode electrically connected to the other electrode of the third sub-transistor, and the other electrode electrically connected to the second driving node.

[0018] The second driving circuit may include a fifth transistor having a gate electrode connected to the second driving node, one electrode connected to the first power line, and the other electrode connected to the other electrode of the third sub-transistor.

[0019] The output circuit included in the n-th scan stage may include a sixth transistor and a seventh transistor. The sixth transistor has a gate electrode electrically connected to the first driving node, one electrode electrically connected to the first clock line for providing the first clock signal, and the other electrode electrically connected to the n-th scan line for outputting the scan signal. The seventh transistor has a gate electrode electrically connected to the first driving node, one electrode electrically connected to the first clock line, and the other electrode electrically connected to the n-th carry line for outputting the carry signal.

[0020] The output circuit included in the n-th scan stage may include a first capacitor having one electrode electrically connected to the gate electrode of the sixth transistor and the other electrode electrically connected to the n-th scan line.

[0021] The output circuit included in the n-th scan stage may include an eighth transistor and a ninth transistor. The eighth transistor has a gate electrode electrically connected to the second driving node, one electrode electrically connected to the second power line providing the second voltage, and the other electrode electrically connected to the n-th scan line. The ninth transistor has a gate electrode electrically connected to the second driving node, one electrode electrically connected to the third power line providing the third voltage, and the other electrode electrically connected to the n-th carry line.

[0022] The output circuit included in the n-th scan stage may include a second capacitor having one electrode electrically connected to the second driving node and the other electrode electrically connected to the second power line.

[0023] The output circuit included in the n-th scan stage may include a second capacitor having one electrode electrically connected to the second driving node and the other electrode electrically connected to the third power line.

[0024] The n-th scan stage may include a tenth transistor and an eleventh transistor. The tenth transistor has a gate electrode electrically connected to the first clock line providing the first clock signal and one electrode electrically connected to the first driving node. The eleventh transistor has a gate electrode electrically connected to the second driving node, one electrode electrically connected to the other electrode of the tenth transistor, and the other electrode electrically connected to the n-th carry line outputting the carry signal.

[0025] The scan driver according to an embodiment may include a plurality of scan stages. The n-th scan stage among the plurality of scan stages may include a first driving circuit, a second driving circuit, and an output circuit. The first driving circuit controls the voltage of the first driving node based on an input signal and a second clock signal, where the input signal is any one of a scan start signal and a previous carry signal. The second driving circuit controls the voltage of the second driving node based on the second clock signal and a first voltage. The output circuit outputs the first clock signal as a scan signal and a carry signal based on the voltage of the first driving node, and outputs the second voltage as a scan signal and a carry signal based on the voltage of the second driving node. The first driving circuit may include a first transistor having a gate electrode electrically connected to the second clock line providing the second clock signal, one electrode electrically connected to the input line providing the input signal, and the other electrode electrically connected to the first driving node. Here, n may be a natural number equal to or greater than 1.

[0026] Each of the plurality of scan stages may be electrically connected to two of the first clock line providing the first clock signal, the second clock line, the third clock line providing the third clock signal, and the fourth clock line providing the fourth clock signal.

[0027] The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal may be set to have the same period. The second clock signal may have a phase difference that is delayed by 1 / 2 cycle with respect to the first clock signal. The third clock signal may have a phase difference that is delayed by 1 / 4 cycle with respect to the first clock signal. And the fourth clock signal may have a phase difference that is delayed by 1 / 2 cycle with respect to the third clock signal.

[0028] The m-th scan stage among the plurality of scan stages may be electrically connected to the first clock line and the second clock line, and the (m + 1)-th scan stage among the plurality of scan stages may be electrically connected to the third clock line and the fourth clock line. Here, m may be a natural number equal to or greater than 1.

[0029] The first transistor may include a first sub-transistor and a second sub-transistor. The first sub-transistor has a gate electrode electrically connected to the second clock line and one electrode electrically connected to the input line. The second sub-transistor has a gate electrode electrically connected to the second clock line, one electrode electrically connected to the other electrode of the first sub-transistor, and the other electrode electrically connected to the first driving node. And the first driving circuit may include a second transistor, which has a gate electrode electrically connected to the first driving node, one electrode electrically connected to the first power line that provides the first voltage, and the other electrode electrically connected to the other electrode of the first sub-transistor.

[0030] The scan driver according to the present disclosure can simplify the scan stage circuit by reducing the number of transistors included in the scan stage and removing the lines required for reset in the scan stage. Description of the Drawings

[0031] By describing its embodiments in more detail with reference to the accompanying drawings, the above and other features will become more apparent. In the drawings:

[0032] Figure 1 is a diagram showing a display device according to an embodiment;

[0033] Figure 2 is a diagram showing an example of an equivalent circuit of a pixel included in Figure 1 the display device;

[0034] Figure 3 is a diagram showing an example of a scan driver included in Figure 1 the display device;

[0035] Figure 4 is a diagram showing an example of an equivalent circuit of the n-th scan stage included in Figure 3 the scan driver;

[0036] Figure 5 is a waveform diagram for explaining Figure 3 the driving method of the scan driver;

[0037] Figure 6 is an equivalent circuit diagram showing an example of the n-th scan stage included in the Figure 3 scan driver;

[0038] Figure 7 is an equivalent circuit diagram showing an example of the n-th scan stage included in the Figure 3 scan driver;

[0039] Figure 8 is an equivalent circuit diagram showing an example of the n-th scan stage included in the Figure 3 scan driver;

[0040] Figure 9 is a diagram showing an example of a scan driver included in the Figure 1 display device; and

[0041] Figure 10 is a waveform diagram illustrating a Figure 9 driving method of the scan driver. DETAILED DESCRIPTION

[0042] Although the present disclosure may be modified in various ways and have additional embodiments, certain specific embodiments are shown in the drawings and will be mainly described in the specification. However, the scope of the present disclosure is not limited to the embodiments in the drawings and the specification, but should be construed to include all variations, equivalents, and alternatives included within the spirit and scope of the present disclosure.

[0043] To clearly describe the present disclosure, parts irrelevant to the description are omitted, and the same reference numerals are used throughout the specification to denote the same or similar components. Therefore, the foregoing reference numerals may be used in other drawings.

[0044] In addition, for ease of description, the dimensions and thicknesses of the elements shown in the drawings are arbitrarily shown, and thus the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness may be exaggerated to clearly show various layers and regions.

[0045] In addition, in this specification, the phrase "in a plan view" means the case when the object part is observed from above, and the phrase "in a schematic cross-sectional view" means the case when a schematic cross-section obtained by vertically cutting the object part is observed from the side. In addition, in this specification, the phrase "on a plane" means observing the object part from the top.

[0046] Additionally, the terms "overlap" or "overlapping" mean that a first object can be above or below a second object or on one side of the second object, and vice versa. Additionally, the term "overlap" can include layers, stacks, surfaces or facing, extending over, covering or partially covering, or any other suitable terms as would be understood and appreciated by one of ordinary skill in the art. The terms "face" and "facing" mean that a first element can be directly or indirectly opposite a second element. In the case where a third element is inserted between a first element and a second element, the first element and the second element can be understood to be indirectly opposite each other, although still facing each other. When an element is described as not overlapping or not being likely to overlap with another element, this can include the elements being spaced apart from each other, offset from each other, or arranged side by side with each other, or any other suitable terms as would be understood and appreciated by one of ordinary skill in the art.

[0047] It will be understood that when an element such as a layer, film, region, substrate or zone is referred to as being on another element, it can be directly on that other element, or there can also be intervening elements. In contrast, when an element is referred to as being directly on another element, there can be no intervening elements between them.

[0048] Furthermore, when a layer, film, region, substrate or zone is referred to as being below another layer, film, region, substrate or zone, it can be directly below that other layer, film, region, substrate or zone, or there can be intervening layers, films, regions, substrates or zones between them. Conversely, when a layer, film, region, substrate or zone is referred to as being directly below another layer, film, region, substrate or zone, there can be no intervening layers, films, regions, substrates or zones between them. Additionally, "above" or "upper" can include being located on or below an object, and not necessarily meaning the direction based on gravity.

[0049] For convenience of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that, in addition to the orientation shown in the drawings, the spatially relative terms are intended to also encompass different orientations of the device during use or operation. For example, in the case where the device shown in the figure is flipped, a device located "below" or "beneath" another device can be placed "above" the other device. Thus, the illustrative term "beneath" can include both lower and upper positions. The device can also be oriented in other directions, and thus the spatially relative terms can be interpreted differently depending on the orientation.

[0050] Throughout the specification, when an element is referred to as being "connected" to another element, the element can be "directly connected" to the other element, or "electrically connected" to the other element with one or more intermediate elements interposed therebetween. It will also be understood that when the terms "comprises", "comprising", "includes", and / or "including" are used in this specification, they or it can indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0051] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from other components. Thus, in accordance with the spirit and scope of the present disclosure, the first component can be the second component, or vice versa.

[0052] As used herein, "about" or "approximately" includes the recited value and means within an acceptable deviation range of the specific value as determined by one of ordinary skill in the art in view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the recited value, or within ±30%, 20%, 10%, 5%.

[0053] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or". In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0055] Figure 1 is a diagram showing a display device according to an embodiment.

[0056] Reference Figure 1 The display device 100 may include a timing controller 110, a data driver 120, a scan driver 130, a sensing unit 140, and a pixel unit 150.

[0057] The timing controller 110 may provide a gray-scale value, a control signal, etc. to the data driver 120. For example, the timing controller 110 may provide a clock signal, a control signal, etc. to each of the scan driver 130 and the sensing unit 140.

[0058] The data driver 120 may generate a data signal using the gray-scale value, the control signal, etc. received from the timing controller 110. For example, the data driver 120 may sample the gray-scale value using a clock signal and apply a data signal corresponding to the gray-scale value to data lines DL1 to DLq (where q may be a natural number) in a pixel row unit.

[0059] The scan driver 130 may receive a clock signal, a control signal, etc. from the timing controller 110 and generate a scan signal to be provided to scan lines SL1, SL2, ……, and SLp (where p may be a natural number). For example, the scan driver 130 may sequentially provide a scan signal having a pulse with a conductive level to the scan lines SL1, SL2, ……, and SLp. For example, the scan driver 130 may generate a scan signal in such a manner that a pulse with a conductive level is sequentially transmitted to the next scan stage according to a clock signal. For example, the scan driver 130 may be in the form of a shift register.

[0060] The clock signal provided to the scan driver 130 may include a first clock signal to a fourth clock signal. In addition to the above first clock signal to fourth clock signal, the scan driver 130 may also receive another clock signal. This will be referred to later with reference to Figure 3 and Figure 5 the first clock signal to the fourth clock signal will be described.

[0061] For example, the scan driver 130 may generate a sensing signal to be provided to sensing lines SS1, SS2, ……, and SSp. For example, the scan driver 130 may sequentially provide a sensing signal having a pulse with a conductive level to the sensing lines SS1, SS2, ……, and SSp. For example, the scan driver 130 may generate a sensing signal in such a manner that a pulse with a conductive level is sequentially transmitted to the next scan stage according to a clock signal.

[0062] The sensing unit 140 may measure the degradation information of the pixel based on the current or voltage received through the receiving lines RL1, RL2, RL3, ……, and RLq. For example, the degradation information of the pixel may be the mobility information and threshold voltage information of the driving transistor, the degradation information of the light-emitting element, and the like. For example, the sensing unit 140 may measure the characteristic information of the pixel according to the current or voltage received through the receiving lines RL1, RL2, RL3, ……, and RLq according to the environment. For example, the sensing unit 140 may also measure the changed characteristic information of the pixel according to the temperature or humidity.

[0063] The pixel unit 150 may include pixels. Each pixel PXij (where i may be a natural number equal to or greater than 1 and equal to or less than p, and j may be a natural number equal to or greater than 1 and equal to or less than q) may be electrically connected to a corresponding data line, scan line, sensing line, and receiving line. The pixel PXij may refer to a pixel circuit in which a scanning transistor may be electrically connected to the i-th scan line and the j-th data line.

[0064] Figure 2 is an equivalent circuit diagram showing an example of a pixel included in Figure 1 the display device of.

[0065] Refer to Figure 2 , the pixel PXij may include thin film transistors M1, M2, and M3 (or transistors), a storage capacitor Cst, and a light-emitting element LD. The thin film transistors M1, M2, and M3 may be N-type transistors. However, the present disclosure is not limited thereto.

[0066] In the first thin film transistor M1, the gate electrode may be electrically connected to the gate node Na, one electrode (or the first electrode) may be electrically connected to the power line ELVDD, and the other electrode (or the second electrode) may be electrically connected to the source node Nb. The first thin film transistor M1 may be referred to as a driving transistor. However, the present disclosure is not limited thereto.

[0067] In the second thin film transistor M2, the gate electrode may be electrically connected to the scan line SLi, one electrode may be electrically connected to the data line DLj, and the other electrode may be electrically connected to the gate node Na. The second thin film transistor M2 may be referred to as a switching transistor, a scanning transistor, etc.

[0068] In the third thin film transistor M3, the gate electrode may be electrically connected to the sensing line SSi, one electrode may be electrically connected to the receiving line RLj, and the other electrode may be electrically connected to the source node Nb. The third thin film transistor M3 may be referred to as an initialization transistor, a sensing transistor, etc.

[0069] In the storage capacitor Cst, one electrode may be electrically connected to the gate node Na, and the other electrode may be electrically connected to the source node Nb.

[0070] In the light-emitting element LD, the anode can be electrically connected to the source node Nb, and the cathode can be electrically connected to the power line ELVSS. The light-emitting element LD can be an organic light-emitting diode, an inorganic light-emitting diode, or the like.

[0071] Figure 3 is a diagram showing an example of a scan driver included in Figure 1 the display device.

[0072] Referring to Figure 3 , the scan driver 130 can include scan stages ST1, ST2, ST3, ST4,..., STn,..., and STp (where n can be a natural number equal to or greater than 1 and equal to or less than p). In Figure 3 , parts necessary for the description of the scan driver 130 are shown.

[0073] Each of the scan stages ST1, ST2, ST3, ST4,..., STn,..., and STp can be electrically connected to a corresponding clock line among the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4. In an embodiment, each of the scan stages ST1, ST2, ST3, ST4,..., STn,..., and STp can be electrically connected to two clock lines among the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4.

[0074] In an embodiment, when the m-th (m can be a natural number less than p) scan stage among the first scan stage ST1 to the p-th scan stage STp can be electrically connected to the first clock line CLK1 and the second clock line CLK2, the (m + 1)-th scan stage can be electrically connected to the third clock line CLK3 and the fourth clock line CLK4. For example, the first scan stage ST1 can be electrically connected to the first clock line CLK1 and the second clock line CLK2, the second scan stage ST2 can be electrically connected to the third clock line CLK3 and the fourth clock line CLK4, the third scan stage ST3 can be electrically connected to the first clock line CLK1 and the second clock line CLK2, and the fourth scan stage ST4 can be electrically connected to the third clock line CLK3 and the fourth clock line CLK4. For example, the n-th scan stage STn can be electrically connected to the first clock line CLK1 and the second clock line CLK2, and the p-th scan stage STp can be electrically connected to the third clock line CLK3 and the fourth clock line CLK4. As described above, the odd-numbered scan stages ST1, ST3,... can be electrically connected to the first clock line CLK1 and the second clock line CLK2, while the even-numbered scan stages ST2, ST4,... can be electrically connected to the third clock line CLK3 and the fourth clock line CLK4.

[0075] However, the connection relationship between the clock lines CLK1 to CLK4 and the scan stages ST1 to STp is not limited to this. For example, the odd-numbered scan stages ST1, ST3,... can be electrically connected to the third clock line CLK3 and the fourth clock line CLK4, while the even-numbered scan stages ST2, ST4,... can be electrically connected to the first clock line CLK1 and the second clock line CLK2.

[0076] For example, in addition to the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, and the fourth clock line CLK4, the scan driver 130 may further include other clock lines. For example, the scan driver 130 may include a fifth clock line and a sixth clock line. In this case, the first scan stage ST1 can be electrically connected to the first clock line CLK1 and the second clock line CLK2, the second scan stage ST2 can be electrically connected to the third clock line CLK3 and the fourth clock line CLK4, and the third scan stage ST3 can be electrically connected to the fifth clock line and the sixth clock line.

[0077] The clock signals for each of the scan stages ST1 to STp can be applied to the first clock line CLK1 to the fourth clock line CLK4. For example, the first clock signal can be applied to the first clock line CLK1, the second clock signal can be applied to the second clock line CLK2, the third clock signal can be applied to the third clock line CLK3, and the fourth clock signal can be applied to the fourth clock line CLK4. The first clock signal to the fourth clock signal will be described later with reference to Figure 5 the description of the first clock signal to the fourth clock signal.

[0078] The scan stages ST1 to STp can be electrically connected to the corresponding lines among the scan lines SL1 to SLp and the carry lines CR1 to CR(p - 1).

[0079] For example, the first scan stage ST1 can be electrically connected to the first scan line SL1 and the first carry line CR1, the second scan stage ST2 can be electrically connected to the second scan line SL2 and the second carry line CR2, the third scan stage ST3 can be electrically connected to the third scan line SL3 and the third carry line CR3, the fourth scan stage ST4 can be electrically connected to the fourth scan line SL4 and the fourth carry line CR4, and the nth scan stage STn can be electrically connected to the nth scan line SLn and the nth carry line CRn. Alternatively, since the scan driver 130 may not include the next scan stage (e.g., the (p + 1)th scan stage) to which the pth scan stage STp can transmit a carry signal, the pth scan stage STp can be electrically connected only to the pth scan line SLp.

[0080] The output signals generated by the respective scan stages ST1 to STp can be applied to the scan lines SL1 to SLp and the carry lines CR1 to CR(p - 1).

[0081] For example, the scan stages ST1 to STp can be electrically connected to an input line that can provide an input signal, which can be either a scan start signal or a previous carry signal. The input line can include a scan start line SSP and carry lines CR1 to CR(p - 1), and the scan start line SSP can provide a scan start signal.

[0082] In an embodiment, the first scan stage ST1 can be electrically connected to the scan start line SSP, and the r-th (r can be a natural number equal to or greater than 2 and equal to or less than p) scan stage can be electrically connected to the (r - 1)-th carry line, which can provide a carry signal output from the (r - 1)-th scan stage. For example, the second scan stage ST2 can be electrically connected to the first carry line CR1, the third scan stage ST3 can be electrically connected to the second carry line CR2, the fourth scan stage ST4 can be electrically connected to the third carry line CR3, the n-th scan stage STn can be electrically connected to the (n - 1)-th carry line CR(n - 1), and the p-th scan stage STp can be electrically connected to the (p - 1)-th carry line CR(p - 1).

[0083] When the display device 100 performs an operation of displaying an image or a plurality of images, the scan driver 130 can sequentially apply scan signals to the first scan line SL1 to the p-th scan line SLp in response to a scan start signal provided through the scan start line SSP. In other words, the scan start signal applied to the first scan stage ST1 can control the start timing of the scan signals output from the scan driver 130. For example, the first scan stage ST1 can output a first scan signal SC1 through the first scan line SL1 in response to the scan start signal, the second scan stage ST2 can output a second scan signal SC2 through the second scan line SL2 in response to the first carry signal after the first scan stage ST1 outputs the first scan signal SC1, the third scan stage ST3 can output a third scan signal SC3 through the third scan line SL3 in response to the second carry signal after the second scan stage ST2 outputs the second scan signal SC2, the fourth scan stage ST4 can output a fourth scan signal SC4 through the fourth scan line SL4 in response to the third carry signal after the third scan stage ST3 outputs the third scan signal SC3, the n-th scan stage STn can output an n-th scan signal SCn through the n-th scan line SLn in response to the (n - 1)-th carry signal after the (n - 1)-th scan stage outputs the (n - 1)-th scan signal, and the p-th scan stage STp can output a p-th scan signal SCp through the p-th scan line SLp in response to the (p - 1)-th carry signal after the (p - 1)-th scan stage outputs the (p - 1)-th scan signal.

[0084] Figure 4 is an equivalent circuit diagram illustrating an example of the n-th scan stage included in the Figure 3 scan driver.

[0085] Reference Figure 4 Figure 3 Figure 3 For example, the n-th scan stage STn may include a first driving circuit 410, a second driving circuit 420, and an output circuit 430. Other scan stages in the described scan stages ST1, ST2, ST3, ST4, …, and STp may include configurations substantially the same as those of the n-th scan stage STn.

[0086] The n-th scan stage STn may include transistors TR1 to TR9 and capacitors C1 and C2. Hereinafter, a description will be given by taking an example in which transistors TR1 to TR9 are N-type transistors (e.g., NMOS), but those skilled in the art can modify the n-th scan stage STn by replacing some or all of transistors TR1 to TR9 with P-type transistors (e.g., PMOS).

[0087] The first driving circuit 410 may include a first transistor TR1 and a second transistor TR2. The first driving circuit 410 may control the voltage of a first driving node Qn based on an input signal and the voltage of a second driving node Qbn, where the input signal may be any one of a scan start signal and a previous carry signal. This will be described later with reference to Figures 3 to 5 this.

[0088] In the first transistor TR1, a gate electrode may be electrically connected to the second driving node Qbn, one electrode may be electrically connected to the (n-1)-th carry line CR(n-1), and the other electrode may be electrically connected to the first driving node Qn.

[0089] However, as described with reference to Figure 3 the first scan stage ST1 may be electrically connected to a scan start line SSP (refer to Figure 3 ). Therefore, the electrodes of the first transistor TR1 included in the first scan stage ST1 may be electrically connected to the scan start line SSP (refer to Figure 3 ).

[0090] In an embodiment, the first transistor TR1 may include a first sub-transistor TR1a and a second sub-transistor TR1b that may be electrically connected in series. In the first sub-transistor TR1a, a gate electrode may be electrically connected to the second driving node Qbn, one electrode may be electrically connected to the (n-1)-th carry line CR(n-1), and the other electrode may be electrically connected to a first node N1 (or an electrode of the second sub-transistor TR1b). In the second sub-transistor TR1b, a gate electrode may be electrically connected to the second driving node Qbn, one electrode may be electrically connected to the first node N1, and the other electrode may be electrically connected to the first driving node Qn.

[0091] In the second transistor TR2, the gate electrode may be electrically connected to the first driving node Qn, one electrode may be electrically connected to the first power line VGH that can provide the first voltage, and the other electrode may be electrically connected to the first node N1 (or the other electrode of the first sub-transistor TR1a).

[0092] The second driving circuit 420 may include a third transistor TR3, a fourth transistor TR4, and a fifth transistor TR5. The second driving circuit 420 may control the voltage of the second driving node Qbn based on the second clock signal provided through the second clock line CLK2 and the first voltage provided through the first power line VGH. This will be described later with reference to Figures 3 to 5 be described.

[0093] In the third transistor TR3, the gate electrode may be electrically connected to the first driving node Qn, one electrode may be electrically connected to the second clock line CLK2, and the other electrode may be electrically connected to the second driving node Qbn.

[0094] In an embodiment, the third transistor TR3 may include a third sub-transistor TR3a and a fourth sub-transistor TR3b that may be electrically connected in series. In the third sub-transistor TR3a, the gate electrode may be electrically connected to the first driving node Qn, one electrode may be electrically connected to the second clock line CLK2, and the other electrode may be electrically connected to the second node N2 (or the electrode of the fourth sub-transistor TR3b). In the fourth sub-transistor TR3b, the gate electrode may be electrically connected to the first driving node Qn, one electrode may be electrically connected to the second node N2, and the other electrode may be electrically connected to the second driving node Qbn.

[0095] In the fourth transistor TR4, the gate electrode may be electrically connected to the second clock line CLK2, one electrode may be electrically connected to the first power line VGH, and the other electrode may be electrically connected to the second driving node Qbn.

[0096] In the fifth transistor TR5, the gate electrode may be electrically connected to the second driving node Qbn, one electrode may be electrically connected to the first power line VGH, and the other electrode may be electrically connected to the second node N2 (or the other electrode of the third sub-transistor TR3a).

[0097] The output circuit 430 may include a sixth transistor TR6, a seventh transistor TR7, an eighth transistor TR8, a ninth transistor TR9, a first capacitor C1, and a second capacitor C2. The output circuit 430 may output the first clock signal provided through the first clock line CLK1 as the n-th scan signal and the n-th carry signal based on the voltage of the first driving node Qn, and output the second voltage provided through the second power line VGL1 or the third voltage provided through the third power line VGL2 as the n-th scan signal and the n-th carry signal based on the voltage of the second driving node Qbn. This will be described later with reference to Figures 3 to 5A description will be given.

[0098] In the sixth transistor TR6, the gate electrode may be electrically connected to the first driving node Qn, one electrode may be electrically connected to the first clock line CLK1, and the other electrode may be electrically connected to the n-th scan line SLn.

[0099] In the first capacitor C1, one electrode may be electrically connected to the gate electrode of the sixth transistor TR6, and the other electrode may be electrically connected to the n-th scan line SLn.

[0100] In the seventh transistor TR7, the gate electrode may be electrically connected to the first driving node Qn, one electrode may be electrically connected to the first clock line CLK1, and the other electrode may be electrically connected to the n-th carry line CRn.

[0101] In the eighth transistor TR8, the gate electrode may be electrically connected to the second driving node Qbn, one electrode may be electrically connected to the second power line VGL1, and the other electrode may be electrically connected to the n-th scan line SLn.

[0102] In the ninth transistor TR9, the gate electrode may be electrically connected to the second driving node Qbn, one electrode may be electrically connected to the third power line VGL2, and the other electrode may be electrically connected to the n-th carry line CRn.

[0103] In the second capacitor C2, one electrode may be electrically connected to the second driving node Qbn, and the other electrode may be electrically connected to the third power line VGL2. In Figure 4 it, the other electrode of the second capacitor C2 may be electrically connected to the third power line VGL2, but this is an example, and the present disclosure is not limited thereto. For example, in the second capacitor C2, one electrode may be electrically connected to the second driving node Qbn, and the other electrode may be electrically connected to the second power line VGL1.

[0104] In Figure 4 it, the n-th scan stage STn may be electrically connected to the first clock line CLK1 and the second clock line CLK2. However, as described in the reference Figure 3 , this is an example, and the present disclosure is not limited thereto. For example, the n-th scan stage STn may be electrically connected to the third clock line CLK3 (refer to Figure 3 ) and the fourth clock line CLK4 (refer to Figure 3 ).

[0105] As an example, in Figure 4Among them, one electrode of the seventh transistor TR7 and one electrode of the sixth transistor TR6 can be electrically connected to the first clock line CLK1, and one electrode of the third transistor TR3 and the gate electrode of the fourth transistor TR4 can be electrically connected to the second clock line CLK2. However, this is an example, and the present disclosure is not limited thereto. For example, one electrode of the seventh transistor TR7 and one electrode of the sixth transistor TR6 can be electrically connected to the second clock line CLK2, and one electrode of the third transistor TR3 and the gate electrode of the fourth transistor TR4 can be electrically connected to the first clock line CLK1.

[0106] Similarly, when the nth scanning stage STn can be electrically connected to the third clock line CLK3 (refer to Figure 3 ) and the fourth clock line CLK4 (refer to Figure 3 ) as described above, one electrode of the seventh transistor TR7 and one electrode of the sixth transistor TR6 can be electrically connected to the third clock line CLK3 (refer to Figure 3 ), and one electrode of the third transistor TR3 and the gate electrode of the fourth transistor TR4 can be electrically connected to the fourth clock line CLK4 (refer to Figure 3 ). Alternatively, one electrode of the seventh transistor TR7 and one electrode of the sixth transistor TR6 can be electrically connected to the fourth clock line CLK4 (refer to Figure 3 ), and the electrode of the third transistor TR3 and the gate electrode of the fourth transistor TR4 can be electrically connected to the third clock line CLK3 (refer to Figure 3 ).

[0107] Figure 5 is a waveform diagram illustrating the driving method of the scanning driver of Figure 3 .

[0108] Refer to Figures 3 to 5 , and the signals applied to the first clock line CLK1, the second clock line CLK2, the third clock line CLK3, the fourth clock line CLK4, the (n - 1)th carry line CR(n - 1), the first driving node Qn, the second driving node Qbn, the nth scanning line SLn, and the nth carry line CRn are shown.

[0109] It should be understood that the numbers and types of the transistors are arbitrary. In addition, it should be understood that the numbers and types of the transistors in the first driving circuit 410, the second driving circuit 420, and the output circuit 430 are arbitrary.

[0110] Figure 5 Illustrate the first clock signal to the fourth clock signal applied to the first clock line CLK1 to the fourth clock line CLK4.

[0111] The first clock signal applied to the first clock line CLK1, the second clock signal applied to the second clock line CLK2, the third clock signal applied to the third clock line CLK3, and the fourth clock signal applied to the fourth clock line CLK4 may have the same period. In an embodiment, the length (or width) of the pulse period of the high level (or logical high level) of each of the first clock line CLK1 to the fourth clock line CLK4 may be the same as the length (or width) of the pulse period of the low level (or logical low level) of each of the first clock line CLK1 to the fourth clock line CLK4. The high level (or logical high level) may correspond to a voltage level sufficient to turn on the transistor, while the low level (or logical low level) may correspond to a voltage level sufficient to turn off the transistor.

[0112] In an embodiment, the second clock signal applied to the second clock line CLK2 may be delayed in phase with respect to the first clock signal applied to the first clock line CLK1. For example, the second clock signal may be delayed by a phase difference of 1 / 2 cycle with respect to the first clock signal. Therefore, the falling edge of the second clock signal may be positioned adjacent to the rising edge of the first clock signal, and the rising edge of the second clock signal may be positioned adjacent to the falling edge of the first clock signal. Therefore, the period of the high level pulse of the first clock signal and the period of the high level pulse of the second clock signal may not overlap with each other.

[0113] For example, the third clock signal applied to the third clock line CLK3 may be delayed in phase with respect to the phase of the first clock signal applied to the first clock line CLK1. For example, the third clock signal may be delayed by a phase difference of 1 / 4 cycle with respect to the first clock signal.

[0114] For example, the fourth clock signal applied to the fourth clock line CLK4 may be delayed in phase with respect to the third clock signal applied to the third clock line CLK3. For example, the fourth clock signal may be delayed by a phase difference of 1 / 2 cycle with respect to the third clock signal. Similarly, the falling edge of the fourth clock signal may be positioned adjacent to the rising edge of the third clock signal, and the rising edge of the fourth clock signal may be positioned adjacent to the falling edge of the third clock signal. Therefore, the period of the high level pulse of the third clock signal and the period of the high level pulse of the fourth clock signal may not overlap with each other.

[0115] Hereinafter, reference will be made to Figures 3 to 5 Describe the operation of the nth scan stage STn. Since the operations of the first scan stage ST1 to the pth scan stage STp may be substantially the same or similar to each other, the operation of the nth scan stage STn will be described as an example of the first scan stage ST1 to the pth scan stage STp.

[0116] When a high-level pulse can be applied to the second clock line CLK2, the fourth transistor TR4 can be turned on, and the second driving node Qbn can be charged to the first voltage at a high level provided by the first power line VGH.

[0117] At the first time point t1, a high-level pulse can be applied to the (n-1)-th carry line CR(n-1). For example, a high-level voltage can be maintained at the second driving node Qbn. In this case, since the first sub-transistor TR1a and the second sub-transistor TR1b can be turned on or remain turned on, the first driving node Qn can be charged to the high level applied to the (n-1)-th carry line CR(n-1). Therefore, the third sub-transistor TR3a and the fourth sub-transistor TR3b can be turned on. Since a high-level pulse can be applied to the second clock line CLK2, a high-level voltage can be maintained at the second driving node Qbn.

[0118] At the first time point t1, the sixth transistor TR6 and the seventh transistor TR7 can be turned on in response to the high-level voltage of the first driving node Qn.

[0119] At the second time point t2, a low-level signal can be applied to the second clock line CLK2. Since the third sub-transistor TR3a and the fourth sub-transistor TR3b are turned on or remain turned on in response to the high-level voltage of the first driving node Qn, the second driving node Qbn can be discharged to the low level applied to the second clock line CLK2. Therefore, the first sub-transistor TR1a and the second sub-transistor TR1b can be turned off, and the eighth transistor TR8 and the ninth transistor TR9 can be turned off.

[0120] For example, at the second time point t2, a high-level pulse can appear in the first clock line CLK1. In this case, the voltage of the first driving node Qn can be increased by the first capacitor C1 to be higher than the high level, and a high-level pulse can be applied to the n-th scan line SLn and the n-th carry line CRn.

[0121] When the first driving node Qn is charged to a high-level voltage (or increased to be higher than the high level), the second transistor TR2 can be turned on. Therefore, the first node N1 can be charged to the first voltage at a high level provided by the first power line VGH.

[0122] For example, the drain-source voltage of the first sub-transistor TR1a (e.g., the voltage between one electrode and the other electrode of the first sub-transistor TR1a) can be the difference between the voltage of the (n-1)-th carry signal and the voltage of the first node N1 (or the first voltage). For example, the drain-source voltage of the second sub-transistor TR1b (e.g., the voltage between one electrode and the other electrode of the second sub-transistor TR1b) can be the difference between the voltage of the first node N1 (or the first voltage) and the voltage of the first drive node Qn.

[0123] For example, in the period when the voltage of the first drive node Qn rises above the high level and the low-level (n-1)-th carry signal is applied to the (n-1)-th carry line CR(n-1), when the voltage of the first drive node Qn rises to about 20V, the voltage of the first node N1 (or the first voltage) can be about 10V, and the voltage of the (n-1)-th carry signal can be about -7V, the drain-source voltage of the first sub-transistor TR1a can be about 17V, and the drain-source voltage of the second sub-transistor TR1b can be about 10V.

[0124] Therefore, since a high-level voltage can be applied to the first node N1 through the second transistor TR2, the drain-source voltages of the first sub-transistor TR1a and the second sub-transistor TR1b will not be relatively large despite the increase in the voltage of the first drive node Qn. Similarly, in the period when the voltage of the second drive node Qbn can be at a high level and a low-level signal can be applied to the second clock line CLK2, since a high-level voltage can be applied to the second node N2 through the fifth transistor TR5, the drain-source voltages of the third sub-transistor TR3a and the fourth sub-transistor TR3b can not be relatively large. Therefore, deterioration of the transistors TR1a, TR1b, TR3a, and TR3b can be prevented.

[0125] At the third time point t3, a high-level pulse can appear in the second clock line CLK2. In this case, the second drive node Qbn can be charged to the high level applied to the second clock line CLK2. Therefore, the first sub-transistor TR1a and the second sub-transistor TR1b can be turned on. In this case, since a low-level (n-1)-th carry signal can be applied to the (n-1)-th carry line CR(n-1), the first drive node Qn can be discharged to the low level applied to the (n-1)-th carry line CR(n-1).

[0126] At the fourth time point t4, a high-level pulse may appear in the first clock line CLK1. However, since the low level is maintained at the (n-1)-th carry line CR(n-1) after the third time point t3, the first driving node Qn can maintain a low-level voltage according to the low level applied to the (n-1)-th carry line CR(n-1). Therefore, the sixth transistor TR6 and the seventh transistor TR7 can be cut off or remain in the cut-off state. As an example, the eighth transistor TR8 and the ninth transistor TR9 can be turned on or remain in the on state in response to the high-level voltage of the second driving node Qbn, and the n-th scan line SLn and the n-th carry line CRn can be electrically connected to the second power line VGL1 that can provide a low-level second voltage and the third power line VGL2 that can provide a low-level third voltage, respectively. Therefore, the high-level pulse may not be output to the n-th scan line SLn and the n-th carry line CRn.

[0127] As described in the reference Figures 3 to 5 The first driving circuit 410 including the first transistor TR1 can control the voltage of the first driving node Qn based on the input signal and the voltage of the second driving node Qbn, where the input signal can be any one of the scan start signal and the previous carry signal. For example, the first driving circuit 410 can charge and discharge the first driving node Qn through the first transistor TR1. Therefore, the first scan stage ST1 to the n-th scan stage STn may not include a separate reset line and a separate transistor for discharging the first driving node Qn. The dummy line for discharging the first driving node Qn of the p-th scan stage STp may not be included. Therefore, the scan stage circuit can be simplified.

[0128] Figure 6 is a circuit diagram showing an example of the n-th scan stage included in the Figure 3 scan driver.

[0129] Referring to Figure 4 and Figure 6 , except for the tenth transistor TR10 and the eleventh transistor TR11, since Figure 6 the n-th scan stage STn_1 of Figure 4 is substantially similar to the n-th scan stage STn of

[0130] the repeated description will not be repeated.

[0131] In the tenth transistor TR10, the gate electrode can be electrically connected to the first clock line CLK1, one electrode can be electrically connected to the first driving node Qn, and the other electrode can be electrically connected to the electrode of the eleventh transistor TR11.

[0132] In the eleventh transistor TR11, the gate electrode can be electrically connected to the second driving node Qbn, one electrode can be electrically connected to the other electrode of the tenth transistor TR10, and the other electrode can be the n-th carry line CRn (or the other electrode of the ninth transistor TR9).

[0133] Reference Figure 5 and Figure 6 , at the fourth time point t4, a high-level pulse can be applied to the first clock line CLK1. In this case, the tenth transistor TR10 can be turned on. For example, the ninth transistor TR9 and the eleventh transistor TR11 can be turned on or remain turned on in response to the high-level voltage of the second driving node Qbn. Therefore, the first driving node Qn can be discharged to the low-level third voltage provided through the third power line VGL2.

[0134] As described in reference Figure 5 and Figure 6 , the n-th scan stage STn_1 including the tenth transistor TR10 and the eleventh transistor TR11 can additionally discharge the first driving node Qn through the tenth transistor TR10 and the eleventh transistor TR11 after outputting the n-th scan signal and the n-th carry signal.

[0135] Figure 7 is a circuit diagram illustrating an example of the n-th scan stage included in the Figure 3 scan driver.

[0136] Reference Figure 4 and Figure 7 , in addition to the first driving circuit 710 (or the connection configuration of the first transistor TR1_1), since the Figure 7 n-th scan stage STn_2 can be substantially similar to the Figure 4 n-th scan stage STn, the repeated description will not be repeated.

[0137] The n-th scan stage STn_2 can include a first driving circuit 710, a second driving circuit 420, and an output circuit 430.

[0138] The first driving circuit 710 can include a first transistor TR1_1 and a second transistor TR2. The first driving circuit 710 can control the voltage of the first driving node Qn based on an input signal and a second clock signal provided through the second clock line CLK2, where the input signal can be any one of a scan start signal and a previous carry signal.

[0139] In the first transistor TR1_1, the gate electrode can be electrically connected to the second clock line CLK2, one electrode can be electrically connected to the (n - 1)-th carry line CR(n - 1), and the other electrode can be electrically connected to the first driving node Qn.

[0140] In an embodiment, the first transistor TR1_1 may include a first sub-transistor TR1a_1 and a second sub-transistor TR1b_1 that may be electrically connected in series. In the first sub-transistor TR1a_1, the gate electrode may be electrically connected to the second clock line CLK2, one electrode may be electrically connected to the (n - 1)-th carry line CR(n - 1), and the other electrode may be electrically connected to the first node N1 (or the electrode of the second sub-transistor TR1b_1). In the second sub-transistor TR1b_1, the gate electrode may be electrically connected to the second clock line CLK2, one electrode may be electrically connected to the first node N1, and the other electrode may be electrically connected to the first driving node Qn.

[0141] Reference Figure 5 and Figure 7 , at the first time point t1, a high-level pulse may be applied to the (n - 1)-th carry line CR(n - 1). For example, a high-level pulse may be applied to the second clock line CLK2. In this case, since the first sub-transistor TR1a_1 and the second sub-transistor TR1b_1 may be turned on or remain turned on, the first driving node Qn may be charged to the high level applied to the (n - 1)-th carry line CR(n - 1).

[0142] At the second time point t2, a low-level signal may be applied to the second clock line CLK2. In this case, the first sub-transistor TR1a_1 and the second sub-transistor TR1b_1 may be turned off.

[0143] At the third time point t3, a high-level pulse may appear in the second clock line CLK2. In this case, the first sub-transistor TR1a_1 and the second sub-transistor TR1b_1 may be turned on. Therefore, the first driving node Qn may be discharged to the low level applied to the (n - 1)-th carry line CR(n - 1).

[0144] After the third time point t3, even if a high-level pulse may be generated in the second clock line CLK2 and thus the first sub-transistor TR1a_1 and the second sub-transistor TR1b_1 may be turned on, since a low-level pulse may be maintained at the (n - 1)-th carry line CR(n - 1), the first driving node Qn may maintain a low-level voltage. Therefore, the sixth transistor TR6 and the seventh transistor TR7 may be turned off or remain turned off.

[0145] As described in reference Figure 5 and Figure 7 , although the gate electrode of the first sub-transistor TR1a_1 and the gate electrode of the second sub-transistor TR1b_1 may be electrically connected to the second clock line CLK2, Figure 7The n-th scan stage STn_2 of Figure 4 can operate substantially the same as or similarly to the n-th scan stage STn of

[0146] Figure 8 is a circuit diagram illustrating an example of the n-th scan stage included in the Figure 3 scan driver.

[0147] Referring to Figure 7 and Figure 8 , except for the tenth transistor TR10 and the eleventh transistor TR11, since Figure 8 the n-th scan stage STn_3 of Figure 7 can be substantially similar to the n-th scan stage STn_2 of

[0148] the n-th scan stage STn_3 may include a tenth transistor TR10 and an eleventh transistor TR11.

[0149] Referring to Figure 6 and Figure 8 , since Figure 8 the tenth transistor TR10 and the eleventh transistor TR11 of Figure 6 can be substantially the same as or similar to the tenth transistor TR10 and the eleventh transistor TR11 of

[0150] The n-th scan stage STn_3 including the tenth transistor TR10 and the eleventh transistor TR11 can additionally discharge the first driving node Qn through the tenth transistor TR10 and the eleventh transistor TR11 after outputting the n-th scan signal and the n-th carry signal.

[0151] Figure 9 is a diagram showing an example of a scan driver included in the Figure 1 display device.

[0152] Referring to Figure 3 and Figure 9 , except for the connection configurations of the first scan start line SSP1, the second scan start line SSP2, and the carry lines CR1 to CR(p - 2), since Figure 9 the scan driver 130_1 of Figure 3 can be substantially the same as or similar to the scan driver 130 of

[0153] The scan stages ST1 to STp can be electrically connected to an input line that provides an input signal, which can be either a scan start signal or a carry signal from a previous stage. The scan start signal can include a first scan start signal and a second scan start signal. The input line can include a first scan start line SSP1 that provides the first scan start signal, a second scan start line SSP2 that provides the second scan start signal, and carry lines CR1 to CR(p - 2). Meanwhile, the first scan start signal can be substantially the same as or similar to the second scan start signal.

[0154] In an embodiment, the first scan stage ST1 can be electrically connected to the first scan start line SSP1, the second scan stage ST2 can be electrically connected to the second scan start line SSP2, and the s-th scan stage (where s can be a natural number equal to or greater than 3 and equal to or less than p) can be electrically connected to the (s - 2)-th carry line that provides a carry signal output from the (s - 2)-th scan stage. For example, the third scan stage ST3 can be electrically connected to the first carry line CR1, the fourth scan stage ST4 can be electrically connected to the second carry line CR2, the n-th scan stage STn can be electrically connected to the (n - 2)-th carry line CR(n - 2), and the p-th scan stage STp can be electrically connected to the (p - 2)-th carry line CR(p - 2).

[0155] When the display device 100 performs an operation of displaying one or more images, the scan driver 130_1 can sequentially apply scan signals to the first scan line SL1 to the p-th scan line SLp in response to the first scan start signal provided by the first scan start line SSP1 and the second scan start signal provided by the second scan start line SSP2. For example, the first scan stage ST1 can output a first scan signal SC1 through the first scan line SL1 in response to the first scan start signal, the second scan stage ST2 can output a second scan signal SC2 through the second scan line SL2 in response to the second scan start signal after the first scan stage ST1 outputs the first scan signal SC1, the third scan stage ST3 can output a third scan signal SC3 through the third scan line SL3 in response to the first carry signal after the second scan stage ST2 outputs the second scan signal SC2, the fourth scan stage ST4 can output a fourth scan signal SC4 through the fourth scan line SL4 in response to the second carry signal after the third scan stage ST3 outputs the third scan signal SC3, the n-th scan stage STn can output an n-th scan signal SCn through the n-th scan line SLn in response to the (n - 2)-th carry signal after the (n - 1)-th scan stage outputs the (n - 1)-th scan signal, and the p-th scan stage STp can output a p-th scan signal SCp through the p-th scan line SLp in response to the (p - 2)-th carry signal after the (p - 1)-th scan stage outputs the (p - 1)-th scan signal.

[0156] ReferenceFigure 4 and Figures 6 to 9 , since Figure 9 the first scan stage ST1 of Figure 9 can be electrically connected to the first scan start line SSP1, the electrodes of the first transistor TR1 or TR1_1 included in the first scan stage ST1 or the electrodes of the first sub-transistor TR1a or TR1a_1 can be electrically connected to the first scan start line SSP1. For example, since

[0157] Since Figure 9 the n-th scan stage STn (except for the first scan stage ST1 and the second scan stage ST2) of

[0158] Figure 10 is a waveform diagram illustrating the driving method of the scan driver of Figure 9 .

[0159] Referring to Figure 5 and Figure 10 , since Figure 9 the n-th scan stage STn of the scan driver 130_1 of Figure 10 can be electrically connected to the (n - 2)-th carry line CR(n - 2), so Figure 5 the waveform diagram of Figure 10 can be basically the same as or similar to the waveform diagram of Figure 10 , except that Figures 3 to 8 shows the signal applied to the (n - 2)-th carry line CR(n - 2) instead of the signal applied to the (n - 1)-th carry line CR(n - 1). Therefore, in the description of referring to

[0160] Referring to Figure 4 and Figures 6 to 10 , as described above, since Figure 9 the n-th scan stage STn of

[0161] The first scan start signal applied to the first scan stage ST1 and the second scan start signal applied to the second scan stage ST2 may control the start timing of the scan signal output from the scan driver 130. For example, the timing at which the first scan stage ST1 may output the first scan signal SC1 and the timing at which the second scan stage ST2 may output the second scan signal SC2 may be controlled. Therefore, the operation of the first scan stage ST1 electrically connected to the first scan start line SSP1 and the operation of the second scan stage ST2 electrically connected to the second scan start line SSP2 may be substantially similar to the operation of the nth scan stage STn electrically connected to the (n-2)th carry line CR(n-2), which will be described below.

[0162] refer to Figure 4 , Figure 9 and Figure 10 , at the first time point t1, a high level pulse may be applied to the (n-2)th carry line CR(n-2). For example, a high level voltage may be maintained at the second drive node Qbn. In this case, since the first sub-transistor TR1a and the second sub-transistor TR1b may be turned on or maintained in a turned-on state, the first drive node Qn may be charged to a high level applied to the (n-2)th carry line CR(n-2).

[0163] At the third time point t3, a high level pulse may appear in the second clock line CLK2. In this case, the second drive node Qbn may be charged to a high level applied to the second clock line CLK2. Therefore, the first sub-transistor TR1a and the second sub-transistor TR1b may be turned on. In this case, the first drive node Qn may be discharged to a low level applied to the (n-2)th carry line CR(n-2).

[0164] At the fourth time point t4, a high level pulse may appear in the first clock line CLK1. However, since a low level pulse may be maintained at the (n-2)th carry line CR(n-2) after the third time point t3, the first drive node Qn may maintain a low level voltage according to the low level pulse applied to the (n-2)th carry line CR(n-2). Therefore, the sixth transistor TR6 and the seventh transistor TR7 may be turned off or maintained in an off state.

[0165] refer to Figure 4 , Figure 6 , Figure 9 and Figure 10 , Figure 9 The scan driver 130_1 may include Figure 6 For example, in addition to the tenth transistor TR10 and the eleventh transistor TR11, due to Figure 6 The nth scanning stage STn_1 can be basically the same asFigure 4 is the same as or similar to the n-th scan stage STn of Figure 6 , the n-th scan stage STn_1 of Figure 4 can operate substantially the same as the n-th scan stage STn of

[0166] Refer to Figure 4 , Figure 7 , Figure 9 and Figure 10 , Figure 9 , the scan driver 130_1 of Figure 7 can include the n-th scan stage STn_2 of Figure 7 . For example, in addition to the first driving circuit 710 (or the connection configuration of the first transistor TR1_1), since the n-th scan stage STn_2 of Figure 4 is the same as or similar to the n-th scan stage STn of

[0167] Refer to Figure 7 , Figure 9 and Figure 10 . At the first time point t1, a high-level pulse can be applied to the (n - 2)-th carry line CR(n - 2). For example, a high-level pulse can be applied to the second clock line CLK2. In this case, since the first sub-transistor TR1a_1 and the second sub-transistor TR1b_1 can be turned on or remain in the on state, the first driving node Qn can be charged to the high level applied to the (n - 2)-th carry line CR(n - 2).

[0168] At the third time point t3, a high-level pulse can appear in the second clock line CLK2. In this case, the first sub-transistor TR1a_1 and the second sub-transistor TR1b_1 can be turned on. Therefore, the first driving node Qn can be discharged to the low level applied to the (n - 2)-th carry line CR(n - 2).

[0169] After the third time point t3, even if a high-level pulse can be generated in the second clock line CLK2 and thus the first sub-transistor TR1a_1 and the second sub-transistor TR1b_1 can be turned on, since a low-level pulse can be maintained at the (n - 2)-th carry line CR(n - 2), the first driving node Qn can maintain a low-level voltage. Therefore, the sixth transistor TR6 and the seventh transistor TR7 can be cut off or remain in the cut-off state.

[0170] Refer to Figures 7 to 10 , Figure 9 , the scan driver 130_1 of Figure 8 can include the n-th scan stage STn_3 of Figure 8The n-th scan stage STn_3 of can be substantially the same as Figure 7 the n-th scan stage STn_2 of, so Figure 8 The n-th scan stage STn_3 of can be substantially the same as Figure 7 the n-th scan stage STn_2 of and operate similarly.

[0171] As referenced in Figure 9 and Figure 10 described, although the first scan start line SSP1 can be electrically connected to the first scan stage ST1, the second scan start line SSP2 can be electrically connected to the second scan stage ST2, and the (n - 2)-th carry line CR(n - 2) can be electrically connected to the n-th scan stage STn (except for the first scan stage ST1 and the second scan stage ST2), Figure 9 the scan driver 130_1 of can operate substantially the same as Figure 3 the scan driver 130 of.

[0172] The accompanying drawings and the detailed description of the present disclosure referred to are only examples of the present disclosure, only for describing the present disclosure, and are not intended to limit the meaning and scope of the present disclosure described in the claims. Therefore, those skilled in the art can understand that various modifications and equivalent other embodiments are possible according to the teachings of the present disclosure.

Claims

1. A scan driver, comprising a plurality of scan stages, wherein the n-th scan stage among the plurality of scan stages comprises: a first driving circuit that controls the voltage of a first driving node based on an input signal and the voltage of a second driving node, wherein the input signal is a scan start signal or a previous carry signal; a second driving circuit that controls the voltage of the second driving node based on a second clock signal and a first voltage; and an output circuit that outputs a first clock signal as a scan signal and a carry signal based on the voltage of the first driving node, and outputs a second voltage as the scan signal and the carry signal based on the voltage of the second driving node; wherein the first driving circuit includes a first transistor, and the first transistor includes a gate electrode electrically connected to the second driving node, one electrode electrically connected to an input line that provides the input signal, and another electrode electrically connected to the first driving node, wherein the second driving circuit includes: a third transistor, including a gate electrode electrically connected to the first driving node, one electrode electrically connected to a second clock line that provides the second clock signal, and another electrode electrically connected to the second driving node; and a fourth transistor, including a gate electrode electrically connected to the second clock line, one electrode electrically connected to a first power line that provides the first voltage, and another electrode electrically connected to the second driving node, wherein n is a natural number equal to or greater than 1.

2. The scan driver according to claim 1, wherein each of the plurality of scan stages is electrically connected to two of a first clock line that provides the first clock signal, a second clock line that provides the second clock signal, a third clock line that provides a third clock signal, and a fourth clock line that provides a fourth clock signal.

3. The scan driver according to claim 2, wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are set with the same period, the second clock signal has a phase difference of 1 / 2 period relative to the first clock signal, the third clock signal has a phase difference of 1 / 4 period relative to the first clock signal, and the fourth clock signal has a phase difference of 1 / 2 period relative to the third clock signal.

4. The scan driver according to claim 3, wherein the m-th scan stage among the plurality of scan stages is electrically connected to the first clock line and the second clock line, and the (m + 1)-th scan stage among the plurality of scan stages is electrically connected to the third clock line and the fourth clock line, wherein m is a natural number equal to or greater than 1.

5. The scan driver according to claim 1, wherein the first transistor includes: a first sub-transistor, including a gate electrode electrically connected to the second driving node and one electrode electrically connected to the input line; and a second sub-transistor, including a gate electrode electrically connected to the second driving node, one electrode electrically connected to the other electrode of the first sub-transistor, and another electrode electrically connected to the first driving node.

6. The scan driver according to claim 5, wherein, the first driving circuit includes a second transistor, and the second transistor includes: a gate electrode electrically connected to the first driving node; one electrode electrically connected to the first power line; and the other electrode electrically connected to the other electrode of the first sub-transistor.

7. The scan driver according to claim 1, wherein, the input line electrically connected to the one electrode of the first transistor included in the first scan stage among the plurality of scan stages is a scan start line for providing the scan start signal, and the input line electrically connected to the one electrode of the first transistor included in the r-th scan stage among the plurality of scan stages is the (r - 1)-th carry line for providing the carry signal output from the (r - 1)-th scan stage among the plurality of scan stages, where r is a natural number equal to or greater than 2.

8. The scan driver according to claim 1, wherein, the scan start signal includes a first scan start signal and a second scan start signal, the input line electrically connected to the one electrode of the first transistor included in the first scan stage among the plurality of scan stages is a first scan start line for providing the first scan start signal, the input line electrically connected to the one electrode of the first transistor included in the second scan stage among the plurality of scan stages is a second scan start line for providing the second scan start signal, and the input line electrically connected to the one electrode of the first transistor included in the s-th scan stage among the plurality of scan stages is the (s - 2)-th carry line for providing the carry signal output from the (s - 2)-th scan stage among the plurality of scan stages, where s is a natural number equal to or greater than 3.

9. The scan driver according to claim 1, wherein, the third transistor includes: a third sub-transistor including a gate electrode electrically connected to the first driving node and one electrode electrically connected to the second clock line; and a fourth sub-transistor including a gate electrode electrically connected to the first driving node, one electrode electrically connected to the other electrode of the third sub-transistor, and the other electrode electrically connected to the second driving node.

10. The scan driver according to claim 9, wherein, the second driving circuit includes a fifth transistor, and the fifth transistor includes: a gate electrode electrically connected to the second driving node; one electrode electrically connected to the first power line; and the other electrode electrically connected to the other electrode of the third sub-transistor.

11. The scan driver according to claim 9, wherein, the output circuit included in the n-th scan stage includes: a sixth transistor including a gate electrode electrically connected to the first driving node, one electrode electrically connected to the first clock line for providing the first clock signal, and the other electrode electrically connected to the n-th scan line for outputting the scan signal; and The seventh transistor includes a gate electrode electrically connected to the first driving node, one electrode electrically connected to the first clock line, and the other electrode electrically connected to the nth carry line for outputting the carry signal.

12. The scan driver according to claim 11, wherein, the output circuit included in the nth scan stage includes a first capacitor, and the first capacitor includes one electrode electrically connected to the gate electrode of the sixth transistor and the other electrode electrically connected to the nth scan line.

13. The scan driver according to claim 12, wherein, the output circuit included in the nth scan stage includes: an eighth transistor, including a gate electrode electrically connected to the second driving node, one electrode electrically connected to the second power line for providing the second voltage, and the other electrode electrically connected to the nth scan line; and a ninth transistor, including a gate electrode electrically connected to the second driving node, one electrode electrically connected to the third power line for providing the third voltage, and the other electrode electrically connected to the nth carry line.

14. The scan driver according to claim 13, wherein, the output circuit included in the nth scan stage includes a second capacitor, and the second capacitor includes one electrode electrically connected to the second driving node and the other electrode electrically connected to the second power line.

15. The scan driver according to claim 13, wherein, the output circuit included in the nth scan stage includes a second capacitor, and the second capacitor includes one electrode electrically connected to the second driving node and the other electrode electrically connected to the third power line.

16. The scan driver according to claim 10, wherein, the nth scan stage includes: a tenth transistor, including a gate electrode electrically connected to the first clock line for providing the first clock signal and one electrode electrically connected to the first driving node; and an eleventh transistor, including a gate electrode electrically connected to the second driving node, one electrode electrically connected to the other electrode of the tenth transistor, and the other electrode electrically connected to the nth carry line for outputting the carry signal.

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