Semiconductor device

Abstract

A semiconductor device includes: a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including: a second substrate located on an upper portion of the first substrate; gate electrodes spaced apart from each other and vertically stacked on the second substrate; a channel structure vertically extending through the gate electrodes into the second substrate; a first isolation region penetrating the gate electrodes between the channel structures and extending in one direction; and a second isolation region vertically extending to penetrate the second substrate from above and having a bent portion due to a change in width.

Description

[0001] Cross - reference to related applications

[0002] The Korean Patent Application No. 10 - 2019 - 0118980, titled "Semiconductor Device", filed with the Korean Intellectual Property Office on September 26, 2019, is hereby incorporated by reference in its entirety. Technical field

[0003] Embodiments relate to a semiconductor device. Background art

[0004] Semiconductor devices are used to process a large amount of data while their size is gradually reduced, thereby driving an increase in the integration degree of semiconductor elements constituting the semiconductor device. The integration degree of the semiconductor device can be increased by using a vertical transistor structure instead of a planar transistor structure. Summary of the invention

[0005] Embodiments relate to a semiconductor device including: a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including: a second substrate located on an upper portion of the first substrate; gate electrodes spaced apart from each other and vertically stacked on the second substrate; a horizontal conductive layer located between the second substrate and the gate electrodes; a channel structure vertically extending through the gate electrodes to the second substrate; a first isolation region penetrating the gate electrodes between the channel structures and extending in one direction; a cell region insulating layer covering the stacked structure of the gate electrodes; and a second isolation region vertically extending to penetrate the second substrate from above. The second isolation region may include a first region and a second region. The first region extends inwardly into the second substrate in the form of a trench from above, the second region is connected to the lower end of the first region within the second substrate, the width of the second region is greater than the width of the first region, and the second region has a circular outer surface.

[0006] Embodiments also relate to a semiconductor device including: a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate located on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, a channel structure vertically extending through the gate electrodes to the second substrate, a first isolation region penetrating the gate electrodes between the channel structures and extending in one direction, and a second isolation region vertically extending to penetrate the second substrate from above, the second isolation region having a bent portion due to a change in width.

[0007] The embodiment also relates to a semiconductor device, including: a first substrate; circuit elements located on the first substrate; a first insulating layer covering the circuit elements; a second substrate disposed on the first insulating layer; gate electrodes spaced apart from each other and vertically stacked on the second substrate; a second insulating layer covering the gate electrodes; and a separation region spaced apart from the gate electrodes, penetrating the second insulating layer and the second substrate to vertically extend into the second substrate, and having a bent portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment;

[0010] Figure 2A and Figure 2B is a schematic partial enlarged view of a semiconductor device according to an exemplary embodiment;

[0011] Figure 3 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0012] Figures 4A to 4C is a partial enlarged view of a semiconductor device according to an exemplary embodiment;

[0013] Figure 5 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0014] Figure 6 is a partial enlarged view of a semiconductor device according to an exemplary embodiment;

[0015] Figure 7A and Figure 7B is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment;

[0016] Figures 8A to 16B is a schematic cross-sectional view showing stages in a method of manufacturing a semiconductor device according to an exemplary embodiment; and

[0017] Figures 17A to 18B is a schematic cross-sectional view showing stages in a method of manufacturing a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

[0019] Figure 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment.

[0020] Figure 2AAnd Figure 2B is a schematic partial enlarged view of a semiconductor device according to an exemplary embodiment. Figure 2A is Figure 1 an enlarged view of region 'A' in Figure 2B is Figure 1 an enlarged view of region 'CELL' in

[0021] Figure 3 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment. Figure 3 shows a cross-section taken along line I-I' in Figure 2A the cross-section taken along line I-I' in

[0022] Referring to Figures 1 to 3 , the semiconductor device 100 may include a peripheral circuit region PC disposed on a substrate 201 and a memory cell region MC disposed on a substrate 101. The memory cell region MC may be disposed on the upper end or surface of the peripheral circuit region PC. In another exemplary embodiment, the memory cell region MC may be disposed on the lower end or surface of the peripheral circuit region PC.

[0023] The peripheral circuit region PC may include a substrate 201, circuit elements 220 disposed on the substrate 201, circuit contact plugs 270, and circuit interconnect lines 280.

[0024] The substrate 201 may have an upper surface extending in the X direction and the Y direction. In the substrate 201, isolation layers may be formed to define active regions. Source / drain regions 205 including impurities may be disposed in a part of the active regions. The substrate 201 may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0025] The circuit elements 220 in the peripheral circuit region PC may include planar transistors. Each of the circuit elements 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The source / drain regions 205 may be disposed in the substrate 201 on opposite sides adjacent to the circuit gate electrode 225. For example, the circuit gate dielectric layer 222 may include silicon oxide, and the circuit gate electrode 225 may include a conductive material such as metal, polysilicon, or metal silicide. The spacer layer 224 may be disposed on opposite sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. The spacer layer 224 may be formed of, for example, silicon nitride.

[0026] The peripheral region insulating layer 290 may be disposed on the circuit element 220 on the substrate 201. The peripheral region insulating layer 290 may be formed of an insulating (e.g., electrically insulating) material. The circuit contact plug 270 may penetrate the peripheral region insulating layer 290 and be connected to the source / drain region 205. The circuit contact plug 270 may include a first contact plug 272, a second contact plug 274, and a third contact plug 276 sequentially stacked from the substrate 201. An electrical signal may be applied to the circuit element 220 through the circuit contact plug 270. In a region not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit interconnect line 280 may be connected to the circuit contact plug 270 and may be provided in multiple layers. The circuit interconnect line 280 may include a first circuit interconnect line 282, a second circuit interconnect line 284, and a third circuit interconnect line 286. The circuit contact plug 270 and the circuit interconnect line 280 may include a metal, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0027] As Figure 1 and Figure 2A shown, the memory cell region MC may include a plurality of cell regions CELL, and the plurality of cell regions CELL may be disposed on the cell region 101M of the substrate 101. The substrate 101 may further include a connection region 101D disposed between the plurality of cell regions CELL. Due to the connection region 101D, the substrate 101 may have a structure connected to the substrate 201 at the edge of the substrate 201 in the wafer state during the manufacturing process. This will be described in more detail below with reference to Figure 9A and Figure 9B In the final semiconductor device 100, the connection region 101D may be disposed in an isolated form between a plurality of adjacent cell regions CELL through the second isolation region 170.

[0028] The memory cell region MC may include: a substrate 101; gate electrodes 130 vertically stacked and spaced apart from each other on the substrate 101; a channel structure CH penetrating the stacked structure of the gate electrodes 130 and vertically extending to the upper surface of the substrate 101; a first isolation region 160 penetrating the stacked structure of the gate electrodes 130 and extending in the Y direction; and a second isolation region 170 vertically extending to the substrate 101 to penetrate the substrate 101. The memory cell region MC may further include a first horizontal conductive layer 104 and a second horizontal conductive layer 105 disposed on the substrate 101, an interlayer insulating layer 120 alternately stacked with the gate electrodes 130, and a cell region insulating layer 190 covering the stacked structure of the gate electrodes 130.

[0029] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material, e.g., a Group-IV semiconductor, a III-V compound semiconductor, or a II-VI compound semiconductor. For example, the Group-IV semiconductor may include silicon, germanium, or silicon-germanium. For example, the substrate 101 may be provided as a polysilicon layer or an epitaxial layer.

[0030] The gate electrodes 130 may be vertically stacked and spaced apart from each other on the substrate 101 to form a stacked structure. Among the gate electrodes 130, at least one bottom-most gate electrode 130 may be associated with the gate of a ground selection transistor, at least one top-most gate electrode 130 may be associated with the gate of a string selection transistor, and the gate electrodes 130 therebetween may be associated with memory cells. The number of gate electrodes 130 associated with the memory cells may be determined according to the capacity of the semiconductor device 100. In an exemplary embodiment, one or more gate electrodes 130 associated with the string selection transistor and the ground selection transistor may be provided, and the one or more gate electrodes 130 may have the same or different structures as the gate electrodes 130 constituting the memory cells. A portion of the gate electrodes 130 may be dummy gate electrodes.

[0031] The gate electrodes 130 may be vertically stacked and spaced apart from each other on the substrate 101, and may extend in different lengths in the X direction and the Y direction to form a stepped terrace. Due to this terrace, the gate electrodes 130 may provide a pad region in which the underlying gate electrodes 130 extend further than the upper gate electrodes 130 to be exposed upward. The gate electrodes 130 may be connected to contact plugs in the pad region to connect to overlying interconnection lines.

[0032] As Figure 2B shown, the gate electrodes 130 may be isolated from each other in the X direction by first isolation regions 160 extending in the Y direction. For example, the gate electrodes 130 between a pair of first isolation regions 160 may be associated with a single memory block. A portion of the gate electrodes 130 (e.g., the gate electrodes 130 associated with the memory cells) may constitute a single layer in a single memory block.

[0033] The gate electrodes 130 may include a metal material, e.g., tungsten (W). In an exemplary embodiment, the gate electrodes 130 may include, e.g., polysilicon or a metal silicide material. In an exemplary embodiment, the gate electrodes 130 may further include a diffusion barrier. The diffusion barrier may include, e.g., tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0034] The interlayer insulating layer 120 may be disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layer 120 may be arranged to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101. The interlayer insulating layer 120 may include an insulating material such as silicon oxide or silicon nitride.

[0035] The channel structures CH may each be associated with a single memory cell string and may be spaced apart from each other while forming rows and columns. The channel structures CH may be arranged to form a grid or may be arranged in a zigzag pattern in one direction. The channel structures CH may have a columnar shape and may have inclined sides that narrow towards the substrate 101 according to the aspect ratio. The number of channel structures CH disposed between the pair of first separation regions 160 may be changed.

[0036] The channel layer 140 may be disposed in the channel structures CH. In the channel structures CH, the channel layer 140 may be formed to have an annular shape surrounding the channel insulating layer 150 therein. In another exemplary embodiment, the channel layer 140 may have a columnar shape such as a cylindrical or prismatic shape without the channel insulating layer 150.

[0037] The channel layer 140 may be connected to the first horizontal conductive layer 104 in the lower portion. The channel layer 140 may include a semiconductor material such as polysilicon or single-crystalline silicon, and the semiconductor material may be an undoped material or a material including p-type impurities or n-type impurities. The channel structures CH disposed in a straight line between the pair of first separation regions 160 in the X direction may be connected to different bit lines respectively according to the arrangement of the upper interconnect structure, additional separation insulating layer, etc. connected to the channel pads 155.

[0038] In the channel structures CH, the channel pads 155 may be disposed on the channel layer 140. The channel pads 155 may be arranged to cover the top surface of the channel insulating layer 150 and are electrically connected to the channel layer 140. The channel pads 155 may include, for example, doped polysilicon.

[0039] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not shown in detail, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer 140. The tunneling layer may allow charges to tunnel into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be, for example, a charge trapping layer or a floating gate conductive layer. The blocking layer may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In an exemplary embodiment, at least a portion of the gate dielectric layer 145 may extend in the horizontal direction along the gate electrode 130.

[0040] The first horizontal conductive layer 104 and the second horizontal conductive layer 105 may be stacked on the upper surface of the substrate 101. At least a part of the first horizontal conductive layer 104 and the second horizontal conductive layer 105 may be used as a part of the common source line of the semiconductor device 100, and may be used as the common source line together with the substrate 101. The first horizontal conductive layer 104 may be directly connected to the channel layer 140 on the perimeter of the channel structure CH. As Figure 3 shown, the first horizontal conductive layer 104 may not extend over the connection region 101D of the substrate 101, and the second horizontal conductive layer 105 may extend over the upper surface of the connection region 101D.

[0041] As Figure 2B shown, in the edge region of the plurality of cell regions CELL, the first horizontal conductive layer 104, the second horizontal conductive layer 105, and the substrate 101 may be electrically connected to the overlying interconnect structure through the source contact plug SC provided on opposite sides of the first isolation region 160. Similar to the connection region 101D, in the edge region, the second horizontal conductive layer 105 may extend longer than the first horizontal conductive layer 104 to be disposed on the substrate 101. The source contact plug SC may be provided to connect to the substrate 101 by penetrating the second horizontal conductive layer 105 located on the substrate 101.

[0042] The first horizontal conductive layer 104 and the second horizontal conductive layer 105 may include a semiconductor material such as polysilicon. In this case, at least the first horizontal conductive layer 104 may be a doped layer, and the second horizontal conductive layer 105 may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 104.

[0043] The first isolation region 160 may be provided to extend in the Y direction through the gate electrode 130. As Figure 2B shown, when viewed from above, the first isolation regions 160 may be provided to be parallel to each other. In an exemplary embodiment, one or more of the first isolation regions 160 may extend intermittently when viewed from above, or one or more of the first isolation regions 160 may be provided only in a partial region. The first isolation region 160 may have a shape in which its width decreases toward the substrate 101 due to a high aspect ratio. In another embodiment, the first isolation region 160 may have side surfaces perpendicular to the upper surface of the substrate 101. The first isolation region 160 may extend to the upper surface of the substrate 101. The first isolation region 160 may include an insulating material such as silicon oxide, silicon nitride, etc.

[0044] As Figure 2AAs shown, the second isolation region 170 may be disposed in a direction perpendicular to the direction in which the connection region 101D of the substrate 101 extends, and may penetrate the connection region 101D to isolate the connection regions 101D from each other. The second isolation region 170 may have a line shape with a length shorter than that of the first isolation region 160 when viewed from above, and may be set to be longer than the connection region 101D in the Y direction. As Figure 3 As shown, the second isolation region 170 may be set to sequentially penetrate the cell region insulating layer 190, the second horizontal conductive layer 105, and the substrate 101 from above. The gate electrode 130 may be set to symmetrically form a stepped region on opposite sides of the second isolation region 170. Since the second isolation region 170 is disposed on the connection region 101D where the gate electrode 130 does not extend, the second isolation region 170 may be spaced apart from the gate electrode 130 and may not be set to penetrate the gate electrode 130.

[0045] The second isolation region 170 may include a first region 170U and a second region 170L stacked vertically. The first region 170U may pass through the cell region insulating layer 190, the second horizontal conductive layer 105, and a part of the substrate 101, and may extend in the form of a trench. The second region 170L may be connected to the lower end of the first region 170U below the first region 170U, and its width may be greater than the width of the first region 170U. A curved portion may be formed at the boundary between the first region 170U and the second region 170L according to the width change. The curved portion may be disposed in the substrate 101.

[0046] The second region 170L may have a shape extending from the first region 170U and may have a circular outer surface. Specifically, the second region 170L may have an outer surface with a shape such that the region connecting the upper surface, the lower surface, and the side surface is circular. The outer surface may have a shape formed by, for example, isotropic etching. The lower surface of the second region 170L may be disposed at a lower level than the lower surface of the first isolation region 160 and may be substantially coplanar with the lower surface of the substrate 101. In another exemplary embodiment, the lower surface of the second region 170L may be disposed below the lower surface of the substrate 101.

[0047] As Figure 3 As shown, a second width W2 of the upper end of the second isolation region 170 may be greater than a first width W1 of the upper end of the first isolation region 160. For example, the second width W2 may be in the range of about twice to about four times the first width W1, and may be in the range of about 300 nm to about 800 nm.

[0048] At the lower end of the first region 170U, the second isolation region 170 may have a third width W3 smaller than the second width W2.

[0049] At the lower end of the second region 170L, the second isolation region 170 may have a fourth width W4 greater than the second width W2.

[0050] The second region 170L may have a first length L1 in the Z direction. In an exemplary embodiment, the first length L1 may vary within a range in which the second isolation region 170 penetrates the substrate 101.

[0051] The second isolation region 170 may be formed of an insulating material and may be formed of the same material as that of the first isolation region 160. The second isolation region 170 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride. In an exemplary embodiment, the second isolation region 170 may include multiple layers.

[0052] The cell region insulating layer 190 may be provided to cover the substrate 101, the gate electrode 130 on the substrate 101, and the peripheral region insulating layer 290 in a region where the substrate 101 is not provided. The cell region insulating layer 190 may include an insulating material such as silicon oxide, silicon nitride, etc.

[0053] Figures 4A to 4C is a partial enlarged view of a semiconductor device according to an exemplary embodiment. Specifically, Figures 4A to 4C is related to Figure 3 an enlarged view of the region corresponding to region 'B' in

[0054] Referring to Figure 4A , in the semiconductor device 100a according to an exemplary embodiment, the second isolation region 170a may include a first region 170U and a second region 170L, respectively. The first region 170U of the second isolation region 170a may be provided to extend only from above to the upper surface of the substrate 101, and the second region 170L of the second isolation region 170a may be provided to penetrate the substrate 101 from the upper surface to the lower surface of the substrate 101.

[0055] The second region 170L may have a second length L2 greater than the first length L1 in the exemplary embodiment of Figure 3 in the Z direction, and the second length L2 may be substantially the same as the thickness of the substrate 101. Such a structure may be formed according to the etching amount of the substrate 101 during the formation of the second region 170L.

[0056] Referring to Figure 4B , in the semiconductor device 100b according to an exemplary embodiment, the second isolation region 170b may include a first region 170U and a second region 170L, respectively. The first region 170U of the second isolation region 170b may extend from above to the upper surface of the substrate 101, and the second region 170L may be provided to penetrate the substrate 101 from the upper surface to the lower surface of the substrate 101.

[0057] Related to Figure 4ACompared with the example embodiment, in the second isolation region 170b, the second region 170L can have such a shape: wherein, its upper surface is planar while its side surface and lower surface are circular. This shape can be obtained by isotropic etching. The second region 170L can be formed to have a shape different from that of Figure 3 and Figure 4A according to the etching conditions, etching thickness, etc.

[0058] Referring to Figure 4C , in the semiconductor device 100c according to the example embodiment, the second isolation region 170 can extend to penetrate the unit region insulating layer 190, the first source sacrificial layer 182, and the electrode material layer 135.

[0059] In the present example embodiment, the second isolation region 170 can be set to penetrate the electrode material layer 135 and the first source sacrificial layer 182 located on the upper and lower surfaces of the electrode material layer 135, rather than penetrating the second horizontal conductive layer 105. For example, when the source sacrificial layer 180 is formed without cutting during the manufacturing process to be described below with reference to Figure 8A and Figure 8B , such a structure can be formed.

[0060] The first source sacrificial layer 182 can include an insulating material such as silicon oxide, and the electrode material layer 135 can be formed of the same material as that of the gate electrode 130. As described above, the structure in which the second isolation region 170 penetrates the first source sacrificial layer 182 and the electrode material layer 135 can be applied to other embodiments. In the example embodiment, the structure and shape of the layer provided on the upper surface of the substrate 101 at the perimeter of the second isolation region 170 can vary in various ways.

[0061] Figure 5 is a schematic cross-sectional view of a semiconductor device according to the example embodiment.

[0062] Referring to Figure 5 , in the semiconductor device 100d, the second isolation region 170d can include a first region 170U and a second region 170L. The first region 170U can penetrate the unit region insulating layer 190, the second horizontal conductive layer 105, and a part of the substrate 101 from above, and can extend in the form of a trench. The second region 170L can be connected to the lower end of the first region 170U below the first region 170U, and its width is smaller than the width of the first region 170U. A curved portion can be formed at the boundary between the first region 170U and the second region 170L according to the change in width. This curved portion can be provided in the substrate 101.

[0063] The second region 170L can have a shape that is contracted relative to the first region 170U or narrower than the first region 170U, and can have a relatively small groove shape. The second region 170L can have a shape formed by recessing the underlying peripheral region insulating layer 290. Accordingly, the lower surface of the second region 170L can be set lower than the lower surface of the substrate 101. The depth L3 by which the lower surface of the second region 170L is recessed from the lower surface of the substrate 101 can vary in the exemplary embodiment.

[0064] The width of the upper end of the second region 170L and the sixth width W6, which is the minimum width of the second region 170L, can be smaller than the fifth width W5, which is the minimum width of the first region 170U, at the lower end of the first region 170U. For example, the sixth width W6 can be in the range of about 50 nm to about 200 nm.

[0065] Figure 6 is a partial enlarged view of a semiconductor device according to an exemplary embodiment. Specifically, Figure 6 is related to Figure 5 an enlarged view of the region corresponding to region 'C' in

[0066] Referring to Figure 6 , in the semiconductor device 100e, the first regions 170Ua and 170Ub of the second isolation region 170e can include multiple layers. The first regions 170Ua and 170Ub can include an outer region 170Ua and an inner region 170Ub, and the inner region 170Ub can have a shape connected to the second region 170L. For example, the inner region 170Ub and the second region 170L can be formed of the same material, and the inner region 170Ub and the outer region 170Ua can be formed of the same material or different materials.

[0067] Figure 7A and Figure 7B is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0068] Referring to Figure 7A , in the semiconductor device 100f according to an exemplary embodiment, the stacked structure of the gate electrode 130 can include a lower stacked structure and an upper stacked structure stacked vertically, and the channel structure CHa can include a first channel structure CH1 and a second channel structure CH2 stacked vertically. When the number of stacked gate electrodes 130 is relatively large, such a structure of the channel structure CHa can be introduced to stably form the channel structure Cha.

[0069] The channel structure CHa can have a shape in which the underlying first channel structure CH1 and the overlying second channel structure CH2 are connected to each other, and can have a bent portion formed due to the width difference in the connection region.

[0070] The channel layer 140, the gate dielectric layer 145, and the channel insulating layer 150 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. The channel pad 155 may be provided only on the upper end of the overlying second channel structure CH2. In another exemplary embodiment, each of the first channel structure CH1 and the second channel structure CH2 may include a channel pad 155, in which case the channel pad 155 of the first channel structure CH1 may be connected to the channel layer 140 of the second channel structure CH2.

[0071] The interlayer insulating layer 125 having a relatively large thickness may be provided on the uppermost part of the lower stack structure. The shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may vary in the exemplary embodiment.

[0072] The first isolation region 160 and the second isolation region 170 may be provided to penetrate both the upper stack structure and the lower stack structure. Thus, the above description made with reference to Figures 1 to 3 may be equally applied to the shapes and structures of the first isolation region 160 and the second isolation region 170.

[0073] With reference to Figure 7B , in the semiconductor device 100g according to the exemplary embodiment, the channel structure CHa may have a structure in which the first channel structure CH1 and the second channel structure CH2 are stacked in the same manner as in Figure 7A . Additionally, in this embodiment, the first isolation region 160g and the second isolation region 170g may also have a structure in which the regions in the lower stack structure and the regions in the upper stack structure are vertically arranged. For example, the first isolation region 160g may include a region 160L in the lower stack structure and a region 160U in the upper stack structure.

[0074] For example, in the second isolation region 170g, the first regions 170U1 and 170U2 may have a structure in which two trench-type regions are vertically connected to each other and may be connected to the second region 170L at the lower end. The second isolation region 170g may have a first bent portion formed due to a width difference in the connection region between the two first regions 170U1 and 170U2, and may also have a second bent portion formed due to a width difference between the first regions 170U1 and 170U2 and the second region 170L.

[0075] Figures 8A to 16B is a schematic cross-sectional view showing the stages in a method of manufacturing a semiconductor device according to an exemplary embodiment. In Figures 8A to 16B , regions corresponding to the regions shown in Figure 2A and Figure 3 are shown.

[0076] With reference to Figure 8A andFigure 8B , a peripheral circuit region PC including circuit elements 220 and an interconnect structure can be formed on a substrate 201, a substrate 101 provided with a memory cell region can be formed on an upper portion of the peripheral circuit region PC, then a source sacrificial layer 180 can be formed, and a horizontal sacrificial layer 185 and an interlayer insulating layer 120 can be alternately stacked.

[0077] A circuit gate dielectric layer 222 and a circuit gate electrode 225 can be sequentially formed on the substrate 201. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 can be formed of, for example, silicon oxide, and the circuit gate electrode 225 can be formed of at least one of, for example, polysilicon and metal silicide. A spacer layer 224 can be formed on opposite sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In an exemplary embodiment, the spacer layer 224 can include multiple layers. An ion implantation process can be performed to form source / drain regions 205 in the substrate 201.

[0078] A circuit contact plug 270 can be formed by forming a part of a peripheral region insulating layer 290, etching and removing a part of the peripheral region insulating layer 290, and filling the removed part with a conductive material. A circuit interconnect line 280 can be formed by, for example, depositing a conductive material and patterning the deposited conductive material.

[0079] The peripheral region insulating layer 290 can include multiple insulating layers. A part of the peripheral region insulating layer 290 can be formed in each process of forming an interconnect structure including the circuit contact plug 270 and the circuit interconnect line 280, and a part of the peripheral region insulating layer 290 can be formed on an upper portion of a third circuit interconnect line 286 (the uppermost interconnect line). Finally, the peripheral region insulating layer 290 can be formed to cover the circuit elements 220 and the interconnect structure.

[0080] The substrate 101 can be formed on the peripheral region insulating layer 290. The substrate 101 can be formed of, for example, polysilicon and can be formed by a CVD process. The polysilicon constituting the substrate 101 can include impurities. The substrate 101 can be patterned to have a size smaller than the size of the substrate 201 shown in Figure 1 .

[0081] The source sacrificial layer 180 can include a first source sacrificial layer 182 and a second source sacrificial layer 184, and can be stacked on the substrate 101 such that the first source sacrificial layer 182 is disposed above and below the second source sacrificial layer 184. The first source sacrificial layer 182 and the second source sacrificial layer 184 can include different materials from each other. The first source sacrificial layer 182 and the second source sacrificial layer 184 can be removed by a subsequent process withFigure 3 The layer replaced by the first horizontal conductive layer 104 in Figure 8B . As shown in Figure 3 , in the region where the second isolation region 170 (see

[0082] The horizontal sacrificial layer 185 may be a layer having a portion to be replaced by the gate electrode 130 (see Figure 3 ) through a subsequent process. The horizontal sacrificial layer 185 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material having etching selectivity that can be etched under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the horizontal sacrificial layer 185 may be formed of a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride different from the material of the interlayer insulating layer 120.

[0083] In the exemplary embodiment, the thicknesses of the interlayer insulating layer 120 and the horizontal sacrificial layer 185 and the number of layers constituting the interlayer insulating layer 120 and the horizontal sacrificial layer 185 may vary, as shown in the drawings. In Figure 8B , a photolithography process and an etching process may be repeatedly performed on the horizontal sacrificial layer 185 using a mask layer, so that the overlying horizontal sacrificial layer 185 may extend less than the underlying horizontal sacrificial layer 185. As a result, the horizontal sacrificial layer 185 may have a stepped shape.

[0084] The cell region insulating layer 190 may be formed to cover the upper portion of the stacked structure of the horizontal sacrificial layer 185 and the interlayer insulating layer 120.

[0085] Referring to Figure 9A and Figure 9B , a channel hole CHH may be formed to penetrate the stacked structure of the horizontal sacrificial layer 185 and the interlayer insulating layer 120. In Figure 9B , a partial region corresponding to the left region in Figure 3 is shown together with the edge of the base substrate 201.

[0086] To form the channel holes CHH, a mask layer MA including an amorphous carbon layer (ACL) may be formed on the unit region insulating layer 190. The mask layer MA may cover the upper surface and the side surface of the unit region insulating layer 190 in the edge region of the substrate body 201 and may extend on the substrate body 201. In the edge region (e.g., the scribe region) of the substrate body 201 in the form of a wafer, the substrate 101 may have a curved structure and be connected to the substrate body 201.

[0087] Each of the channel holes CHH may have a hole shape and may be formed by, for example, an isotropic etching process. Depending on the height of the stacked structure, the sidewalls of the channel holes CHH may not be perpendicular to the upper surface of the substrate 101. The channel holes CHH may be formed to recess a part of the substrate 101.

[0088] When a plasma dry etching process is used during the formation of the channel holes CHH, a potential difference or potential may appear or be manifested in the upper and lower parts of the channel holes CHH through the ions generated in the channel holes CHH. In an exemplary embodiment, the substrate 101 is connected to the substrate body 201 in the edge region, while the respective unit regions 101M of the substrate 101 are connected to each other through the connection regions 101D, thereby allowing charge dissipation. For example, allowing cations to flow through the substrate 101 to the substrate body 201 and allowing anions to flow through the mask layer MA to the substrate body 201. Therefore, an arc fault caused by a potential difference can be prevented.

[0089] Referring to Figure 10A and Figure 10B , at least a part of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and the channel pad 155 may be sequentially formed in the channel holes CHH to form the channel structure CH.

[0090] The gate dielectric layer 145 may be formed to have a uniform thickness using, for example, an ALD or CVD process. In this case, all or part of the gate dielectric layer 145 may be formed, and a part that extends vertically along the channel structure CH to the substrate 101 may be formed. The channel layer 140 may be formed on the gate dielectric layer 145 in the channel structure CH. The channel insulating layer 150 may be formed to fill the channel structure CH and may include an insulating material. In an exemplary embodiment, the inside of the channel layer 140 may be filled with a conductive material instead of the channel insulating layer 150. The channel pad 155 may be formed of a conductive material such as polysilicon.

[0091] Referring to Figure 11A and Figure 11B, the first opening OP1 and the second opening OP2 can be formed to penetrate the stacked structure of the horizontal sacrificial layer 185 and the interlayer insulating layer 120. The sacrificial spacer layer 187 can be formed on the inner sidewalls of the first opening OP1 and the second opening OP2.

[0092] Before forming the first opening OP1 and the second opening OP2, the unit region insulating layer 190 can also be formed on the channel structure CH. It can be formed Figure 3 The first opening OP1 can be formed at the position of the first isolation region 160 in Figure 9A and Figure 9B The second opening OP2 can be formed at the position of the second isolation region 170. The first opening OP1 and the second opening OP2 can be formed simultaneously by forming a mask layer using a photolithography process and anisotropically etching the stacked structure using a dry etching process. In this case, as described above with reference to

[0093] The first opening OP1 can be formed in the form of a trench extending in the Y direction, and the second opening OP2 can be formed in the form of a relatively short and wide rectangular trench. The source sacrificial layer 180 can be exposed below the first opening OP1, and the second opening OP2 can extend into the substrate 101 to expose the substrate 101 therebelow.

[0094] When the first opening OP1 and the second opening OP2 are formed together in the same process, the first opening OP1 and the second opening OP2 can be formed to have different depths from each other by adjusting the process conditions, such that the minimum width of the second opening OP2 is equal to about twice or more the minimum width of the first opening OP1. The width of the second opening OP2 can be greater than the width of the first opening OP1. Therefore, the etching rate of the second opening OP2 can be relatively high, and thus, the second opening OP2 can be deeply etched.

[0095] As Figure 11A shown, the second opening OP2 can be formed in the Y direction to have a length L5 less than the length L4 of the connection region 101D of the substrate 101. If the length L5 of the second opening OP2 is equal to the length L4 of the connection region 101D, due to process deviation, the second opening OP2 can extend downward while denting the underlying peripheral region insulating layer 290 outside the connection region 101D, which makes it difficult to control the depth of the second opening OP2.

[0096] A sacrificial spacer layer 187 may be formed on the inner sidewalls of the first opening OP1 and the second opening OP2, and the sacrificial spacer layer 187 may include a material different from that of the source sacrificial layer 180. The sacrificial spacer layer 187 may protect the horizontal sacrificial layer 185 in subsequent processes.

[0097] Referring Figure 12A and Figure 12B , the source sacrificial layer 180 may be removed through the first opening OP1, and a first horizontal conductive layer 104 may be formed in the region where the source sacrificial layer 180 has been removed.

[0098] After selectively removing the second source sacrificial layer 184 through the first opening OP1, the first source sacrificial layer 182 may be removed. The source sacrificial layer 180 may be removed by, for example, a wet etching process. In the process of removing the first source sacrificial layer 182, a portion of the gate dielectric layer 145 exposed in the region where the second source sacrificial layer 184 has been removed may also be removed.

[0099] After forming the first horizontal conductive layer 104 by depositing a conductive material on the region where the source sacrificial layer 180 has been removed, the sacrificial spacer layer 187 in the first opening OP1 and the second opening OP2 may be removed. The first horizontal conductive layer 104 may be in direct contact with the channel layer 140 in the region where the gate dielectric layer 145 has been removed.

[0100] Referring Figure 13A and Figure 13B , the horizontal sacrificial layer 185 may be removed through the first opening OP1 to form a lateral opening LT.

[0101] The horizontal sacrificial layer 185 may be selectively removed with respect to the interlayer insulating layer 120 and the first horizontal conductive layer 104 and the second horizontal conductive layer 105 using, for example, wet etching. Thus, a plurality of lateral openings LT may be formed between the interlayer insulating layers 120, and a portion of the sidewall of the channel structure CH may be exposed through the lateral openings LT.

[0102] Referring Figure 14A and Figure 14B , the lateral openings LT may be filled with a conductive material to form a gate electrode 130. The conductive material constituting the gate electrode 130 may fill the lateral openings LT. The conductive material may include, for example, a metal, polysilicon, or metal silicide material. After forming the gate electrode 130, the conductive material deposited in the first opening OP1 and the second opening OP2 may be removed through an additional process.

[0103] Referring Figure 15A and Figure 15B, an insulating material can be deposited in the first opening OP1 and the second opening OP2 to form the first separation region 160 and the spacer layer SP. Due to the width difference between the first opening OP1 and the second opening OP2, the insulating material can completely fill the first opening OP1 to form the first separation region 160 in the first opening OP1, while being deposited on the inner sidewalls of the second opening OP2.

[0104] By controlling the etching conditions and the distribution of the etchant, the insulating material deposited on the lower end of the second opening OP2 can be removed while protecting the upper end of the first separation region 160. Thus, the spacer layer SP can be formed. As Figure 15B shown, in this case, the second opening OP2 can extend downward such that the lower end of the second opening OP2 can be set below the lower surface of the spacer layer SP.

[0105] Referring to Figure 16A and Figure 16B , the substrate 101 exposed at the lower end of the second opening OP2 can be removed to form the second opening extension OP2L.

[0106] The substrate 101 can be removed at the lower end of the second opening OP2 by a wet etching process, and the underlying peripheral region insulating layer 290 can be exposed through the second opening OP2. The etchant can be supplied to the substrate 101 through the second opening OP2. The etching process can be selectively performed on the material of the substrate 101. Thus, the spacer layer SP can be retained without being removed.

[0107] The second opening extension OP2L can have an outer surface rounded according to an isotropic etching process. As Figure 16A shown, the second opening extension OP2L can extend from the second opening OP2 in the X direction and the Y direction. Thus, in the Y direction, the length L6 of the second opening extension OP2L can be greater than the length L4 of the connection region 101D of the substrate 101, and the connection region 101D can be completely cut in a direction perpendicular to the extension direction. As a result, the substrate 101 can be divided between multiple cell regions CELL.

[0108] Next, referring again to Figure 3 , an insulating material can be deposited in the second opening OP2 and the second opening extension OP2L to form the second separation region 170. In an exemplary embodiment, when the insulating material includes a material different from that of the spacer layer SP, its boundary can be identified in the second separation region 170.

[0109] As described above, the process of forming the first isolation region 160 can be used to form the second isolation region 170. Therefore, the second isolation region 170 can be formed without adding a lithography process. After forming the channel holes CHH and the first opening OP1 and the second opening OP2, the substrate 101 can be divided into a plurality of cell regions CELL, and arc faults can be prevented.

[0110] Figures 17A to 18B are schematic cross-sectional views showing the stages in a method of manufacturing a semiconductor device according to an exemplary embodiment. In Figure 17A and Figure 18B are shown regions corresponding to the regions shown in Figure 2A and Figure 5 respectively.

[0111] Referring to Figure 17A and Figure 17B , the above-described process with reference to Figures 8A to 14B can be performed in the same manner. However, in this embodiment, when performing the process, as shown in Figure 17A , the second opening OP2' can be formed to be longer than the connection region 101D of the substrate 101 in the Y direction.

[0112] Referring to Figure 18A and Figure 18B , an insulating material can be deposited in the first opening OP1 and the second opening OP2' to form the first isolation region 160 and the isolation spacer layer SP, and the substrate 101 exposed at the lower end of the second opening OP2' can be removed to form the second opening extension OP2L'.

[0113] The first isolation region 160 and the isolation spacer layer SP can be formed in the same manner as described with reference to Figure 15A and Figure 15B . The second opening extension OP2L' can be formed by anisotropically etching the substrate 101 at the lower end of the second opening OP2' using a dry etching process. Therefore, the second opening extension OP2L' can be shrunk from the overlying second opening OP2' to have a shape similar to that of the second opening OP2'.

[0114] The second opening extension OP2L' can be formed by shrinking the thickness of the isolation spacer layer SP in the X and Y directions from the second opening OP2'. The second opening extension OP2L' can be formed to divide the substrate 101 between the plurality of cell regions CELL.

[0115] Next, referring again to Figure 5, an insulating material may be deposited on the second opening OP2' and the second opening extension OP2L' to form a second isolation region 170d. The process used to form the first isolation region 160 may be used to form the second isolation region 170d. Thus, the second isolation region 170d is formed without adding a lithography process, and the substrate may be divided into a plurality of cell regions CELL after forming the channel holes CHH and the first opening OP1 and the second opening OP2' to prevent an arc fault.

[0116] As described above, the isolation region penetrating the substrate provided with the memory cell region may be formed to have a curved portion.

[0117] As described above, the exemplary embodiments may provide a semiconductor device having improved reliability.

[0118] Exemplary embodiments have been disclosed herein. Although specific terms are employed, they are used and interpreted in a general and illustrative sense only and not for purposes of limitation. In some instances, as will be apparent to one of ordinary skill in the art upon submission of the present application, unless otherwise specifically stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A peripheral circuit region, which includes a first substrate and circuit elements on the first substrate; And A memory cell region, which includes: a second substrate, which is located on an upper portion of the first substrate; gate electrodes, which are spaced apart from each other and vertically stacked on the second substrate; a horizontal conductive layer, which is located between the second substrate and the gate electrodes; a channel structure, which vertically extends through the gate electrodes to the second substrate; a first isolation region, which penetrates the gate electrodes between the channel structures and extends in one direction; a cell region insulating layer, which covers the stacked structure of the gate electrodes; and a second isolation region, which vertically extends to penetrate the second substrate from above, Wherein, the second isolation region includes a first region and a second region, the first region extends into the second substrate from above in the form of a trench, the second region is connected to a lower end of the first region within the second substrate, a width of the second region is greater than a width of the first region, and the second region has a circular outer surface.

2. The semiconductor device according to claim 1, wherein, The second isolation region penetrates the cell region insulating layer and the horizontal conductive layer from above, and extends to the second substrate.

3. The semiconductor device according to claim 1, wherein, Each of the first isolation regions has a first width at an upper end of the first isolation region, and the second isolation region has a second width at an upper end of the second isolation region, the second width being greater than the first width.

4. The semiconductor device according to claim 3, wherein, The second width is in a range of two to four times the first width.

5. The semiconductor device according to claim 4, wherein, The second width is in a range of 300 nm to 800 nm.

6. The semiconductor device according to claim 1, wherein, The second isolation region has the second width at an upper end of the first region, has a third width smaller than the second width at a lower end of the first region, and has a fourth width greater than the second width at a lower end of the second region.

7. The semiconductor device according to claim 1, wherein, A lower surface of the second isolation region is substantially coplanar with a lower surface of the second substrate.

8. The semiconductor device according to claim 1, wherein, A lower surface of the first isolation region is disposed at a horizontal height higher than a lower surface of the first region.

9. The semiconductor device according to claim 1, wherein, The first isolation region and the second isolation region are formed of an insulating material.

10. The semiconductor device according to claim 1, wherein: The memory cell region includes a plurality of cell regions, The second substrate includes a connection region extending between the cell regions adjacent to each other in one direction, and The second isolation region penetrates the connection region to divide the second substrate between the plurality of cell regions.

11. The semiconductor device according to claim 10, wherein: The gate electrodes are disposed within the plurality of cell regions such that the gate electrodes do not extend to the connection region, and The second isolation region does not penetrate the gate electrodes.

12. The semiconductor device according to claim 10, wherein The memory cell region further includes source contact plugs, the source contact plugs are disposed outside the first isolation region in an edge region of the plurality of cell regions, and the source contact plugs are electrically connected to the horizontal conductive layer.

13. The semiconductor device according to claim 1, wherein, The horizontal conductive layer includes a first conductive layer and a second conductive layer vertically stacked.

14. The semiconductor device according to claim 1, wherein, The channel structure includes a first channel structure and a second channel structure vertically stacked on the second substrate.

15. The semiconductor device according to claim 14, wherein, The first region of the second isolation region includes two regions vertically stacked on the second substrate.

16. A semiconductor device includes: An outer circuit region including a first substrate and circuit elements on the first substrate; And A memory cell region including: a second substrate located on an upper portion of the first substrate; gate electrodes spaced apart from each other and vertically stacked on the second substrate; a channel structure vertically extending through the gate electrodes to the second substrate; a first isolation region penetrating the gate electrodes between the channel structures and extending in one direction; and a second isolation region vertically extending to penetrate the second substrate from above and having a bent portion due to a change in width, Wherein the second isolation region includes a first region and a second region, the first region extends from above in the form of a trench, the second region is connected to a lower end of the first region, the second region is within the second substrate, the width of the second region is greater than the width of the first region, and the second region has a circular outer surface.

17. The semiconductor device according to claim 16, wherein, The bent portion of the second isolation region is provided in the second substrate.

18. A semiconductor device includes: A first substrate; Circuit elements located on the first substrate; A first insulating layer covering the circuit elements; A second substrate provided on the first insulating layer; Gate electrodes spaced apart from each other and vertically stacked on the second substrate; A second insulating layer covering the gate electrodes; And An isolation region spaced apart from the gate electrodes, penetrating the second insulating layer and the second substrate to vertically extend to the second substrate and having a bent portion, Wherein the isolation region includes a first region and a second region, the first region extends from above in the form of a trench, the second region is connected to a lower end of the first region, the second region is within the second substrate, the width of the second region is greater than the width of the first region, and the second region has a circular outer surface.

19. The semiconductor device according to claim 18, wherein, The second region has a shape formed by isotropic etching.

Images