Image sensor and method of forming the same

Abstract

Various embodiments of the present disclosure relate to an image sensor, the image sensor comprising a first photodetector and a second photodetector, each of which is disposed in a semiconductor substrate. An isolation structure extends from a front side surface of the semiconductor substrate to a rear side surface of the semiconductor substrate. The front side surface is opposite to the rear side surface, and the isolation structure is laterally located between the first photodetector and the second photodetector. A readout transistor is disposed on the front side surface of the semiconductor substrate. A first side of the readout transistor overlies the first photodetector and a second side of the readout transistor overlies the second photodetector. The first side is opposite to the second side and the readout transistor extends continuously over the isolation structure.

Description

Technical Field

[0001] An embodiment of the present invention relates to an image sensor. Background Art

[0002] Many modern electronic devices (e.g., digital cameras, optical imaging devices, etc.) include image sensors. Image sensors convert optical images into digital data that can be represented as digital images. Image sensors include a pixel sensor array, which is a unit device for converting optical images into digital data. Some types of pixel sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors (CIS). Compared with CCD image sensors, CIS is more popular due to low power consumption, small size, fast data processing, direct data output, and low manufacturing cost, among other reasons. Summary of the invention

[0003] An embodiment of the present invention provides an image sensor, comprising: a first photodetector disposed in a semiconductor substrate; a second photodetector disposed in the semiconductor substrate; an isolation structure extending from a front side surface of the semiconductor substrate to a back side surface of the semiconductor substrate, wherein the front side surface is opposite to the back side surface, and wherein the isolation structure is laterally located between the first photodetector and the second photodetector; and a readout transistor disposed on the front side surface of the semiconductor substrate, wherein a first side of the readout transistor overlies the first photodetector and a second side of the readout transistor overlies the second photodetector, wherein the first side is opposite to the second side, and wherein the readout transistor extends continuously over the isolation structure.

[0004] An embodiment of the present invention provides an image sensor, comprising: a first pixel sensor and a second pixel sensor, each comprising a plurality of photodetectors, a plurality of transfer transistors, and a floating diffusion node, wherein the plurality of photodetectors are disposed in a semiconductor substrate, and wherein the plurality of transfer transistors are disposed on a front side surface of the semiconductor substrate and selectively electrically couple the plurality of photodetectors to the floating diffusion node. An isolation structure disposed in the semiconductor substrate, wherein the isolation structure continuously surrounds each photodetector in the first pixel sensor and each photodetector in the second pixel sensor, and wherein the isolation structure extends completely through the semiconductor substrate. A source follower transistor overlying the first pixel sensor and gated by the floating diffusion node of the first pixel sensor. And a row select transistor overlying the second pixel sensor and having a source / drain region electrically coupled to a source / drain region of the source follower transistor.

[0005] An embodiment of the present invention provides a method for forming an image sensor, the method comprising: forming a shallow trench isolation structure on a front side surface of a semiconductor substrate. Forming a first photodetector and a second photodetector in the semiconductor substrate, wherein the first photodetector and the second photodetector are separated laterally by the shallow trench isolation structure. Forming a readout transistor on the front side surface, wherein a first sidewall of the readout transistor overlies the first photodetector and a second sidewall of the readout transistor overlies the second photodetector, wherein the first sidewall is opposite to the second sidewall, and wherein the readout transistor extends continuously above the upper surface of the shallow trench isolation structure. Forming a first source / drain region along the first sidewall of the readout transistor. Forming a first junction isolation structure along the first sidewall of the readout transistor, wherein the first junction isolation structure is laterally located between the first source / drain regions. And forming a deep trench isolation structure on the back side surface of the semiconductor substrate, wherein the deep trench isolation structure extends from the back side surface to the shallow trench isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Layout diagrams showing some embodiments of image sensors having pixel devices extending over isolation structures.

[0008] Figure 2 Shown along line A-A' Figure 1Cross-sectional views of some alternative embodiments of image sensors are shown.

[0009] Figure 3A Layout diagrams showing some embodiments of image sensors having multiple pixel devices each having a source / drain region disposed on a single side of a gate electrode.

[0010] Figure 3B and Figure 3C Show Figure 3A A portion of the image sensor shown (eg Figure 3A Layout diagrams of some alternative embodiments (shown in the dashed box in FIG. ).

[0011] Figure 4 Layout diagrams of some embodiments of image sensors having multiple pixel sensors and pixel devices extending over isolation structures are shown.

[0012] Figure 5 Shown according to line BB' Figure 4 Cross-sectional views of some alternative embodiments of image sensors are shown.

[0013] Figure 6 Show according to Figure 4 A layout diagram of an image sensor of an alternative embodiment of an image sensor is shown, wherein the image sensor has more than one pixel device, each of the pixel devices extending over an isolation structure.

[0014] Figure 7 Show Figure 4 Circuit diagrams of some alternative embodiments of image sensors are shown.

[0015] Figure 8 and Fig. 9 Shown according to line C-C' Figure 6 Cross-sectional views of some alternative embodiments of image sensors are shown.

[0016] Figures 10 to 17 A series of cross-sectional views illustrating some embodiments of methods for forming an image sensor having a pixel device extending over an isolation structure.

[0017] Fig.18 A flow chart illustrating some embodiments of a method for forming an image sensor having a pixel device extending over an isolation structure. DETAILED DESCRIPTION

[0018] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0020] Some complementary metal oxide semiconductor image sensors (CIS) have a pixel sensor array. The pixel sensors of the pixel sensor array include a photodetector array (e.g., a 2×2 photodetector array) disposed in a semiconductor substrate. In some embodiments, the photodetectors may be separated from each other by an isolation structure (e.g., a full depth isolation structure). In addition, the pixel sensor includes a plurality of pixel devices (e.g., a transfer transistor, a reset transistor, a source follower transistor, and / or a row select transistor) disposed on an active region of the semiconductor substrate. Typically, the plurality of pixel devices are disposed laterally adjacent to the corresponding photodetector array and do not extend across the isolation structure. An interconnect structure overlies the semiconductor substrate and the pixel device. The interconnect structure electrically couples the photodetector to the pixel device. The pixel sensor uses a photodetector to record incident radiation (e.g., photons) and facilitates digital readout of the record using the pixel device.

[0021] One challenge for the above-mentioned CIS is poor noise performance (e.g., random noise, fixed pattern noise, flicker noise, shot noise, thermal noise, white noise, etc.). One factor of noise performance is the size of the multiple pixel devices (e.g., the size of the source follower device). In some embodiments, the isolation structure is a full-depth deep trench isolation (DTI) structure extending from the front side of the semiconductor substrate to the back side of the semiconductor substrate. The front side is opposite to the back side. In such an embodiment, the full-depth DTI structure can improve the full well capacity of the image sensor and / or increase the electrical isolation between adjacent photodetectors and / or pixel devices disposed in / on the semiconductor substrate. Since the isolation structure is a full-depth DTI structure, it will consume the surface area of ​​the semiconductor substrate, thereby reducing the size of the active area of ​​the semiconductor substrate. In addition, the pixel sensor is limited to overlying the active area of ​​the semiconductor substrate, wherein the pixel sensor is generally not overlying the full-depth DTI structure. Therefore, to accommodate the full-depth DTI structure, the pixel device is usually reduced so that the pixel device, the isolation structure and the photodetector are disposed on / in the semiconductor substrate. However, reducing the size of the pixel device can have a negative impact on noise (e.g., due to the reduced size of the source follower device), resulting in poor noise performance. In such an embodiment, as the size of the pixel device is reduced, the effective length of the selectively formable channel under each gate electrode (e.g., source follower gate electrode) of the pixel device is reduced. As the effective length of the selectively formable channel is reduced, the flicker noise present in the pixel device will increase. This increases the noise in the image sensor, thereby reducing the accuracy and / or reliability of the image generated from the image sensor.

[0022] Various embodiments of the present disclosure relate to an image sensor including at least one pixel device, which extends over an isolation structure (e.g., a full-depth DTI structure) disposed between a first pixel sensor and a second pixel sensor. The first pixel sensor and the second pixel sensor are adjacent to each other. The first pixel sensor and the second pixel sensor each include a photodetector array (e.g., a 2×2 photodetector array) and a plurality of pixel devices. The plurality of pixel devices may include readout transistors, such as a reset transistor, a source follower transistor, a selection transistor, a transfer transistor, and the like. The photodetector array and the plurality of pixel devices are disposed on and / or within a semiconductor substrate, respectively. The isolation structure is disposed within the semiconductor substrate and laterally surrounds each photodetector of an adjacent pixel sensor. The readout transistor (e.g., a source follower transistor) is disposed on the semiconductor substrate and laterally extends over the isolation structure. The readout transistor extends continuously from over the photodetector in the first pixel sensor to over the photodetector in the second pixel sensor.

[0023] Since the readout transistor extends continuously over the isolation structure between adjacent pixel sensors, the readout transistor can have an enlarged gate electrode. In addition, the readout transistor can be configured to act as two transistors in parallel with each other, with a single conductive contact overlying the readout gate electrode. In this embodiment, the metal line and another conductive contact that would otherwise be used to electrically couple the two gate electrodes in parallel with each other are omitted, thereby reducing the overall conductive density of the interconnect structure (e.g., reducing parasitic capacitance present in the interconnect structure). In addition, since the readout transistor can act as two transistors in parallel with each other, the effective channel resistance of the readout transistor can be reduced. This partially reduces the noise in the readout transistor, thereby improving the accuracy and / or reliability of the image generated from the image sensor.

[0024] In addition, a first source / drain region and a second source / drain region of the readout transistor are respectively arranged along the first side of the readout gate electrode. A junction isolation structure is arranged laterally between the first source / drain region and the second source / drain region. In some embodiments, the junction isolation structure may extend a certain distance below the readout gate electrode toward the second side of the readout gate electrode opposite to the first side. As the distance increases, the effective length of the selective conductive channel located below the readout gate electrode and between the first source / drain region and the second source / drain region increases. As the effective length increases, the noise (e.g., flicker noise) present in the readout transistor decreases. This further reduces the noise in the readout transistor, thereby further improving the accuracy and / or reliability of the image generated from the image sensor.

[0025] Figure 1A layout diagram of some embodiments of an image sensor 100 is shown having a readout transistor 120c extending over a first isolation structure 110 (shown in dashed lines). The first isolation structure 110 may be referred to as a deep trench isolation (DTI) structure, for example. Figure 2 Shown along line A-A' Figure 1 A cross-sectional view 200 of some alternative embodiments of image sensor 100 is shown.

[0026] like Figure 1 As shown, the image sensor 100 includes a first pixel sensor 106 and a second pixel sensor 108, respectively, disposed on a substrate 102. In some embodiments, the substrate 102 is a bulk substrate (e.g., silicon) including a first doping type (e.g., p-type). The first pixel sensor 106 may include a first plurality of photodetectors 106a to 106b (shown in dashed lines), and the second pixel sensor 108 may include a second plurality of photodetectors 108a to 108b (shown in dashed lines). The first plurality of photodetectors 106a to 106b and the second plurality of photodetectors 108a to 108b (e.g., photodiodes) are respectively configured to absorb incident radiation (e.g., photons) and generate electrical signals corresponding to the incident radiation. The first plurality of photodetectors 106a to 106b and the second plurality of photodetectors 108a to 108b are disposed within the substrate 102 and each include a second doping type (e.g., n-type) opposite to the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. The first isolation structure 110 is disposed in the substrate 102 and laterally surrounds each of the first plurality of photodetectors 106a-106b and the second plurality of photodetectors 108a-108b. When viewed in cross section, a second isolation structure 131 (referred to as a shallow trench isolation (STI) structure in some embodiments) overlies the substrate 102 and the first isolation structure 110.

[0027] A first plurality of pickup well contact regions 114a-114b are disposed in the substrate 102. The first plurality of pickup well contact regions 114a-114b correspond to the first plurality of photodetectors 106a-106b, respectively. In addition, a second plurality of pickup well contact regions 129a-129b are disposed in the substrate 102, and the second plurality of pickup well contact regions 129a-129b correspond to the second plurality of photodetectors 108a-108b, respectively. The first plurality of pickup well contact regions 114a-114b and the second plurality of pickup well contact regions 129a-129b may each include the same doping type as the substrate 102, such as the first doping type (e.g., p-type) at a higher doping concentration than the substrate 102.

[0028] A first plurality of floating diffusion nodes 116a-116b are disposed in the substrate 102, and the first plurality of floating diffusion nodes 116a-116b correspond to the first plurality of photodetectors 106a-106b, respectively. A second plurality of floating diffusion nodes 128a-128b are disposed in the substrate 102, and the second plurality of floating diffusion nodes 128a-128b correspond to the second plurality of photodetectors 108a-108b, respectively. The first plurality of floating diffusion nodes 116a-116b and the second plurality of floating diffusion nodes 128a-128b may each include a second doping type (e.g., n-type) at a higher doping concentration than the substrate 102.

[0029] A first plurality of transfer transistors 112a-112b are disposed on / in the substrate 102, and the transfer transistors 112a-112b each overlie a corresponding photodetector in the first plurality of photodetectors 106a-106b. For example, the first transfer transistor 112a overlies the first photodetector 106a, and the second transfer transistor 112b overlies the second photodetector 106b. A second plurality of transfer transistors 126a-126b are disposed on / in the substrate 102, and the transfer transistors 126a-126b each overlie a corresponding photodetector in the second plurality of photodetectors 108a-108b. In some embodiments, the first plurality of transfer transistors 112a-112b and the second plurality of transfer transistors 126a-126b are respectively configured to form a conductive channel between a corresponding photodetector and a corresponding floating diffusion node, wherein charge accumulated in the corresponding photodetector (e.g., by absorbing incident radiation) can be transferred to the corresponding floating diffusion node. For example, the first transfer transistor 112a is configured to form a conductive channel between the first photodetector 106a and the first floating diffusion node 116a, wherein the charge accumulated in the first photodetector 106a can be transferred to the first floating diffusion node 116a. In some embodiments, each transfer transistor of the first plurality of transfer transistors 112a-112b and the second plurality of transfer transistors 126a-126b includes a transfer gate electrode 109 having an embedded conductive body 111 extending into the substrate 102. In addition, at least a portion of each transfer gate electrode 109 is connected to the substrate 102 through a gate dielectric layer (e.g., Figure 2 The gate dielectric layer 202 is shown separated from the substrate 102 .

[0030] A first plurality of readout transistors 120a to 120c (e.g., reset transistors, source follower transistors, row selection transistors, etc.) are disposed on the substrate 102. In some embodiments, the first plurality of readout transistors 120a to 120c include readout gate electrodes 122a to 122c and source / drain regions 124a to 124h, respectively. In some embodiments, the first plurality of readout transistors 120a to 120c may each be, for example, a metal-oxide semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a high-electron-mobility transistor (HEMT), etc.

[0031] In some embodiments, the first readout transistor 120a includes a first readout gate electrode 122a and source / drain regions 124a-124b. The second readout transistor 120b includes a second readout gate electrode 122b and source / drain regions 124c-124d. The third readout transistor 120c includes a third readout gate electrode 122c and source / drain regions 124e-124h. The readout transistors 120a-120c each include a gate dielectric layer that separates each readout transistor 120a-120c from the substrate 102 (e.g., the third readout transistor 120c includes a gate dielectric layer that separates each readout transistor 120a-120c from the substrate 102). Figure 2 202 as shown in the figure).

[0032] A first plurality of junction isolation structures 118a to 118d are located in the substrate 102, and each of the junction isolation structures 118a to 118d is disposed between the readout transistors 120a to 120c and a gate electrode adjacent to the readout transistor. The first plurality of junction isolation structures 118a to 118d are configured to increase isolation between the source / drain regions 124a to 124h. In some embodiments, each of the junction isolation structures 118a to 118d includes a first doping type (e.g., p-type) at a higher doping concentration than the substrate 102.

[0033] A plurality of vias 130 and a plurality of conductive wires 132 overlie the substrate 102 (when viewed in cross section) and electrically couple devices and / or doped regions (e.g., the first plurality of readout transistors 120a to 120c, source / drain regions 124a to 124d, the first plurality of pickup well contact regions 114a to 114b, etc.) to each other. When viewed in cross section, the plurality of vias 130 extend from the lower surface of the plurality of conductive wires 132 to the underlying devices or doped regions, respectively. In some embodiments, the vias 130 and the conductive wires 132 are part of an interconnect structure overlying the substrate 102 when viewed in cross section. Figure 1 For clarity in the figure, the via 130 is shown by an "X" disposed within a box.

[0034] The substrate 102 includes a first plurality of active regions 103a-103b and a second plurality of active regions 104a-104b. The first plurality of active regions 103a-103b and the second plurality of active regions 104a-104b include doped regions of a first pixel sensor 106 and a second pixel sensor 108, respectively. For example, the first plurality of active regions 103a-103b include the first plurality of photodetectors 106a-106b, the first plurality of pickup well contact regions 114a-114b, and the first plurality of floating diffusion nodes 116a-116b. Thus, the first plurality of active regions 103a-103b corresponds to the first pixel sensor 106. In another example, the second plurality of active regions 104a-104b include a second plurality of photodetectors 108a-108b, the second plurality of pickup well contact regions 129a-129b, and the second plurality of floating diffusion nodes 128a-128b. Thus, the second plurality of active areas 104 a - 104 b corresponds to a second pixel sensor 108 .

[0035] The first plurality of readout transistors 120a to 120c are configured to read out the charge accumulated by the first plurality of photodetectors 106a to 106b. In some embodiments, the first readout transistor 120a is configured as a reset transistor, the second readout transistor 120b is configured as a row select transistor, and the third readout transistor 120c is configured as a source follower transistor. Since the third readout transistor 120c extends from the first plurality of photodetectors 106a to 106b to the second plurality of photodetectors 108a to 108b over the first isolation structure 110 (and / or the second isolation structure 131), the effective size of the third readout transistor 120c is increased. This is because the third readout transistor 120c can act as two transistors in parallel (such as Figure 7 ). Therefore, the size of the third readout transistor 120c can be larger than when the third readout transistor 120c is confined to directly overlying / disposed in a single active area of ​​the first plurality of active areas 103a to 103b and / or the second plurality of active areas 104a to 104b. Therefore, the presence of noise (e.g., flicker noise) in the image sensor 100 is reduced, thereby improving the reliability, durability, and performance of the image sensor 100.

[0036] Furthermore, in some embodiments, by disposing the second readout transistor 120b above the first active region 104a of the second plurality of active regions 104a to 104b, the readout transistors 120a to 120c are not in close proximity to each other. Therefore, the size of the second readout transistor 120b can be larger than when the second readout transistor 120b is disposed adjacent to another readout transistor device in the first active region 104a. This further reduces the presence of noise (e.g., flicker noise) in the image sensor 100, thereby further improving the reliability, durability, and performance of the image sensor 100.

[0037] In some embodiments, another factor of noise is the total conductive density of the interconnect structures (e.g., vias 130 and conductive wiring 132). For example, as the number of vias 130 and / or conductive wiring 132 increases, the parasitic capacitance between the conductive elements in the interconnect structures increases. This increases the noise in the image sensor 100. Since the third readout gate electrode 122c extends above the first isolation structure 110 and between the source / drain regions 124e to 124f and the source / drain regions 124g to 124h, a single via 130 overlies the third readout gate electrode 122c. This enables the third readout transistor 120c to act as two transistors in parallel, thereby reducing the effective channel resistance of the third readout transistor 120c while reducing the total conductive density of the interconnect structures. Therefore, the image sensor 100 can have further improved noise performance while reducing the time and cost associated with forming the image sensor 100.

[0038] like Figure 2 As shown, the substrate 102 has a front side 102f opposite to the back side 102b. The second isolation structure 131 extends from above the front side 102f to a point in the substrate 102 below the front side 102f. The first isolation structure 110 extends from the back side 102b to a point in the substrate 102, wherein the top surface of the first isolation structure 110 directly contacts and / or is aligned with the bottom surface of the second isolation structure 131. In such an embodiment, the first isolation structure 110 and the second isolation structure 131 may form a full-depth deep trench isolation (DTI) structure that extends completely through the substrate 102. This may partially increase the well capacity of the image sensor 100.

[0039] A readout transistor well region 204 may be provided in the substrate 102, and the readout transistor well region 204 is directly below the third readout transistor 120c. In some embodiments, the third readout transistor 120c may be configured to form a conductive channel in the readout transistor well region 204. In other embodiments, the readout transistor well region 204 may include a first doping type (e.g., p-type) at a higher doping concentration than the substrate 102. The third readout transistor 120c overlies the second photodetector 106b of the first plurality of photodetectors 106a to 106b and overlies the second photodetector 108b of the second plurality of photodetectors 108a to 108b. In addition, the third readout transistor 120c extends continuously over the segment 110a of the first isolation structure 110, and the segment 110a of the first isolation structure 110 is laterally located between the second photodetector 106b of the first plurality of photodetectors 106a to 106b and the second photodetector 108b of the second plurality of photodetectors 108a to 108b.

[0040] Figure 3A Show according to Figure 1 Layout diagrams of image sensors 300 a of some alternative embodiments of image sensor 100 are shown. Figure 3A The image sensor 300a shown in FIG. 1 is not provided with the via hole 130 and the conductive wiring 132. Figure 1 An image sensor 100 is shown.

[0041] like Figure 3A As shown, at least a portion of each junction isolation structure 118a to 118d is directly located under the corresponding readout gate electrode 122a to 122c. In some embodiments, the junction isolation structures 118a to 118d each include a first doping type (e.g., p-type) at a doping concentration in the range of about 1017 atoms / cm3 to 1019 atoms / cm3. In other embodiments, the source / drain regions 124a to 124h have a second doping type (e.g., n-type) at a doping concentration approximately equal to that of the junction isolation structures 118a to 118d (e.g., in the range of about 1017 atoms / cm3 to 1019 atoms / cm3). Since the junction isolation structures 118a to 118d are directly located under the corresponding readout gate electrodes 122a to 122c, and each source / drain region 124a to 124h is located on a single side of its corresponding readout gate electrode 122a to 122c, the effective length of the underlying conductive channel can be increased (e.g., as shown in FIG. 1 ). Figure 3B to Figure 3C By increasing the effective length of the conductive channel under each readout gate electrode 122a-122c, image sensor 300a can have improved noise performance.

[0042] Figure 3B Show Figure 3A A portion of the image sensor 300a is shown (eg Figure 3A Cross-sectional view 300b of some alternative embodiments (shown in dashed box in FIG. 3 ).

[0043] When viewed from the cross section, the third readout gate electrode 122c is aligned with the front side of the substrate 102 ( Figure 2 102f) is provided between the readout gate insulator layer 302. In some embodiments, the readout gate insulator layer 302 acts as a gate dielectric layer and / or may be, for example, or may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k dielectric material (e.g., tantalum oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, zirconium aluminum oxide, hafnium aluminum oxide, titanium bromide oxide, strontium titanium oxide, combinations of the above materials, etc.). The high-k dielectric material used herein is a dielectric material having a dielectric constant greater than 3.9. In yet other embodiments, the readout gate insulator layer 302 may be a gate dielectric layer (e.g., Figure 2 1, wherein the read gate insulator layer 302 continuously extends from the source / drain region 124e to the source / drain region 124f along the sidewall of the junction isolation structure 118c. In some embodiments, the source / drain regions 124e to 124f and the junction isolation structure 118c are respectively disposed along the sidewall 122csw of the third read gate electrode 122c.

[0044] The junction isolation structure 118c extends continuously from the source / drain region 124e to the source / drain region 124f, includes a first doping type (e.g., p-type), and / or has a doping concentration in the range of about 1017 atoms / cm3 to 1019 atoms / cm3. In some embodiments, the high doping concentration of the junction isolation structure 118c can block and / or prevent the formation of a conductive channel under a portion of the third readout gate electrode 122c where the junction isolation structure 118c is located. Thus, the conductive channel is first formed around the junction isolation structure 118c. The source / drain regions 124e to 124f each include a second doping type (e.g., n-type) and / or have a doping concentration in the range of about 1017 atoms / cm3 to 1019 atoms / cm3. In some embodiments, the junction isolation structure 118c and the source / drain regions 124e to 124f have approximately the same doping concentration (e.g., in the range of about 1017 atoms / cm3 to 1019 atoms / cm3). The junction isolation structure 118c is configured to electrically isolate the source / drain regions 124e to 124f from each other. In some embodiments, when appropriate bias conditions are applied to the third readout gate electrode 122c, a conductive channel 304 may be formed in the substrate 102 below the third readout gate electrode 122c. In such embodiments, the formation of the conductive channel 304 facilitates the flow of charge carriers (e.g., electrons) from the source / drain region 124e to the source / drain region 124f, and vice versa. In some embodiments, the effective length of the conductive channel 304 is Figure 3B As the effective length of the conductive channel 304 increases, the noise performance of the third readout transistor 120c improves.

[0045] The junction isolation structure 118c has a width w1 defined between the source / drain regions 124e to 124f, wherein the width w1 is, for example, in a range of about 50 nanometers to 500 nanometers. In some embodiments, if the width w1 is less than 50 nanometers, noise in the third readout transistor 120c may make it unusable. In other embodiments, if the width w1 is greater than 500 nanometers, the scaling of the image sensor is limited and the cost associated with forming the third readout transistor 120c may increase. In some embodiments, the readout gate insulator layer 302 directly overlies the conductive channel 304. In such an embodiment, the top view layout of the conductive channel 304 may correspond to the top view layout of the readout gate insulator layer 302, wherein the conductive channel 304 has the same area as the readout gate insulator layer 302.

[0046] Figure 3C Show Figure 3A A portion of the image sensor 300a is shown (eg Figure 3A Cross-sectional views of some alternative embodiments (shown in the dashed box in FIG. ).

[0047] The junction isolation structure 118c extends a distance d1 below the third readout gate electrode 122c to a point that is laterally offset from the sidewall 122csw of the third readout gate electrode 122c. The readout gate insulator layer 302 extends continuously around the perimeter of the junction isolation structure 118c below the third readout gate electrode 122c. In some embodiments, the distance d1 is, for example, in the range of about 20 nanometers to 300 nanometers. In some embodiments, if the distance d1 is 20 nanometers or greater, the noise performance of the third readout transistor 120c may be suitable for use at advanced process nodes. In other embodiments, if the distance d1 is greater than 300 nanometers, the scaling of the image sensor is limited and / or the cost associated with forming the third readout transistor 120c may increase.

[0048] Figure 4 Show according to Figure 1 Layout diagrams of some embodiments of image sensor 400 that are some alternative embodiments to image sensor 100 are shown.

[0049] Image sensor 400 includes first pixel sensor 106 and second pixel sensor 108. Image sensor 400 also includes a second plurality of readout transistors 405a to 405b corresponding to third pixel sensor 402. In some embodiments, third pixel sensor 402 has the same photodetector, transfer transistor, and / or readout transistor layout as first pixel sensor 106 (not shown). However, for ease of illustration, Figure 4 4. A portion of the photodetector, transfer transistor, and readout transistor of the third pixel sensor 402 have been omitted. In some embodiments, the substrate 102 includes any type of semiconductor body (e.g., single crystal silicon / CMOS bulk, silicon-germanium (SiGe), silicon on insulator (SOI), etc.) having a first doping type (e.g., p-type).

[0050] The first pixel sensor 106 includes a first plurality of photodetectors 106a to 106d, a first plurality of transfer transistors 112a to 112d, a first plurality of pickup well contact regions 114a to 114d, and a first plurality of floating diffusion nodes 116a to 116d. The first plurality of photodetectors 106a to 106d may include a second doping type (e.g., n-type) opposite to the first doping type. The first plurality of pickup well contact regions 114a to 114d may include the first doping type (e.g., p-type) at a higher doping concentration than the substrate 102. The first plurality of floating diffusion nodes 116a to 116d may include the second doping type (e.g., n-type) at a higher doping concentration than the substrate 102. The first plurality of transfer transistors 112a to 112d are disposed on / in the substrate 102 and are respectively located on photodetectors of the first plurality of photodetectors 106a to 106d. For example, the first transfer transistor 112a overlies the first photodetector 106a (when viewed in cross-section) and the second transfer transistor 112b overlies the second photodetector 106b.

[0051] In some embodiments, the first plurality of transfer transistors 112a to 112d are respectively configured to form a conductive channel between a corresponding photodetector and a corresponding floating diffusion node so that charge accumulated in the corresponding photodetector (e.g., by absorbing incident radiation) can be transferred to the corresponding floating diffusion node. For example, the first transfer transistor 112a is configured to form a conductive channel between the first photodetector 106a and the first floating diffusion node 116a, wherein the charge accumulated in the first photodetector 106a can be transferred to the first floating diffusion node 116a. In some embodiments, each transfer transistor of the first plurality of transfer transistors 112a to 112d may include a transfer gate electrode 109 having an embedded conductive body 111 extending into the substrate 102. In addition, at least a portion of the transfer gate electrode 109 is respectively separated from the substrate 102 by a gate dielectric layer.

[0052] The second plurality of readout transistors 405a to 405b (e.g., reset transistors, source follower transistors, row selection transistors, etc.) are disposed on the substrate 102. In some embodiments, the second plurality of readout transistors 405a to 405b include readout gate electrodes 406a to 406b and source / drain regions 410, respectively. In some embodiments, the second plurality of readout transistors 405a to 405b may be, for example, metal oxide semiconductor field effect transistors (MOSFETs), respectively. In other embodiments, the second plurality of readout transistors 405a to 405b overlie the photodetectors 106c to 106d of the first plurality of photodetectors 106a to 106d, respectively.

[0053] A second plurality of junction isolation structures 407a-407b are disposed laterally between the second plurality of readout transistors 405a-405b and adjacent transfer gates from the first plurality of transfer transistors 112a-112d. The second plurality of junction isolation structures 407a-407b are configured to increase isolation between source / drain regions 410 of the second plurality of readout transistors 405a-405b. In some embodiments, the second plurality of junction isolation structures 407a-407b and the second plurality of readout transistors 405a-405b are respectively as shown in FIG. Figure 3B or Figure 3C The third readout transistor 120c is configured as shown. In this embodiment, a readout gate insulator layer 302 is provided between the substrate 102 and each readout gate electrode 406a to 406b. In addition, when viewed from a cross-section, the second plurality of junction isolation structures 407a to 407b extend under the corresponding readout gate electrodes 406a to 406b, respectively. Therefore, the effective length (e.g., the length of the conductive channel formed under each readout gate electrode 406a to 406b) can be increased. Figure 3B This improves the noise performance of the second plurality of readout transistors 405a to 405b, thereby reducing noise (eg, flicker noise) in the image sensor 400.

[0054] In addition, if Figure 4 As shown, the first plurality of readout transistors 120a to 120c are each as shown in FIG. Figure 3C The third readout transistor 120c is configured as shown. In this embodiment, the first plurality of readout transistors 120a to 120c respectively include a readout gate insulator layer 302 disposed between the substrate 102 and the corresponding readout gate electrodes 122a to 122c. Therefore, the effective length of the conductive channel formed in the substrate 102 under each readout gate electrode 122a to 122c can be increased, thereby improving the noise performance of the readout transistors 120a to 120c. This further reduces the noise in the image sensor 400.

[0055] In addition, in some embodiments, the first via 130a of the via 130 directly overlies the second pickup well contact region 114b of the first plurality of pickup well contact regions 114a to 114d and / or is electrically coupled to the second pickup well contact region 114b of the first plurality of pickup well contact regions 114a to 114d. The first via 130a may be configured as a substrate contact node or a ground node and / or may be referred to as a ground via or a substrate contact via. In some embodiments, the first via 130a may be electrically coupled to ground, wherein a pixel well region (not shown) disposed below the second pickup well contact region 114b and along a sidewall adjacent to the second photodetector 106b is electrically coupled to ground. In addition, the second via 130b of the via 130 directly overlies the source / drain region 124f of the third readout transistor 120c and / or is electrically coupled to the source / drain region 124f of the third readout transistor 120c. In such an embodiment, the second via 130b is electrically coupled to a power source (e.g., a direct current (DC) power source) so that the second via 130b is configured as a power supply via and / or a power supply node. In some embodiments, the first via 130a is the closest or proximal via to the second via 130b. In other embodiments, the distance between the first via 130a and the second via 130b is less than the distance between the first via 130a and any other via in the plurality of vias 130. This can partially reduce the number of vias 130 and / or conductive wiring disposed on the substrate 102, thereby reducing the time and cost associated with forming the image sensor 400.

[0056] Figure 5 Shown according to line BB' Figure 4 Cross-sectional views 500 of some alternative embodiments of image sensor 400 are shown.

[0057] The substrate 102 has a front side 102f opposite to the back side 102b. The second isolation structure 131 extends from above the front side 102f to a point in the substrate 102 below the front side 102f. The first isolation structure 110 extends from the back side 102b to a point in the substrate 102, wherein the top surface of the first isolation structure 110 directly contacts and / or is aligned with the bottom surface of the second isolation structure 131. In such an embodiment, the first isolation structure 110 and the second isolation structure 131 may form a full-depth deep trench isolation (DTI) structure that extends completely through the substrate 102. This may partially increase the well capacity of the image sensor 100. The third readout transistor 120c extends continuously over a segment 110a of the first isolation structure 110, and the segment 110a of the first isolation structure 110 is laterally located between a second photodetector 106b of the first plurality of photodetectors 106a-106b and a second photodetector 108b of the second plurality of photodetectors 108a-108b. The readout transistor 405b of the second plurality of readout transistors 405a-405b extends continuously over another segment 110b of the first isolation structure 110. The other segment 110b of the first isolation structure 110 is laterally offset from the segment 110a by a non-zero distance. In such an embodiment, the readout transistor 405b of the second plurality of readout transistors 405a-405b extends continuously from over the photodetector 106d of the first pixel sensor 106 to a photodetector (not shown) of the third pixel sensor 402. Thus, in some embodiments, image sensor 400 includes more than one transistor (e.g., readout transistors 405b and 120c) that extend continuously and completely over a segment of first isolation structure 110. In such embodiments, the segment of first isolation structure 110 is sandwiched between two pixel sensors.

[0058] In some embodiments, the anti-reflective layer 502 extends along the back side 102b of the substrate 102. In some embodiments, the anti-reflective layer 502 is configured to reduce the amount of incident radiation reflected by the substrate 102. In other embodiments, the anti-reflective layer 502 may be or may include, for example, an oxide, a high-k dielectric, a nitride, etc. In other embodiments, the anti-reflective layer 502 may include a first layer including an oxide stacked on a second layer including a high-k dielectric, or vice versa.

[0059] A plurality of color filters 504 (e.g., red filters, blue filters, green filters, etc.) directly contact the anti-reflective layer 502. In some embodiments, the color filters 504 are arranged in an array below the anti-reflective layer 502. The color filters 504 are each configured to transmit incident radiation of a specific wavelength. For example, a first color filter (e.g., a red color filter) may transmit light having a wavelength within a first range, while a second color filter (e.g., a blue color filter) may transmit light having a wavelength within a second range different from the first range. In addition, a plurality of microlenses 506 are disposed below the color filters 504. The microlenses 506 are configured to direct incident radiation (e.g., photons) toward an overlying photodetector (e.g., Figure 4 The first plurality of photodetectors 106a to 106d) are shown focused.

[0060] Figure 6 Shown corresponding to Figure 4 A layout diagram of some embodiments of an image sensor 600 that is an alternative embodiment to image sensor 400 is shown.

[0061] The image sensor 600 includes a first pixel sensor 106, a second pixel sensor 108, a third pixel sensor 402, a fourth pixel sensor 602a, a fifth pixel sensor 602b, and a sixth pixel sensor 602c. In some embodiments, the image sensor 600 includes a pixel sensor array, wherein Figure 4 The image sensor 400 is shown disposed adjacent to another image sensor configured as the image sensor 400. In this embodiment, the fourth pixel sensor 602a is configured as Figure 4 The first pixel sensor 106 and the fifth pixel sensor 602b are configured as Figure 4 The second pixel sensor 108 is shown, and the sixth pixel sensor 602c is configured as Figure 4 A third pixel sensor 402 is shown.

[0062] The fourth pixel sensor 602a includes a fourth plurality of photodetectors 604, a fourth plurality of transfer transistors 606, a fourth plurality of floating diffusion nodes 608, a fourth plurality of junction isolation structures 610, source / drain regions 612, and a third plurality of readout transistors 611a to 611c. In some embodiments, the aforementioned regions, devices, and / or structures of the fourth pixel sensor 602a are configured as corresponding regions, devices, and / or structures of the first pixel sensor 106, such as Figure 1 , Figure 2 , FIG. 3A to FIG. 3C , Figure 4 and / or Figure 5The fifth pixel sensor 602b includes a fifth plurality of photodetectors 620, a fifth plurality of transfer transistors 622, and a fifth plurality of floating diffusion nodes 624. In some embodiments, the aforementioned regions, devices, and / or structures of the fifth pixel sensor 602b are configured as corresponding regions, devices, and / or structures of the second pixel sensor 108, such as Figure 1 , Figure 2 , Figure 3A , Figure 4 and / or Figure 5 In addition, the sixth pixel sensor 602c includes a third plurality of readout transistors 630a to 630b, a source / drain region 632, and a plurality of junction isolation structures 634. In some embodiments, the aforementioned regions, devices, and / or structures of the sixth pixel sensor 602c are configured as corresponding regions, devices, and / or structures of the third pixel sensor 402, such as Figure 4 shown and / or described.

[0063] like Figure 6 As shown, the third readout transistor 611c of the third plurality of readout transistors 611a to 611c extends continuously across the first isolation structure 110 and the second isolation structure 131 in the lateral direction from above the photodetector 604 of the fourth pixel sensor 602a to above the photodetector 620 of the fifth pixel sensor 602b. Therefore, the noise performance of the fourth pixel sensor 602a can be improved. In addition, the width 650 of the first isolation structure 110 between the first pixel sensor 106 and the fourth pixel sensor 602a is less than the width 652 of the second isolation structure 131 between the first pixel sensor 106 and the fourth pixel sensor 602a.

[0064] The second pickup well contact region 114b and the fourth pickup well contact region 114d of the first pixel sensor 106 each directly overlie and / or are directly electrically coupled to an underlying pixel well region (not shown). The pixel well region is a doped region of the substrate 102 that includes a first doping type (e.g., p-type) and extends along a sidewall of an adjacent photodetector. For example, the pixel well region is located below the second pickup well contact region 114b and extends along a sidewall of the second photodetector 106b. In some embodiments, a pixel well region including the first doping type is located below each pickup well contact region (e.g., pickup well contact regions 114a to 114d, 129a to 129b) of the pixel sensors 106, 108, 402, 602a to 602d and abuts an adjacent photodetector. The pickup well contact regions 615a-615b of the fourth pixel sensor 602a directly overlie and / or are directly electrically coupled to pixel well regions (not shown) disposed along adjacent photodetectors in the fourth plurality of photodetectors 604. The pickup well contact regions 114b, 114d, 615a-615b are electrically coupled to an overlying first conductive wire 132a through the vias 130. By connecting the pickup well contact regions 114b, 114d, 615a-615b to a single conductive wire (e.g., the first conductive wire 132a), the number of conductive wires 132 disposed over the substrate 102 is reduced, thereby reducing the overall conductive density of the interconnect structure and the cost associated with forming the image sensor 600.

[0065] The second conductive wiring 132b extends over the source / drain regions 124f, 124h of the third readout transistor 120c and is electrically coupled to the source / drain regions 124f, 124h through the underlying via 130. The second conductive wiring 132b extends continuously over the first isolation structure 110 to the source / drain region 612 of the first readout transistor 611a of the fourth pixel sensor 602a. The second conductive wiring 132b is directly electrically coupled to the source / drain region 612 of the first readout transistor 611a. Therefore, the source / drain regions 124f, 124h of the third readout transistor 120c are directly electrically coupled to the source / drain region 612 of the first readout transistor 611a, thereby improving the noise performance of the image sensor 600. Additionally, this may reduce the number of conductive traces 132 and / or vias 130 disposed over substrate 102 , thereby reducing the overall conductive density of the interconnect structures and the costs associated with forming image sensor 600 .

[0066] Figure 7 Shown corresponding to Figure 4 or Figure 6A circuit diagram 700 of some embodiments of a circuit representation of the first pixel sensor 106 is shown.

[0067] Circuit diagram 700 illustrates some embodiments of receiving and processing incident electromagnetic radiation disposed on the first plurality of photodetectors 106a to 106d. Charge collection circuit 701 includes the first plurality of photodetectors 106a to 106d electrically coupled to a first node 712 through the first plurality of transfer transistors 112a to 112d, respectively. Charge collection circuit 701 is configured to transfer / remove charge collected from incident electromagnetic radiation within the first plurality of photodetectors 106a to 106d to the first node 712. For example, the first plurality of transfer transistors 112a to 112d are configured to transfer / remove charge collected from incident electromagnetic radiation within the first plurality of photodetectors 106a to 106d to the first node 712, respectively. For example, the first plurality of transfer transistors 112a to 112d are configured to transfer / remove charge collected from incident electromagnetic radiation within the first plurality of photodetectors 106a to 106d to respective floating diffusion nodes (e.g., Figure 4 The first plurality of floating diffusion nodes 116a to 116d are shown to remove / transfer charge collected from incident electromagnetic radiation within each of the first plurality of photodetectors 106a to 106d. Transfer voltages are applied to TX1 node 702, TX2 node 704, TX3 node 706, and TX4 node 708 to electrically couple the first plurality of photodetectors 106a to 106d to the first plurality of floating diffusion nodes ( Figure 4 The aforementioned nodes are electrically coupled to the transfer gate electrodes ( Figure 4 109). In some embodiments, the first source / drain region of each transfer transistor 112a to 112d is electrically coupled to a ground node 710 (e.g., the ground node 710 is electrically coupled to ground) through a corresponding photodetector 106a to 106d, and the second source / drain region of each transfer transistor 112a to 112d is electrically coupled to a first node 712. In the aforementioned embodiments, the first plurality of transfer transistors 112a to 112d are electrically coupled to each other in parallel. The first node 712 is electrically coupled to the first plurality of floating diffusion nodes ( Figure 4 116a to 116d), a first source / drain region of a first readout transistor 120a (e.g., a reset transistor), and a readout gate electrode of a third readout transistor 120c (e.g., a source follower transistor). In some embodiments, ground node 710 is electrically coupled to a directly overlying and / or directly electrically coupled to Figure 4 or Figure 6 Each via 130 on the first plurality of pickup well contact regions 114a to 114d is shown.

[0068] The precharge circuit 714 includes a first readout transistor 120a (e.g., a reset transistor). The precharge circuit 714 is electrically coupled to an output terminal (e.g., a first node 712) of the charge collection circuit 701. The precharge circuit 714 is configured to set the first node 712 to an initial charge state (e.g., to a first voltage value, such as 5 volts (V)). During operation of the circuit 700, the voltage at the first node 712 may be set to the initial charge state and / or may fluctuate from the initial charge state, and the precharge circuit 714 may be used to set the voltage at the first node 712 back to the initial charge state. In some embodiments, a first source / drain region of the first readout transistor 120a is electrically coupled to the first node 712, and a second source / drain region of the first readout transistor 120a is electrically coupled to a power supply node 718. In some embodiments, the power supply node 718 is electrically coupled to a power supply (e.g., a direct current (DC) power supply) that supplies a voltage Vdd. In other embodiments, a reset gate voltage RSTG is applied to a first readout gate electrode ( Figure 4 As shown in 122a), the voltage Vdd at the power supply node 718 is applied to the first node 712.

[0069] The charge transfer circuit 719 includes a third readout transistor 120c (e.g., a source follower transistor) and a second readout transistor 120b (e.g., a row selection transistor) electrically coupled to each other. An input terminal of the charge transfer circuit 719 is electrically coupled to an output terminal (e.g., a first node 712) of the precharge circuit 714. An output terminal of the charge transfer circuit 719 is electrically coupled to an output node 722 (e.g., Vout or a word line). During operation of the circuit 700, if the charge level at the first node 712 is high enough, the charge transfer circuit 719 is configured to selectively output charge to the output node 722 according to the second readout transistor 120b. In some embodiments, a first source / drain region of the third readout transistor 120c is electrically coupled to a power supply node 718. A second source / drain region of the third readout transistor 120c is electrically coupled to a first source / drain region of the second readout transistor 120b. A second source / drain region of the second readout transistor 120b is electrically coupled to the output node 722. A select gate voltage SELG is applied to the gate electrode of the second readout transistor 120 b . The select gate voltage SELG is configured to control the output of the charge to the output node 722 .

[0070] In some embodiments, Figure 7 As can be seen, the third readout transistor 120c may include two transistors 120c1 to 120c2 electrically coupled to each other in parallel. In this embodiment, this can be achieved because the third readout gate electrode ( Figure 4122c) in the first isolation structure ( Figure 4 110) is shown extending continuously above a section. Figure 4 In the layout diagram shown, the first transistor 120c1 may overlie the second photodetector 106b of the first plurality of photodetectors 106a to 106d, and the second transistor 120c2 may overlie the photodetector ( Figure 4 In addition, the first isolation structure ( Figure 4 110) is located laterally between the source / drain region of the first transistor 120c1 and the source / drain region of the second transistor 120c2. Since the third readout transistor 120c includes two transistors 120c1 to 120c2 electrically coupled to each other in parallel, the third readout gate electrode ( Figure 4 122c) below the substrate ( Figure 4 The effective length of the conductive channel formed in 102) can be increased. This will improve Figure 4 The noise performance of image sensor 400 is shown.

[0071] In addition, the two transistors 120c1 to 120c2 share a gate electrode (eg, a third readout gate electrode ( Figure 4 122c)). This at least omits the conductive wiring and the via hole originally used to electrically couple the two separate gate electrodes together, thereby reducing Figure 4 The total conductive density of the interconnect structures (eg, vias 130 and conductive traces 132) is shown. As the total conductive density of the interconnect structures is reduced, the noise performance of the image sensor 400 is further improved.

[0072] In some embodiments, during operation of the circuit 700, if the charge level within the first plurality of photodetectors 106a to 106d is sufficiently high when the corresponding transfer transistors 112a to 112d are activated, the third readout transistor 120c is activated and the charge is selectively output according to the operation of the second readout transistor 120b for addressing. The first readout transistor 120a may be used to reset (e.g., set to an initial voltage, such as 5 volts) the photodetectors 106a to 106d between exposure cycles to incident radiation.

[0073] Figure 8 Shows the line C-C' according to Figure 6 A cross-sectional view of image sensor 800 of some embodiments of image sensor 600 is shown.

[0074] The image sensor 800 includes an interconnect structure 802 overlying a front side 102f of a substrate 102. The substrate 102 may be, for example, a bulk silicon substrate including a first doping type (e.g., p-type). The image sensor 800 also includes a readout transistor 120 disposed between a first transfer transistor 112 and a second transfer transistor 126. The first transfer transistor 112 overlies a first photodetector 801, and the second transfer transistor 126 overlies a second photodetector 803. The first photodetector 801 and the second photodetector 803 each include a second doping type (e.g., n-type). In some embodiments, the image sensor 800 includes a plurality of pixel sensors arranged in an array of columns and rows. The pixel sensors each include a transfer transistor, a readout transistor, and a photodetector. For example, the first transfer transistor 112, the first photodetector 801, and the readout transistor 120 may each be part of a first pixel sensor, and the second transfer transistor 126 and the second photodetector 803 may each be part of a second pixel sensor. Thus, readout transistor 120 extends continuously over first isolation structure 110 from over the first pixel sensor to over the second pixel sensor.

[0075] In some embodiments, the readout transistor 120 may be configured as Figure 1 , Figure 2 , FIG. 3A to FIG. 3C , Figure 4 , Figure 5 or Figure 6 The third readout transistor 120c shown and / or described is configured. The first photodetector 801 may be configured as Figure 1 , Figure 2 , Figure 3A , Figure 4 , Figure 5 or Figure 6 The second photodetector 106b of the first pixel sensor 106 shown and / or described is configured as follows. Figure 1 , Figure 2 , Figure 3A , Figure 4 , Figure 5 or Figure 6 The second photodetector 108b of the second pixel sensor 108 is shown and / or described as being configured.

[0076] The interconnect structure 802 includes an interconnect dielectric structure 824, a plurality of vias 130, a plurality of conductive wires 132, and a conductive bonding pad 820. The interconnect structure 802 is configured to electrically couple doped regions, devices, and / or structures of the substrate 102 together. In other embodiments, the interconnect structure 802 may be bonded to and / or electrically coupled to another integrated circuit (IC) die 830 (e.g., an integrated circuit (IC) die or a carrier substrate including one or more semiconductor devices). In some embodiments, the other integrated circuit die 830 may be, for example, an application-specific integrated circuit (ASIC). In some embodiments, the other integrated circuit die 830 may include, for example, a transistor, a power MOSFET device, a dynamic random-access memory (DRAM) device, a combination of the foregoing devices, and the like.

[0077] The second isolation structure 131 extends into the front side 102f of the substrate 102 and contacts the first isolation structure 110. The first isolation structure 110 includes a first isolation layer 110c and a second isolation layer 110d. The first isolation layer 110c extends from the back side 102b of the substrate 102 to the second isolation structure 131 and may be as shown in FIG. Figure 5 The anti-reflection layer 502 is configured. The first isolation structure 110 and the second isolation structure 131 are configured to electrically isolate adjacent semiconductor devices disposed in / on the substrate 102 from each other. For example, the first photodetector 801 is electrically isolated from the second photodetector 803 by the first isolation structure 110 and the second isolation structure 131. In some embodiments, the first isolation structure 110 and the second isolation structure 131 are referred to as full-depth deep trench isolation (DTI) structures. A plurality of color filters 504 are disposed along the first isolation structure 110, and a plurality of micro lenses 506 are disposed along the plurality of color filters 504.

[0078] In some embodiments, an isolation region 808 is disposed along the upper surface of the first photodetector 801 and the second photodetector 803. The isolation region 808 may be a doped region of the substrate 102, which is configured to increase the electrical isolation between the first photodetector 801 and the second photodetector 803 and the overlying semiconductor device and / or doped region (e.g., the readout transistor well region 204). The isolation region 808 includes a first doping type (p-type). The transfer transistor well region 804 is disposed between the first transfer transistor 112 and the second transfer transistor 126 and the first isolation structure 110 and the second isolation structure 131, respectively. The transfer transistor well region 804 includes a first doping type (e.g., p-type).

[0079] The first transfer transistor 112 and the second transfer transistor 126 include a transfer gate electrode 109, a gate dielectric layer 202, a lower gate implant region 806, and a sidewall spacer structure 818, respectively. The lower gate implant region 806 has a first doping type (e.g., p-type) and is configured to improve the interface between the gate dielectric layer 202 and the substrate 102, thereby reducing dark current in the first transfer transistor 112 and the second transfer transistor 126. This can partially improve the noise performance of the image sensor 800. In addition, a first floating diffusion node 116 and a second floating diffusion node 128 are respectively disposed along the sidewalls of the first transfer transistor 112 and the second transfer transistor 126. The first floating diffusion node 116 and the second floating diffusion node 128 include a second doping type (e.g., n-type), respectively.

[0080] The readout transistor 120 is laterally disposed between the first transfer transistor 112 and the second transfer transistor 126. The readout transistor 120 includes a readout gate electrode 122, a sidewall spacer structure 818, a gate dielectric layer 202, source / drain regions 812, 814, a lightly doped region 816, and a readout transistor well region 204. In some embodiments, the readout transistor 120 is configured to facilitate reading out electrical signals from the first photodetector 801. In such embodiments, the readout transistor 120 may not perform reading out electrical signals from the second photodetector 803 so that the first photodetector 801 is part of a first pixel sensor, and the second photodetector 803 is part of a second pixel sensor separate from the first pixel sensor.

[0081] Fig. 9 Show according to Figure 8 Cross-sectional views of image sensors 900 are shown that illustrate some alternative embodiments of image sensor 800 .

[0082] The first isolation layer 110c of the first isolation structure 110 may, for example, have a non-planar pattern (e.g., a jig-saw pattern) configured to increase a light receiving surface area of ​​incident radiation disposed on the first photodetector 801 and the second photodetector 803. This partially improves the sensitivity and / or quantum efficiency (QE) of the image sensor 900.

[0083] In addition, if Fig. 9As shown, the readout gate electrode 122 and / or the transfer gate electrode 109 may each include a plurality of gate electrode layers 902, 904, 906. In such an embodiment, the aforementioned electrodes may be configured as high-k metal gates, wherein the gate dielectric layer 202 includes a high-k dielectric material. In addition, the gate electrode layers 902, 904, 906 may each be or may include, for example, titanium nitride, tantalum nitride, titanium, tantalum, tungsten, aluminum, etc.

[0084] Figures 10 to 17 Cross-sectional views 1000 to 1700 illustrate some embodiments of methods of forming an image sensor according to various aspects of the present disclosure. Figures 10 to 17 The cross-sectional views 1000 to 1700 shown are described with reference to the method, however, it should be understood that Figures 10 to 17 The structures shown are not limited to the described methods but can be independent of the described methods. Figures 10 to 17 It is described as a series of actions, however, it should be understood that these actions are not limited to other embodiments in which the order of the actions can be changed, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted in whole or in part. In some embodiments, Figures 10 to 17 It can be used, for example, to form Figure 8 The image sensor 800 is shown. In this embodiment, Figures 10 to 17 The layout of regions, structures and / or devices shown may correspond to Figure 6 The layout according to line CC' is shown.

[0085] like Fig.10As shown in the cross-sectional view 1000 shown, a substrate 102 is provided and a second isolation structure 131 (in some embodiments, referred to as a shallow trench isolation (STI) structure) is formed on the front side 102f of the substrate 102. In some embodiments, the substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, before forming the second isolation structure 131, a first implantation process is performed to dope the substrate 102 with a first doping type (e.g., p-type). In such an embodiment, the substrate 102 may, for example, have a doping concentration in the range of about 1013 atoms / cm3 to 1016 atoms / cm3. In some embodiments, the process for forming the second isolation structure 131 may include: 1) selectively etching the substrate 102 to form a trench in the substrate 102, the trench extending from the front side 102f into the substrate 102; and 2) filling the trench with a dielectric material (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.). In some embodiments, the second isolation structure 131 may be, for example, or may include silicon dioxide, nitride, or another suitable dielectric material. In other embodiments, the second isolation structure 131 has a thickness t1 in the range of about 0.05 microns to 0.40 microns.

[0086] like Fig.11 As shown in the cross-sectional view 1100 shown, a first photodetector 801 and a second photodetector 803 are formed in the substrate 102. The first photodetector 801 and the second photodetector 803 are each a region of the substrate 102 including a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). In some embodiments, the first photodetector 801 and the second photodetector 803 may be formed by a selective ion implantation process that utilizes a mask layer (not shown) on the front side 102f of the substrate 102 to selectively implant ions into the substrate 102. In some embodiments, the first photodetector 801 and the second photodetector 803 may each have a doping concentration in the range of approximately 1015 atoms / cm3 to 1018 atoms / cm3. In addition, the first photodetector 801 and the second photodetector 803 are each vertically offset from the second isolation structure 131 by a non-zero distance in a direction away from the front side 102f of the substrate 102. In some embodiments, referring to Figure 6 , the first photodetector 801 may correspond to Figure 6The second photodetector 106b of the first pixel sensor 106 is shown, and the second photodetector 803 may correspond to Figure 6 The second photodetector 108 b of the second pixel sensor 108 is shown.

[0087] In addition, Fig.11 As shown, one or more doped regions are formed in the substrate 102. For example, an isolation region 808 is formed above the first photodetector 801 and the second photodetector 803. In some embodiments, the isolation region 808 includes a first doping type (e.g., p-type) with a doping concentration in a range of approximately 1017 atoms / cm3 to 1019 atoms / cm3. In other embodiments, during operation of the image sensor, a pn junction is formed between the isolation region 808 and the first photodetector 801 and the second photodetector 803 and a depletion region is thereby formed. In such an embodiment, at least a portion of the isolation region 808 is not depleted (e.g., a region vertically offset from the first photodetector 801 or the second photodetector 803), wherein the isolation region 808 is biased by a substrate contact via (not shown) to increase the pn junction capacitance of the image sensor. In some embodiments, a portion of the isolation region 808 is not depleted due to the application of a bias. In some embodiments, refer to Figure 6 , the isolation region 808 can be biased through the conductive via 130 overlying the pickup well contact region 114b of the first pixel sensor 106. In such an embodiment, the isolation region 808 is electrically coupled to the pickup well contact region 114b. In addition, transfer transistor well regions 804 are formed along the upper surfaces and sidewalls of the first photodetector 801 and the second photodetector 803, respectively. The readout transistor well region 204 is formed vertically above the first photodetector 801 and the second photodetector 803 between the transfer transistor well regions 804. In some embodiments, the transfer transistor well region 804 and / or the readout transistor well region 204 can each include a first doping type (e.g., p-type) in the range of about 1016 atoms / cm3 to 1018 atoms / cm3. In other embodiments, the transfer transistor well region 804 and / or the readout transistor well region 204 can each have a lower doping concentration than the isolation region 808. In some embodiments, the formation of the aforementioned one or more doped regions may include performing at least one selective ion implantation process that selectively implants ions into the substrate 102 using a mask layer (not shown) on the front side 102 f of the substrate 102 .

[0088] like Fig.12As shown in the cross-sectional view 1200 shown, the substrate 102 is patterned to form a vertical gate electrode opening 1202. In some embodiments, the patterning process includes: 1) forming a mask layer (not shown) over the front side 102f of the substrate 102; 2) exposing the unmasked area of ​​the substrate 102 to one or more etchants to define the vertical gate electrode opening 1202 and the upper surface 102us of the substrate 102; and 3) performing a removal process to remove the mask layer. The upper surface 102us of the substrate 102 is vertically offset from the front side 102f of the substrate 102 by a distance d2. In some embodiments, the distance d2 is in the range of about 0.1 microns to 0.6 microns. After forming the vertical gate electrode opening 1202, a lower gate implant region 806 having a first doping type (e.g., p-type) is formed in the substrate 102. In some embodiments, the lower gate implant region 806 has a doping concentration in the range of about 5×1016 atoms / cm3 to 5×1018 atoms / cm3. In other embodiments, the lower gate implant region 806 is formed by performing a selective ion implantation process based on a mask layer (not shown) disposed on the front side 102 f of the substrate 102 .

[0089] like Fig.13 As shown in the cross-sectional view 1300, a gate dielectric layer 202 is formed on the substrate 102. The gate dielectric layer 202 at least partially opens the vertical gate electrode ( Fig.12 1202) is lined and overlies at least a portion of the front side 102f of the substrate 102 directly above the readout transistor well region 204. In addition, in the vertical gate electrode opening ( Fig.121202), and a readout gate electrode 122 is formed on the readout transistor well region 204. In some embodiments, the above layers and / or structures are formed by the following steps: 1) depositing a gate dielectric film on the substrate 102; 2) then depositing a gate electrode layer of the gate dielectric film; and 3) patterning the gate dielectric film and the gate electrode layer according to a mask layer (not shown) to define the gate dielectric layer 202, the transfer gate electrode 109, and the readout gate electrode 122. In some embodiments, the gate dielectric film and / or the gate electrode layer can be deposited and / or grown, for example, by CVD, PVD, ALD, thermal oxidation, sputtering, another suitable deposition process, or a combination of the foregoing methods. In some embodiments, the gate dielectric layer 202 can be, for example, or can include silicon oxide, a high dielectric constant dielectric material, etc. In other embodiments, the transfer gate electrode 109 and / or the readout gate electrode 122 can be, for example, or can include metal (e.g., aluminum, titanium, etc.), polysilicon, or another suitable conductive material, respectively. Furthermore, after forming the transfer gate electrode 109 and / or the readout gate electrode 122, a selective ion implantation process may be performed to form a lightly doped region 816 in the readout transistor well region 204 on the opposite side of the readout gate electrode 122. The lightly doped region 816 may, for example, include a second doping type (e.g., n-type) having a lower doping concentration than the isolation region 808.

[0090] like Fig.14 As shown in the cross-sectional view 1400, a sidewall spacer structure 818 is formed on the front side 102f of the substrate 102 and along the sidewalls of the transfer gate electrode 109 and the sidewalls of the readout gate electrode 122. In addition, a first floating diffusion node 116, a second floating diffusion node 128, a first junction isolation structure 810a, a second junction isolation structure 810b, and source / drain regions 812, 814 are formed on the front side 102f of the substrate 102. This defines a first transfer transistor 112 above the first photodetector 801, a second transfer transistor 126 above the second photodetector 803, and a readout transistor 120 above the first photodetector 801 and the second photodetector 803. The first floating diffusion node 116 and the second floating diffusion node 128 and the source / drain regions 812, 814 each have a second doping type (e.g., n-type) with a higher doping concentration than the lightly doped region 816. The first junction isolation structure 810 a and the second junction isolation structure 810 b each have a first doping type (eg, p-type) having a doping concentration in a range of approximately 10 17 atoms / cm 3 to 10 19 atoms / cm 3 .

[0091] In some embodiments, the lightly doped region 816 and the source / drain regions 812, 814 may each include a first doping type (e.g., p-type). In such embodiments, the readout transistor well region 204 and the first and second junction isolation structures 810a, 810b may each include a second doping type (e.g., n-type).

[0092] In some embodiments, reference Figure 6 , the first junction isolation structure 810a may correspond to the junction isolation structure 118c disposed along the first sidewall 122csw1 of the third readout transistor 120c. In addition, the second junction isolation structure 810b may correspond to the junction isolation structure 118d disposed along the second sidewall 122csw2 of the third readout transistor 120c. In such an embodiment, the source / drain regions 124e to 124h may be formed simultaneously with the source / drain region 812. In addition, the first junction isolation structure 810a and the second junction isolation structure 810b may be formed as shown in FIG. Figure 3B The junction isolation structure 118c shown or Figure 3C The junction isolation structures shown are configured in such a way that each is formed.

[0093] In some embodiments, the sidewall spacer structure 818 may be formed by depositing a spacer layer (e.g., by CVD, PVD, ALD, etc.) over the front side 102f of the substrate 102. The spacer layer is then etched to form the sidewall spacer structure 818 around the sidewalls of the transfer gate electrode 109 and around the sidewalls of the readout gate electrode 122. In some embodiments, the spacer layer may be, for example, or may include, nitride, oxide, or some other suitable dielectric material. In some embodiments, the first floating diffusion node 116 and the second floating diffusion node 128, the source / drain regions 812, 814, and the first junction isolation structure 810a and the second junction isolation structure 810b may be formed by at least one selective ion implantation process, respectively, which selective ion implantation process utilizes a mask layer (not shown) on the front side 102f of the substrate 102 to selectively implant ions (e.g., n-type (e.g., phosphorus) or p-type (e.g., boron)) into the substrate 102. In some other embodiments, an annealing process (eg, laser annealing, rapid thermal annealing (RTA), etc.) is performed after the at least one selective ion implantation process to activate the selectively implanted dopants.

[0094] In some embodiments, reference Figure 6 , the readout transistor 120 corresponds to the third readout transistor 120c of the first pixel sensor 106. In this embodiment, the readout transistor 120 extends continuously in the lateral direction between the first pixel sensor 106 and the second pixel sensor 108. In addition, referring to Figure 6, the first transfer transistor 112 corresponds to the second transfer transistor 112 b of the first pixel sensor 106 , and the second transfer transistor 126 corresponds to the second transfer transistor 126 b of the second pixel sensor 108 .

[0095] like Fig.15 As shown in the cross-sectional view 1500, an interconnect structure 802 is formed on the front side 102f of the substrate 102. The interconnect structure 802 includes an interconnect dielectric structure 824, a plurality of vias 130, a plurality of conductive wires 132, and a conductive bonding pad 820. In some embodiments, the interconnect dielectric structure 824 may be formed to have a substantially flat upper surface and may include one or more dielectric layers including, for example, oxides, nitrides, low-k dielectric materials, etc. In some embodiments, the interconnect dielectric structure 824 may be formed by CVD, PVD, ALD, etc. In other embodiments, a planarization process (e.g., a chemical-mechanical planarization (CMP) process) may be performed on the interconnect dielectric structure 824 to form a substantially flat upper surface.

[0096] In some embodiments, the plurality of vias 130 are formed in the interconnect dielectric structure 824. In addition, the vias 130 extend from the conductive wiring 132 to the doped regions (e.g., source / drain regions 812, 814) and / or transistor gate electrodes (e.g., transfer gate electrode 109, readout gate electrode 122, etc.) of the substrate 102. In addition, the upper surface of the conductive bonding pad 820 is aligned with the substantially flat upper surface of the interconnect dielectric structure 824. The conductive bonding pad 820 is electrically coupled to the vias 130 and the conductive wiring 132 (not shown). In some embodiments, the process for forming the vias 130 includes depositing a lower portion of the interconnect dielectric structure 824, followed by etching into the lower portion to form a through-hole opening corresponding to the vias 130. In other embodiments, the via openings may be filled by depositing or growing a conductive material (eg, tungsten) covering the interconnect dielectric structure 824 filling the contact openings and then performing a planarization process (eg, CMP) on the via 130 and the interconnect dielectric structure 824 .

[0097] In addition, Fig.15As shown, the conductive wire 132 and / or the conductive bonding pad 820 are formed in the interconnect dielectric structure 824. In some embodiments, the process for forming the conductive wire 132 and / or the conductive bonding pad 820 includes: 1) depositing the upper portion of the interconnect dielectric structure 824; 2) forming a mask layer (not shown) over the upper portion; 3) performing an etching process in the upper portion to form an opening corresponding to the conductive wire 132 and / or the conductive bonding pad 820; 4) filling the opening with a conductive material (e.g., copper, aluminum, etc.); and 5) then performing a planarization process (e.g., CMP) on the conductive material. In addition, the substrate 102 has an initial thickness ti defined from the front side 102f of the substrate 102 to the back side 102b of the substrate 102. The front side 102f is opposite to the back side 102b. In some embodiments, the via 130, the conductive wire 132 and / or the conductive bonding pad 820 may be, for example, respectively or may include tungsten, aluminum, copper, a combination of the foregoing materials, or another suitable conductive material. In other embodiments, the conductive bonding pad 820 and the interconnect dielectric structure 824 may be bonded to another integrated circuit die 830 (e.g., an integrated circuit (IC) die or a carrier substrate including one or more semiconductor devices) (e.g., by a hybrid bonding process). In some embodiments, the other integrated circuit die 830 may be, for example, an application specific integrated circuit (ASIC).

[0098] like Fig.16 As shown in the cross-sectional view 1600, Fig.15 The structure shown is flipped (eg, rotated 180 degrees) and the substrate 102 is increased from an initial thickness ( Fig.15 ti) is thinned to a thickness ts. For example, Fig.15 The initial thickness ti is greater than Fig.16 The thickness ts of the substrate 102 is shown. In some embodiments, the thinning process can be performed, for example, by a planarization process, an etch-back process, a grinding process, a combination of the above processes, etc. In other embodiments, the planarization process can be a CMP process. In some embodiments, the thickness ts is in the range of about 2 microns to 10 microns.

[0099] In addition, Fig.16As shown, a first isolation structure 110 (in some embodiments, referred to as a deep trench isolation (DTI) structure) is formed in the substrate 102. The first isolation structure 110 extends from the back side 102b into the substrate 102 to a point below the back side 102b. In some embodiments, the first isolation structure 110 extends from the back side 102b to the top surface of the second isolation structure 131. In other embodiments, the first isolation structure 110 extends from the back side 102b of the substrate 102 to the front side 102f of the substrate 102 (not shown). The first isolation structure 110 includes a first isolation layer 110c and a second isolation layer 110d. The first isolation layer 110c extends from the back side 102b of the substrate 102 to the second isolation structure 131 and may be as shown in FIG. Figure 5 The anti-reflective layer 502 is configured. In some embodiments, the process for forming the first isolation structure 110 includes: 1) selectively etching the substrate 102 to form a trench in the substrate 102, the trench extending from the back side 102b into the substrate 102; 2) depositing a first isolation layer 110c on the substrate 102 (e.g., by CVD, PVD, ALD, etc.), thereby filling a portion of the trench; and 3) filling the remaining portion of the trench with a second isolation layer 110d (e.g., by CVD, PVD, ALD, sputtering, etc.). In some embodiments, the first isolation layer 110c may be, for example, or may include a high-k dielectric material, an oxide (e.g., silicon dioxide), a silicon nitride (e.g., Si3N4), a combination of the foregoing materials, etc. In some embodiments, the second isolation layer 110d may be, for example, or may include a high-k dielectric material, an oxide (silicon dioxide), a silicon nitride (e.g., Si3N4), polysilicon, tungsten, aluminum, copper, etc. In other embodiments, the second isolation layer 110d may include a conductive segment surrounded by a dielectric layer, such as a conductive pillar (e.g., copper) lined by an insulating dielectric layer (e.g., a high-k dielectric material) (not shown). In some embodiments, the readout gate electrode 122 extends laterally across the entire width w2 of the segment 110a of the first isolation structure 110.

[0100] like Fig.17As shown in the cross-sectional view 1700 shown, a plurality of color filters 504 are formed on the first isolation structure 110. The color filter 504 is formed of a material capable of transmitting incident radiation (e.g., light) having a specific wavelength range, while blocking incident wavelengths having another wavelength outside the specific range. In other embodiments, the color filter 504 may be formed by CVD, PVD, ALD, etc., and / or may be flattened (e.g., by CMP) after formation. In addition, a plurality of microlenses 506 are formed on the color filter 504. The plurality of microlenses 506 may be formed by depositing a lens material on the color filter 504 (e.g., by a spin coating method or a deposition process). A lens template (not shown) having a curved upper surface is patterned above the lens material. The microlenses 506 are then formed by selectively etching the lens material according to the lens template.

[0101] Fig.18 A method 1800 of forming an image sensor according to the present disclosure is shown. Although method 1800 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in a different order than shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may also be included.

[0102] At act 1802, a shallow trench isolation (STI) structure is formed on a front side of a substrate. Fig.10 Cross-sectional view 1000 corresponding to some embodiments of act 1802 is shown.

[0103] At act 1804, a first photodetector and a second photodetector are formed in a substrate. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 1804 is shown.

[0104] At act 1806, a first patterning process is performed on the substrate, defining vertical gate electrode openings in the substrate above the first photodetector and the second photodetector, respectively. Fig.12 Cross-sectional view 1200 of some embodiments corresponding to act 1806 is shown.

[0105] A gate dielectric layer is formed over the substrate at act 1808. The gate dielectric layer lines the vertical gate electrode opening, and segments of the gate dielectric layer extend over the first photodetector and the second photodetector. Fig.13 Cross-sectional view 1300 corresponding to some embodiments of act 1808 is shown.

[0106] At act 1810, a transfer gate electrode is formed in the vertical gate electrode opening. Additionally, a readout gate electrode is formed over the segment of the gate dielectric layer that extends over the first photodetector and the second photodetector. Fig.13 Cross-sectional view 1300 corresponding to some embodiments of act 1810 is shown.

[0107] At act 1812, source / drain regions are formed on opposite sides of the readout gate electrode. Additionally, a floating diffusion node is formed adjacent to the transfer gate electrode. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 1812 is shown.

[0108] At activity 1814, an interconnect structure is formed over the readout gate electrode and the transfer gate electrode. Fig.15 Cross-sectional view 1500 corresponding to some embodiments of act 1814 is shown.

[0109] At act 1816, a deep trench isolation (DTI) structure is formed in the back side of the substrate, where the back side is opposite the front side. The DTI structure contacts the STI structure, and the readout gate electrode extends continuously across a segment of the DTI structure. Fig.16 Cross-sectional view 1600 corresponding to some embodiments of act 1816 is shown.

[0110] At act 1818, a plurality of color filters are formed on the DTI structure, and a plurality of microlenses are formed on the color filters. Fig.17 Cross-sectional view 1700 corresponding to some embodiments of act 1818 is shown.

[0111] Thus, in some embodiments, the present disclosure relates to an image sensor including an array of pixel sensors, each pixel sensor including a plurality of photodetectors. A DTI structure extends continuously around each photodetector. A readout transistor extends continuously laterally over the DTI structure and overlies a first pixel sensor and a second pixel sensor.

[0112] In some embodiments, the present application provides an image sensor, the image sensor comprising: a first photodetector disposed in a semiconductor substrate; a second photodetector disposed in the semiconductor substrate; an isolation structure extending from a front side surface of the semiconductor substrate to a back side surface of the semiconductor substrate, wherein the front side surface is opposite to the back side surface, and wherein the isolation structure is laterally located between the first photodetector and the second photodetector; and a readout transistor disposed on the front side surface of the semiconductor substrate, wherein a first side of the readout transistor overlies the first photodetector and a second side of the readout transistor overlies the second photodetector, wherein the first side is opposite to the second side, and wherein the readout transistor extends continuously over the isolation structure. In one embodiment of the present invention, the above-mentioned image sensor, wherein the readout transistor comprises: a readout gate electrode, wherein the readout gate electrode extends continuously from above the first photodetector to above the second photodetector. A first source / drain region is disposed along a first sidewall of the readout gate electrode. And a second source / drain region is disposed along the first sidewall of the readout gate electrode, wherein the first sidewall overlies the first photodetector. In one embodiment of the present invention, the above-mentioned image sensor further includes: a junction isolation structure located in the semiconductor substrate, located between the first source / drain region and the second source / drain region in the lateral direction and adjacent to the first source / drain region and the second source / drain region, wherein the junction isolation structure has a doping type opposite to that of the first source / drain region and the second source / drain region. In one embodiment of the present invention, the above-mentioned image sensor, wherein the junction isolation structure has a sidewall located below the readout gate electrode, and wherein the sidewall of the junction isolation structure is arranged to be a non-zero distance from the first sidewall of the readout gate electrode in the direction toward the second photodetector. In one embodiment of the present invention, the above-mentioned image sensor further includes: a floating diffusion node arranged in the semiconductor substrate and arranged above the first photodetector. And a first transfer transistor, adjacent to the floating diffusion node in the lateral direction, wherein the top surface of the first transfer transistor is flush with the top surface of the readout transistor, wherein the first transfer transistor includes a first transfer gate electrode, and wherein two or more planar sidewalls of the first transfer gate electrode face the direction toward the floating diffusion node respectively. In one embodiment of the present invention, the above-mentioned image sensor further includes: a second transfer transistor, which is arranged above the second photodetector.and wherein the readout transistor is laterally disposed between the first transfer transistor and the second transfer transistor, wherein a first junction isolation structure extends along the first side of the readout transistor and is laterally disposed between the readout transistor and the first transfer transistor, and wherein a second junction isolation structure extends along the second side of the readout transistor and is laterally disposed between the readout transistor and the second transfer transistor. In one embodiment of the present invention, the above-mentioned image sensor further includes: a third photodetector adjacent to the first photodetector and diagonally opposite to the second photodetector. And a reset transistor disposed on the semiconductor substrate and overlying the third photodetector, wherein the first sidewall of the reset transistor is laterally aligned with the first sidewall of the readout transistor located on the first side of the readout transistor. In one embodiment of the present invention, the above-mentioned image sensor further includes: a fourth photodetector adjacent to the second photodetector and the third photodetector and diagonally opposite to the first photodetector. A selection transistor disposed on the semiconductor substrate and overlying the fourth photodetector, wherein the first sidewall of the selection transistor is laterally aligned with the second sidewall of the readout transistor located on the second side of the readout transistor. and wherein the second sidewall of the reset transistor is opposite to the first sidewall of the reset transistor, and the second sidewall of the selection transistor is opposite to the first sidewall of the selection transistor, and wherein the isolation structure is located below the second sidewall of the selection transistor and the second sidewall of the reset transistor. In one embodiment of the present invention, the above-mentioned image sensor further includes: a first selection source / drain region and a second selection source / drain region, arranged along the first sidewall of the selection transistor, wherein a selection junction isolation structure is arranged between the first selection source / drain region and the second selection source / drain region. And a first reset source / drain region and a second reset source / drain region, arranged along the first sidewall of the reset transistor, wherein a reset junction isolation structure is arranged between the first reset source / drain region and the second reset source / drain region. In one embodiment of the present invention, the above-mentioned image sensor, wherein the readout transistor has opposite sidewalls extending between the first side and the second side of the readout transistor, and wherein the opposite sidewalls are spaced apart laterally between the opposite inner sidewalls of the isolation structure.

[0113] In some embodiments, the present application provides an image sensor, the image sensor comprising: a first pixel sensor and a second pixel sensor, each comprising a plurality of photodetectors, a plurality of transfer transistors, and a floating diffusion node (FDN), wherein the plurality of photodetectors are disposed in a semiconductor substrate, and wherein the plurality of transfer transistors are disposed on a front surface of the semiconductor substrate and selectively electrically couple the plurality of photodetectors to the FDN; an isolation structure disposed in the semiconductor substrate, wherein the isolation structure continuously surrounds each photodetector in the first pixel sensor and each photodetector in the second pixel sensor, and wherein the isolation structure completely extends through the semiconductor substrate; a source follower transistor overlying the first pixel sensor and gated by the FDN of the first pixel sensor; and a row selection transistor overlying the second pixel sensor and having a source / drain region electrically coupled to a source / drain region of the source follower transistor. In one embodiment of the present invention, the above-mentioned image sensor, wherein the source follower transistor continuously extends from a first photodetector in the first pixel sensor to a second photodetector in the second pixel sensor, and wherein the source follower transistor continuously extends over a segment of the isolation structure disposed between the first photodetector and the second photodetector. In one embodiment of the present invention, the image sensor described above, wherein the isolation structure includes a shallow trench isolation structure and a deep trench isolation structure, wherein the shallow trench isolation structure extends from the front side surface of the semiconductor substrate to a point below the front side surface, wherein the deep trench isolation structure extends from the back side surface of the semiconductor substrate to the point, and wherein the front side surface is opposite to the back side surface. In one embodiment of the present invention, the image sensor described above, wherein the first pixel sensor includes a first pixel well and a second pixel well, and wherein the image sensor further includes: a third pixel sensor adjacent to the first pixel sensor and including a third pixel well and a fourth pixel well, wherein the third pixel well is opposite to the second pixel well along a diagonal line and the fourth pixel well is opposite to the first pixel well along a diagonal line. And an H-shaped wiring having four ends, wherein the four ends are respectively overlaid on the first pixel well, the second pixel well, the third pixel well and the fourth pixel well and are respectively electrically coupled to the first pixel well, the second pixel well, the third pixel well and the fourth pixel well. In one embodiment of the present invention, the image sensor described above, further includes: a reset transistor disposed on the third pixel sensor, wherein the third pixel sensor is adjacent to the first pixel sensor.and a single conductive wiring extending laterally across the isolation structure from a first end of the single conductive wiring to a second end of the single conductive wiring, wherein the first end overlies the source / drain region of the source follower transistor and the second end overlies the source / drain region of the reset transistor. In one embodiment of the present invention, the above-mentioned image sensor further includes: a pickup well contact region having the same doping type as the pixel well region disposed along the sidewall of the photodetector in the first pixel sensor and directly located on the pixel well region. A substrate contact via directly electrically coupled to the pickup well contact region. And a power supply via directly electrically coupled to the source / drain region of the source follower transistor, wherein the distance between the substrate contact via and the power supply via is less than the distance from the power supply via to any other via in the image sensor. In one embodiment of the present invention, the above-mentioned image sensor, wherein the source follower transistor includes: a readout gate electrode disposed on the front side surface of the semiconductor substrate. A first source / drain region and a second source / drain region are disposed along a first side wall of the readout gate electrode, wherein a first junction isolation structure extends along the first side wall and is laterally disposed between the first source / drain region and the second source / drain region. And an insulator layer is disposed between the readout gate electrode and the semiconductor substrate, wherein the insulator layer extends along one side of the first junction isolation structure.

[0114] In some embodiments, the present application provides a method for forming an image sensor, the method comprising: forming a shallow trench isolation (STI) structure on a front side surface of a semiconductor substrate; forming a first photodetector and a second photodetector in the semiconductor substrate, wherein the first photodetector and the second photodetector are laterally separated by the STI structure; forming a readout transistor on the front side surface, wherein a first sidewall of the readout transistor overlies the first photodetector and a second sidewall of the readout transistor overlies the second photodetector, wherein the first sidewall is opposite to the second sidewall, and wherein the readout transistor extends continuously above the upper surface of the STI structure; forming a first source / drain region along the first sidewall of the readout transistor; forming a first junction isolation structure along the first sidewall of the readout transistor, wherein the first junction isolation structure is laterally located between the first source / drain regions; and forming a deep trench isolation (DTI) structure on the back side surface of the semiconductor substrate, wherein the DTI structure extends from the back side surface to the STI structure. In one embodiment of the present invention, the above method further comprises: forming a second source / drain region along the second sidewall of the readout transistor. and forming a second junction isolation structure along the second sidewall of the readout transistor, wherein the second junction isolation structure is laterally located between the second source / drain regions. In one embodiment of the present invention, the method further includes: forming a first transfer transistor and a second transfer transistor simultaneously with the readout transistor, wherein a top surface of the first transfer transistor and a top surface of the second transfer transistor are flush with a top surface of the readout transistor, and wherein the first transfer transistor overlies the first photodetector and the second transfer transistor overlies the second photodetector.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0116] [Explanation of Symbols]

[0117] 100, 300a, 400, 600, 800, 900: Image sensors

[0118] 102: Substrate

[0119] 102b: Rear

[0120] 102f: front side

[0121] 102us: upper surface

[0122] 103a, 103b: first plurality of active regions

[0123] 104a, 104b: second plurality of active regions

[0124] 106: First pixel sensor

[0125] 106a, 106b, 106c, 106d: first plurality of photodetectors

[0126] 108: Second pixel sensor

[0127] 108a, 108b: a second plurality of photodetectors

[0128] 109: Transfer gate electrode

[0129] 110: First isolation structure

[0130] 110a, 110b: Segment

[0131] 110c: first isolation layer

[0132] 110d: Second isolation layer

[0133] 111: Embedded conductive body

[0134] 112: First transfer transistor

[0135] 112a, 112b, 112c, 112d: first plurality of transfer transistors

[0136] 114a, 114b, 114c, 114d: first plurality of pickup well contact regions

[0137] 116: First floating diffusion node

[0138] 116a, 116b, 116c, 116d: first plurality of floating diffusion nodes

[0139] 118a, 118b, 118c, 118d: first plurality of junction isolation structures

[0140] 120: Readout transistor

[0141] 120a, 120b, 120c: first plurality of readout transistors

[0142] 120c1: First transistor

[0143] 120c2: Second transistor

[0144] 122, 406a, 406b: read-out gate electrode

[0145] 122a: first readout gate electrode

[0146] 122b: second readout gate electrode

[0147] 122c: third readout gate electrode

[0148] 122csw: Sidewall

[0149] 122csw1: First side wall

[0150] 122csw2: Second side wall

[0151] 124a, 124b, 124c, 124d, 124e, 124f, 124g, 124h, 410, 612, 632, 812, 814: source / drain regions

[0152] 126: Second transfer transistor

[0153] 126a, 126b: second plurality of transfer transistors

[0154] 128: Second floating diffusion node

[0155] 128a, 128b: second plurality of floating diffusion nodes

[0156] 129a, 129b: Second plurality of pickup well contact regions

[0157] 130: Via hole

[0158] 130a: first conductive hole

[0159] 130b: second via hole

[0160] 131: Second isolation structure

[0161] 132: Conductive wiring

[0162] 132a: first conductive wiring

[0163] 132b: Second conductive wiring

[0164] 200, 300b, 500, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700: Sectional view

[0165] 202: Gate dielectric layer

[0166] 204: Read transistor well region

[0167] 302: Reading out the gate insulator layer

[0168] 304: Conductive channel

[0169] 402: Third pixel sensor

[0170] 405a, 405b: Second plurality of readout transistors

[0171] 407a, 407b: Second plurality of junction isolation structures

[0172] 502: Anti-reflective layer

[0173] 504: Color Filter

[0174] 506: Microlens

[0175] 602a: Fourth pixel sensor

[0176] 602b: Fifth pixel sensor

[0177] 602c: Sixth pixel sensor

[0178] 604: Fourth multiple photodetector

[0179] 606: fourth plurality of transfer transistors

[0180] 608: Fourth multiple floating diffusion nodes

[0181] 610: Fourth multiple junction isolation structure

[0182] 611a, 611b, 611c, 630a, 630b: a third plurality of readout transistors

[0183] 615a, 615b: Pickup well contact area

[0184] 620: Fifth multiple photodetector

[0185] 622: Fifth plurality of transfer transistors

[0186] 624: Fifth multiple floating diffusion nodes

[0187] 634: Junction Isolation Structure

[0188] 650, 652, w1, w2: width

[0189] 700: Circuit

[0190] 701: Charge Collection Circuit

[0191] 702: TX1 node

[0192] 704: TX2 node

[0193] 706: TX3 node

[0194] 708: TX4 node

[0195] 710: Ground node

[0196] 712: First Node

[0197] 714: Precharge circuit

[0198] 718: Power supply node

[0199] 719: Charge transfer circuit

[0200] 722: Output node

[0201] 801: First photodetector

[0202] 802: Inline structure

[0203] 803: Second photodetector

[0204] 804: Transfer transistor well region

[0205] 806: Lower gate injection region

[0206] 808: Quarantine

[0207] 810a: First junction isolation structure

[0208] 810b: Second junction isolation structure

[0209] 816: Lightly doped region

[0210] 818: Sidewall spacer structure

[0211] 820: Conductive bonding pad

[0212] 824: Interconnect Dielectric Structure

[0213] 830: Integrated Circuit (IC) Die

[0214] 902, 904, 906: Gate electrode layer

[0215] 1202: Vertical gate electrode opening

[0216] 1800: Methods

[0217] 1802, 1804, 1806, 1808, 1810, 1812, 1814, 1816, 1818: Action

[0218] A-A', B-B', C-C': Line

[0219] d1, d2: distance

[0220] RSTG: reset gate voltage

[0221] SELG: Select gate voltage

[0222] t1, ts: thickness

[0223] ti: initial thickness

[0224] Vdd: voltage.

Claims

1. An image sensor, comprising: A first photodetector is disposed in the semiconductor substrate; A second photodetector is disposed in the semiconductor substrate; an isolation structure extending from a front side surface of the semiconductor substrate to a back side surface of the semiconductor substrate, wherein the front side surface is opposite to the back side surface, and wherein the isolation structure is laterally located between the first photodetector and the second photodetector; as well as a readout transistor disposed on the front side surface of the semiconductor substrate, wherein a first side of the readout transistor overlies the first photodetector and a second side of the readout transistor overlies the second photodetector, wherein the first side is opposite to the second side, and wherein the readout transistor extends continuously over the isolation structure, wherein the readout transistor comprises: a readout gate electrode, wherein the readout gate electrode extends continuously from over the first photodetector to over the second photodetector; a first source / drain region disposed along a first sidewall of the readout gate electrode; and A second source / drain region is disposed along the first sidewall of the readout gate electrode, wherein the first sidewall overlies the first photodetector.

2. The image sensor according to claim 1, further comprising: A junction isolation structure is located in the semiconductor substrate, is located laterally between the first source / drain region and the second source / drain region and is adjacent to the first source / drain region and the second source / drain region, wherein the junction isolation structure has an opposite doping type to that of the first source / drain region and the second source / drain region.

3. The image sensor of claim 2 , wherein the junction isolation structure has a sidewall located below the readout gate electrode, and wherein the sidewall of the junction isolation structure is arranged to be a non-zero distance from the first sidewall of the readout gate electrode in a direction toward the second photodetector.

4. The image sensor according to claim 1, further comprising: a floating diffusion node disposed in the semiconductor substrate and above the first photodetector; as well as A first transfer transistor is laterally adjacent to the floating diffusion node, wherein a top surface of the first transfer transistor is flush with a top surface of the readout transistor, wherein the first transfer transistor includes a first transfer gate electrode, and wherein two or more planar sidewalls of the first transfer gate electrode face in a direction toward the floating diffusion node, respectively.

5. The image sensor according to claim 4, further comprising: a second transfer transistor disposed above the second photodetector; and wherein the readout transistor is laterally disposed between the first transfer transistor and the second transfer transistor, wherein a first junction isolation structure extends along the first side of the readout transistor and is laterally disposed between the readout transistor and the first transfer transistor, and wherein a second junction isolation structure extends along the second side of the readout transistor and is laterally disposed between the readout transistor and the second transfer transistor.

6. The image sensor according to claim 1, further comprising: a third photodetector, adjacent to the first photodetector and diagonally opposite to the second photodetector; as well as A reset transistor is disposed on the semiconductor substrate and overlying the third photodetector, wherein a first sidewall of the reset transistor is laterally aligned with a first sidewall of the readout transistor located on the first side of the readout transistor.

7. The image sensor according to claim 6, further comprising: a fourth photodetector, adjacent to the second photodetector and the third photodetector and diagonally opposite to the first photodetector; a select transistor disposed on the semiconductor substrate and overlying the fourth photodetector, wherein a first sidewall of the select transistor is laterally aligned with a second sidewall of the readout transistor located on the second side of the readout transistor; and The second sidewall of the reset transistor is opposite to the first sidewall of the reset transistor, and the second sidewall of the selection transistor is opposite to the first sidewall of the selection transistor, and the isolation structure is located below the second sidewall of the selection transistor and the second sidewall of the reset transistor.

8. The image sensor according to claim 7, further comprising: a first selection source / drain region and a second selection source / drain region disposed along the first sidewall of the selection transistor, wherein a selection junction isolation structure is disposed between the first selection source / drain region and the second selection source / drain region; as well as A first reset source / drain region and a second reset source / drain region are arranged along the first side wall of the reset transistor, wherein a reset junction isolation structure is arranged between the first reset source / drain region and the second reset source / drain region.

9. The image sensor of claim 1, wherein the readout transistor has opposing sidewalls extending between the first side and the second side of the readout transistor, and wherein the opposing sidewalls are laterally spaced apart between opposing inner sidewalls of the isolation structure.

10. An image sensor, comprising: a first pixel sensor and a second pixel sensor, each comprising a plurality of photodetectors, a plurality of transfer transistors, and a floating diffusion node, wherein the plurality of photodetectors are disposed within a semiconductor substrate, and wherein the plurality of transfer transistors are disposed on a front side surface of the semiconductor substrate and selectively electrically couple the plurality of photodetectors to the floating diffusion node; an isolation structure disposed within the semiconductor substrate, wherein the isolation structure continuously surrounds each photodetector in the first pixel sensor and each photodetector in the second pixel sensor, and wherein the isolation structure extends completely through the semiconductor substrate; a source follower transistor overlying the first pixel sensor and gated by the floating diffusion node of the first pixel sensor; as well as A row select transistor overlying the second pixel sensor and having a source / drain region electrically coupled to a source / drain region of the source follower transistor.

11. The image sensor of claim 10, wherein the source follower transistor extends continuously from a first photodetector in the first pixel sensor to a second photodetector in the second pixel sensor, and wherein the source follower transistor extends continuously over a segment of the isolation structure disposed between the first photodetector and the second photodetector.

12. The image sensor according to claim 10, wherein the isolation structure comprises a shallow trench isolation structure and a deep trench isolation structure, wherein the shallow trench isolation structure extends from a front side surface of the semiconductor substrate to a point below the front side surface, wherein the deep trench isolation structure extends from a back side surface of the semiconductor substrate to the point, and wherein the front side surface is opposite to the back side surface.

13. The image sensor of claim 10, wherein the first pixel sensor comprises a first pixel well and a second pixel well, and wherein the image sensor further comprises: a third pixel sensor adjacent to the first pixel sensor and comprising a third pixel well and a fourth pixel well, wherein the third pixel well is diagonally opposite to the second pixel well and the fourth pixel well is diagonally opposite to the first pixel well; and The H-shaped wiring has four ends, which respectively overlie the first pixel well, the second pixel well, the third pixel well and the fourth pixel well and are respectively electrically coupled to the first pixel well, the second pixel well, the third pixel well and the fourth pixel well.

14. The image sensor according to claim 10, further comprising: a reset transistor disposed on a third pixel sensor, wherein the third pixel sensor is adjacent to the first pixel sensor; as well as A single conductive wire extends laterally across the isolation structure from a first end of the single conductive wire to a second end of the single conductive wire, wherein the first end overlies a source / drain region of the source follower transistor and the second end overlies a source / drain region of the reset transistor.

15. The image sensor according to claim 10, further comprising: a pickup well contact region having the same doping type as a pixel well region disposed along a sidewall of a photodetector in the first pixel sensor and located directly on the pixel well region; a substrate contact via electrically coupled directly to the pickup well contact region; and A power supply via is electrically coupled directly to a source / drain region of the source follower transistor, wherein a distance between the substrate contact via and the power supply via is less than a distance from the power supply via to any other via in the image sensor.

16. The image sensor of claim 10, wherein the source follower transistor comprises: a readout gate electrode disposed on the front side surface of the semiconductor substrate; a first source / drain region and a second source / drain region disposed along a first sidewall of the readout gate electrode, wherein a first junction isolation structure extends along the first sidewall and is laterally disposed between the first source / drain region and the second source / drain region; as well as An insulator layer is disposed between the readout gate electrode and the semiconductor substrate, wherein the insulator layer extends along one side of the first junction isolation structure.

17. A method of forming an image sensor, the method comprising: forming a shallow trench isolation structure on the front side surface of the semiconductor substrate; forming a first photodetector and a second photodetector in the semiconductor substrate, wherein the first photodetector and the second photodetector are laterally separated by the shallow trench isolation structure; forming a readout transistor on the front side surface, wherein a first sidewall of the readout transistor overlies the first photodetector and a second sidewall of the readout transistor overlies the second photodetector, wherein the first sidewall is opposite to the second sidewall, and wherein the readout transistor extends continuously above an upper surface of the shallow trench isolation structure; forming a first source / drain region along the first sidewall of the readout transistor; forming a first junction isolation structure along the first sidewall of the readout transistor, wherein the first junction isolation structure is laterally located between the first source / drain regions; as well as A deep trench isolation structure is formed on the backside surface of the semiconductor substrate, wherein the deep trench isolation structure extends from the backside surface to the shallow trench isolation structure.

18. The method according to claim 17, further comprising: forming a second source / drain region along the second sidewall of the readout transistor; as well as A second junction isolation structure is formed along the second sidewall of the readout transistor, wherein the second junction isolation structure is laterally located between the second source / drain regions.

19. The method according to claim 17, further comprising: A first transfer transistor and a second transfer transistor are formed simultaneously with the readout transistor, wherein a top surface of the first transfer transistor and a top surface of the second transfer transistor are flush with a top surface of the readout transistor, and wherein the first transfer transistor overlies the first photodetector and the second transfer transistor overlies the second photodetector.

Images