Communication control circuit used in power chip

Abstract

Disclosed is a communication control circuit used in a power supply circuit. By forming control circuits with different reference grounds on multiple chips, two chips that need to communicate are connected through level conversion circuits, so that the level conversion circuits are subjected to corresponding voltage differences, and electrical isolation can be achieved without a high-voltage isolation ring, thereby reducing the process difficulty of chip manufacturing and reducing costs.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a communication control circuit used in a power chip. Background Art

[0002] In the application of power chips, the most common method is to achieve electrical isolation on the same chip. Two control circuits with different reference grounds need to be isolated by a circle of isolation circuits. At the same time, if the voltage difference between the two control circuits is very high, a high-voltage isolation ring is also required to isolate the high-voltage device from the low-voltage device, which consumes a relatively large chip area and requires an epitaxial layer manufacturing process. The chip production cycle is long and the cost is high. Summary of the invention

[0003] In view of this, the object of the present invention is to provide a communication control circuit used in a power chip. By forming control circuits with different reference grounds on multiple chips, two chips that need to communicate are connected through level conversion circuits, so that the level conversion circuit is subjected to the corresponding voltage difference, and electrical isolation can be achieved without a high-voltage isolation ring, thereby reducing the process difficulty of chip manufacturing and reducing costs.

[0004] The present invention proposes a communication control circuit applied to a power chip, comprising:

[0005] A main control chip, including a main control circuit; and

[0006] A plurality of sub-control chips are respectively used to receive control signals sent by the main control chip, wherein each of the sub-control chips includes a sub-control circuit, wherein

[0007] The reference ground of the sub-control chip is different from the reference ground of the main control chip, and the reference ground of each sub-control chip is different. The main control chip and each sub-control chip communicate with each other through corresponding level conversion circuits.

[0008] Preferably, the sub-control chip is manufactured using a low-pressure manufacturing process.

[0009] Preferably, the number of the level conversion circuits is equal to the number of the sub-control chips.

[0010] Preferably, the plurality of level conversion circuits are all arranged in the main control chip.

[0011] Preferably, the plurality of level conversion circuits are respectively arranged in a plurality of independent conversion chips.

[0012] Preferably, each of the sub-control chips further includes a signal receiving circuit configured to receive the control signal and convert it into a signal required by the sub-control circuit, so that the sub-control circuit performs corresponding functional control.

[0013] Preferably, the level conversion circuit is configured to convert the level of the control signal transmitted by the main control circuit into a level suitable for the sub-control chip, so as to realize communication between the main control chip and the sub-control chip.

[0014] Preferably, the maximum withstand voltage of the level conversion circuit is the maximum difference between the levels of the sub-control chip and the main control chip.

[0015] Preferably, the main control chip and the multiple sub-control chips are packaged in one chip.

[0016] Preferably, the main control circuit is configured to generate a logic drive signal for a power tube in the power supply circuit and a drive signal for a power tube connected to a reference ground of the main control chip.

[0017] Preferably, each of the sub-control circuits is configured to generate a driving signal for a corresponding power tube that is not connected to a reference ground of the main control chip.

[0018] Preferably, each of the level conversion circuits is configured to receive the logic driving signal to convert it into a signal suitable for the level of the sub-control chip, thereby controlling the sub-control circuit to generate the driving signal.

[0019] Preferably, the level conversion circuit includes a power tube, wherein the control end of the power tube is controlled by the logic drive signal, the first power end is connected to the power supply of the sub-control chip, and the second power end is connected to the reference ground of the main control circuit to achieve level conversion.

[0020] Preferably, each of the level conversion circuits is identical.

[0021] In summary, by forming control circuits with different reference grounds on multiple chips, the two chips that need to communicate are connected through level conversion circuits, so that the level conversion circuit is subjected to the corresponding voltage difference, and electrical isolation can be achieved without a high-voltage isolation ring, thereby reducing the process difficulty of chip manufacturing and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0023] Figure 1 is a schematic diagram of a first communication control circuit according to an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a second communication control circuit according to an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of a communication control circuit applied to a first power supply circuit according to an embodiment of the present invention; and

[0026] Figure 4 FIG. 4 is a schematic diagram of a communication control circuit applied to a second power supply circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0028] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0029] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0030] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0031] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0032] Figure 1 FIG. 1 is a structural diagram of a first communication control circuit according to an embodiment of the present invention. Figure 1 As shown, the communication control circuit includes a main control chip IC 0 And multiple sub-control chips. Main control chip IC 0It includes a main control circuit and a plurality of level conversion circuits. In this embodiment, the main control chip IC 0 The example of including N level conversion circuits is described, where N is a positive integer. In this embodiment, the number of level conversion circuits corresponds to the number of sub-control chips. In this embodiment, the communication control circuit includes N sub-control chips IC 1 -IC N Each sub-control chip is used to receive the main control chip IC 0 The control information sent is used to perform corresponding control respectively, and the reference grounds of the N sub-control chips are different. In addition, each sub-control chip includes a sub-control circuit. It should be noted that the reference ground of the sub-control chip is also different from the reference ground of the main control circuit.

[0033] In addition, it should be understood that the main control circuit and sub-control circuit mentioned in the present invention can be circuits that implement any control function, which can generate different control signals to control other circuit parts, such as drive control circuits, feedback control circuits, protection circuits, etc., which are not limited here.

[0034] Furthermore, each sub-control chip also includes a signal receiving circuit for receiving the signal from the main control chip IC. 0 The signal transmitted by the corresponding level conversion circuit in the sub-control circuit is converted into the signal required by the sub-control circuit. In this embodiment, the sub-control chip IC 1 It includes a signal receiving circuit 1 and a sub-control circuit 1, ..., a sub-control chip IC N It includes a signal receiving circuit N and a sub-control circuit N.

[0035] Specifically, the main control chip IC 0 And sub-control chip IC 1 The communication between the sub-control chip and the main control chip is described as an example. The principle of communication between other sub-control chips and the main control chip is the same. The level conversion circuit 1 is used to convert the level of the control signal G1 transmitted by the main control circuit into a level suitable for the sub-control chip IC. 1 The receiving level is used to realize the master chip IC 0 And sub-control chip IC 1 It should be understood that the level of the control signal G1 generated by the main control circuit is relative to the main control chip IC 0 When it is passed to the reference ground, the sub-control chip IC with different reference ground 1 The signal level needs to be converted before it can be used to control the sub-control chip IC. 1 The circuit in.

[0036] At the same time, the maximum withstand voltage of the devices in the level conversion circuit 1 is the main control chip IC 0 And sub-control chip IC 1The maximum voltage difference between the two levels, so the high voltage is only borne by the level conversion circuit 1, and because the sub-control chip IC 1 With the main control chip IC 0 Separated, the high-voltage level conversion circuit is integrated in the main control chip IC 0 There is no need to use a high-voltage isolation ring, that is, although the main control chip IC 0 The present invention includes a level conversion circuit that withstands high voltage, but it does not require a high voltage isolation ring, so it does not require an epitaxial layer process, thereby reducing the manufacturing cost and process difficulty of the chip, and greatly reducing the area of ​​the chip. Of course, any level conversion circuit that can achieve the above function in the prior art can be used in the present invention, and this is not limited here.

[0037] like Figure 1 As shown, the main control chip IC 0 The multiple level conversion circuits 1-N in the chip are connected to the sub-control chip IC through wiring or redistribution layer. 1 -IC N The signal receiving circuits in the main control chip are connected one by one. It should be understood that the connection method between the chips is not limited to this. In this embodiment, the main control chip IC 0 And sub-control chip IC 1 -IC N Finally, they are packaged in the same chip. Here, no high-voltage isolation ring is required between control circuits with different reference grounds, so the size of the packaged chip is greatly reduced.

[0038] Figure 2 A structural diagram of a second communication control circuit according to an embodiment of the present invention is given. Figure 2 As shown, the communication control circuit includes a main control chip IC 0 , multiple sub-control chips and multiple conversion chips, wherein the number of conversion chips corresponds to the number of sub-control chips. In this embodiment, the number of sub-control chips and conversion chips is N as an example, where N is a positive integer. Main control chip IC 0 Includes the main control circuit, which is used to generate various control signals. 1 -IC N The structure is the same as that of the above embodiment and will not be described here. The difference is that Figure 1 The main control chip IC 0 Each level conversion circuit in the chip is a separate chip, that is, a conversion chip IC. 01 -IC 0N . Due to the level conversion circuit and the main control chip IC 0 Therefore, the level conversion circuit 1-N is separated from the main control chip IC through wire bonding or redistribution layer 0The main control circuit in the converter is connected to receive the control signals G1-Gn transmitted by the main control circuit. 01 -IC 0N The level conversion circuits 1-N in the circuit are connected to the sub-control chip IC through wire bonding or redistribution layer. 1 -IC N The signal receiving circuits 1-N in the circuit are connected correspondingly to connect the main control chip IC 0 The level of the transmitted control signal G1-Gn is converted to a level suitable for the sub-control chip IC 1 -IC N The received level enables the master chip IC 0 And each sub-control chip IC 1 -IC N Communication between.

[0039] In this embodiment, the level conversion circuit is used as a conversion chip alone, so that a level conversion circuit with similar functions can be designed with only one conversion chip, and complex functions can be realized by placing multiple identical conversion chips, which is conducive to modular design.

[0040] Figure 3 A schematic diagram of a communication control circuit applied to a first power supply circuit according to an embodiment of the present invention is given. Figure 1 The communication control circuit shown is used as an example for explanation, and it should be understood that the second communication control circuit is also applicable.

[0041] In this embodiment, the bridgeless PFC circuit includes a load R connected in parallel L The two bridge arms at both ends, wherein the first bridge arm includes power tubes Q1 and Q2 connected in series, and the second bridge arm includes power tubes Q3 and Q4 connected in series. At the same time, the AC input voltage V AC The first end of the inductor L B The common node SW1 of the power tubes Q1 and Q2 is connected, and the second end of the AC input voltage VAC is connected to the common node SW2 of the power tubes Q3 and Q4. Here, the power tubes Q1 and Q2 are controlled by the high-frequency PWM pulse signal to perform the switching action, and the power tubes Q3 and Q4 are controlled by the power frequency square wave signal to perform the switching action. It should be understood that other control methods in the prior art can also be applied here, and the present invention is not limited to this.

[0042] Since the drivers of power tubes Q1 and Q3 are floating, if a traditional drive control circuit is used, the control chip needs to be isolated by a high-voltage isolation ring, which occupies a large amount of chip area. However, by adopting the solution of the embodiment of the present invention, the main control circuit and two level conversion circuits are designed on one chip (i.e., the main control chip IC 0), and the sub-control circuit 1 (here, the drive control circuit 1) and the signal receiving circuit 1 corresponding to the power tube Q1 are designed on a chip (ie, the sub-control chip IC 1 ), the sub-control circuit 2 (herein, the drive control circuit 2) and the signal receiving circuit 2 corresponding to the power tube Q2 are designed on a chip (ie, the sub-control chip IC 2 ), thus achieving isolation without the use of a high voltage isolation ring.

[0043] In this embodiment, the main control circuit is used to generate the logic drive signal of each power tube (Q1-Q4), and the level conversion circuit 1 receives the logic drive signal GT1 and converts it into a level suitable for the sub-control chip IC. 1 The signal receiving circuit 1 receives the signal and converts it into a signal that can control the drive control circuit 1, so that the drive control circuit 1 outputs the drive signal GS1 of the power tube Q1. Similarly, the level conversion circuit 2 receives the logic drive signal GT3 and converts it into a signal suitable for the sub-control chip IC. 2 The signal receiving circuit 2 receives the signal and converts it into a signal capable of controlling the drive control circuit 2 so that it outputs the drive signal GS3 of the power tube Q3. Since the power tubes Q2 and Q4 are grounded, the corresponding drive control circuits are arranged in the main control circuit to directly generate the drive signals GS2 and GS4 of the power tubes Q2 and Q4.

[0044] In some embodiments, each level conversion circuit may include two switch tubes, each switch tube is controlled to be turned on or off according to the control signal output by the main control circuit, and the first power end of each switch tube is connected to the high-voltage power supply of the sub-control chip, and the second power end is connected to the reference ground of the main control circuit, so that only the switch tube bears the high voltage voltage difference. Therefore, the sub-control chip itself can be manufactured using a low-voltage process, and because the sub-control chip is separated from the main control chip, the high-voltage switch tube does not need to use a high-voltage isolation ring when it is integrated in the main control chip, that is, although the main control chip includes a switch tube that withstands high voltage, it does not need a high-voltage isolation ring, nor does it need an epitaxial layer process, thereby reducing the manufacturing cost and process difficulty of the chip, and greatly reducing the area of ​​the chip.

[0045] In this embodiment, the functions and implementation methods of the level conversion circuits 1 and 2 are the same, so only one chip of the level conversion circuit can be designed. Figure 2 The second communication control circuit architecture shown separates the level conversion circuit and simplifies the circuit design by placing multiple identical chips.

[0046] Figure 4 A schematic diagram of a communication control circuit used in the second power supply circuit is given. Figure 4A bridgeless PFC with staggered parallel connection is given to further reduce the current ripple. As shown in the figure, the bridgeless PFC includes a load R L There are multiple bridge arms at both ends, and three bridge arms are used as an example for explanation. AC input voltage V AC The first end of the inductor L B1 Connected to the common node SW1 of the power tubes Q1 and Q2 in the first bridge arm, and the first end is also connected through the inductor L B2 Connected to the common node SW2 of the power tubes Q3 and Q4 in the second bridge arm; AC input voltage V AC The second end is connected to the common node SW3 of the power tubes Q5 and Q6 in the third bridge arm. In this embodiment, since the upper power tubes (Q1, Q3 and Q5) of multiple bridge arms are all floating, the reference grounds of the sub-control chips corresponding to the upper power tubes are different.

[0047] In this embodiment, the main control chip IC 0 The main control circuit in the middle is used to generate the logic drive signal of each power tube. The sub-control circuit and signal receiving circuit corresponding to the upper power tube of each bridge arm are designed on one chip to form multiple sub-control chip ICs. 1 -IC 3 Each sub-control chip is designed to be separated from the main control chip, thereby avoiding the use of a high-voltage isolation ring, greatly saving chip area, and reducing chip cost. At the same time, since each sub-control chip is used to drive the upper power tube of each bridge arm in this embodiment, its structure and implemented functions are the same, so the level conversion circuit used to realize communication between control circuits with different reference grounds can be designed separately on a chip, that is, only one conversion chip including the level conversion circuit is designed, so that the control of multiple upper power tubes can be realized by placing multiple conversion chips.

[0048] like Figure 4 As shown, the level conversion circuits 1-3 are respectively placed in the conversion chip IC 01 -IC 03 In order to receive the logic drive signals GT1, GT3 and GT5 from the main control circuit respectively, and convert them into suitable signals for the corresponding sub-control chip IC 1 -IC 3 Specifically, the level conversion circuit 1 receives the logic drive signal GT1 and converts it into a level suitable for the sub-control chip IC 1 The signal receiving circuit 1 receives the signal and converts it into a signal capable of controlling the drive control circuit 1, so that the drive control circuit 1 outputs the drive signal GS1 of the power tube Q1. The generation of the drive signals GS3 and GS5 is similar and will not be elaborated here.

[0049] Since the lower power tubes (Q2, Q4 and Q6) of each bridge arm are connected to the ground level, the corresponding drive control circuits are arranged in the main control circuit to directly generate drive signals GS2, GS4 and GS6 for the power tubes Q2, Q4 and Q6.

[0050] The power circuit of the embodiment of the present invention is only described by taking the bridgeless PFC circuit as an example. It should be understood that other power circuits including power tubes with different reference grounds can be applied. Furthermore, the architecture of the communication control circuit of the embodiment of the present invention can be applied to circuits that need to transmit control signals with different reference grounds.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A communication control circuit used in a power chip, It is characterized in that include: Main control chip, including main control circuit; as well as A plurality of sub-control chips are respectively used to receive control signals sent by the main control chip, wherein each of the sub-control chips includes a sub-control circuit, wherein The reference ground of the sub-control chip is different from the reference ground of the main control chip, and the reference ground of each sub-control chip is different. The main control chip and each sub-control chip communicate with each other through corresponding level conversion circuits.

2. The communication control circuit according to claim 1, It is characterized in that The sub-control chip is manufactured by adopting a low-pressure manufacturing process.

3. The communication control circuit according to claim 1, It is characterized in that The number of the level conversion circuits is equal to the number of the sub-control chips.

4. The communication control circuit according to claim 3, It is characterized in that A plurality of level conversion circuits are all arranged in the main control chip.

5. The communication control circuit according to claim 3, It is characterized in that The plurality of level conversion circuits are respectively arranged in a plurality of independent conversion chips.

6. The communication control circuit according to claim 1, It is characterized in that Each of the sub-control chips also includes a signal receiving circuit configured to receive the control signal and convert it into a signal required by the sub-control circuit, so that the sub-control circuit performs corresponding functional control.

7. The communication control circuit according to claim 1, It is characterized in that The level conversion circuit is configured to convert the level of the control signal transmitted by the main control circuit into a level suitable for the sub-control chip to achieve communication between the main control chip and the sub-control chip.

8. The communication control circuit according to claim 1, It is characterized in that The maximum withstand voltage of the level conversion circuit is the maximum difference between the levels of the sub-control chip and the main control chip.

9. The communication control circuit according to claim 1, It is characterized in that The main control chip and the plurality of sub-control chips are packaged in one chip.

10. The communication control circuit according to claim 1, It is characterized in that The main control circuit is configured to generate a logic drive signal for the power tube in the power supply circuit and a drive signal for the power tube connected to the reference ground of the main control chip.

11. The communication control circuit according to claim 10, It is characterized in that Each of the sub-control circuits is configured to generate a driving signal for a corresponding power tube that is not connected to a reference ground of the main control chip.

12. The communication control circuit according to claim 11, It is characterized in that Each of the level conversion circuits is configured to receive the logic driving signal to convert it into a signal suitable for the level of the sub-control chip, so as to control the sub-control circuit to generate the driving signal.

13. The communication control circuit according to claim 12, It is characterized in that The level conversion circuit includes a power tube, wherein the control end of the power tube is controlled by the logic drive signal, the first power end is connected to the power supply of the sub-control chip, and the second power end is connected to the reference ground of the main control circuit to achieve level conversion.

14. The communication control circuit according to claim 12, It is characterized in that Each of the level shifting circuits is identical.

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