A small digital brushless DC motor drive circuit and control method

Abstract

The present invention belongs to the field of motor drive technology, and particularly relates to a small digital brushless DC motor drive circuit and control method. A small digital brushless DC motor drive circuit includes a main control chip, a power module, a motor signal drive module, a signal control module, a signal detection module, a data transmission module and a data storage module. The output ends of the power module, the signal control module and the signal detection module are respectively connected to the main control chip, the output end and the input end of the data transmission module and the data storage module are respectively connected to the main control chip, the input end of the motor signal drive module is connected to the main control chip, and the output end of the motor signal drive module is electrically connected to the DC brushless motor. The present invention divides the drive circuit into different modules according to function, realizes the overall modularization of the circuit, is easy to maintain, convenient for miniaturization, and has low cost; at the same time, a data storage module is added to store various signals sent by the control system for data analysis.

Description

Technical Field

[0001] The invention belongs to the technical field of motor drive, and in particular relates to a small digital brushless DC motor drive circuit and a control method. Background Art

[0002] DC brushed motors require mechanical commutation and brushes, have poor reliability, require frequent maintenance, generate electromagnetic interference during commutation, and produce high noise, which affects the application of DC brushed motors in control systems. With the development of new permanent magnet materials, microelectronics technology, automatic control technology, and power electronics technology, especially high-power switching devices, brushless DC motors continue to develop. Brushless DC motors have been widely used due to their good speed regulation performance, simple control methods, ultra-high power density, and efficiency advantages in low-power motors.

[0003] The existing brushless DC motor drive circuit is complex. While detecting Hall signals, limit signals, steering signals, speed control signals, etc., it converts the steering command into a three-phase full-bridge motor drive signal that can drive the rudder motor to achieve motor speed regulation and forward and reverse control. The circuit maintenance is complex and costly. In addition, the existing brushless DC motor drive circuit has no data storage function. When a problem occurs in the circuit, it is impossible to quickly check the operation history data and perform corresponding data analysis. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a small digital brushless DC motor drive circuit and control method. By dividing the drive circuit into different modules according to function, the overall circuit is modularized, easy to maintain, convenient for miniaturization, and low cost. At the same time, a data storage module is added to store various signals sent by the control system for historical data analysis.

[0005] The technical solution of the present invention is: a small digital direct current brushless motor drive circuit, including a main control chip, a power supply module, a motor signal drive module, a signal control module, a signal detection module, a data transmission module and a data storage module, wherein: the output ends of the power supply module, the signal control module and the signal detection module are respectively connected to the main control chip, the output end and the input end of the data transmission module and the data storage module are respectively connected to the main control chip, the input end of the motor signal drive module is connected to the main control chip, and the output end of the motor signal drive module is electrically connected to the direct current brushless motor.

[0006] The main control chip is an FPGA main control chip.

[0007] The power supply module is a secondary power supply module, and the secondary power supply module provides +3.3V and +1.5V voltages for the main control chip.

[0008] The motor signal driving module includes a bootstrap boost circuit and a three-phase full-bridge driving circuit. The input end of the bootstrap boost circuit is electrically connected to the main control chip, the output end of the bootstrap boost circuit is electrically connected to the input end of the three-phase full-bridge driving circuit, and the output end of the three-phase full-bridge driving circuit is electrically connected to the DC brushless motor.

[0009] The data storage module is a FLASH data storage module.

[0010] The signal detection module comprises a Hall signal detection module and a limit signal detection module, and the output ends of the Hall signal detection module and the limit signal detection module are electrically connected to the main control chip respectively.

[0011] The signal control module comprises a speed code control module and a steering control module, and the output ends of the speed code control module and the steering control module are electrically connected to the main control chip respectively.

[0012] The data transmission module comprises a serial port data reading module and a CAN receiving module. The input end of the serial port data reading module and the output end of the CAN receiving module are electrically connected to the main control chip respectively.

[0013] The bootstrap boost circuit is an IR2110S bootstrap boost circuit, the FLASH memory 5 is a memory chip S29GL512P11TFI01 produced by SPANSION, the steering control module 9 is an operational amplifier LM2904D produced by TI and an optocoupler PS2801 produced by NEC, the FPGA main control chip is an A3P600-2PQG208I chip of the ProASIC3 series of Actel, and the A3P600-2PQG208I chip has a total of 66 I / O Ports, 2 I / O ports of the A3P600-2PQG208I chip are used as receiving ports of the CAN receiving module, 9 I / O ports are used as receiving ports of the Hall signal detection module, 6 I / O ports are used as receiving ports of the limit signal detection module, 6 I / O ports are used as receiving ports of the steering control module, 25 I / O ports are used as address lines of the FLASH data storage module, 16 I / O ports are used as data lines of the FLASH data storage module, and 2 I / O ports are used as serial data reading interfaces of the serial port data reading module.

[0014] A control method for a small digital brushless DC motor drive circuit, using any of the small digital brushless DC motor drive circuits described above, specifically comprising the following steps:

[0015] S1: After the circuit is powered on, it is initialized first. The initialization process includes: IO port initialization, CAN port initialization, serial port initialization and driver module initialization;

[0016] S2: After initialization, the main control chip receives the steering command from the control system, and samples the Hall signal, limit signal, and steering signal after conditioning;

[0017] S3: Determine whether the motor needs to rotate according to the direction and limit signals. Only when there is no limit on forward rotation or no limit on reverse rotation, the main control chip will modulate the PWM wave, that is, AND the PWM wave with the switch states of the six MOS tubes of the motor's forward or reverse rotation, and output the result to the corresponding control port; otherwise, when there is a positive limit on forward rotation or a negative limit on reverse rotation, the motor stops.

[0018] S4: First, the main control chip receives the steering signal for judgment. When the steering signal is valid, the speed code is searched in the table. Since the duty cycle of the speed code sent by the host computer is nonlinear, in order to simplify the algorithm, a corresponding table is made between the nonlinear speed code and 0-255. When the FPGA main control chip receives the nonlinear speed code, it first searches the table to find the corresponding linear value, and uses the value to generate a PWM wave. When the signal is invalid, there is no need to look up the table to directly output a fixed value of 0Xcc, and the main control chip outputs a fixed PWM wave.

[0019] S5: The FPGA main control chip determines which phase of the three-phase full-bridge drive circuit is connected according to the current Hall state, obtains the switch state of the six MOS tubes at the next moment according to the forward and reverse timing table of the motor, and performs AND operation on the switch state of the MOS when the motor is running at the next moment and the PWM, modulates the PWM wave, and then outputs it from the six I / O ports to the PWM wave input port of the IR2110S. The device output port signal is directly sent to the three-phase full-bridge drive circuit, and the purpose of controlling the motor to rotate at the set speed is achieved by changing the duty cycle of the PWM wave; the I / O port of the FPGA main control chip has no driving capability, and the IR2110S amplifies the signal output by the I / O port so that the PWM wave signal can drive the MOS tube of the three-phase full-bridge drive circuit; the three outputs of the three-phase full-bridge drive circuit are connected to the three-phase windings A, B, and C of the brushless motor, and the three Hall signals are connected to the FPGA main control chip, and the Hall signals are fed back to the FPGA main control chip in real time for analysis and processing.

[0020] The technical effects of the present invention are as follows: 1. Compared with the conventional brushless DC motor drive circuit, the present invention specially arranges a FLASH data storage module in its drive circuit to store the rudder speed code, steering and limit signals issued by the control system, and reads out historical data through the serial port to perform data analysis; 2. The present invention divides the drive circuit into functional modules such as a power supply module, a motor signal drive module, a signal control module, a signal detection module, a data transmission module and a data storage module, adopts an embedded microprocessor FPGA main control chip to receive the CAN bus steering command sent by the host computer, and converts the command into a three-phase full-bridge motor drive signal that can drive the rudder motor to work, and simultaneously detects the Hall signal, limit signal, steering signal and speed control signal, and finally realizes the speed regulation and forward and reverse control of the motor. The overall circuit is modularized, easy to maintain, convenient for miniaturization and low cost.

[0021] The following is a further description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The present invention is a block diagram of a small digital brushless DC motor drive circuit.

[0023] Figure 2 The present invention is a block diagram of a specific composition of a small digital brushless DC motor drive circuit.

[0024] Figure 3 The present invention is a hardware implementation block diagram of a small digital brushless DC motor drive circuit.

[0025] Figure 4 The present invention is a schematic diagram of the layout of a main control chip of a small digital brushless DC motor drive circuit.

[0026] Figure 5 The present invention is a control flow chart of a small digital brushless DC motor drive circuit.

[0027] Figure numerals: 1-FPGA main control chip, 2-secondary power supply module, 3-bootstrap boost circuit, 4-three-phase full-bridge drive circuit, 5-FLASH data storage module, 6-Hall signal detection module, 7-limit signal detection module, 8-speed code control module, 9-steering control module, 10-serial port data reading module, 11-CAN receiving module. DETAILED DESCRIPTION

[0028] Example 1

[0029] In order to overcome the problems that the existing DC brushless motor drive circuit is complex, the circuit maintenance cost is high, and there is no data storage function, and the circuit cannot be quickly checked after a problem occurs, the present invention provides a Figure 1The present invention shows a small digital brushless DC motor drive circuit. The present invention divides the drive circuit into different modules according to function to realize the overall modularization of the circuit, which is easy to maintain, miniaturized and low in cost. At the same time, a data storage module is added to store various signals sent by the control system and perform historical data analysis.

[0030] like Figure 1 As shown, a small digital brushless DC motor drive circuit includes a main control chip, a power module, a motor signal drive module, a signal control module, a signal detection module, a data transmission module and a data storage module, wherein: the output ends of the power module, the signal control module and the signal detection module are respectively connected to the main control chip, the output end and the input end of the data transmission module and the data storage module are respectively connected to the main control chip, the input end of the motor signal drive module is connected to the main control chip, and the output end of the motor signal drive module is electrically connected to the DC brushless motor.

[0031] The present invention divides the driving circuit into different modules according to function, thereby realizing overall modularization of the circuit, facilitating maintenance, miniaturization and low cost; at the same time, a data storage module is added to store various signals sent by the control system and perform historical data analysis.

[0032] Example 2

[0033] like Figure 2 As shown, preferably, on the basis of Example 1, in this embodiment, the main control chip is an FPGA main control chip 1.

[0034] The power module is a secondary power module 2 , and the secondary power module 2 provides +3.3V and +1.5V voltages for the main control chip 1 .

[0035] The motor signal driving module includes a bootstrap boost circuit 3 and a three-phase full-bridge driving circuit 4, the input end of the bootstrap boost circuit 3 is electrically connected to the main control chip, the output end of the bootstrap boost circuit 3 is electrically connected to the input end of the three-phase full-bridge driving circuit 4, and the output end of the three-phase full-bridge driving circuit 4 is electrically connected to the DC brushless motor.

[0036] The data storage module is a FLASH data storage module 5 .

[0037] The signal detection module comprises a Hall signal detection module 6 and a limit signal detection module 7, and the output ends of the Hall signal detection module 6 and the limit signal detection module 7 are electrically connected to the main control chip respectively.

[0038] The signal control module comprises a speed code control module 8 and a steering control module 9, and the output ends of the speed code control module 8 and the steering control module 9 are electrically connected to the main control chip respectively.

[0039] The data transmission module comprises a serial port data reading module 10 and a CAN receiving module 11. The input end of the serial port data reading module 10 and the output end of the CAN receiving module 11 are electrically connected to the main control chip respectively.

[0040] In actual use, the motor speed code sent by the host computer is sent to the FPGA main control chip through the CAN interface. The relevant direction signal, limit signal and Hall signal fed back by the motor sent by the control system are sent to the FPGA main control chip at the same time. The FPGA main control chip contains CAN command parsing, PWM generator, Hall decoding, limit control, steering control, serial port control, FLASH control and other modules. Finally, the logic synthesis of all control quantities is completed through logic synthesis, and the rotation of the motor is judged to generate the next control instruction. The control instructions generated by the FPGA main control chip control the three-phase full-bridge drive circuit through the bootstrap boost circuit, and finally realize the drive of three DC brushless motors. At the same time, this circuit also has the function of steering information storage, which stores the steering speed code, steering and limit signals sent by the control system, and can read historical data through the serial port for data analysis.

[0041] like Figure 3 , Figure 4 As shown, preferably, the bootstrap boost circuit is an IR2110S bootstrap boost circuit, the FLASH memory 5 is a memory chip S29GL512P11TFI01 produced by SPANSION, and the steering control module 9 is an operational amplifier LM2904D produced by TI and an optocoupler PS2801 produced by NEC. The FPGA main control chip 1 is an A3P600-2PQG208I chip of Actel's ProASIC3 series. The A3P600-2PQG208I chip has a total of 66 I / O ports. Two I / O ports of the A3P600-2PQG208I chip are used as receiving ports of the CAN receiving module 11, 9 I / O ports are used as receiving ports of the Hall signal detection module 6, 6 I / O ports are used as receiving ports of the limit signal detection module 7, 6 I / O ports are used as receiving ports of the steering control module 9, 25 I / O ports are used as address lines of the FLASH data storage module 5, 16 I / O ports are used as data lines of the FLASH data storage module 5, and 2 I / O ports are used as serial data reading interfaces of the serial port data reading module 10.

[0042] In actual use, the FPGA main control chip receives the steering commands sent by the host computer through the CAN bus interface, and the embedded microprocessor parses the commands. The FPGA main control chip receives the Hall signal, limit signal, control signal, and steering signal from the external sensor, and performs logic synthesis through the FPGA main control chip to generate the original control signals of 18 motors, 6 signals for each motor, and then the IR2110S bootstrap boost circuit generates the upper and lower bridge arm control signals of 18 three-phase full-bridge circuits to control the MOS tube, and finally realize the speed regulation and forward and reverse control of the motor.

[0043] Example 3

[0044] A control method for a small digital brushless DC motor drive circuit, using any of the above small digital brushless DC motor drive circuits, such as Figure 5 As shown, the specific steps include:

[0045] S1: After the circuit is powered on, it is initialized first. The initialization process includes: IO port initialization, CAN port initialization, serial port initialization and driver module initialization;

[0046] S2: After initialization, the main control chip receives the steering command from the control system, and samples the Hall signal, limit signal, and steering signal after conditioning;

[0047] S3: Determine whether the motor needs to rotate according to the direction and limit signals. Only when there is no limit on forward rotation or no limit on reverse rotation, the main control chip will modulate the PWM wave, that is, AND the PWM wave with the switch states of the six MOS tubes of the motor's forward or reverse rotation, and output the result to the corresponding control port; otherwise, when there is a positive limit on forward rotation or a negative limit on reverse rotation, the motor stops.

[0048] S4: First, the main control chip receives the steering signal for judgment. When the steering signal is valid, the speed code is searched in the table. Since the duty cycle of the speed code sent by the host computer is nonlinear, in order to simplify the algorithm, a corresponding table is made between the nonlinear speed code and 0-255. When the FPGA main control chip receives the nonlinear speed code, it first searches the table to find the corresponding linear value, and uses the value to generate a PWM wave. When the signal is invalid, there is no need to look up the table to directly output a fixed value of 0Xcc, and the main control chip outputs a fixed PWM wave.

[0049] S5: The FPGA main control chip determines which phase of the three-phase full-bridge drive circuit is connected according to the current Hall state, obtains the switch state of the six MOS tubes at the next moment according to the forward and reverse timing table of the motor, and performs AND operation on the switch state of the MOS when the motor is running at the next moment and the PWM, modulates the PWM wave, and then outputs it from the six I / O ports to the PWM wave input port of the IR2110S. The device output port signal is directly sent to the three-phase full-bridge drive circuit, and the purpose of controlling the motor to rotate at the set speed is achieved by changing the duty cycle of the PWM wave; the I / O port of the FPGA main control chip has no driving capability, and the IR2110S amplifies the signal output by the I / O port so that the PWM wave signal can drive the MOS tube of the three-phase full-bridge drive circuit; the three outputs of the three-phase full-bridge drive circuit are connected to the three-phase windings A, B, and C of the brushless motor, and the three Hall signals are connected to the FPGA main control chip, and the Hall signals are fed back to the FPGA main control chip in real time for analysis and processing.

[0050] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A control method for a small digital brushless DC motor drive circuit, characterized in that: A small digital brushless DC motor drive circuit is used, the drive circuit comprising a main control chip, a power module, a motor signal drive module, a signal control module, a signal detection module, a data transmission module and a data storage module, wherein: the output ends of the power module, the signal control module and the signal detection module are respectively electrically connected to the main control chip, the output end and the input end of the data transmission module and the data storage module are respectively electrically connected to the main control chip, the input end of the motor signal drive module is electrically connected to the main control chip, the output end of the motor signal drive module is electrically connected to the brushless DC motor, the main control chip is an FPGA main control chip (1), and the control process comprises the following steps: S1: After the circuit is powered on, it is initialized first. The initialization process includes: IO port initialization, CAN port initialization, serial port initialization and driver module initialization; S2: After initialization, the main control chip receives the steering command from the control system, and samples the Hall signal, limit signal, and steering signal after conditioning; S3: Determine whether the motor needs to rotate according to the direction and limit signals. Only when there is no limit on forward rotation or no limit on reverse rotation, the main control chip will modulate the PWM wave, that is, AND the PWM wave with the switch states of the six MOS tubes of the motor's forward or reverse rotation, and output the result to the corresponding control port; otherwise, when there is a positive limit on forward rotation or a negative limit on reverse rotation, the motor stops. S4: First, the main control chip receives the steering signal for judgment. When the steering signal is valid, the speed code is searched in the table. Since the duty cycle of the speed code sent by the host computer is nonlinear, in order to simplify the algorithm, a corresponding table is made between the nonlinear speed code and 0-255. When the FPGA main control chip receives the nonlinear speed code, it first searches the table to find the corresponding linear value, and uses the value to generate a PWM wave. When the signal is invalid, there is no need to look up the table to directly output a fixed value of 0Xcc, and the main control chip outputs a fixed PWM wave. S5: The FPGA main control chip determines which phase of the three-phase full-bridge drive circuit is connected according to the current Hall state, obtains the switch state of the six MOS tubes at the next moment according to the forward and reverse timing table of the motor, performs AND operation on the switch state of the MOS tube when the motor is running at the next moment and the PWM, modulates the PWM wave, and then outputs it from the six I / O ports to the PWM wave input port of the IR2110S. The output port signal of the PWM wave of the IR2110S is directly sent to the three-phase full-bridge drive circuit, and the purpose of controlling the motor to rotate at the set speed is achieved by changing the duty cycle of the PWM wave; the I / O port of the FPGA main control chip has no driving capability, and the IR2110S amplifies the signal output by the I / O port so that the PWM wave signal can drive the MOS tube of the three-phase full-bridge drive circuit; the three outputs of the three-phase full-bridge drive circuit are connected to the three-phase windings A, B, and C of the brushless motor, and the three Hall signals are connected to the FPGA main control chip, and the Hall signals are fed back to the FPGA main control chip in real time for analysis and processing.

2. The control method of a small digital brushless DC motor drive circuit according to claim 1, characterized in that: The power supply module is a secondary power supply module (2), and the secondary power supply module (2) provides +3.3V and +1.5V voltages for the FPGA main control chip (1).

3. The control method of a small digital brushless DC motor drive circuit according to claim 2, characterized in that: The motor signal drive module comprises a bootstrap boost circuit (3) and a three-phase full-bridge drive circuit (4); the input end of the bootstrap boost circuit (3) is electrically connected to the main control chip; the output end of the bootstrap boost circuit (3) is electrically connected to the input end of the three-phase full-bridge drive circuit (4); and the output end of the three-phase full-bridge drive circuit (4) is electrically connected to the brushless DC motor.

4. The control method of a small digital brushless DC motor drive circuit according to claim 3, characterized in that: The data storage module is a FLASH data storage module (5).

5. The control method of a small digital brushless DC motor drive circuit according to claim 4, characterized in that: The signal detection module comprises a Hall signal detection module (6) and a limit signal detection module (7), and the output ends of the Hall signal detection module (6) and the limit signal detection module (7) are respectively electrically connected to the main control chip.

6. The control method of a small digital brushless DC motor drive circuit according to claim 5, characterized in that: The signal control module comprises a speed code control module (8) and a steering control module (9), and the output ends of the speed code control module (8) and the steering control module (9) are respectively electrically connected to the main control chip.

7. The control method of a small digital brushless DC motor drive circuit according to claim 6, characterized in that: The data transmission module comprises a serial port data reading module (10) and a CAN receiving module (11), and the input end of the serial port data reading module (10) and the output end of the CAN receiving module (11) are electrically connected to the main control chip respectively.

8. The control method of a small digital brushless DC motor drive circuit according to claim 7, characterized in that: The bootstrap boost circuit (3) is an IR2110S bootstrap boost circuit, the FLASH data storage module (5) is a storage chip S29GL512P11TFI01 produced by SPANSION, the steering control module (9) includes an operational amplifier LM2904D produced by TI and an optical coupler PS2801 produced by NEC, the FPGA main control chip (1) is an A3P600-2PQG208I chip of the ProASIC3 series of Actel, the A3P600-2PQG208I chip has a total of 66 I / O ports, and the Two I / O ports of the A3P600-2PQG208I chip are used as receiving ports of the CAN receiving module (11), nine I / O ports are used as receiving ports of the Hall signal detection module (6), six I / O ports are used as receiving ports of the limit signal detection module (7), six I / O ports are used as receiving ports of the steering control module (9), 25 I / O ports are used as address lines of the FLASH data storage module (5), 16 I / O ports are used as data lines of the FLASH data storage module (5), and two I / O ports are used as serial data reading interfaces of the serial port data reading module (10).

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