Operational Amplifier and Signal Amplification Method

Abstract

The present invention provides an operational amplifier and a signal amplification method. The operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier is arranged to receive an input signal and amplify the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage-controlled current source circuit that operates in response to a bias voltage input. The current controller is coupled to the voltage-controlled current source circuit, the current controller receives the input signal, and generates a bias voltage input according to the input signal. According to the operational amplifier and the signal amplification method of the present invention, an enhanced slew rate of the amplifier can be achieved, thereby improving the output of the amplifier.

Description

Technical Field

[0001] The present invention relates to amplifying an input signal to generate an output signal, and more particularly, to an operational amplifier using a single-stage amplifier with slew-rate enhancement (e.g., class AB slew-rate enhancement) and related methods thereof. Background Art

[0002] It should be understood that, in general, the most effective type of operational amplifier is a single-stage amplifier with a single pole. A single-stage amplifier can easily achieve high bandwidth and low noise. However, a single-stage amplifier is limited in terms of slew rate. The slew rate of an operational amplifier represents the maximum rate of change of a signal at any point in the circuit. In other words, the limitation in terms of slew rate can cause non-linear effects, and if the frequency of the amplifier input signal exceeds the slew rate limit of the operational amplifier, the non-linear effects will cause severe distortion of the amplifier output. Summary of the Invention

[0003] In view of this, the present invention provides an operational amplifier using a single-stage amplifier with slew-rate enhancement (e.g., class AB slew-rate enhancement) and related methods thereof.

[0004] According to a first aspect of the present invention, an operational amplifier is disclosed, which includes a single-stage amplifier and a current controller. The single-stage amplifier is arranged to receive an input signal and amplify the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage-controlled current source circuit that operates in response to a bias voltage input. The current controller is coupled to the voltage-controlled current source circuit, wherein the current controller receives the input signal and generates the bias voltage input according to the input signal.

[0005] According to a second aspect of the present invention, an exemplary signal amplification method is disclosed. The exemplary signal amplification method includes: generating a bias voltage input according to an input signal; and amplifying the input signal through a single-stage amplifier to generate an output signal, wherein the single-stage amplifier includes a voltage-controlled current source circuit that operates in response to the bias voltage input.

[0006] According to the operational amplifier and the signal amplification method of the present invention, enhanced slew rate of the amplifier can be achieved, thereby improving the output of the amplifier.

[0007] These and other objects of the present invention will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various figures and drawings. Brief Description of the Drawings

[0008] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and, together with the specification, are used to explain the principles of the present invention. In the drawings:

[0009] Figure 1 is a schematic diagram showing an operational amplifier according to an embodiment of the present invention.

[0010] Figure 2 is a schematic diagram showing a cascode amplifier according to an embodiment of the present invention.

[0011] Figure 3 is a schematic diagram showing a current controller according to an embodiment of the present invention.

[0012] Figure 4 is a schematic diagram showing a current controller operating in a case where the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN-.

[0013] Figure 5 is a schematic diagram showing a cascode amplifier operating in a case where the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN-.

[0014] Figure 6 is a schematic diagram showing a current controller operating in a case where the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN-.

[0015] Figure 7 is a schematic diagram showing a cascode amplifier operating in a case where the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN-.

[0016] Figure 8 is a schematic diagram showing a common-mode feedback circuit according to an embodiment of the present invention. Detailed Description

[0017] In the specification and claims, certain terms are used to refer to particular components. Those of ordinary skill in the art should understand that electronic device manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in names as a way to distinguish components, but rather use the difference in functions of components as the basis for distinction. The term "comprising" mentioned throughout the specification and claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described in the text that the first device is electrically connected to the second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0018] Figure 1 It is a schematic diagram showing an operational amplifier according to an embodiment of the present invention. The operational amplifier 100 includes a single-stage amplifier 102, a current controller 104, and a common-mode feedback circuit (CMFB) 106. The common-mode feedback circuit 106 may be optional. For example, when the single-stage amplifier 102 is a single-ended amplifier, the common-mode feedback circuit 106 can be omitted. To better understand the technical features of the present invention, it is assumed hereinafter that the single-stage amplifier 102 is a fully differential amplifier.

[0019] The single-stage amplifier 102 is arranged to receive an input signal and amplify the input signal to generate an output signal. For example, the single-stage amplifier 102 is a differential amplifier, such that the input signal is a differential signal composed of a positive signal IN+ and a negative signal IN-, and the output signal is a differential signal composed of a positive signal OUT+ and a negative signal OUT-. In some embodiments of the present invention, the single-stage amplifier 102 can be implemented by a telescopic amplifier.

[0020] Figure 2 It is a schematic diagram showing a telescopic amplifier according to an embodiment of the present invention. Figure 1 The shown single-stage amplifier 102 can be implemented by Figure 2 the shown telescopic amplifier 200. As Figure 2 shown, the telescopic amplifier 200 includes P-channel metal-oxide semiconductor (PMOS) transistors MP1, MP2, MP3, MP4, MP5, MP6 and N-channel metal-oxide semiconductor (NMOS) transistors MN1, MN2, MN3, MN4, MN5, MN6. The PMOS transistors MP1, MP3, MP5 and the NMOS transistors MN1, MN3, MN5 are cascaded between two reference voltages, and the two reference voltages include a power supply voltage VDD and a ground voltage GND, where VDD > GND. In addition, the PMOS transistors MP2, MP4, MP6 and the NMOS transistors MN2, MN4, MN6 are cascaded between two reference voltages including the power supply voltage VDD and the ground voltage GND.

[0021] The source node of PMOS transistor MP1 is arranged to receive a reference voltage (e.g., power supply voltage VDD), and the gate node of PMOS transistor MP1 is arranged to receive bias voltage VTP1. The source node of PMOS transistor MP2 is arranged to receive a reference voltage (e.g., power supply voltage VDD), and the gate node of PMOS transistor MP2 is arranged to receive bias voltage VTP2. The source node of NMOS transistor MN1 is arranged to receive another reference voltage (e.g., ground voltage GND), and the gate node of NMOS transistor MN1 is arranged to receive bias voltage VTN1. The source node of NMOS transistor MN2 is arranged to receive another reference voltage (e.g., ground voltage GND), and the gate node of NMOS transistor MN2 is arranged to receive bias voltage VTN2.

[0022] The gate node of PMOS transistor MP3 is arranged to receive positive signal P+ (P+ = IN+), and the gate node of PMOS transistor MP4 is arranged to receive negative signal P- (P- = IN-), where positive signal P+ and negative signal P- form a differential signal. Additionally, the gate node of NMOS transistor MN3 is arranged to receive positive signal N+ (N+ = IN+), and the gate node of NMOS transistor MN4 is arranged to receive negative signal N- (N- = IN-), where positive signal N+ and negative signal N- form a differential signal. As Figure 1 shown, positive signals P+ and N+ are respectively obtained from the same positive signal IN+ through coupling capacitors C1 and C2, while negative signals P- and N- are obtained from the same negative signal IN- through coupling capacitors C3 and C4 respectively. Ideally, coupling capacitors C1 - C4 can be the same capacitor.

[0023] The gate nodes of PMOS transistor MP5 and NMOS transistor MN5 are arranged to receive bias voltages Vbp1 and Vbn1 respectively, and the drain nodes of PMOS transistor MP5 and NMOS transistor MN5 are both coupled to the negative signal OUT- of the differential amplifier output. Additionally, the gate nodes of PMOS transistor MP6 and NMOS transistor MN6 are arranged to receive bias voltages Vbp2 and Vbn2 respectively, and the drain nodes of PMOS transistor MP6 and NMOS transistor MN6 are both coupled to the positive signal OUT+ of the differential amplifier output.

[0024] The cascode amplifier 200 has a voltage-controlled current source 202, where the voltage-controlled current source 202 includes a top current source 204 and a tail current source 206. The voltage-controlled current source 202 operates in response to a bias voltage input, and the bias voltage includes VTP1, VTP2, VTN1, and VTN2, where the top current source 204 is controlled by the bias voltages VTP1 and VTP2, and the tail current source 206 is controlled by the bias voltages VTN1 and VTN2. In this embodiment, Figure 1 the current controller 104 shown in is coupled to the voltage-controlled current source circuit 202 and is arranged to receive an input signal (the input signal includes a positive signal IN+ and a negative signal IN-, where IN+ = P+ = N+ and IN- = P- = N-), and generate a bias voltage input (including bias voltages VTP1, VTP2, VTN1, and VTN2) according to the input signal (including the positive signal IN+ and the negative signal IN-, where IN+ = P+ = N+ and IN- = P- = N-). Therefore, the bias voltage input {VTP1, VTP2, VTN1, VTN2} is not fixed and is dynamically adjusted in response to the input signal {IN+, IN-}.

[0025] Figure 3 is a schematic diagram showing a current controller according to an embodiment of the present invention. Figure 1 The current controller 104 shown can be implemented by a current controller 300. The bias voltage input dynamically adjusted by the current controller 300 can achieve class-AB slew rate enhancement for the voltage-controlled current source circuit 202 of the cascode amplifier 200 as a single-stage amplifier.

[0026] Please refer in combination with Figure 5 to Figure 4 . Figure 4 is a schematic diagram showing the current controller 300 operating in the case where the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN-. Figure 5 is a schematic diagram showing the cascode amplifier 200 operating in the case where the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN-. Assume Figure 1 the single-stage amplifier 102 shown in is implemented by Figure 2 the cascode amplifier 200 shown, Figure 1 the current controller 104 shown is implemented by Figure 3 the current controller 300 shown.

[0027] When the voltage level of the positive signal IN+ becomes lower than the voltage level of the negative signal IN-, the voltage levels of the positive signals P+ and N+ decrease, and the voltage levels of the negative signals P- and N- increase. Therefore, since IN+ = P+ = N+, Figure 4 the voltage at the gate node of the PMOS transistor MP7 shown in Figure 4 decreases, and the voltage at the gate node of the NMOS transistor MN7 shown in Figure 4 also decreases. And since IN- = P- = N-, Figure 4 the voltage at the gate node of the PMOS transistor MP8 shown in Figure 3 or Figure 4 increases, and the voltage at the gate node of the NMOS transistor MN8 shown in

[0028] also increases. The current flowing through the PMOS transistor MP7 increases, while the PMOS transistor MP8 is turned off. Additionally, the current flowing through the NMOS transistor MN8 increases, while the NMOS transistor MN7 is turned off. Therefore, the bias voltages VTP1 and VTN1 are pushed up, and the bias voltages VTP2 and VTN2 are pulled down. In short, when the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN-, the current controller 300 is arranged to increase the bias voltages VTP1 and VTN1 and decrease the bias voltages VTP2 and VTN2. Note that the specific structure of the current controller 300 provided here is not a limitation of the present invention. As long as the above functions can be achieved, those skilled in the art can adopt any suitable circuit structure or can make any appropriate changes or modifications to the Figure 5As shown, due to the increase in the bias voltage VTP1, the PMOS transistor MP1 can be turned off; due to the increase in the voltage of the negative signal P-, the PMOS transistor MP4 can be turned off; due to the decrease in the voltage of the positive signal N+, the NMOS transistor MN3 can be turned off; due to the decrease in the bias voltage VTN2, the NMOS transistor MN2 can be turned off. Due to the decrease in the bias voltage VTP2 at the gate node of the PMOS transistor MP2 and the decrease in the voltage of the positive signal P+ at the gate node of the PMOS transistor MP3, the output node of the negative signal OUT- can draw a large current IP1 from the power supply voltage VDD. Additionally, due to the increase in the bias voltage VTN1 at the gate node of the NMOS transistor MN1 and the increase in the voltage of the negative signal N- at the gate node of the NMOS transistor MN4, a large current IN1 can be drawn from the output node of the positive signal OUT+ to the ground voltage GND. The bias voltages VTP1, VTP2, VTN1, and VTN2 are not fixed but are dynamically adjusted by the current controller 300. With the aid of the current controller 300, large currents IP1 and IN1 can be provided to enhance the slew rate of the telescopic amplifier 200 when the voltage level of the positive signal IN+ is lower than the voltage level of the negative signal IN-.

[0029] Please refer to Figure 7 for reference Figure 6 , Figure 6 which is a schematic diagram showing the current controller 300 operating when the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN-. Figure 7 which is a schematic diagram showing the telescopic amplifier 200 operating when the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN-. Assume that Figure 1 the single-stage amplifier 102 shown is implemented by Figure 2 the telescopic amplifier 200 shown, Figure 1 and the current controller 104 shown is implemented by Figure 3 the current controller 300 shown. When the voltage level of the positive signal IN+ becomes higher than the voltage level of the negative signal IN-, the voltage levels of the positive signal P+ and the positive signal N+ increase, and the voltage levels of the negative signal P- and the negative signal N- decrease. Therefore, since IN+ = P+ = N+, Figure 6 the voltage at the gate node of the PMOS transistor MP7 shown increases and Figure 6 the voltage at the gate node of the NMOS transistor MN7 shown increases; and since IN- = P- = N-, Figure 6 the voltage at the gate node of the PMOS transistor MP8 shown decreases and Figure 6The voltage at the gate node of the NMOS transistor MN8 shown decreases. The current flowing through the PMOS transistor MP8 increases, while the PMOS transistor MP7 can be turned off. Additionally, the current flowing through the NMOS transistor MN7 increases, while the NMOS transistor MN8 can be turned off. As a result, the bias voltages VTP1 and VTN1 are pulled down, while the bias voltages VTP2 and VTN2 are pushed up. In short, when the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN-, the current controller 300 is arranged to decrease the bias voltages VTP1 and VTN1 and increase the bias voltages VTP2 and VTN2. Note that the specific structure of the current controller 300 provided here is not a limitation of the present invention. As long as the above functions can be achieved, those skilled in the art can adopt any suitable circuit structure or can make any appropriate changes or modifications to Figure 3 or Figure 6 the current controller shown.

[0030] As Figure 7 shown, due to the increase in the bias voltage VTP2, the PMOS transistor MP2 can be turned off; due to the increase in the voltage of the positive signal P+, the PMOS transistor MP3 can be turned off; due to the decrease in the voltage of the negative signal N-, the NMOS transistor MN4 can be turned off; due to the decrease in the bias voltage VTN1, the NMOS transistor MN1 can be turned off. Due to the decrease in the bias voltage VTP1 at the gate node of the PMOS transistor MP1 and the decrease in the voltage of the negative signal P- at the gate node of the PMOS transistor MP4, the output node of the positive signal OUT+ can draw a large current IP2 from the power supply voltage VDD. Additionally, due to the increase in the bias voltage VTN2 at the gate node of the NMOS transistor MN2 and the increase in the voltage of the positive signal N+ at the gate node of the NMOS transistor MN3, a large current IN2 can be drawn from the output node of the negative signal OUT- to the ground voltage GND. The bias voltages VTP1, VTP2, VTN1, and VTN2 are not fixed but are dynamically adjusted by the current controller 300. With the help of the current controller 300, large currents IP2 and IN2 can be provided to enhance the slew rate of the telescopic amplifier 200 when the voltage level of the positive signal IN+ is higher than the voltage level of the negative signal IN-.

[0031] In this embodiment, Figure 2 the PMOS transistors MP1, MP2 and the NMOS transistors MN1, MN2 shown in Figure 3 are biased via the floating gate current source of the current controller 300 shown. As Figure 5 and Figure 7As shown, the class-AB control includes PMOS transistors MP3, MP4 and NMOS transistors MN3, MN4, and operates in response to input signals {IN+ = P+ = N+, IN- = P- = N-}. As Figure 4 and Figure 6 shown, the floating-gate current source includes PMOS transistors MP7, MP8 and NMOS transistors MN7, MN8, and operates in response to input signals {IN+ = P+ = N+, IN- = P- = N-}. The floating-gate current source has the same structure and the same power-supply voltage dependence as the class-AB control, resulting in the static currents of PMOS transistors MP1, MP2 and NMOS transistors MN1, MN2 being independent of the power-supply voltage.

[0032] When the single-stage amplifier 102 is implemented by a fully differential amplifier, a common-mode feedback circuit 106 can be employed to minimize the offset of the common-mode voltage of the differential output {OUT+, OUT-} generated by the single-stage amplifier 102. Figure 8 is a schematic diagram showing a common-mode feedback circuit according to an embodiment of the present invention. Figure 1 The shown common-mode feedback circuit 106 can be implemented by a common-mode feedback circuit 800. The common-mode feedback circuit 800 is arranged to monitor the common-mode voltage of the positive signal OUT+ and the negative signal OUT-, and compare the common-mode voltage with a reference voltage VCM to generate a feedback control voltage VFBP. For example, the reference voltage VCM can be equal to half of the power-supply voltage VDD. Considering the case where the current controller 104 is implemented by Figure 3 the shown current controller 300, the current controller 300 includes a PMOS transistor MP9, and the gate node of the PMOS transistor MP9 is arranged to receive the feedback control voltage VFBP generated from the common-mode feedback circuit 800. In other words, the current controller 300 is further arranged to receive the feedback control voltage VFBP and affect the bias voltage inputs {VTP1, VTP2, VTN1, VTN2} in response to the feedback control voltage VFBP.

[0033] Considering the case where the common-mode voltage is higher than the reference voltage VCM, the feedback control voltage VFBP is reduced by the common-mode feedback circuit 800, and the current flowing through the PMOS transistor MP9 of the current controller 300 increases, thereby further increasing the bias voltages VTP1, VTP2, VTN1 and VTN2. Regarding Figure 5 the shown scenario, the current IP1 flowing through the PMOS transistor MP2 decreases, while the current IN1 flowing through the NMOS transistor MN4 increases. Regarding Figure 7 the shown scenario, the current IP2 flowing through the PMOS transistor MP1 decreases, while the current IN2 flowing through the NMOS transistor MN2 increases. In each case, the common-mode voltage is reduced.

[0034] Consider another case where the common-mode voltage is lower than the reference voltage VCM. The feedback control voltage VFBP is increased by the common-mode feedback circuit 800, and the current flowing through the PMOS transistor MP9 of the current controller 300 is reduced, thereby further reducing the bias voltages VTP1, VTP2, VTN1, and VTN2. Regarding Figure 5 the scenario shown, the current IP1 flowing through the PMOS transistor MP2 increases, while the current IN1 flowing through the NMOS transistor MN4 decreases. Regarding Figure 7 the scenario shown in, the current IP2 flowing through the PMOS transistor MP1 increases, while the current IN2 flowing through the NMOS transistor MN2 decreases. In each case, the common-mode voltage increases.

[0035] The common-mode feedback circuit 800 may include an optional Miller compensation circuit coupled between the output signals {OUT+, OUT-} and the bias voltage inputs {VTP1, VTP2, VTN1, VTN2} for stability compensation of the common-mode feedback loop. In this embodiment, the Miller compensation circuit may include Miller capacitors CM5, CM6, CM7, CM8, CM9, CM10, CM11, and CM12. Additionally, Miller compensation may be applied to the single-stage amplifier 102 by using Miller capacitors CM1, CM2, CM3, and CM4 as shown in Figure 1 . However, these are for illustrative purposes only and do not imply a limitation of the present invention.

[0036] For a typical single-stage amplifier without the proposed class-AB slew-rate enhancement scheme, it can achieve a high signal-to-noise and distortion ratio (SDNR) (e.g., 106 dB) by consuming a large amount of static current (e.g., 4000 uA). Compared with a typical single-stage amplifier, the operational amplifier 100 of the present invention (including the single-stage amplifier 102 with the proposed class-AB slew-rate enhancement scheme) can achieve a higher SDNR (e.g., 110 dB) by consuming less static current (e.g., 740 uA), where the static current of the single-stage amplifier 102 can be 640 uA, and the static current of the current controller 104 can be 100 uA.

[0037] Those skilled in the art will readily recognize that various modifications and alterations can be made to the apparatus and method while maintaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the bounds of the appended claims.

Claims

1. An operational amplifier, comprising: A single-stage amplifier arranged to receive an input signal and amplify the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage-controlled current source circuit that operates in response to a bias voltage input; and A current controller coupled to the voltage-controlled current source circuit, wherein the current controller receives the input signal and generates the bias voltage input according to the input signal; Wherein the bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage, and the voltage-controlled current source circuit includes a top current source coupled to the first bias voltage and the second bias voltage and a bottom current source coupled to the third bias voltage and the fourth bias voltage; Wherein the top current source includes: A first P-channel metal-oxide-semiconductor (PMOS) transistor whose gate node receives the first bias voltage and whose source node receives a first reference voltage; and A second PMOS transistor whose gate node receives the second bias voltage and whose source node receives the first reference voltage; Wherein the bottom current source includes: A first N-channel metal-oxide-semiconductor (NMOS) transistor whose gate node receives the third bias voltage and whose source node receives a second reference voltage, wherein the second reference voltage is lower than the first reference voltage; and A second NMOS transistor whose gate node receives the fourth bias voltage and whose source node receives the second reference voltage.

2. The operational amplifier according to claim 1, characterized in that, The bias voltage input dynamically adjusted by the current controller enables the voltage-controlled current source circuit to achieve class-AB slew rate enhancement.

3. The operational amplifier according to claim 1, characterized in that, The single-stage amplifier is a cascode amplifier.

4. The operational amplifier according to claim 3, wherein The input signal is a differential signal including a positive signal and a negative signal; when the voltage level of the positive signal is lower than the voltage level of the negative signal, the current controller is arranged to increase the first bias voltage and the third bias voltage and decrease the second bias voltage and the fourth bias voltage; When the voltage level of the positive signal is higher than the voltage level of the negative signal, the current controller is arranged to decrease the first bias voltage and the third bias voltage and increase the second bias voltage and the fourth bias voltage.

5. The operational amplifier according to claim 1, characterized in that, The output signal is a differential signal including a positive signal and a negative signal; the operational amplifier further includes: A common-mode feedback circuit arranged to monitor the common-mode voltage of the positive signal and the negative signal and compare the common-mode voltage with a reference voltage to generate a feedback control voltage, wherein the current controller is further configured to receive the feedback control voltage and affect the bias voltage input in response to the feedback control voltage.

6. The operational amplifier according to claim 5, wherein The common-mode feedback circuit further includes: A Miller compensation circuit coupled between the output signal and the bias voltage input.

7. A signal amplification method, comprising: Generating a bias voltage input according to an input signal; And Amplifying the input signal through a single-stage amplifier to generate an output signal, wherein the single-stage amplifier includes a voltage-controlled current source circuit that operates in response to the bias voltage input. Among them, the bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. The voltage-controlled current source circuit includes a top current source coupled to the first bias voltage and the second bias voltage, and a bottom current source coupled to the third bias voltage and the fourth bias voltage; Among them, the top current source includes: A first P-channel metal-oxide-semiconductor (PMOS) transistor, whose gate node receives the first bias voltage and whose source node receives a first reference voltage; and A second PMOS transistor, whose gate node receives the second bias voltage and whose source node receives the first reference voltage; Among them, the bottom current source includes: A first N-channel metal-oxide-semiconductor (NMOS) transistor, whose gate node receives the third bias voltage and whose source node receives a second reference voltage, where the second reference voltage is lower than the first reference voltage; and A second NMOS transistor, whose gate node receives the fourth bias voltage and whose source node receives the second reference voltage.

8. The signal amplification method according to claim 7, wherein In response to the input signal, the bias voltage input is dynamically adjusted so that the voltage-controlled current source circuit can achieve class-AB slew rate enhancement.

9. The signal amplification method according to claim 7, wherein The single-stage amplifier is a cascode amplifier.

10. The signal amplification method according to claim 9, wherein The input signal is a differential signal including a positive signal and a negative signal; The step of generating the bias voltage input according to the input signal includes: When the voltage level of the positive signal is lower than the voltage level of the negative signal, increasing the first bias voltage and the third bias voltage, and decreasing the second bias voltage and the fourth bias voltage; and When the voltage level of the positive signal is higher than the voltage level of the negative signal, decreasing the first bias voltage and the third bias voltage, and increasing the second bias voltage and the fourth bias voltage.

11. The signal amplification method according to claim 7, wherein The output signal is a differential signal including a positive signal and a negative signal; The signal amplification method further includes: Monitoring the common-mode voltage of the positive signal and the negative signal; and Comparing the common-mode voltage with a reference voltage to generate a feedback control voltage, where the generation of the bias voltage input is affected by the feedback control voltage.

12. The signal amplification method according to claim 11, wherein It further includes: Providing Miller compensation between the output signal and the bias voltage input.

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