Integrated circuit chip and device including the integrated circuit chip

Abstract

The present invention provides an integrated circuit chip and a device including the integrated circuit chip. The integrated circuit chip includes: a first on-chip oscillator for generating a first oscillator clock signal, the first oscillator clock signal having a relatively accurate frequency and a relatively high degree of jitter; a second on-chip oscillator for generating a second oscillator clock signal, the second oscillator clock signal having a relatively low degree of jitter and a relatively inaccurate frequency; and a clock generator for generating an output clock signal from the first oscillator clock signal and the second oscillator clock signal, so that the output clock signal has the jitter characteristics of the second oscillator clock signal over a frequency range and the frequency accuracy of the first oscillator clock signal.

Description

[0001] This application is a divisional application of the invention patent application with the application date of November 20, 2012, application number 201280067552.3, and title “Clock Generator”. This application is filed for the divisional application with the application date of November 20, 2012, application number 201710702456.6, and title “Integrated Circuit, Device Including Integrated Circuit, and Integrated Circuit Chip”. Technical Field

[0002] The present invention relates to a frequency locked loop and in particular to a frequency locked loop suitable for use as a clock generator in the form of an integrated circuit. Background Art

[0003] It is known to use a frequency locked loop (FLL) to generate a clock signal at a frequency that is a multiple of the frequency of an existing (input) clock signal. For example, a high frequency output clock is used to clock a counter. At the edge of the existing clock signal, the accumulated count is latched and the counter is reset. Therefore, the count represents the ratio of the frequency of the output clock to the frequency of the existing clock. This ratio is subtracted from the input value representing the ideal ratio, and the frequency error signal obtained thereby is fed to a filter. The filter integrates the frequency error to produce an integrated error signal, which is used to drive a numerically controlled oscillator, and the output of the numerically controlled oscillator is fed back as a high frequency output clock to clock the counter. The output clock that is fed back means that if the frequency of the output clock becomes higher than the ideal frequency, a negative frequency error signal is generated, resulting in a reduction in the output frequency. Conversely, if the frequency of the output clock becomes lower than the ideal frequency, a positive frequency error signal is generated, resulting in an increase in the output frequency. Therefore, the frequency of the generated clock converges to the ideal frequency.

[0004] One application of such a frequency locked loop is in digital audio signal processing or reproduction circuitry, and in host devices employing such circuitry, including but not limited to portable electronic devices, mobile phones, personal digital assistants, netbooks, laptops, tablet computers, computers. For high quality audio reproduction, it is important that the clock driving the output digital-to-analog converter has low jitter (especially within the audio frequency band) to avoid noise, distortion or spurious tones. The clock accompanying the input data may not be of high quality due to poor quality clock sources or degradation along the transmission channel, and the clock used for signal processing may need to be a multiple of the data transmission clock.

[0005] Furthermore, the generated clock must be tightly synchronized with the incoming data: any accumulated clock slip will result in dropped samples or gaps in the data to be processed.

[0006] Furthermore, in some applications, the clock may be intermittent, perhaps because data is transmitted in bursts. Or, the clock source may change when the mode of the host device is changed to serve different usage scenarios and save any unnecessary power consumption. However, any such clock transitions should be imperceptible in the reproduced audio.

[0007] Also preferably, for an economical implementation in integrated circuit form, there should be as few external components as possible, such as large capacitors: a predominantly digital solution is ideal. Summary of the invention

[0008] According to a first aspect of the present invention, there is provided a clock generator for generating an output clock signal, the clock generator comprising:

[0009] A first clock signal input, for receiving a first input clock signal;

[0010] a first frequency comparator, configured to generate a first frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the first input clock signal;

[0011] a first subtractor for forming a first error signal representing a difference between an input ideal frequency ratio and the first frequency comparison signal;

[0012] a first digital filter for receiving the first error signal and forming a filtered first error signal;

[0013] A second clock signal input, for receiving a second input clock signal;

[0014] a second frequency comparator, configured to generate a second frequency comparison signal based on a ratio of a frequency of the output clock signal to a frequency of the second input clock signal;

[0015] a second subtractor for forming a second error signal representing a difference between the filtered first error signal and the second frequency comparison signal;

[0016] a second digital filter for receiving the second error signal and forming a filtered second error signal; and

[0017] A numerically controlled oscillator is configured to receive the filtered second error signal and generate the output clock signal.

[0018] According to a second aspect of the present invention, there is provided an audio processing integrated circuit, comprising:

[0019] at least one digital audio interface for receiving digital audio data and an accompanying audio data clock;

[0020] a digital-to-analog converter for reconstructing analog audio data based on the received digital audio data; and

[0021] According to the clock generator of the first aspect, the audio data clock is supplied to the clock generator as a first input clock signal, and an output clock signal of the clock generator is used as a clock of the digital-analog converter.

[0022] According to a third aspect of the present invention, there is provided a device, the device comprising the audio processing integrated circuit according to the second aspect, and further comprising:

[0023] a communications processor for receiving a cellular call, the processor being coupled to the at least one digital audio interface via a digital audio bus; and / or

[0024] an application processor for retrieving audio data from a local memory, the processor being coupled to the at least one digital audio interface via a digital audio bus; and / or

[0025] A wireless modem for transmitting and / or receiving audio data from a peripheral device, the modem being coupled to the at least one digital audio interface via a digital audio bus.

[0026] According to a fourth aspect of the present invention, there is provided an integrated circuit, comprising:

[0027] The clock generator according to the first aspect;

[0028] a first oscillator for generating a first oscillator clock signal and connected to a first clock signal input of the clock generator; and

[0029] a second oscillator for generating a second oscillator clock signal and connected to a second clock signal input of the clock generator,

[0030] The first oscillator and the second oscillator are configured such that the first oscillator clock signal has lower jitter than the second oscillator clock signal, and the second clock signal has higher frequency accuracy than the first oscillator clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] For a better understanding of the invention, and to show how it may be put into practice, reference will now be made, by way of example, to the accompanying drawings, in which:

[0032] Figure 1 is a schematic diagram illustrating the general form of a frequency generator according to the present invention;

[0033] Figure 2 In more detail, Figure 1The frequency generator shown in ;

[0034] Figure 3 is a frequency curve diagram, showing Figure 2 The performance of the frequency generator;

[0035] Figure 4 A first alternative frequency generator according to the invention is shown;

[0036] Figure 5 A second alternative frequency generator according to the present invention is shown;

[0037] Figure 6 A third alternative frequency generator according to the present invention is shown;

[0038] Figure 7(a) , 7(b) 7(c), 7(d), 7(e) and 7(f) show in more detail possible forms of the numerically controlled oscillator in the frequency generator according to the present invention;

[0039] Figure 8 A first system comprising a frequency generator according to the invention is shown;

[0040] Fig. 9 Show Figure 8 A first possible form of a delta-sigma modulator in a system of;

[0041] Fig.10 Show Figure 8 A second possible form of a delta-sigma modulator in a system of;

[0042] Fig.11 Show Figure 8 A third possible form of a delta-sigma modulator in a system of;

[0043] Fig.12 showing a first known audio processing channel;

[0044] Fig.13 showing a second known audio processing channel;

[0045] Fig.14 shows an audio processing channel comprising a frequency generator according to the invention;

[0046] Fig.15 A second system comprising a frequency generator according to the invention is shown;

[0047] Fig.16 A third system comprising a frequency generator according to the invention is shown;

[0048] Fig.17 A fourth system comprising a frequency generator according to the invention is shown;

[0049] Fig.18 A fifth system is shown which comprises a frequency generator according to the invention. DETAILED DESCRIPTION

[0050] Figure 1 A clock generator (or equivalently, a frequency generator or frequency synthesizer) 10 is shown, which operates using the principle of a frequency locked loop. The clock generator 10 may be provided, for example, in the form of an integrated circuit, or may be provided as a functional module that is part of a larger integrated circuit. The clock generator 10 receives a first input clock signal DCK having a frequency f and a second input clock signal RCK and generates an output clock signal CKout. DCK , the second input clock signal RCK has a frequency f RCK , the output clock signal CKout has a frequency f CKout The clock generator 10 also receives an input value or frequency control word P at the frequency control input FC, which input value or frequency control word P represents the ideal value of the ratio of the frequency of the output clock signal CKout and the frequency of the first input clock signal DCK. CKout The output clock signal CKout is at an available frequency f DCK In the case of a clock signal DCK, the value of P is set equal to f CKout / f DCK .

[0051] The output clock signal CKout is applied to the clock input (CK) of the first counter 12, acting as a first frequency detector or a first frequency comparator. The first input clock signal DCK is applied to the reset (RST) input of the first counter 12. Therefore, the first counter 12 counts the number of pulses of the output clock signal CKout generated in each pulse of the first input clock signal DCK, and the count value CNT1 output from the first counter 12 is a first frequency comparison signal, which represents the ratio of the frequency of the output clock signal CKout and the first input clock signal DCK, that is, CNT1=f CKout / f DCK .

[0052] The input value P input at the frequency control input FC is applied to the first input of the first subtractor 14, and the count value CNT1 (i.e., the first frequency comparison signal) output from the first counter 12 is applied to the second input of the subtractor 14. The resulting first error signal Merr1 is applied to the input (IN) of the first digital filter 16, which is clocked by the first input clock signal DCK, and generates a filtered first error signal Nerr1 at its output (OUT). The first digital filter 16 can be an integrator or some other type of low-pass filter with a higher gain at low frequencies and a lower gain at higher frequencies.

[0053] The output clock signal CKout is also applied to the clock input (CK) of the second counter 18, acting as a second frequency detector or a second frequency comparator. The second input clock signal RCK is applied to the reset input (RST) of the second counter 18. Therefore, the second counter 18 counts the number of pulses of the output clock signal CKout generated in each pulse of the second input clock signal RCK, and the count value CNT2 output from the second counter 18 is a second frequency comparison signal, which represents the ratio of the frequency of the output clock signal CKout and the second input clock signal RCK, that is, CNT2=f CKout / f RCK .

[0054] The filtered first error signal Nerr1 is applied to the first input of the second subtractor 20, and the count value CNT2 (i.e., the second frequency comparison signal) output from the second counter 18 is applied to the second input of the second subtractor 20. The second error signal Merr2 obtained as a result is applied to the input (IN) of the second digital filter 22, which is clocked by the second input clock signal RCK, and generates the filtered second error signal Nerr2 at its output (OUT). The second digital filter 22 can be an integrator with a higher gain at low frequencies and a lower gain at higher frequencies, or some other type of low-pass filter.

[0055] The filtered second error signal Nerr2 is transmitted to a numerically controlled oscillator (NCO) 24 which generates an output clock signal CKout in dependence on its input signal Nerr2.

[0056] In some embodiments, the digital filters 16 and 22 are integrators or other types of low-pass filters that have a higher gain at low frequencies than at higher frequencies. Therefore, for bounded output values, the average input value of each integrator must be close to zero. The operation of the frequency generator 10 can be understood by considering that in the steady state, the feedback loop must operate so that the output signal Merr1 of the first subtractor 14 tends to zero, that is, so that:

[0057] Merr1=P-CNT1=0, that is,

[0058] P = f CKout / f DCK ,or

[0059] f CKout =P·f DCK

[0060] In this embodiment, the value of P is constant, or changes at least relatively slowly over time compared to either the generated frequency or the loop bandwidth, so that the output clock f CKout The frequency tracks a slowly changing desired value.

[0061] Similarly, it can be shown that:

[0062] Merr2=Nerr1-CNT2=0, that is,

[0063] Nerr1=f CKout / f RCK ,

[0064] That is, the output of the integrator settles to an average value equal to f CKout / f RCK .

[0065] In steady state, the output of the second filter 22 will settle to the value required by the NCO 24 to provide the desired frequency P·f at CKout. DCK .

[0066] Figure 2 The form of frequency generator 10 is shown in greater detail in one specific embodiment.

[0067] like Figure 2As shown in FIG. 1 , the first counter 12 includes a delay element 30, which is clocked by the output clock CKout, with the result that for each pulse of the output clock CKout, the adder 32 adds the received value +1 to the current count value. A multi-bit storage register 34 (drawn as a single-bit D-type flip-flop for simplicity) receives the current count value in each time period, and latches and outputs the accumulated count to the first subtractor 14 at each rising edge of the first input clock DCK. At the same time, the rising edge of the first input clock DCK controls the multiplexer 36 so that the value 0 is transmitted to the adder 32. This resets the counter value of the first counter 12 to zero until the next CKout pulse arrives.

[0068] There are many possible implementations of this counter module 12: for example, the multiplexer can be omitted so that the output of the delay module increases continuously, and then the previously delivered output value is subtracted at each rising edge of the first input clock DCK. Of course, this module and other modules can be designed to be triggered at a falling edge instead of a rising edge.

[0069] Therefore, the accumulated count value CNT1 (ie, the first frequency comparison signal) output to the first subtractor 14 is the number of pulses of the output clock CKout for each cycle of the first input clock DCK, and is made available to the subtractor 14 whenever necessary.

[0070] Similarly, the second counter 18 may include a delay element 40, which is clocked by the output clock CKout, with the result that the adder 42 adds the received value +1 to the current count value for each pulse of the output clock CKout. The multi-bit storage register 44 receives the current count value in each time period, and latches the accumulated count at each rising edge of the second input clock RCK, i.e., outputs it to the second subtractor 20. At the same time, the rising edge of the second input clock RCK controls the multiplexer 46 so that the value 0 is passed to the adder 42. This resets the counter value of the second counter 18. In addition, alternative embodiments of suitable counters are also possible.

[0071] Therefore, the accumulated count value CNT2 (ie, the second frequency comparison signal) output to the second subtractor 20 is the number of pulses of the output clock CKout for each cycle of the second input clock RCK, and is made available to the second subtractor 20 whenever necessary.

[0072] exist Figure 2In the embodiment shown in FIG. 1 , the first filter 16 takes the form of an integrator, comprising an adder 50, a delay element 52 (which is clocked by a first input clock DCK) and a multiplier 53, with the result that during each cycle of the first input clock DCK, the value Merr1 received from the first subtractor 14 is added to the previous running total output from the delay element 52 to form a new running total, which is then scaled by a factor γ1 to form a new filter output value Nerr1. The multiplier may simply be a bit shifter to implement 2 N A scaling factor of the form γ1, or some other simple "shift-and-add" structure to achieve 2 N1 +2 N2 A scaling factor γ1 of the form or a similar form is used, rather than a full multiplier, as is known.

[0073] Similarly, the second filter 22 takes the form of an integrator of similar structure, including an adder 60, a delay element 62 (which is clocked by the second input clock RCK), and a multiplier 63, as a result of which, during each cycle of the second input clock RCK, the value Merr2 received from the second subtractor 20 is added to the previous running total output from the delay element 62 to form a new running total, which is then scaled by a factor of γ2 to form a new filter output value Nerr2.

[0074] like Figure 2 As shown in FIG. , the numerically controlled oscillator (NCO) 24 may include a digital-to-analog converter (DAC) 70 and a voltage controlled oscillator (VCO) 72, and thus the numerically controlled oscillator generates an output signal CKout at a frequency corresponding to the value output by the second integrator.

[0075] In this illustrated embodiment, the first integrator is designed to have a much lower gain (ie, a longer time constant) than the second integrator.

[0076] Figure 3 is a frequency curve diagram, illustrating Figure 2 80 represents the jitter transfer function from the DCK input to the NCO output CKout, i.e., any jitter present at the DCK input at a particular frequency is scaled by a factor when it reaches the output CKout. Similarly, curve 82 represents the jitter transfer function from the RCK input to the NCO output CKout, while curve 84 represents the jitter transfer function from the input of the NCO 24 to its output CKout.

[0077] The break point is defined by the unity gain frequency of the first and second integrators. More specifically, the break point f of the transfer function from DCK input to NCO output CKout (ie, curve 80) is 80 By 80 =f(DCK)*γ1 / 2π, where γ1 is the gain of the first integrator; and the turning point f of the transfer function from RCK input to NCO output CKout (ie, curve 82) is 82 By 82 =f(RCK)*γ2 / 2π, where γ2 is the gain of the second integrator.

[0078] In this embodiment, the gain values ​​are set so that: 80 is at about 2Hz (12rad / s), and the turning point f 82 It is at about 20kHz (120krad / s).

[0079] Because the integrators are all first-order integrators, the slopes of the jitter transfer functions 80, 82, and 84 are approximately 20 dB / decade, except that the NCO transfer function 84 has a lower turning point f 80 The following has a slope of 40dB / decade, and the RCK transfer function 80 has an upper turning point f 82 The above has a slope of negative 40dB / decade.

[0080] Therefore, at the middle jitter frequency - at the two turning points f 80 and f 82 The long time constant of the first integrator will tend to keep the output Nerr1 of the first integrator constant, and therefore very little jitter from the first clock signal DCK will propagate to the output, while the second integrator will have a high gain, and therefore the feedback loop including the second integrator and the frequency comparator 18 will control the NCO 24 so that the output CKout of the NCO 24 follows the second clock signal RCK regardless of the inherent jitter of the NCO 24.

[0081] Thus, at these intermediate frequencies, jitter on the output clock CKout will tend to track jitter on the second clock signal RCK, while jitter on the first clock signal DCK will be attenuated by 6 dB at 4 Hz, and even more at higher frequencies.

[0082] As a result, in Figure 2The circuit shown in is particularly useful for situations where there are two clock signals available, one of which has a frequency that is desired to be used as a basis for generating the output clock signal CKout, but which has relatively low quality (i.e., it has relatively high jitter), while the other clock signal has relatively high quality (low jitter) but has an inappropriate frequency. In that case, the relatively high jitter clock signal can be used as the first input clock signal DCK to the circuit 10, and the relatively low jitter clock signal can be used as the second input clock signal RCK.

[0083] This means that by appropriately choosing the value of P the output clock signal CKout can be generated from the first input clock signal DCK with an ideally accurate frequency ratio, but it also means that the jitter on the output clock signal CKout (within the frequency band of interest) depends only on the low level of jitter on the high quality second input clock signal RCK, provided that the gain of the integrator is appropriately set.

[0084] As mentioned above, in the illustrated embodiment, the first integrator is designed to have a much longer time constant than the second integrator. However, the first integrator may have a shorter time constant than the second integrator.

[0085] As mentioned above, the integrators are all first order integrators in this embodiment. However, it will be appreciated that higher order integrators may be used, or indeed other filters that depend on the expected jitter spectrum of the input clock or the desired jitter spectrum at the output. For example, it may be desirable to notch out known interfering frequencies, in which case filter 16 may be a notch filter, while filter 22 is a bandpass filter, with parameters designed to maintain stability of both feedback loops.

[0086] As described above, the integrator settles to a value equal to f CKout / f RCK At start-up, typically all circuitry will be reset to zero, so such a low bandwidth integrator may take some time to ramp up to the required value.

[0087] Figure 4 An alternative frequency generator 90 is shown in which many of the component modules are the same as those of the frequency generator 10. These component modules are Figure 4 In and Figure 1 and Figure 2 The same reference numerals are used for the same embodiments and no further description is given.

[0088] exist Figure 4In the frequency generator 90 shown in FIG. 1 , the count (CNT2) output of the second counter 18 is applied to the first input of the third subtractor 92 and is compared with f CKout / f RCK The input value Q equal to the expected value or nominal value of is applied to the second input of the third subtractor 92 to be subtracted from CNT2. As a result of this subtraction, a frequency comparison signal CNT2X is obtained and applied to the second subtractor 20 to be subtracted from the filtered error signal Nerr1.

[0089] In operation, the output value CNT2 of the second counter 18 must still be equal to f on average. CKout / f RCK , but if RCK is close to the desired frequency, subtracting Q from CNT2 will give a value close to 0. The new error signal CNT2X forwarded to the second subtractor will now be small, so the first integrator only needs to ramp up to settle to a much smaller value, i.e., just the error in the estimated Q (f CKout / f RCK -Q), rather than the full amount of Q. Therefore, the time taken to settle to an acceptable accuracy can be greatly reduced.

[0090] As an equivalent alternative, the second counter 18 may be preset to a count value of -Q so that it subsequently ramps up to a value close to zero during each RCLK cycle, rather than using an explicit subtractor 92. As another equivalent alternative, the output of the integrator may be preset to Q at start-up.

[0091] Figure 5 Another alternative frequency generator 110 is shown, in which many of the component modules are the same as the component modules of the frequency generator 10. These component modules are Figure 5 In and Figure 1 and Figure 2 The same reference numerals are used for the same embodiments and no further description is given.

[0092] exist Figure 5 In the frequency generator 110 shown in FIG. 1 , the output clock CKout is not directly transmitted to the first counter 12 and the second counter 18, but is transmitted through the common frequency divider 116 and then respectively through the first frequency divider 112 and the second frequency divider 114. The common frequency divider 116 receives the common frequency division ratio N0 and generates a frequency signal at a frequency f CKout The first frequency divider 112 receives the first frequency division ratio N1 and generates a common divided clock signal CKout0 at a frequency f CKout / N0N1 generates a first divided clock signal CKout1, and the first frequency divider supplies the first divided clock signal to the clock (CK) input of the first counter 12. Similarly, the second frequency divider 114 receives the second frequency division ratio N2 and generates a first divided clock signal CKout1 at a frequency f CKout / N0N2 generates a second divided clock signal CKout2, and the second frequency divider supplies the second divided clock signal to the clock (CK) input of the second counter 18.

[0093] The common frequency divider 116, the first frequency divider 112 and the second frequency divider 114 may be fixed frequency dividers and they have the effect that the first counter 12 and the second counter 18 may run more slowly than if they were directly supplied with the output clock CKout, which has the advantage that power consumption is reduced and that the counters 12, 18 are only required to be able to count to smaller values ​​without seriously affecting the frequency f of the output clock CKout. CKout If required, the common divided clock signal CKout0, the first divided clock signal CKout1 and / or the second divided clock signal CKout2 can be provided as clock signals to other modules of a larger circuit. Depending on the requirements, one or more of the dividers 112, 114, 116 may be unnecessary and omitted.

[0094] Alternatively, one or more of these dividers may be configurable during operation by changing the values ​​of N1 and / or N2 to provide different input clock frequencies for different operating modes or different system requirements. The dividers may be implemented as multiple chains of "devided-by-2 stages" to implement 2 N The frequency division ratio may be in the form of a counter or may be a counter including decoding and appropriate reset logic or other similar techniques as is known.

[0095] In some applications, one or both of the input clock signals (DCK, RCK) may not always be present. It would be desirable to still maintain some output clocks in the above situations to allow at least some of the various parts of the host system to continue to operate.

[0096] In the embodiment described above, if the first input clock signal DCK disappears, while the second input clock signal RCK is still present, the filtered error signal Nerr1 becomes constant, and the NCO 24 is controlled only by the loop including the second counter 18. This loop will keep the output frequency at a frequency based on the frozen value of Nerr1 and the frequency of RCK.

[0097] Alternatively, if in the embodiment described above, the second input clock signal RCK disappears, the second digital filter 22 will become unlocked, and thus the output Nerr2 of the filter will remain at its last value. This will cause the NCO output frequency to become constant, at a frequency corresponding to this value.

[0098] Figure 6 Another alternative frequency generator 130 is shown, in which many of the component modules are the same as the component modules of the frequency generator 10. These component modules are Figure 6 In Figure 1 and Figure 2 The same reference numerals are used for the components and will not be described further.

[0099] exist Figure 6 In the frequency generator 130 shown in FIG. 1 , a first clock detector 132 is connected to an input receiving a first clock signal DCK and is used to control a first limiter module 134. Similarly, a second clock detector 136 is connected to an input receiving a second clock signal RCK and is used to control a second limiter module 138.

[0100] Clock detectors 132, 136 and limiter modules 134, 138 are provided to handle problems that may arise if an input clock becomes temporarily unavailable. For example, if the first clock signal DCK disappears, it may have a slightly different frequency when it reappears (perhaps because the frequency of the upstream clock generator has drifted with temperature changes, or perhaps even because the signal is being obtained from a different clock source). If the second clock RCK disappears, the NCO 24 operates in an open loop for a period of time, and the frequency of the NCO 24 may have drifted by the time the RCK signal reappears. The step change in the effective input clock frequency caused by the sudden re-imposition of the clock may result in a large step transient in the frequency comparison signal, which may stimulate the feedback loop to produce a significant output frequency transient overshoot.

[0101] exist Figure 6 The frequency generator 130 shown in FIG. 1 helps alleviate these problems because the clock detectors 132, 136 detect when the corresponding clock signals DCK, RCK are absent, and then detect when the corresponding clock signals DCK, RCK reappear. The clock detectors 132, 136 then limit the input of the corresponding digital filter 16, 22 during the recovery period after the clock signal reappears to help reduce any large signal transient overshoot within the loop, and therefore reduce any transient overshoot in the output frequency.

[0102] Numerically controlled oscillator (NCO) 24 may take many possible forms. Figure 2An NCO 24 is shown including a voltage output DAC 70 driving a voltage controlled oscillator 72. As an alternative, FIG7(a) shows an NCO in the form of a simple RC oscillator 440 having digitally programmable resistor elements 442 and capacitor elements 444, while FIG7(b) shows an NCO in the form of a transconductance / capacitor (Gm-C) ring oscillator 446, also having digitally programmable resistor elements 448a, 448b, 448c and capacitor elements 450a, 450b, 450c.

[0103] Fig. 7 (c) shows one possible form of programmable capacitor element 444 or 450a, 450b, 450c in more detail, with multiple capacitors 452a, 452b, 452c connectable in parallel combination by means of switches 454a, 454b, 454c, which include MOS transistors or other suitable active devices. In other embodiments, some or all of the capacitors constituting the programmable capacitor element can be connected to other capacitors in series.

[0104] Figure 7(d) shows in more detail the form of a programmable resistor element 442 having a plurality of resistors 456a, 456b, 456c, 456d connectable in series or in parallel combinations by means of switches comprising MOS transistors or other suitable active devices.

[0105] Therefore, in Figure 7(c) and 7(d) In the embodiment of the present invention, a binary signal representing a numerical input, or a corresponding bit of a binary signal derived from the numerical input, can control which of the capacitors and resistors are connected and thus control the frequency of the oscillator.

[0106] FIG7( e) shows an alternative NCO in which the oscillator element is a ring oscillator 458, in which case the source current is digitally controllable. (Similarly, the source voltage or other bias voltage of the ring oscillator may be digitally controllable.) Thus, in FIG7( e), the ring oscillator 458 comprises three inverting stages 460a, 460b, 460c (which may be simple CMOS inverter stages), but of course any suitable number of such inverters may be provided. Three PMOS transistors 462a, 462b, 462c are arranged in an array, and the corresponding bits of the binary signal representing the numerical input may control whether the gates of the PMOS transistors are connected to a suitable bias voltage V B or source voltage V DD . is connected to the bias voltage V B The gate pair can be used to drive the total current I ctrlcontributes to, and thus controls, the source voltage V of the ring oscillator 458 ctrl and output frequency.

[0107] The output of the digital filter will typically be 20 bits to 30 bits wide, however, and it is not practical to provide sufficient passive components to provide such a high resolution directly.To alleviate this problem, word length reduction techniques can be used.

[0108] FIG7( f) shows a possible form of a numerically controlled oscillator (NCO) 140, which can be used to replace the numerically controlled oscillator (NCO) 24 described above. The numerically controlled oscillator (NCO) 140 includes a digital-to-analog converter (DAC) 70 and a voltage controlled oscillator (VCO) 72, which are connected to the NCO 140. Figure 2 Modules denoted by the same reference numerals in have the same functions and these will not be described further. In the numerically controlled oscillator (NCO) 140, the value output by the second digital filter 22 is first passed to a word length reduction (WLR) circuit 142, such as a noise shaper or a delta-sigma modulator. This helps ensure that any noise caused by quantizing this value is pushed out to higher frequencies where it will not have any significant effect in the output jitter at the low and medium frequencies. The output of the word length reduction (WLR) circuit 142 is then passed to a digital-to-analog converter (DAC) 70.

[0109] The output of the digital-to-analog converter (DAC) 70 may be passed to an analog low pass filter 144 to further help attenuate the quantization noise introduced by the DAC 70 and to help decouple any other high frequency noise relative to the local ground of the VCO. The filtered low pass signal is then passed to a voltage controlled oscillator (VCO) 72 to generate an output signal CKout at a frequency corresponding to the value of the integrator output.

[0110] This allows a relatively low resolution (perhaps 6 bits) DAC to have a much finer effective DC resolution (eg 16 bits) in terms of the average value applied to the VCO and the corresponding output frequency accuracy.

[0111] Similarly, the word length reduction circuit can be used to control the programmable resistor and / or capacitor elements in the structure shown in Figure 7 (a) or 7 (b), or the PMOS transistor in the structure shown in Figure 7 (e). In the example of Figure 7 (e), the capacitor C filt will act as a low pass filter element.

[0112] So far, the value P applied to the frequency control input FC has been assumed to be constant with time, or at least to change slowly with time compared to any generated frequency or loop bandwidth, so that the frequency of the output clock tracks a slowly changing required value corresponding to P.

[0113] Alternatively, the changes may be fast enough, that is, exceeding the FLL loop bandwidth, so that the effect of the first low-pass filter 16 and the second low-pass filter 22 is to cause the output clock f CKout The average frequency of depends on the average value of P, and any modulation of this frequency is negligible. For example, P may alternate rapidly between two or more adjacent values ​​such that the average of the two or more adjacent values ​​represents the ideal frequency, or the input value P applied to the first input of the first subtractor 14 may be any sequence or stream of values ​​having ideal characteristics in terms of average value and quantization noise spectrum, and may be, for example, a stream of multi-bit words or single-bit words output from a multi-bit or single-bit delta-sigma modulator.

[0114] Figure 8 Another alternative frequency generator 120 is shown, in which inputs having values ​​"a" and "b" are input to a modulator 122, such as a delta-sigma modulator, to generate a stream of output values ​​having an average value a / b. Thus, an accurate fractional average output value can be obtained by supplying integer values ​​a and b. The stream of output values ​​is supplied to a frequency generator submodule 124 to be used as a frequency control word applied to the input FC. The frequency generator submodule 124 can take the form of any frequency generator described herein (i.e., frequency generators 10, 90, 110, 130), and the stream of output values ​​is supplied as an input ideal value P of the frequency ratio. Therefore, if it is desired to generate an output clock signal at a frequency that is an accurate fractional multiple of the available clock frequency, the modulator 122 can be used to generate an ideal value for the multiple by selecting appropriate values ​​of a and b, and this value can be supplied to the frequency generator submodule 124 as an ideal multiplication factor P in the form of a stream of modulator output values.

[0115] Fig. 9A first order delta-sigma modulator 330 is illustrated for use as the modulator 122 in one embodiment of the present invention. The delta-sigma modulator 330 includes a first input terminal 331 for receiving a first input value a. An adding element 332 (which may be an adder) receives the first input value a from the first input terminal 331. A memory element 334 is coupled to the output of the adding element 332 and maintains a cumulative count. The output of the memory element 334 is coupled to a modulus element 336 and a comparison element 338, which may be a comparator. The delta-sigma modulator 330 also includes a second input terminal 335 for receiving a second input value b, which is provided to the modulus element 336 and the comparison element 338. The comparison element 338 provides a first output m on an output line 339, and the modulus element 336 provides a second output ε on a second output line 340, which is also fed back to the adding element 332.

[0116] Thus, the delta-sigma modulator 330 has two input terminals 331, 335 for receiving a first input value a and a second input value b. Input a represents the numerator of the fractional input and input b represents the denominator of the fractional input. The first input value a and the second input value b are thus selected such that a / b=P.

[0117] Preferably, though not necessarily, the input values ​​a and b are selected so that they are relatively prime, i.e., they have no common factors other than 1, to eliminate tones in the output of delta-sigma modulator 330. If the input values ​​a and b are not relatively prime, the presence of tones in the output may sacrifice performance, especially in audio systems. However, other non-audio systems may be able to tolerate such a sacrifice.

[0118] The value b may be represented by a binary word, and in particular the binary word may have more than one non-zero bit, and therefore b need not be 2. N in the form of.

[0119] In the delta-sigma modulator 330, the adding element 332 adds the first input value a to the accumulated count until the comparing unit 338 determines that the accumulated count held in the memory element 334 is greater than or equal to the threshold value b. When the accumulated count is greater than or equal to the threshold value b, an output pulse is generated at the output 339, and the counter is reset by the modulo element 336. That is, the modulo element performs a modulo operation on its input, subtracting the value b from the count value received from the memory element 334, repeatedly if necessary, until the result is less than b. Thus, in the delta-sigma modulator 330, the threshold is set by the second input value b, which sets the modular point of the delta-sigma modulator.

[0120] The mode point or rollover point of the delta-sigma modulator is a threshold value b which, when exceeded by the accumulated count, causes a pulse to be output at output 339 and the count to be reset.

[0121] The ability to set the mode point to a second input value, b, enables the delta-sigma modulator to synthesize based on the basis b. Thus, the average value of the pulse density of the output 339 is exactly equal to a / b, since the synthesis is quantized to b, which is the denominator of the input a / b. N The ability to form b-values ​​allows a wider range of frequencies to be accurately synthesized, rather than having ratios rounded to a certain number of binary digits.

[0122] When the accumulated count exceeds the threshold value, the excess amount of the accumulated count over the threshold value is transferred (rolled over) as a remainder at the beginning of the next addition cycle.

[0123] Output terminal 340 outputs the error value ε of delta-sigma modulator 330. This error value is reduced in higher order delta-sigma modulators because it is cascaded to the following delta-sigma modulation stages. Fig. 9 In the delta-sigma modulator 330 shown in FIG. 1 , the error value is discarded.

[0124] The invention is not limited to first order delta-sigma modulators and can also be used in higher order modulators containing at least two delta-sigma modulation stages and a recombination stage at the output of each stage to combine the outputs to produce a pulse density modulated output.

[0125] Traditionally, modular operations, such as those performed by modular unit 336, are computationally expensive. Fig.10 An alternative delta-sigma modulator 341 is shown for use in one embodiment of the present invention, in which the modulo unit is simplified to a multiplexer 342 and a subtractor 344.

[0126] The delta-sigma modulator 341 is connected with Fig. 9The delta-sigma modulator 330 operates in a manner similar to that described above. A first input value a from input terminal 331 is added to a cumulative count maintained in memory cell 334 via an adding element 332. The cumulative count, together with the cumulative count from subtractor 344 minus an input value b input from input terminal 335, is input to a multiplexer 342. Multiplexer 342 selects an output from one of the inputs depending on whether comparison element 338 determines that the cumulative count is greater than or equal to input value b. If comparison element 338 determines that the cumulative count is greater than or equal to input value b, comparison element 338 outputs a pulse at output 339, which is also transmitted to multiplexer 342, indicating that multiplexer 342 should select an output having the cumulative count minus input value b for feedback to adding element 332. This simplified circuit is Fig. 9 An acceptable alternative to the circuit shown in , if the relationship between the values ​​a and b is known will not require repeated subtraction of the value b. As a simplified circuit, this will have a smaller chip area and therefore lower cost, and also has the advantage of lower power consumption.

[0127] Fig.11 An example of a third-order delta-sigma modulator 400 according to an embodiment of the present invention is shown. The delta-sigma modulator 400 includes a first input terminal 401 for receiving a first input value a. An adding element 402 receives the first input value a from the first input terminal 401. A first delta-sigma modulation stage 404 is coupled to the output of the adding element 402, which may take the form of Fig. 9 The delta-sigma modulator 330 shown in FIG. Fig.10 The first output 405 of the first delta-sigma modulation stage 404 is coupled to the recombination stage 420 and is a pulse density modulated signal having an average value of The second output 406 of the first delta-sigma modulation stage 404 is the error ε1 of the first delta-sigma modulation stage 404. The second output 406 is connected to the input of the second delta-sigma modulation stage 407. The second delta-sigma modulation stage may take Fig. 9 The delta-sigma modulator 330 shown in FIG. Fig.10 The first output 408 of the second delta-sigma modulation stage 407 is coupled to the recombination stage 420 and is a pulse density modulated signal having an average value of The second output 409 of the second delta-sigma modulation stage 407 is the error ε2 of the second delta-sigma modulation stage 407, and the second output 409 is connected to the input of the third delta-sigma modulation stage 410, which can take the form of Fig. 9 The delta-sigma modulator 330 shown in FIG. Fig.10 The output 411 of the third delta-sigma modulation stage 410 is coupled to the recombination stage 420 and is a pulse density modulated signal having an average value of

[0128] The delta-sigma modulator 400 further includes a second input terminal 434 for receiving a second input value b. Fig.11 Not shown in FIG. 4 , the second input value b is provided to the delta-sigma modulation stages 404, 407, 410. As discussed previously, the second input value b determines the mode point of the delta-sigma modulation stages.

[0129] The recombining stage 420 combines the outputs from the three modulation stages 404, 407, and 410 respectively. and The combination is performed to generate an output 432, and the manner of combination is known to those skilled in the art, so it will not be further described here.

[0130] A dither unit 430 (which receives a dither control signal) applies dither to the summing element 402. Dither is a form of noise that is intentionally applied in order to randomize the quantization error and prevent or at least substantially reduce the formation of tones within the output of the delta-sigma modulator 400. The dither is introduced to eliminate tones in the power / frequency response of the delta-sigma modulator in a manner that is known per se to those skilled in the art and will not be described further herein.

[0131] A clock generator having a number of advantageous properties has thus been described.

[0132] Such a clock generator as described above is useful in consumer devices / host devices that include audio reproduction or other audio signal processing, such as, but not limited to, smartphones, game consoles, tablets, laptops, desktop computers, hi-fi systems, etc. In such applications, it is necessary to use a clock with low jitter and with exactly the same frequency as the rate of the incoming data (or a multiple thereof) for good audio reproduction to avoid missing or adding data samples.

[0133] Fig.12A known audio processing channel 150 is shown, which in this case may be an audio reproduction channel that accepts input digital data and outputs an analog signal suitable for driving a speaker or headphone directly or indirectly. The incoming data is transmitted according to one or more clocks (e.g., a frame clock or a bit clock in the case of a serial data format). One of these clocks is used to capture the incoming data in an audio interface (AIF) 151. This data is then subjected to some digital signal processing (e.g., interpolation or decimation) in a digital signal processing module (DSP) 152 to produce processed data "Data'", which is then output through a delta-sigma DAC 154, the DAC and DSP being clocked according to some processing clock or clocks.

[0134] The processing clock may be simply a (buffered) version of one of the interface clocks (as shown by dashed line 155), or may be passed through a frequency generator 156, for example multiplying an incoming frame clock LRCLK at, say, 48kHz to a higher speed clock (e.g., 3072kHz) CKsys which can be used to clock the output DAC 154.

[0135] However, the incoming clock may be subject to some jitter due to distortion or noise added in transmission, or the clock generator available on the digital processor chip may be of low quality. This jitter, when present on the sampling clock of the DAC, may result in noise, distortion or spurious intermodulation products.

[0136] Fig.13 An alternative audio processing channel 150 is shown in which the DAC clock CKsys is derived from a local clock generator 157. However, especially in systems with multiple channels from multiple sources, the local clock CKsys may not be synchronized to the incoming clock, or may not have the same actual frequency as the incoming clock, even if it is the same nominal frequency. In order to cope with the possible asynchrony between the incoming data and the local clock, it is necessary to include an asynchronous sample rate converter module 158 in the signal chain, such as interpolating or upsampling the input data to a very high sampling rate, smoothing the input data through a filter, and then decimating or downsampling the input data to the ideal sampling rate. This costs considerable digital hardware and power consumption, and may degrade the audio quality, especially if the input data is compressed and expanded or otherwise nonlinearly encoded.

[0137] When the audio processing device 150 is used in a consumer device such as a smartphone, PDA, or digital camera, the consumer device may include a good quality, low jitter clock for other functions of the device, for example from a crystal generating a clock signal at 19.2 MHz or 12 MHz.

[0138] Fig.14 One configuration of an audio processing channel 150 that may be advantageously used in the above scenario is shown, including a frequency generator 159, which may take the form of any of the frequency generators described herein (ie, frequency generators 10, 90, 110, 130) or the like.

[0139] In this case, the input data is accompanied by a low quality clock CKIN, for example, an audio word clock LRCLK, the nominal frequency of which is a 1 / P fraction of the frequency of the output clock CKout. The clock CKIN can then be supplied to a first clock (DCK) input of a frequency generator 159, while a high quality clock from a crystal (XTAL) can be supplied to a second clock (RCK) input of the frequency generator 159. As described above, by appropriate selection of input values, the frequency generator 159 can be caused to generate a clock signal CKout that is synchronized with the long term frequency of the incoming LRCLK, but retains the bass band jitter of the clock signal from the crystal (XTAL). This clock signal can then be supplied to each DSP 152 and DAC 154 that decodes each audio data channel. It is not necessary to provide an asynchronous sample rate converter (ASRC) on at least this one channel or any other channel that is synchronized with this channel, for example, another one in a stereo pair, or other channels with a common LRCLK. As a result, this configuration is advantageous in terms of power, area, etc. compared to alternatives that require a low jitter clock to be provided to the DAC and / or require asynchronous sample rate conversion to allow for different clock bases to maintain accurate frequency and avoid missing data samples.

[0140] In practice, the clock actually delivered to the DAC and / or DSP may be a divided-down version of the frequency generator output, but such possible dividers are omitted from the drawing for simplicity.

[0141] Fig.15An alternative bidirectional audio processing channel 160 is shown. Thus, when an audio interface (AIF) 161 receives digital data, the audio interface passes the digital data to a digital signal processing module (DSP) 162 to produce processed data "data'", which is output through a DAC 164, an ADC 163 receives analog data, which is converted to digital form and then processed in the DSP 162 and output via the AIF 161. The ADC 163, as well as the DSP 162 and DAC 164, are clocked using a clock signal CKsys output from the frequency generator 159.

[0142] Fig.16 The use of a frequency generator as described in a system having multiple audio channels and associated clocks is shown. Specifically, Fig.16 An audio hub circuit 202 is shown, which may be implemented as an integrated circuit, such as for use in a consumer host device 203, such as a smartphone or portable audio convergence device.

[0143] Mobile phone signals from and to the RF front end 204 are coupled through a first processing circuit system (e.g., a cellular communications ("comms") processor 206) that includes an audio interface (AIF) 207 to transmit these signals in the form of a stream of sampled digital audio data to and from a first audio interface 208 on the audio hub 202. The "comms" processor 206 includes a clock generation circuit system 210 that is synchronized to the RF receive / transmit channel, i.e., to the external telephone network. Thus, the sampling rate of the audio data stream between the communications processor and the audio hub is synchronized to the external network.

[0144] The consumer / host device 203 may also play back or record audio signals stored in a local memory or removable medium 224 that is coupled to a second interface 226 on the audio hub 202 via a second processing circuit system, such as an applications ("apps") processor 228, having an associated clock circuit system 230 and including an audio interface 232 to transmit these signals to and from the second interface in the form of a sampled digital audio data stream. The sampling rate associated with timing the audio data entering and leaving the storage medium 224 does not necessarily need to be synchronized to any external reference clock: the sampling rate only needs to be sufficiently accurate and stable so that pitch errors are not noticed. Therefore, there is no need to synchronize the sampling rate of the audio data stream between the application processor and the audio hub to any external network or other external source.

[0145] The host / consumer device 203 may also have other audio data sources, such as a Bluetooth transceiver, an FM radio, a Wi-Fi transceiver, or a High-Fidelity Multimedia Interface (HDMI), an S / PDIF interface, or a USB interface, represented in this example by a PHY module 234, which is directed through an additional processing circuit system 236, which includes an audio interface 238 to transmit the audio data to and from a third audio interface 240 on the audio hub 202 in the form of a stream of sampled digital audio data. In some cases, these additional audio channels may need to be synchronized to the external circuit system or network, and in other cases, this may not be necessary. Therefore, the sampling rate of the audio data stream between the PHY module and the audio hub may need to be synchronized to the external network or other external source in some usage scenarios, but not in other scenarios.

[0146] The audio hub 202 also includes a DSP mixer module 260, which may include signal routing, mixing, conditioning and other DSP functions. Signals from the audio interfaces 208, 226, 240 or from the ADC analog interfaces 268a, 270a, 272a (possibly after processing by an optional dedicated DSP module 262a, 264a, 266a) may be mixed, conditioned or otherwise processed by the DSP module 260, and the resulting signals are output via the audio interfaces 208, 226, 248 or from the DAC 268b, 270b, 272b (possibly after processing by an optional dedicated DSP module 262b, 264b, 266b).

[0147] The mixer 260, DSP modules 262, 264, 266, and DAC / ADC analog interfaces 268, 270 and 272 are clocked by a clock signal CKsys generated by a clock generator 256 (or a clock signal that may be divided down or otherwise derived from CKsys), which may be included on the same audio hub integrated circuit.

[0148] The processing of all audio data streams within the DSP module 260 must preferably be synchronized to a common clock CKsys, despite the various audio data sampling rate synchronization requirements generated from the digital audio sources connected in various ways. Therefore, preferably, the frequency generator circuit 256 can take the form of any frequency generator described herein, that is, frequency generator 10, 90, 110, 130 or the like.

[0149] In the illustrated embodiment, the clock signal generated by the communication processor 206 and the clock signal generated by the application processor 228 are passed to the multiplexer 258 (or equivalent arrangement). When the device receives a cellular telephone call, the multiplexer 258 is controlled so that the clock signal generated by the clock generator 210 on the communication processor 206 is passed to the DCK input of the frequency generator 256. The frequency generator output clock CKsys is used to process data, which is connected through the communication processor to maintain data synchronization with an external network. It may also be required to simultaneously connect data from the local memory 224 via the application processor 228, for example for recording incoming calls, perhaps as a local voicemail function. Because the sampling rate of this data does not need to be synchronized to any external clock reference, this data stream can also be based on the same clock CKsys, rather than using some clock generated, for example, on the application processor, which clock may require asynchronous sampling rate conversion of the audio data stream to be processed synchronously with CKsys.

[0150] The telephone communication type device may also process the audio data stream, for example, when not receiving a network call (e.g., for MP3 / MP4 file playback). In this case, the cellular communication processor 206 is preferably turned off to save power, and the master clock for this system may be generated on the application processor 228 or possibly on some other chip in the system (e.g., power management IC (PMIC) 280). Therefore, in this case, the multiplexer 258 is controlled so that the clock signal generated or used by the application processor 228 is passed to the DCK input of the frequency generator 256.

[0151] The communication device may also be required to process audio data streams to / from other processors 236. Fig.16 In an embodiment, to allow for usage scenarios where these data streams must be synchronized to some external network or external clock source while the audio hub clock CKsys maintains audio synchronization with the cellular network based on, for example, a communications processor module, the audio interface 240 includes an asynchronous sampling rate converter (ASRC) 242 to generate or receive an audio data stream synchronized with the CKsys clock from the asynchronous clock used by the processor 236.

[0152] In an alternative embodiment, this ASRC may be separate from the audio interface, and the audio hub may include routing circuitry to route audio data streams from other audio interfaces through this ASRC while allowing a path directly between the interface 240 and the DSP module 260, possibly with a third input to a multiplexer 258 to pass the clock from the processor 236 to the clock generator 256, for scenarios where it is desirable to base CKsys on a clock from the processor 236 and perhaps convert the sample rate of some other channel, or where the audio data passing through the processor 236 is not required to be synchronized to some external reference. Alternative embodiments may have fewer or more channels, each of which may be substantially similar to one of the three channels already described.

[0153] Both the communication processor 206 and the application processor 228 are large, complex digital circuits, so any clock sent from them is likely to be corrupted by on-chip digital crosstalk and thus have high jitter. As mentioned above, the frequency generator 256 has the advantage of reducing this jitter to allow better audio quality. In an application similar to this, with multiple possible master clock sources, there is an additional advantage that when the DCK input is switched to different sources, there may be no false signals in the output clock, and the output frequency will not change suddenly because it is locked to RCK, and the input to the NCO 24 in the frequency generator will only change slowly with a time constant of the order of magnitude of the sub-audio bandwidth of the external loop. Therefore, the transition from one system clock to another, for example, if an incoming voice message is recorded to a local voice mailbox while playing some MP3 music, will not be heard by the listener.

[0154] In other system modes, it may be desirable to even shut down the application processor 228 or at least run the processor at a very slow duty cycle, just to keep the system in some kind of standby mode. In such a mode, the DCK input to the frequency generator may be disabled altogether, or at least periodically. As described above, the frequency generator will then continue to generate a clock close to the nominal frequency, based on the held values ​​of the Nerr1 and RCK frequencies. Again, transitions into and out of this standby mode will occur, or with DCK appearing and disappearing periodically, without abrupt changes in the phase or frequency of the output clock.

[0155] Note also that even if RCK were to temporarily disappear, the NCO would continue to oscillate at a frequency corresponding to the held value of Nerr2, so some clock would still be available to maintain some function in the system. This frequency would still be fairly accurate, within the resolution or error of the held value of Nerr2, although it might eventually drift due to any changes in temperature or source voltage.

[0156] Fig.17 Device 170 is shown in which data is supplied from a USB source 172. This data is supplied to an audio and / or video codec 174 via an interface 173 of the device 170. The USB source 172 provides a burst of data, for example, every 1 ms or so. Typically, the data is buffered in a temporary storage circuit system 175 such as a FIFO. The buffered data is passed to a digital-to-analog converter (DAC) 177, the analog output of which can be used, for example, to drive audio from a speaker 178 internal to the device, or audio from a speaker or headphone 179 external to the device.

[0157] The USB source 172 also provides a clock, typically at a frequency of 12 MHz. This clock can be present as long as the USB source 172 is available and connected to the codec 174, or it can disappear between data bursts. When the clock is only periodically available from the USB source 172, it is still necessary to have a stable local clock to provide continuous output data conversions with the aid of the DAC 177. It is also necessary to avoid glitches when the USB clock returns periodically to avoid audible artifacts.

[0158] When the device 170 is a consumer device / host device such as a smartphone or laptop computer, the device may include a good quality, low jitter clock for other functions of the device, such as from a crystal that generates a clock signal at a known frequency. In such a case, a frequency generator or clock generator 176 may be advantageously used. The frequency generator 176 may take the form of any frequency generator described herein, i.e., frequency generators 10, 90, 110, 130, or the like.

[0159] The USB clock may then be supplied to a first clock (DCK) input of a frequency generator 176, while the clock from the crystal (XTAL) may be supplied to a second clock (RCK) input of the frequency generator 176. A frequency control (FC) word P is also supplied to the frequency generator 176.

[0160] This has the effect that the clock signal CKout supplied to the codec 174 can be derived from the USB clock. However, when the USB clock and associated data bursts are not present, the output of the integrator in the frequency generator 176 will remain constant and therefore the output frequency f CKout will remain at the same fixed ratio as the frequency of the clock (RCK) from the crystal. Therefore, the clock signal CKout supplied to the codec 174 will remain close to the expected frequency f CKout .

[0161] There may be a small error in the frequency of the output clock CKout between each burst. The filtered first error signal Nerr1 will typically vary slightly from one DCK cycle to the next due to the limited resolution of the digital filter (i.e., quantization noise) plus any noise injected into the loop possibly by any delta-sigma modulation of P or cycle-by-cycle variation in synchronization of DCK to CKout. To achieve an error of one quarter of a 12MHz DCK period over a 1ms interval between bursts of USB data, Nerr1 is required to have an accuracy of 1 / 48000. If Nerr1 can be, for example, 1 / 16 of full scale under certain conditions, this requires 20 bits of resolution in Nerr1. The size of the storage circuit system 175 may be slightly increased to allow for temporary storage of a cache of data to accommodate temporary or short-term variations in the output clock frequency; the long-term frequency will be accurate, and therefore errors in the clock will not accumulate, so this storage will never overflow if sized appropriately.

[0162] In some applications, to save space and reduce bill of materials costs, it is undesirable to use off-chip components, such as a crystal (XTAL), so it is desirable to generate the required accurate and low-jitter clock using completely on-chip circuitry.

[0163] It is difficult to design a complete on-chip oscillator that can output a clock signal with a stable frequency and low jitter characteristics without having to design a complex circuit that is large in integrated circuit (IC) chip area and / or requires a relatively large amount of power to operate. Such IC design difficulties are due to factors such as: IC manufacturing tolerances in terms of doping levels and structural dimensions; and changes in, for example, IC operating temperature or supply voltage during subsequent use.

[0164] To overcome these problems, a solution was devised where the clock generator is provided with multiple clock signals generated completely on-chip.

[0165] Fig.18One embodiment of an integrated circuit 180 is illustrated that includes a clock generator 182 and first and second on-chip oscillators 186, 184. The clock generator 182 may be any clock generator previously described herein, ie, frequency generators 10, 90, 110, 130 or the like.

[0166] The first oscillator 186 may be specifically designed to have an output frequency that is insensitive to temperature and source voltage, but with little concern for jitter. This oscillator may, for example, be a completely on-chip RC-based oscillator, using temperature-stable on-chip capacitors (as commonly available) and zero temperature coefficient resistors. The zero temperature coefficient resistors may be obtained by a properly designed mesh structure that includes a mix of multiple types of on-chip resistors that may have positive and negative temperature coefficients. In order to obtain an initial absolute frequency accuracy, one or more of the components of the first oscillator 186 may be trimmed, i.e., adjusted, during or after manufacture so that the first oscillator 186 outputs a very accurate desired frequency. Once trimmed, such a time-constant type oscillator will have a relatively stable, i.e., relatively accurate output frequency, but will have high jitter characteristics.

[0167] The first oscillator 186 may be the one discussed above and in Figure 7(a) , 7(b) Or one of the types illustrated in 7(e), including digitally programmable resistors, capacitors or other elements, the control digital bits of the oscillator may be stored in an on-chip non-volatile memory such as a ROM or a fusible element.

[0168] The first oscillator 186 is connected to the clock generator 182 so that the output of the first oscillator 186 is supplied as a first input clock signal (DCK) to the clock generator 182. The first input clock signal DCK is therefore a clock signal of relatively accurate frequency, but with a relatively high degree of jitter.

[0169] Compared to the first oscillator, the second oscillator 184 should be designed to generate a low-jitter clock, but with less attention to frequency accuracy or stability. The second oscillator 184 can be composed of an oscillator including a completely on-chip resonant circuit, such as an LC-type oscillator, which includes an on-chip inductor L and an on-chip capacitor C. Without the impracticability of taking the design of complex circuits discussed above, a relatively low-power resonant oscillator can be designed using an on-chip inductor to provide an output clock signal with low jitter characteristics, but it is difficult to simultaneously provide an output frequency that is very insensitive to temperature and source voltage. For a completely on-chip LC oscillator, the difficulty is further increased because the resonant circuit including an on-chip inductor (L) in the prior art has a lower Q factor than an equivalent resonant circuit including an off-chip inductor. The second oscillator will therefore generate a clock with low jitter but with a frequency that varies over time.

[0170] The second oscillator 184 is connected to the clock generator 182 so that the output of the second oscillator 184 is supplied as a second input clock signal (RCK) of the clock generator 182. The second input clock signal RCK is therefore a relatively low jitter clock signal but has relatively poor frequency accuracy.

[0171] As discussed above, the clock generator 182 functions to generate an output clock signal having the frequency accuracy of the clock signal provided by the first oscillator 186 , but having the low jitter characteristics of the clock signal provided by the second oscillator 184 .

[0172] Designing two separate oscillators, each focusing on a different performance aspect, is much easier than trying to meet all requirements with a single oscillator, and such a design provides a less complex and therefore cheaper circuit, and consumes less power despite the additional circuitry of the clock generator.

[0173] therefore, Fig.18 The circuit shown in is particularly useful in situations where it is undesirable or impossible to use off-chip components in generating a stable (ie, accurate) output clock (CKout) having low jitter for any reason.

[0174] In the process of generating two clock signals in a completely on-chip manner, one clock signal (DCK) has an appropriate (i.e., ideal) frequency and is relatively accurate over time but has relatively high jitter, while the other clock signal (RCK) has an inappropriate (i.e., relatively inaccurate) frequency but has relatively low jitter characteristics, and these two clock signals are used as clock inputs to the clock generator described above, then the optimal characteristics of each of the two clock signals (RCK, DCK) generated on-chip exist in the clock generator output signal (CKout).

[0175] This means that by suitable choice of the value of P, the output clock signal CKout can be generated from the second input clock signal DCK at a desired exact frequency ratio, but the jitter on the output clock signal CKout (within the frequency band of interest) depends only on a low degree of jitter on the second input clock signal RCK.

[0176] It should be noted that the second oscillator may alternatively be constituted by some other relatively high-Q resonant element, for example by means of a MEMS (Micro Electro Mechanical System) type oscillator as part of an integrated circuit.

[0177] Thus, a frequency generator for generating a signal at a desired frequency having advantageous characteristics is provided.

Claims

1. An integrated circuit chip, comprising: a first oscillator for generating a first oscillator clock signal; a second oscillator for generating a second oscillator clock signal; as well as a clock generator for generating an output clock signal from the first oscillator clock signal and the second oscillator clock signal, in: The first oscillator is a first on-chip oscillator; The first oscillator clock signal has a relatively accurate frequency and a relatively high degree of jitter; The second oscillator is a second on-chip oscillator; The second oscillator clock signal has a relatively low level of jitter and a relatively inaccurate frequency; The output clock signal has the jitter characteristics of the second oscillator clock signal over a frequency range and the frequency accuracy of the first oscillator clock signal.

2. The integrated circuit chip of claim 1, wherein the first on-chip oscillator is an RC oscillator.

3. The integrated circuit chip of claim 2, wherein the RC oscillator comprises a temperature stable capacitor and a zero temperature coefficient resistor.

4. The integrated circuit chip of claim 1, wherein one or more components of the first oscillator can be trimmed to obtain a desired frequency of the first oscillator clock signal.

5. The integrated circuit chip of claim 1, wherein the second oscillator is an LC type oscillator.

6. The integrated circuit chip according to claim 1, wherein the second oscillator is a MEMS (Micro Electro Mechanical System) type oscillator.

7. The integrated circuit chip of claim 1, wherein the first oscillator clock signal has a more accurate frequency than the second oscillator clock signal, and The second oscillator clock signal has a lower degree of jitter than the first oscillator clock signal.

8. The integrated circuit chip according to claim 1, further comprising: An input for receiving a signal representing a desired ratio between the output clock signal and the first oscillator clock signal.

9. The integrated circuit chip according to claim 8, further comprising: a first frequency comparator for generating a first frequency comparator output based on a ratio between the output clock signal and the first oscillator clock signal; as well as A first subtractor is configured to form a first error signal based on a difference between an input signal and the output of the first frequency comparator.

10. The integrated circuit chip of claim 9, further comprising a first filter such that a first error signal is formed as a filtered version of the difference between the input signal and the first frequency comparator output.

11. The integrated circuit chip of claim 9, wherein the first frequency comparator comprises a counter.

12. The integrated circuit chip according to claim 9, further comprising: a second frequency comparator for generating a second frequency comparator output based on a ratio between the output clock signal and the second oscillator clock signal; as well as A second subtractor is configured to form a second error signal based on a difference between the first error signal and the second frequency comparator output.

13. The integrated circuit chip of claim 12, further comprising a second filter such that the second error signal is formed as a filtered version of the difference between the first error signal and the second frequency comparator output.

14. The integrated circuit chip according to claim 12, further comprising: A controlled oscillator is used to generate the output clock signal from the second error signal.

15. The integrated circuit chip of claim 12, wherein the second frequency comparator comprises a counter.

16. A device comprising the integrated circuit chip according to claim 1.

17. The device of claim 16, wherein the device is a smartphone, a game console, a tablet, a laptop, a desktop computer, or a hi-fi system.

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