Distortion compensation device, wireless communicator and predistorter

Abstract

A distortion compensation circuit according to the present invention includes: a first distortion compensation circuit having a first distortion compensation characteristic for compensating a first distortion generated in an output of an amplifier, and compensating the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating a second distortion generated in an output of the amplifier, and compensating the second distortion; and an updating unit that updates the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, and the second distortion is a distortion having a shorter time variation than the first distortion. The updating unit updates the second distortion compensation characteristic at a frequency higher than the updating frequency of the first distortion compensation characteristic.

Description

Technical Field

[0001] The present invention relates to a distortion compensation device, a wireless communicator, a predistorter, a distortion compensation method and a computer program. This application claims priority to Japanese Patent Application No. 2018-160463 filed on August 29, 2018, the entire contents of which are incorporated herein by reference. Background Art

[0002] The amplifier has nonlinear characteristics. Distortion compensation technology is used to compensate for signal distortion caused by the nonlinear characteristics. Patent document 1 discloses an example of distortion compensation technology.

[0003] Reference List

[0004] [Patent Document]

[0005] Patent Document 1: Japanese Laid-Open Patent Publication No. 2014-204148 Summary of the invention

[0006] A distortion compensation device according to one mode of the present disclosure includes: a first distortion compensation circuit having a first distortion compensation characteristic for compensating a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose time variation is faster than the first distortion, and the updating unit updates the second distortion compensation characteristic at a frequency higher than the update frequency of the first distortion compensation characteristic.

[0007] A wireless communicator according to one mode of the present disclosure includes: an amplifier configured to amplify a signal having a radio frequency; a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in an output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose time variation is faster than the first distortion, and the updating unit updates the second distortion compensation characteristic at a frequency higher than the update frequency of the first distortion compensation characteristic.

[0008] A predistorter according to one mode of the present disclosure is connected to an external distortion compensation circuit configured to compensate for a first distortion generated in an output of an amplifier. The predistorter includes a distortion compensation circuit having a distortion compensation characteristic for compensating for a second distortion different from the first distortion among the distortions generated in the output of the amplifier; and an update unit configured to update the distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is a distortion whose time variation is faster than the first distortion, and the update unit updates the distortion compensation characteristic at a frequency higher than the update frequency of the external distortion compensation circuit.

[0009] A distortion compensation method according to one mode of the present disclosure includes the steps of: performing a first distortion compensation process, the first distortion compensation process compensating a first distortion generated in an output of an amplifier; performing a second distortion compensation process, the second distortion compensation process compensating a second distortion generated in the output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating the second distortion in the second distortion compensation process. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose time variation is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of a first distortion compensation characteristic for compensating the first distortion in the first distortion compensation process.

[0010] A distortion compensation method according to another mode of the present disclosure is to be performed by a predistorter connected to an external predistorter configured to compensate for a first distortion generated in an output of an amplifier. The distortion compensation method includes the steps of compensating for a second distortion different from the first distortion among the distortions generated in the output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is a distortion whose time variation is faster than that of the first distortion, and the predetermined frequency is a frequency higher than the update frequency of the first distortion compensation characteristic for compensating for the first distortion.

[0011] A computer program according to one mode of the present disclosure is used to set a first distortion compensation circuit and a second distortion compensation circuit, the first distortion compensation circuit having a first distortion compensation characteristic for compensating a first distortion generated in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion, and the second distortion compensation circuit having a second distortion compensation characteristic for compensating a second distortion generated in an output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion. The computer program causes a computer to perform the following steps at a predetermined frequency: calculating a parameter for setting the second distortion compensation characteristic; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose time variation is faster than the first distortion, and the predetermined frequency is a frequency higher than the update frequency of the first distortion compensation characteristic.

[0012] A computer program according to another mode of the present disclosure is used to set a second distortion compensation circuit connected to a first distortion compensation circuit, the first distortion compensation circuit being configured to compensate for a first distortion generated in an output of an amplifier. The computer program causes a computer to perform the following steps at a predetermined frequency: calculating a parameter for setting a distortion compensation characteristic of the second distortion compensation circuit; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion compensation circuit is a circuit configured to compensate for a second distortion, the second distortion is a distortion whose time variation is faster than the first distortion, and the predetermined frequency is a frequency higher than an update frequency of the distortion compensation characteristic of the first distortion compensation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a structural diagram of a wireless communicator including a distortion compensation device according to an embodiment.

[0014] Figure 2 is a structural diagram of a distortion compensation device according to an embodiment.

[0015] Figure 3 is a functional block diagram of a distortion compensation apparatus according to an embodiment.

[0016] Figure 4 is a flowchart illustrating an example of a process of an operation performed by a first predistorter according to an embodiment.

[0017] Figure 5 is a flowchart illustrating an example of a first update process.

[0018] Figure 6 is a flowchart illustrating an example of a procedure of an operation performed by a second predistorter according to an embodiment.

[0019] Figure 7 is a flowchart illustrating an example of the second update process.

[0020] Figure 8 is a structural diagram of an improved distortion compensation device according to an embodiment.

[0021] Fig. 9 is a structural diagram of an improved distortion compensation device according to an embodiment.

[0022] Fig.10 is a structural diagram of an improved distortion compensation device according to an embodiment.

[0023] Fig.11 is a structural diagram of an improved wireless communicator according to an embodiment.

[0024] Fig.12 is a structural diagram of an improved wireless communicator according to an embodiment.

[0025] Fig.13 is a structural diagram of an improved wireless communicator according to an embodiment.

[0026] Fig.14 is a structural diagram of an improved wireless communicator according to an embodiment.

[0027] Fig.15 is a structural diagram of a wireless communicator including an improved distortion compensation device according to an embodiment.

[0028] Fig.16 is a structural diagram of an improved distortion compensation device according to an embodiment.

[0029] Fig.17 is a flowchart showing a procedure of operations performed by an improved distortion compensation apparatus according to an embodiment.

[0030] Fig.18 is a structural diagram of an improved distortion compensation device according to an embodiment. DETAILED DESCRIPTION

[0031] <Problems to be Solved by the Present Disclosure>

[0032] For example, transient distortion changes may occur in a compound semiconductor amplifier (GaN amplifier) ​​formed of gallium nitride. In a GaN amplifier, there is a transient response called Idq drift. Idq drift is a transient response in which the drain current becomes lower than a set value when the amplifier transitions from a high-power state to a power-off state. In a GaN amplifier, distortion changes instantaneously in response to signal power fluctuations due to Idq drift. In particular, signal power fluctuations are likely to occur in, for example, a communication system in which transmission and reception are performed alternately, such as time division duplex (TDD).

[0033] For example, changes in distortion in an amplifier are sometimes handled by updating distortion compensation coefficients used in a distortion compensation device in response to the changes in distortion. By updating the distortion compensation coefficients, the distortion compensation characteristics of the distortion compensation device are updated in response to the changes in distortion.

[0034] To track instantaneous changes in distortion caused by Idq drift, etc., it is considered to frequently perform updating of the distortion compensation characteristic. However, since the processing load for updating the distortion compensation characteristic is large, it is not always easy to frequently perform updating of the distortion compensation characteristic in preparation for changes in distortion.

[0035] <Effects of the Present Disclosure>

[0036] According to the present disclosure, variations in distortion can be handled.

[0037] <Overview of Embodiments of the Present Disclosure>

[0038] Hereinafter, an overview of embodiments of the present disclosure is listed and described.

[0039] (1) According to the present embodiment, the distortion compensation device includes: a first distortion compensation circuit having a first distortion compensation characteristic for compensating a first distortion generated in the output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose time variation is faster than the first distortion, and the updating unit updates the second distortion compensation characteristic at a frequency higher than the updating frequency of the first distortion compensation characteristic. Therefore, the time variation of the second distortion can be processed. In addition, both the nonlinear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved. "Nonlinear distortion" refers to a phenomenon in which an output signal having a waveform similar to that of an input signal cannot be obtained due to the nonlinear input / output characteristics of an amplifier. "Memory effect distortion" refers to a phenomenon in which an output signal having a waveform that depends not only on the current input signal but also on the history of past input signals is obtained. In addition, "updating the second distortion compensation characteristic at a frequency higher than the update frequency of the first distortion compensation characteristic" includes not only the case where the first distortion compensation characteristic is updated at a specific frequency but also the case where the first distortion compensation characteristic is not updated. That is, when the first distortion compensation characteristic is not updated, updating the second distortion compensation characteristic at an arbitrary frequency corresponds to "updating the second distortion compensation characteristic at a frequency higher than the first distortion compensation characteristic".

[0040] (2) In the distortion compensation device according to this embodiment, the second distortion may include at least one of the nonlinear distortion and the memory effect distortion. Therefore, in the second distortion compensation circuit, the nonlinear distortion and the memory effect distortion can be processed simultaneously, and higher-precision distortion compensation can be achieved.

[0041] (3) In the distortion compensation device according to the present embodiment, the first distortion compensation characteristic can be specified by a first characteristic formula of a predetermined order, and the second distortion compensation characteristic can be specified by a second characteristic formula whose order is lower than that of the first characteristic formula. Therefore, even when the updating of the second distortion compensation characteristic is performed at a high frequency, the processing load can be suppressed.

[0042] (4) In the distortion compensation device according to the present embodiment, the first distortion compensation circuit can output an output signal having a first frequency bandwidth, and the second distortion compensation circuit can output an output signal having a second frequency bandwidth narrower than the first frequency bandwidth. In accordance with an increase in the frequency bandwidth of the output signal, the processing load increases. Therefore, when the second frequency bandwidth is set to be narrow, the processing load can be suppressed even when the update of the second distortion compensation characteristic is performed at a high frequency.

[0043] (5) In the distortion compensation device according to the present embodiment, the updating unit may include a first updating unit configured to update the first distortion compensation characteristic; and a second updating unit configured to update the second distortion compensation characteristic. The first updating unit may update the first distortion compensation characteristic based on a first monitoring signal obtained from the output signal of the amplifier, the second updating unit may update the second distortion compensation characteristic based on a second monitoring signal obtained from the output signal of the amplifier, and the frequency bandwidth of the second monitoring signal may be narrower than the frequency bandwidth of the first monitoring signal. Therefore, the second distortion compensation characteristic can be appropriately updated by using the second monitoring signal for which a frequency band not used in the distortion compensation of the second distortion compensation circuit is eliminated.

[0044] (6) A wireless communicator according to the present embodiment includes: an amplifier configured to amplify a signal having a radio frequency; a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in an output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an updating unit configured to update the second distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is distortion whose time variation is faster than the first distortion, and the updating unit updates the second distortion compensation characteristic at a frequency higher than the update frequency of the first distortion compensation characteristic. Therefore, the time variation of the second distortion can be processed. In addition, both the nonlinear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved.

[0045] The wireless communicator according to the present embodiment may further include: a first filter configured to convert a monitoring signal obtained from the output signal of the amplifier into a first monitoring signal; and a second filter configured to convert the monitoring signal into a second monitoring signal having a frequency bandwidth narrower than that of the first monitoring signal. The updating unit may include a first updating unit configured to update the first distortion compensation characteristic based on the first monitoring signal output from the first filter, and a second updating unit configured to update the second distortion compensation characteristic based on the second monitoring signal output from the second filter. Therefore, the second distortion compensation characteristic can be appropriately updated by using the second monitoring signal for which a frequency band not used in the distortion compensation of the second distortion compensation circuit is eliminated.

[0046] (8) The predistorter according to the present embodiment is connected to an external distortion compensation circuit configured to compensate for a first distortion generated in the output of the amplifier. The predistorter includes: a distortion compensation circuit having a distortion compensation characteristic for compensating for a second distortion different from the first distortion among the distortions generated in the output of the amplifier; and an update unit configured to update the distortion compensation characteristic. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is a distortion whose time variation is faster than the first distortion, and the update unit updates the distortion compensation characteristic at a frequency higher than the update frequency of the external distortion compensation circuit. Therefore, the time variation of the second distortion can be processed. In addition, both the nonlinear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved.

[0047] (9) The distortion compensation method according to the present embodiment includes the steps of: performing a first distortion compensation process, the first distortion compensation process compensating a first distortion generated in the output of an amplifier; performing a second distortion compensation process, the second distortion compensation process compensating a second distortion generated in the output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating the second distortion in the second distortion compensation process. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is a distortion whose time variation is faster than the first distortion, and the predetermined frequency is a frequency higher than the update frequency of the first distortion compensation characteristic, the first distortion compensation characteristic for compensating the first distortion in the first distortion compensation process. Therefore, the time variation of the second distortion can be processed. In addition, both the nonlinear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved.

[0048] (10) The distortion compensation method according to the present embodiment is to be performed by a predistorter connected to an external predistorter configured to compensate for a first distortion generated in the output of an amplifier. The distortion compensation method includes the steps of: compensating for a second distortion different from the first distortion among the distortions generated in the output of the amplifier; and performing an update process at a predetermined frequency, the update process updating a second distortion compensation characteristic for compensating for the second distortion. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is a distortion whose time variation is faster than the first distortion, and the predetermined frequency is a frequency higher than the update frequency of the first distortion compensation characteristic for compensating for the first distortion. Therefore, the time variation of the second distortion can be processed. In addition, both the nonlinear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved.

[0049] The computer program according to the present embodiment is used to set a first distortion compensation circuit and a second distortion compensation circuit, the first distortion compensation circuit having a first distortion compensation characteristic for compensating a first distortion generated in the output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion, and the second distortion compensation circuit having a second distortion compensation characteristic for compensating a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion. The computer program causes the computer to perform the following steps at a predetermined frequency: calculating a parameter for setting the second distortion compensation characteristic; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion is a distortion whose time variation is faster than the first distortion, and the predetermined frequency is a frequency higher than the update frequency of the first distortion compensation characteristic. Therefore, the time variation of the second distortion can be processed. In addition, both the nonlinear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved.

[0050] (12) According to the computer program of the present embodiment, a second distortion compensation circuit is provided to be connected to a first distortion compensation circuit, the first distortion compensation circuit being configured to compensate for a first distortion generated in an output of an amplifier, the computer program causing a computer to execute the following steps at a predetermined frequency: calculating a parameter for setting a distortion compensation characteristic of the second distortion compensation circuit; and setting the calculated parameter to the second distortion compensation circuit. The first distortion includes nonlinear distortion and memory effect distortion, the second distortion compensation circuit is a circuit configured to compensate for a second distortion, the second distortion is a distortion whose time variation is faster than the first distortion, and the predetermined frequency is a frequency higher than the update frequency of the distortion compensation characteristic of the first distortion compensation circuit. Therefore, the time variation of the second distortion can be processed. In addition, both the nonlinear distortion and the memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved.

[0051] <Details of Embodiments of the Present Disclosure>

[0052] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. At least a part of the embodiments described below may be combined together as needed.

[0053] [1. Configuration of distortion compensation equipment]

[0054] Figure 1A wireless communicator 100 including a distortion compensation device 20 is shown. The wireless communicator 100 is, for example, a base station or a mobile station for mobile communication. The distortion compensation device 20 performs pre-distortion compensation on a baseband signal x[n] output from a baseband processing unit (not shown), and outputs a distortion compensation signal y[n]'. The distortion compensation signal y[n]' is converted into an analog signal by a digital-to-analog converter (DAC) 30, and is converted into a radio frequency signal by an up-converter 40. The signal output from the up-converter 40 is amplified by a power amplifier (PA) 50. The signal output from the amplifier 50 is transmitted through an antenna 60.

[0055] The power amplifier 50 is, for example, a compound semiconductor amplifier formed of gallium nitride (hereinafter, referred to as a "GaN amplifier"). In a GaN amplifier, Idq drift causes instantaneous distortion changes in the amplifier 50. The power amplifier 50 is not limited to a GaN amplifier, and may be any amplifier in which Idq drift or high-speed drift occurs. Idq drift may occur in a high electron mobility transistor (HEMT) device formed of compound semiconductors using not only GaN but also AlN (aluminum nitride), InN (indium nitride), and AlGaN, InAIN, and InGaN based on these crystal systems. Moreover, high-speed drift occurs in a compound semiconductor amplifier formed of GaAs, InAs, InP, and the like. That is, the above-mentioned drift is observed in an amplifier that is a HEMT device formed of a compound semiconductor of the III-V group or its crystal system.

[0056] The communicator 100 includes a coupler 36 for monitoring the output of the amplifier 50. The coupler 36 outputs a monitoring signal z[n]. The monitoring signal z[n] is down-converted by a down-converter 70 and converted into a digital signal by an analog-to-digital converter (ADC) 80. Assume that the ADC 80 has a sampling frequency f s The monitoring signal z[n] is sampled at a frequency f s is sampled as discrete sample data.

[0057] The sampled data z[n] is supplied to the distortion compensation device 20. The distortion compensation device 20 updates the distortion compensation characteristic based on the sampled data z[n].

[0058] Figure 1 The distortion compensation device 20 shown includes a plurality of predistorters A and B. The plurality of predistorters each perform predistortion. Figure 1 In the example, predistorter A and predistorter B are cascaded to each other. Figure 1 In FIG. 2 , the distortion compensation device 20 includes two predistorters A and B, but the distortion compensation device 20 may include three or more predistorters.

[0059] The predistorter A is used to compensate for distortion that does not change with time or changes slowly with time in the distortion in the amplifier 50. The distortion that changes slowly with time is, for example, a variation portion of the distortion caused by temperature variation.

[0060] Regarding distortion compensation, the predistorter B complements the predistorter A. That is, the predistorter B is used to compensate for distortion components that cannot be compensated by the predistorter A. The predistorter B according to the embodiment compensates for distortion whose time variation is fast, which time variation is faster than the time variation of the distortion to be compensated by the predistorter A. For example, the distortion whose time variation is fast is distortion that changes instantaneously due to Idq drift.

[0061] In order to compensate for distortion that does not change with time or changes slowly with time, predistorter A does not update the distortion compensation characteristic or updates the distortion compensation characteristic at a low frequency. On the other hand, in order to deal with distortion whose time changes quickly, predistorter B updates the distortion compensation characteristic at a high frequency. Hereinafter, the distortion compensated by predistorter A is also referred to as "first nonlinear distortion", and the distortion to be compensated by predistorter B is also referred to as "second nonlinear distortion".

[0062] Figure 2 An example of a predistorter A and an example of a predistorter B are shown. Figure 2 The predistorter 21A is Figure 1 An example of a predistorter A is shown. Figure 2 The predistorter 21B is Figure 1 An example of a predistorter B is shown.

[0063] The predistorter 21A is configured to perform digital predistortion (DPD). The predistorter 21A includes a first distortion compensation circuit 210. The first distortion compensation circuit 210 performs predistortion on a baseband signal (signal y[n] output from the predistorter 21B). The first distortion compensation circuit 210 is implemented, for example, as a wired logic circuit such as a field programmable gate array (FPGA). Distortion compensation is performed based on a first distortion compensation coefficient 215a. The first distortion compensation coefficient 215a is a parameter that determines the distortion compensation characteristics of the predistorter 21A. The wired logic circuit may be a reconfigurable logic circuit such as an FPGA, or may be a non-reconfigurable logic circuit.

[0064] The distortion compensation characteristics of the first distortion compensation circuit 210 (hereinafter, referred to as "first distortion compensation characteristics") are specified by a model (hereinafter, referred to as "first distortion compensation characteristics model") expressed by, for example, the following formula (1) (hereinafter, also referred to as "first characteristic formula").

[0065] [Mathematical formula 1]

[0066]

[0067] Wherein, y represents the input signal of the first distortion compensation circuit 210, y' represents the output signal of the first distortion compensation circuit 210, k1 represents an index related to the compensation function for nonlinear distortion, m1 represents an index related to the compensation function for memory effect distortion, K1 and M1 represent constants, n represents discrete time, and h k1,m1 The first distortion compensation coefficient h is represented by (hereinafter referred to as "first distortion compensation coefficient"). That is, the first distortion compensation circuit 210 having the first distortion compensation characteristic has a function of compensating each of the nonlinear distortion and the memory effect distortion. By specifying the first distortion compensation coefficient h k1,m1 The first characteristic formula is a first polynomial for compensating the first nonlinear distortion, and the first distortion compensation coefficient h k1,m1 corresponds to each term of the first polynomial.

[0068] Figure 3 2 is a functional block diagram showing the functions of the distortion compensation device 20 according to the embodiment. The first distortion compensation circuit 210 has a function as a first nonlinear compensation unit 221 and a function as a first memory effect compensation unit 231. The first nonlinear compensation unit 221 corresponds to a compensation function for nonlinear distortion, and the first memory effect compensation unit 231 corresponds to a compensation function for memory effect distortion. The first distortion compensation characteristic is a distortion compensation characteristic including those corresponding distortion compensation characteristics of the first nonlinear compensation unit 221 and the first memory effect compensation unit 231.

[0069] The first distortion compensation characteristic specified by the above first characteristic formula is an example. The first distortion compensation characteristic may be specified by a model different from the formula (1).

[0070] Reference again Figure 2 . When K1 increases, the order of the first characteristic formula is increased. The distortion compensation performed by the predistorter 21A compensates for relatively high-order distortion (high-order nonlinearity) up to 5th-order or 7th-order distortion, for example. That is, K1 is set to a relatively large value, such as 5 or more. Since distortion up to high-order distortion can be compensated, high-precision distortion compensation can be achieved, but the number of the first distortion compensation coefficients 215a is increased.

[0071] The predistorter 21A includes a first updating unit 213 that updates the first distortion compensation coefficient 215a. In this embodiment, the first updating unit 213 is implemented as a computer including a processor 211 and a memory 212. The processor 211 executes a coefficient updating program 214, which is a computer program stored in the memory 212. Each function of the first updating unit 213 is exhibited by the processor 211, which executes the coefficient updating program 214, which is a computer program stored in the memory 212 of the computer. The coefficient updating program 214 may be stored in a storage medium such as a CD-ROM. The processor 211 executes the coefficient updating program 214 to perform a first updating process described later.

[0072] The coefficient updating program 214 includes program code for causing the processor 211 to execute a first updating process for updating the first distortion compensation coefficient 215a. The first updating process is executed based on, for example, sample data 215b indicating the output z[n] of the amplifier 50. The sample data 215b obtained by the predistorter 21A is stored in the memory 212.

[0073] In the first updating process, for example, the processor 211 solves the normal equation according to the least square method based on several thousand sample data 215b obtained by sampling within a predetermined time (for example, several minutes), thereby calculating the first distortion compensation coefficient 215a. The calculated first distortion compensation coefficient 215a is provided to the first distortion compensation circuit 210 to update the distortion compensation coefficient used in the first distortion compensation circuit 210.

[0074] A calculation method such as the least square method can calculate the coefficients with high accuracy, but the processing burden is large and the processing time is long. In addition, the number of coefficients to be calculated is large, which further increases the processing burden. In addition, when a calculation method such as the least square method that requires a large amount of sample data 215b for coefficient update is used, it takes time to obtain a large amount of sample data 215b.

[0075] However, the above problem does not constitute a problem in the predistorter 21A. Since the first update process is performed by the processor 211 at a low frequency, for example, once every few minutes, a sufficient time margin for coefficient update is ensured, and therefore, the time taken for this process does not cause a problem. In addition, since the change of distortion caused by temperature change occurs smoothly, the gentle change of distortion can be tracked even if the coefficient update is performed at a low frequency. However, the predistorter 21A cannot track the instantaneous change of distortion caused by Idq drift, etc. The instantaneous change of distortion is handled by the predistorter 21B.

[0076] The calculation function of the first distortion compensation coefficient 215a by the least square method is an example. For example, the first distortion compensation coefficient 215a can be calculated by another algorithm such as LMS, RMS (root mean square) or RLS (recursive least squares). Alternatively, the first distortion compensation coefficient 215a can be derived by using a correspondence table between the sampled data and the first distortion compensation coefficient.

[0077] The predistorter 21A may not necessarily have the first updating unit 213. That is, the predistorter 21A may have a first distortion compensation characteristic that does not change. In this case, the predistorter 21A does not need to obtain the sampled data 215b. When the predistorter 21A does not have the first updating unit 213, the time variation of the distortion is processed by the predistorter 21B.

[0078] As described above, the predistorter 21B processes variations in distortion, particularly instantaneous variations in distortion, which cannot be processed by the predistorter 21A. Figure 2 The predistorter 21B shown in FIG. 1 is configured to perform digital predistortion (DPD). Figure 2 In the embodiment, the predistorter 21B is connected to the input side of the predistorter A (connected between the predistorter A and the baseband processing unit). For example, the predistorter 21B is implemented as a wired logic circuit such as a field programmable gate array (FPGA). The wired logic circuit may be a reconfigurable logic circuit such as an FPGA, or may be a non-reconfigurable logic circuit.

[0079] The predistorter 21B includes a circuit serving as a second distortion compensation circuit 217. The second distortion compensation circuit 217 includes a wired logic circuit for performing predistortion on a baseband signal (here, a signal x[n] output from a baseband processing unit). Distortion compensation is performed based on a second distortion compensation coefficient 219a stored in a coefficient storage unit in the predistorter 21B. The second distortion compensation coefficient 219a is a parameter that determines the distortion compensation characteristic of the predistorter 21B.

[0080] The distortion compensation characteristics of the second distortion compensation circuit 217 (hereinafter, referred to as "second distortion compensation characteristics") are specified by a model (hereinafter, referred to as "second distortion compensation characteristics model") expressed by, for example, the following formula (2) (hereinafter, also referred to as "second characteristic formula").

[0081] [Mathematical formula 2]

[0082]

[0083] Wherein, x represents the input signal of the second distortion compensation circuit 217, y represents the output signal of the second distortion compensation circuit 217, k2 represents an index related to the compensation function for nonlinear distortion, m2 represents an index related to the compensation function for memory effect distortion, K2 and M2 represent constants, n represents discrete time, and h k2,m2 The second distortion compensation circuit 217 having the second distortion compensation characteristic has a function of compensating each of the nonlinear distortion and the memory effect distortion. By specifying the second distortion compensation coefficient h k2,m2 The second characteristic formula is a second polynomial for compensating the second nonlinear distortion, and the second distortion compensation coefficient h k2,m2 corresponds to each term of the second polynomial.

[0084] refer to Figure 3 The second distortion compensation circuit 217 has a function as a second nonlinear compensation unit 222 and a function as a second memory effect compensation unit 232. The second nonlinear compensation unit 222 corresponds to a compensation function for nonlinear distortion, and the second memory effect compensation unit 232 corresponds to a compensation function for memory effect distortion. The second distortion compensation characteristic is a distortion compensation characteristic including those of the second nonlinear compensation unit 222 and the second memory effect compensation unit 232.

[0085] The second distortion compensation characteristic specified by the above second characteristic formula is an example. The second distortion compensation characteristic may be a characteristic that compensates for one of nonlinear distortion or memory effect distortion, or may be a characteristic that compensates for distortion different from nonlinear distortion and memory effect distortion. In this case, the second distortion compensation characteristic is specified by a model different from formula (2).

[0086] Reference again Figure 2 . The distortion compensation of the predistorter 21B compensates for relatively low-order distortion (low-order nonlinearity) such as third-order distortion, for example. That is, K2 is a constant smaller than K1, and is set to a relatively low value, such as 3 or less. Since low-order distortion is compensated, fewer second distortion compensation coefficients 219a are required. Therefore, the processing burden in the predistorter 21B is smaller. Therefore, an increase in the circuit scale of the predistorter 21B is suppressed.

[0087] When the nonlinear order of the distortion compensation characteristic model increases, the frequency bandwidth of the output signal of the distortion compensation circuit increases. The first distortion compensation circuit 210 and the second distortion compensation circuit 217 are composed of multiple nonlinear Volterra operators. When the signal passes through the nonlinear Volterra operator, the signal bandwidth increases in proportion to the order of the nonlinearity. For example, the third-order nonlinear Volterra operator expands the signal bandwidth by three times. Therefore, the final bandwidth of the output signal depends on the highest-order nonlinear Volterra operator. Therefore, since the first distortion compensation circuit 210 has a first distortion compensation characteristic specified by a relatively high-order first characteristic formula, the frequency bandwidth of the output signal is relatively wide. On the contrary, since the second distortion compensation circuit 217 has a second distortion compensation characteristic specified by a relatively low-order second characteristic formula, the frequency bandwidth of the output signal is relatively narrow.

[0088] When viewed from the predistorter 21B side, there are only distortion components of the distortion of the amplifier 50 that are not compensated by the predistorter 21A, and therefore, the nonlinearity of the distortion to be compensated by the predistorter 21B is not particularly strong. Therefore, even when the predistorter 21B compensates only for low-order distortion, no serious problem is caused.

[0089] The predistorter 21B includes a circuit serving as a second updating unit 218 for updating the second distortion compensation coefficient 219a. The second updating unit 218 includes a wired logic circuit for performing a second updating process to update the second distortion compensation coefficient 219a. The second updating process is performed based on, for example, sampling data 219b indicating the output z[n] of the amplifier 50. The sampling data 219b obtained by the predistorter 21B is stored in a sampling data storage unit of the second updating unit 218.

[0090] The second updating unit 218 performs calculations for updating the second distortion compensation coefficient 219a at a frequency higher than the frequency of the predistorter A. For example, the second updating unit 218 updates the second distortion compensation coefficient 219a for each sampling period 1 / f of the sampled data 219b. s [s], or update the second distortion compensation coefficient 219a for the sampling period 1 / f s The second distortion compensation coefficient 219a for each period is several times the length of [s]. In the following, it is described that for each sampling period 1 / f s [s] Example of updating the second distortion compensation coefficient 219a. For example, the second updating unit 218 calculates the second distortion compensation coefficient 219a by least mean square (LMS) based on one or more sample data 219b. The calculated second distortion compensation coefficient 219a is provided to the second distortion compensation circuit 217 to update the distortion compensation coefficient used in the second distortion compensation circuit 217.

[0091] The amount of sample data 219b used for one coefficient update by the second update unit 218 is small. Therefore, a few flip-flops provided in the second update unit 218 are sufficient as a coefficient storage unit for storing the sample data 219b therein. The coefficient storage unit does not need to be a large-capacity memory.

[0092] For example, the second distortion compensation coefficient based on LMS is calculated based on the following formulas (3) and (4): Based on formula (2), distortion compensation using the calculated second distortion compensation coefficient is performed.

[0093] [Mathematical formula 3]

[0094]

[0095] [Formula 4]

[0096]

[0097] In the above formula, n is discrete time, α is a predetermined coefficient, K is a polynomial vector for distortion compensation, z[n-1] is sampled data at discrete time n-1, h[n] and h[n-1] are second distortion compensation coefficient vectors at discrete time n and discrete time n-1, respectively, y[n] and y[n-1] are outputs (distortion compensation signals) of the predistorter 21B at discrete time n and discrete time n-1, respectively, and λ is a weight (0<λ<1). The coefficient vector h[n] and the polynomial vector K(z[n]) at time n are defined by the following formulas (5) and (6). T represents transpose and H represents conjugate transpose.

[0098] [Formula 5]

[0099] h[n]=(h 1，0 [n],h 1，1 [n],…,h 1,M [n],h 2,0 [n],…,h 2,M [n],…,h K,0 [n],…,h K,M [n]) T ····(5)

[0100] [Mathematical formula 6]

[0101] K(z[n])=(z[n],z[n-1],…,z[nM],|z[n]|·z[n],…,|z[nM]|·z[nM],…,|z[n]| K-1 z[n], …, |z[nM]| K-1 ·z[nM])····(6)

[0102] Formula (3) calculates the updated value of the second distortion compensation coefficient vector h[n-1] based on the sampled data z[n-1] and the output y[n-1] of the predistorter 21B. Formula (4) calculates the time average value of the value updated by formula (3). The calculation of formula (2) is performed by using the time average value of the second distortion compensation coefficient calculated by formula (3). When the predistorter 21B obtains the sampled data, if there is no less than one sampling period 1 / f s If the delay d is [s], then “n-1” in formulas (3) and (4) can be replaced by “nd”.

[0103] The calculation method such as LMS has lower calculation accuracy than the least squares method, but has a smaller processing burden than the least squares method because the calculation is relatively simple. In addition, the number of coefficients to be calculated and the number of sample data 219b required for coefficient update are both smaller than the least squares method.

[0104] For example, for each sampling period 1 / f s [s] or for sampling period 1 / f s The coefficient update by the second update unit 218 is performed at a high frequency for each cycle that is several times the length of [s]. In addition, the second update unit 218 is a wired logic circuit and can therefore perform calculations at high speed. Therefore, the second update unit 218 can track instantaneous changes in distortion caused by Idq drift, etc., to quickly update the second distortion compensation coefficient 219a.

[0105] Although the second updating unit 218 updates the coefficient at a high frequency, since the processing burden of each update is not large, the processing burden can be reduced and the circuit scale can also be reduced compared to the case where the coefficient updating process with a large processing burden is performed at a high frequency.

[0106] according to Figure 2 In the distortion compensation device 20 shown, the predistorter 21A compensates for distortion during normal operation, rather than compensating for distortion when an instantaneous distortion change occurs due to Idq drift, etc., and at the same time, the predistorter 21B tracks the instantaneous change of distortion due to Idq drift, etc. in real time to perform distortion compensation. In addition, since the predistorter 21A is provided, an increase in the processing load of the predistorter 21B is suppressed, thereby suppressing an increase in the hardware scale.

[0107] The LMS as the calculation algorithm of the second distortion compensation coefficient 219a may be NLMS (Normalized Least Mean Square). The calculation function of the second distortion compensation coefficient 219a by LMS is Figure 3An example of the second updating unit 218 is shown. For example, the second distortion compensation coefficient 219a may be calculated by another algorithm such as least squares, RMS or RLS. Alternatively, the second distortion compensation coefficient 219a may be derived by using a correspondence table between the sampled data and the second distortion compensation coefficient.

[0108] exist Figure 2 In the example shown, the predistorter 21B is implemented as a wired logic circuit. However, regarding the update of the distortion compensation coefficient, the predistorter 21B may be implemented as a computer having a processor and a memory, just like the predistorter 21A. In this case, the coefficient update process in the predistorter 21B is performed by the processor executing a computer program stored in the memory.

[0109] [2. Operation of distortion compensation device]

[0110] Next, the operation of the distortion compensation device 20 according to the present embodiment is described. Figure 4 is a flowchart showing an example of an operation procedure performed by the predistorter 21A.

[0111] The processor 211 of the predistorter 21A performs a first update process (step S101 ). Through the first update process, the first distortion compensation coefficient 215 a is determined, and the first distortion compensation characteristic of the first distortion compensation circuit 210 is set.

[0112] The first distortion compensation circuit 210, which has been set with the first distortion compensation characteristic, performs a first distortion compensation process (step S102). The first distortion compensation process is a process in which the first distortion compensation circuit 210 receives an input signal y[n], performs distortion compensation on the input signal y[n] according to the first distortion compensation characteristic to generate an output signal y[n]', and outputs the output signal y[n]'.

[0113] The processor 211 determines whether the update timing for the first distortion compensation characteristic has been reached (step S103). The first update process is performed at a low frequency. Therefore, the interval between updates is set to a relatively long time. For example, for a sampling period of 1 / f s The first update process is performed every cycle of several tens to several hundreds times the length of [s].

[0114] When the update timing has not been reached (No in step S103), the process returns to step S102, and the first distortion compensation circuit 210 performs the first distortion compensation process. s A first distortion compensation process is performed.

[0115] When the update timing has been reached (YES in step S103), the process returns to step S101, and the processor 211 executes the first update process again.

[0116] By repeatedly performing the above operation, the first distortion compensation characteristic is updated at a low frequency, and for each sampling period f s A first distortion compensation process is performed.

[0117] Figure 5 is a flowchart illustrating an example of a first update process.

[0118] The processor 211 receives the sampled data 215b (step S111), and stores the sampled data 215b in the memory 212 (step S112). The sampled data 215b corresponding to the past predetermined period of time is accumulated in the memory 212. That is, in step S112, the newly received sampled data is added and stored in the memory 212 storing the past sampled data 215b.

[0119] The processor 211 reads out the sample data 215b corresponding to the predetermined period from the memory 212 (step S113). The processor 211 uses the read sample data 215b to solve the normal equation by the least square method, thereby calculating the first distortion compensation coefficient 215a (step S114).

[0120] The processor 211 sends the first distortion compensation coefficient 215a to the first distortion compensation circuit 210 to set the first distortion compensation circuit 210 (step S115). Thus, the first distortion compensation characteristic is updated. Then, the first update process ends.

[0121] Next, the operation of the predistorter 21B is described. Figure 6 is a flowchart showing an example of an operation procedure performed by the predistorter 21B.

[0122] The second updating unit 218 of the predistorter 21B performs a second updating process (step S201 ), through which the second distortion compensation coefficient 219 a is determined and the second distortion compensation characteristic of the second distortion compensation circuit 217 is set.

[0123] The second distortion compensation circuit 217, to which the second distortion compensation characteristic has been set, performs a second distortion compensation process (step S202). The second distortion compensation process is a process in which the second distortion compensation circuit 217 receives an input signal z[n], performs distortion compensation on the input signal z[n] according to the second distortion compensation characteristic to generate an output signal y[n], and outputs the output signal y[n].

[0124] When the second distortion compensation process is finished, the second update process is performed again (step S201). That is, in this example, the second update process and the second distortion compensation process are repeatedly performed. For example, for each sampling period 1 / f s [s] Perform the second updating process and the second distortion compensation process.

[0125] As described above, the second update process is performed at a high frequency. For example, the sampling period may be 1 / f of the sampling period. s The second update process is performed every cycle which is several times the length of [s].

[0126] By repeatedly performing the above operation, the second distortion compensation characteristic is updated at a high frequency, and for each sampling period f s A second distortion compensation process is performed.

[0127] Figure 7 is a flowchart illustrating an example of the second update process.

[0128] The second update unit 218 receives the sample data 219b (step S211), and stores the sample data 219b (step S212). The sample data 219b corresponding to the past predetermined period of time (a period shorter than the storage period of the sample data 215b) is accumulated in the second update unit 218. That is, in step S212, the newly received sample data is added and stored in the sample data storage unit storing the past sample data 219b.

[0129] The second updating unit 218 reads out the sample data 219b corresponding to the predetermined period from the sample data storage unit (step S213). The second updating unit 218 uses the read sample data 219b to solve the normal equation by LMS, thereby calculating the second distortion compensation coefficient 219a (step S214).

[0130] The second updating unit 218 sends the second distortion compensation coefficient 219a to the second distortion compensation circuit 217 to set the second distortion compensation circuit 217 (step S215). Thus, the second distortion compensation characteristic is updated. Then, the second updating process ends.

[0131] In the distortion compensation device 20 according to the present embodiment, the first distortion compensation circuit 210 processes distortion that does not change with time or changes slowly with time due to the state of the amplifier 50 such as temperature, operating time or power, and the second distortion compensation circuit 217 processes distortion that changes quickly with time due to high-speed drift such as Idq drift. That is, the distortion caused by the amplifier 50 includes a first distortion that does not change with time or changes slowly with time, and a second distortion that changes faster than the first distortion. The second update unit 218 updates the second distortion compensation characteristic at a higher frequency than the first update unit 213. Therefore, the time variation of the second distortion can be processed. In addition, the first distortion compensation circuit 210 compensates for both nonlinear distortion and memory effect distortion. Therefore, both nonlinear distortion and memory effect distortion included in the first distortion can be processed. Therefore, high-precision distortion compensation can be achieved.

[0132] The second distortion compensation circuit 217 can compensate for both nonlinear distortion and memory effect distortion, thereby achieving distortion compensation with higher accuracy.

[0133] The second distortion compensation characteristic of the second distortion compensation circuit 217 can be specified by a second characteristic formula having a lower order than the first characteristic formula. Therefore, even when updating of the second distortion compensation characteristic is performed at a high frequency, the processing load can be suppressed.

[0134] The frequency bandwidth of the output signal of the second distortion compensation circuit 217 can be narrower than the frequency bandwidth of the output signal of the first distortion compensation circuit 210. According to the increase in the frequency bandwidth of the output signal, the processing load is increased. Therefore, when the second frequency bandwidth is set to be narrow, the processing load can be suppressed even when the update of the second distortion compensation characteristic is performed at a high frequency.

[0135] [3. Other examples of distortion compensation devices]

[0136] Figure 8 Another example of a distortion compensation device 20 is shown. Figure 8 The distortion compensation device 20 shown includes a predistorter 22A and a predistorter 22B connected in cascade to each other. Figure 8 In the embodiment, the predistorter 22A is Figure 1 An example of a predistorter A is shown in FIG. Figure 8 In the example, the predistorter 22B is Figure 1 An example of a predistorter B is shown in FIG.

[0137] Figure 8 The predistorter 22A shown in FIG. 5 performs analog predistortion (APD). The predistorter 22A is implemented as an analog circuit having an inverse characteristic of the amplification characteristic of the amplifier 50 . Figure 8The predistorter 22A shown in FIG. 1 is functionally equivalent to the predistorter 22A with the coefficient update function eliminated. Figure 2 The predistorter 21A is shown. Figure 8 The illustrated predistorter 22A does not have an updating function for the distortion compensation characteristics and therefore cannot handle time variations of the distortion. The predistorter 22B handles time variations of the distortion, including instantaneous variations of the distortion.

[0138] The predistorter 22B is configured to perform digital predistortion (DPD). The configuration and function of the predistorter 22B are similar to those of Figure 2 The configuration and function of the predistorter 21B shown are the same. The coefficient update module in the predistorter 22B may be implemented as a computer having a memory and a processor.

[0139] according to Figure 8 In the distortion compensation device 20 shown, the predistorter 22A excludes the distortion component corresponding to the time-varying portion from the distortion of the compensation amplifier 50, and the predistorter 22B tracks the time variation of the distortion in real time to perform distortion compensation. In addition, since the predistorter 22A is provided, the increase in the processing load of the predistorter 22B is suppressed, thereby suppressing the increase in the hardware scale.

[0140] exist Figure 8 In the embodiment, a DAC 22C is provided between the predistorter 22B and the predistorter 22A. The digital distortion compensation signal output from the predistorter 22B is converted into an analog signal by the DAC 22C. The analog distortion compensation signal is provided to the predistorter 22A. Since the output of the predistorter 22A is an analog signal, Figure 8 No need to Figure 1 The DAC 30 is provided between the distortion compensation device 20 and the up-converter 40.

[0141] Fig. 9 Yet another example of a distortion compensation device 20 is shown. Fig. 9 The distortion compensation device 20 shown includes a predistorter A and a predistorter B connected in cascade to each other. Fig. 9 In the example, the arrangement of predistorter A and predistorter B is similar to Figure 1 The arrangement shown is reversed and predistorter B is connected to the output side of predistorter A.

[0142] Also in Fig. 9 In the distortion compensation device 20 shown, the predistorter A compensates for distortion during normal operation, rather than compensating for distortion when an instantaneous distortion change occurs due to Idq drift, etc., and at the same time, the predistorter B tracks the instantaneous change of distortion due to Idq drift, etc. in real time to perform distortion compensation. In addition, since the predistorter A is provided, an increase in the processing burden of the predistorter B is suppressed, thereby suppressing an increase in the hardware scale.

[0143] Fig.10 Yet another example of a distortion compensation device 20 is shown. Fig.10 The distortion compensation device 20 shown includes a predistorter A and a predistorter B connected in parallel. Fig.10 In the present invention, the baseband signal x[n] is provided to the predistorter A and the predistorter B. The predistorter A compensates for the distortion during normal operation, rather than compensating for the distortion when the instantaneous distortion changes due to Idq drift, etc. The predistorter A outputs a first distortion compensation signal y1[n]. The predistorter B processes the instantaneous distortion changes due to Idq drift, etc., and outputs a second distortion compensation signal y2[n]. The first distortion compensation signal y1[n] and the second distortion compensation signal y2[n] are added by an adder. The distortion compensation device 20 outputs the distortion compensation signal y[n] obtained by the addition.

[0144] Also in Fig.10 In the distortion compensation device 20 shown, the predistorter A compensates for distortion during normal operation, rather than compensating for distortion when an instantaneous distortion change occurs due to Idq drift, etc., and at the same time, the predistorter B tracks the instantaneous distortion change due to Idq drift, etc. in real time to perform distortion compensation. In addition, since the predistorter A is provided, an increase in the processing burden of the predistorter B is suppressed, thereby suppressing an increase in the hardware scale.

[0145] Fig.11 Another example of a wireless communicator is shown. Fig.11 The wireless communicator 100 shown includes a first filter 401 and a second filter 402 that convert the monitoring signal z[n].

[0146] The signal line on the output side of the ADC 80 is branched. A first filter 401 as a digital filter is connected to one branch, and a second filter 402 as a digital filter is connected to the other branch.

[0147] Each of the first filter 401 and the second filter 402 may be a filter that allows a signal in a specific frequency band to pass through, and may be, for example, one of a low-pass filter, a band-pass filter, and a high-pass filter. The type of filter (passband) may be determined based on the frequency band on which the down-converter 70 performs down-conversion. For example, when the wireless communicator 100 is a zero intermediate frequency type, i.e., a direct conversion receiver, the first filter 401 and the second filter 402 may be implemented as low-pass filters, respectively. In the case of a zero intermediate frequency wireless communicator, the center frequency of the output signal of the ADC 80 is generally a direct current (frequency = 0), and when the first filter 401 and the second filter 402 are implemented as low-pass filters, respectively, signals in the signal band and the adjacent frequency band are allowed to pass therethrough.

[0148] The output side of the first filter 401 is connected to the first update unit 213. The first monitor signal z1[n], which is an output signal from the first filter 401, is input to the first update unit 213. The first update unit 213 obtains sampling data from the input first monitor signal z1[n], and based on the sampling data, updates the first distortion compensation coefficient to be provided to the first distortion compensation circuit 310 through a first update process.

[0149] The output side of the second filter 402 is connected to the second update unit 218. The second monitor signal z2[n], which is an output signal from the second filter 402, is input to the second update unit 218. The second update unit 218 obtains sampling data from the input second monitor signal z2[n], and based on the sampling data, updates the second distortion compensation coefficient to be provided to the second distortion compensation circuit 320 through a second update process.

[0150] The passband of the second filter 402 is narrower than the passband of the first filter 401. That is, the frequency bandwidth of the second monitoring signal z2[n] as the output signal from the second filter 402 is narrower than the frequency bandwidth of the first monitoring signal z1[n] as the output signal from the first filter 401. Since the second distortion compensation circuit 320 compensates for relatively low-order distortion (low-order nonlinearity), it is not necessary to monitor the outer band corresponding to the high-order distortion in the entire frequency band of the signal z[n]. In addition, the signal component in the outer band may cause the instability of the second distortion compensation coefficient. In the present improvement, since the passband of the second filter 402 is narrower than the passband of the first filter 401, the second monitoring signal z2[n] with the signal component of the outer band eliminated can be obtained, and the instability of the second distortion compensation coefficient can be suppressed.

[0151] When compared with the second distortion compensation circuit 320, the first distortion compensation circuit 310 compensates for distortion up to high-order distortion (high-order nonlinearity), and therefore requires an outer band corresponding to the high-order distortion. In contrast, the lack of signal components in the outer band can lead to instability of the first distortion compensation coefficient. In the present improvement, since the passband of the first filter 401 is wider than the passband of the second filter 402, the first monitoring signal z1[n] containing the signal components in the outer band can be obtained, thereby suppressing the instability of the first distortion compensation coefficient.

[0152] The first filter 401 may not necessarily be a filter that allows a specific frequency band to pass, such as a low-pass filter, a band-pass filter, or a high-pass filter. For example, the first filter 401 may be a filter that allows the entire bandwidth to pass, such as an all-pass filter.

[0153] Each of the first filter 401 and the second filter 402 may be an analog filter. Fig.12An example of a wireless communicator is shown, in which the first filter 401 and the second filter 402 are respectively implemented as analog filters.

[0154] The signal line on the output side of the down converter 70 is branched. A first filter 401 as an analog filter is connected to one branch, and a second filter 402 as an analog filter is connected to the other branch. An anti-aliasing filter 411 and an ADC 421 are connected in series on the output side of the first filter 401. An anti-aliasing filter 412 and an ADC 422 are connected in series on the output side of the second filter 402.

[0155] Each of the first filter 401 and the second filter 402 may be a filter that allows a signal in a specific frequency band to pass through, and may be, for example, one of a low-pass filter, a band-pass filter, and a high-pass filter. The type of filter (passband) may be determined based on the frequency band on which the down-converter 70 performs down-conversion. For example, when the wireless communicator 100 is a zero intermediate frequency type, i.e., a direct conversion receiver, the first filter 401 and the second filter 402 may be implemented as low-pass filters, respectively. In the case of a zero intermediate frequency wireless communicator, the center frequency of the output signal of the ADC 80 is generally a direct current (frequency = 0), and when the first filter 401 and the second filter 402 are implemented as low-pass filters, respectively, signals in the signal band and the adjacent frequency band are allowed to pass therethrough.

[0156] The output side of the ADC 421 is connected to the first update unit 213. The first monitor signal z1[n], which is an output signal from the ADC 421, is input to the first update unit 213. The first update unit 213 obtains sampling data from the input first monitor signal z1[n], and based on the sampling data, updates the first distortion compensation coefficient to be provided to the first distortion compensation circuit 310 through a first update process.

[0157] The output side of the ADC 422 is connected to the second update unit 218. The second monitor signal z2[n], which is an output signal from the ADC 422, is input to the second update unit 218. The second update unit 218 obtains sampling data from the input second monitor signal z2[n], and based on the sampling data, updates the second distortion compensation coefficient to be provided to the second distortion compensation circuit 320 through a second update process.

[0158] The passband of the second filter 402 is narrower than the passband of the first filter 401. That is, the frequency bandwidth of the second monitoring signal z2[n] as the output signal from the ADC 422 is narrower than the frequency bandwidth of the first monitoring signal z1[n] as the output signal from the ADC 421. In the present improvement, since the passband of the second filter 402 is narrower than the passband of the first filter 401, the second monitoring signal z2[n] from which the signal components in the outer band are eliminated can be obtained, and the instability of the second distortion compensation coefficient can be suppressed. In addition, since the passband of the first filter 401 is wider than the passband of the second filter 402, the first monitoring signal z1[n] containing the signal components in the outer band can be obtained, and the instability of the first distortion compensation coefficient can be suppressed.

[0159] Fig.13 Another example of a wireless communicator is shown, in which the first filter 401 and the second filter 402 are respectively implemented as analog filters.

[0160] The signal line on the output side of the down converter 70 is branched. The first filter 401 is connected to one branch, and the second filter 402 is connected to the other branch. The first filter 401 is an anti-aliasing filter. The ADC 421 is connected to the output side of the first filter 401. The second filter 402 is a filter that allows a signal in a specific frequency band to pass, and can be, for example, one of a low-pass filter, a band-pass filter, and a high-pass filter. The anti-aliasing filter 412 and the ADC 422 are connected in series on the output side of the second filter 402.

[0161] Fig.14 Another example of a wireless communicator is shown, in which the first filter 401 and the second filter 402 are respectively implemented as analog filters.

[0162] The signal line on the output side of the coupler 36 is branched, and the down converters 471, 472 are connected to the corresponding branches. The first filter 401 is connected to the output side of the down converter 471, and the second filter 402 is connected to the output side of the down converter 472. The anti-aliasing filter 411 and the ADC 421 are connected in series on the output side of the first filter 401. The anti-aliasing filter 412 and the ADC 422 are connected in series on the output side of the second filter 402.

[0163] Fig.15 Yet another example of a distortion compensation device is shown. Fig.15 The distortion compensation device 300 shown includes a first distortion compensation circuit 310, a second distortion compensation circuit 320, and an updating unit 330. The updating unit 330 updates a first distortion compensation characteristic of the first distortion compensation circuit 310 and a second distortion compensation characteristic of the second distortion compensation circuit 320.

[0164] The first distortion compensation circuit 310 has a first distortion compensation characteristic represented by, for example, a first characteristic formula of Formula (1). The second distortion compensation circuit 320 has a second distortion compensation characteristic represented by, for example, a second characteristic formula of Formula (2).

[0165] Fig.16 3 is a block diagram showing an example of the configuration of the distortion compensation device 300 in the present improvement. The distortion compensation device 300 in this example includes an update unit 330 implemented as a computer having a processor 331 and a memory 332. The processor 331 executes a coefficient update program 333, which is a computer program stored in the memory 332. Each function of the update unit 330 is exhibited by the processor 331, and the processor 331 executes the coefficient update program 333, which is a computer program stored in the memory 332 of the computer. The coefficient update program 333 may be stored in a storage medium such as a CD-ROM. The processor 331 executes the coefficient update program 333 to perform the first update process and the second update process described later.

[0166] The coefficient updating program 333 includes a program code that causes the processor 331 to perform a first updating process for updating the first distortion compensation coefficient 334a and a second updating process for updating the second distortion compensation coefficient 334b. The first updating process and the second updating process are performed based on, for example, the sampled data 335 indicating the output z[n] of the amplifier 50. The sampled data 335 obtained by the distortion compensation device 300 is stored in the memory 332.

[0167] In the first updating process, for example, the processor 331 solves the normal equation according to the least square method based on several thousand sample data 335 obtained by sampling within a predetermined time (for example, several minutes), thereby calculating the first distortion compensation coefficient 334a. The calculated first distortion compensation coefficient 334a is provided to the first distortion compensation circuit 310 to update the distortion compensation coefficient used in the first distortion compensation circuit 310.

[0168] In the second updating process, for example, the processor 331 solves LMS according to, for example, formulas (3) and (4) based on a portion of the sampled data 335, thereby calculating a second distortion compensation coefficient 334b. The calculated second distortion compensation coefficient 334b ​​is provided to the second distortion compensation circuit 320 to update the distortion compensation coefficient used in the second distortion compensation circuit 320.

[0169] The number of the second distortion compensation coefficients 334b ​​is smaller than the number of the first distortion compensation coefficients 334a. Therefore, the processing load for calculating the second distortion compensation coefficients 334b ​​is smaller than the processing load for calculating the first distortion compensation coefficients 334a. The first update process is performed at a low frequency, while the second update process is performed at a high frequency.

[0170] Next, the operation of the distortion compensation device 300 in this example is described. Fig.17 is a flowchart showing an example of a procedure of an operation performed by the distortion compensation apparatus 300 .

[0171] The processor 331 performs a first update process (step S301 ). Through the first update process, the first distortion compensation coefficient 334 a is determined, and the first distortion compensation characteristic of the first distortion compensation circuit 310 is set.

[0172] The processor 331 performs a second updating process (step S302 ). Through the second updating process, the second distortion compensation coefficient 334 b is determined, and the second distortion compensation characteristic of the second distortion compensation circuit 320 is set.

[0173] The first distortion compensation circuit 310, which has been set with the first distortion compensation characteristic, performs a first distortion compensation process (step S303). The first distortion compensation process is a process in which the first distortion compensation circuit 310 receives an input signal y[n], performs distortion compensation on the input signal y[n] according to the first distortion compensation characteristic to generate an output signal y[n]', and outputs the output signal y[n]'.

[0174] The second distortion compensation circuit 320, to which the second distortion compensation characteristic has been set, performs a second distortion compensation process (step S304). The second distortion compensation process is a process in which the second distortion compensation circuit 320 receives an input signal z[n], performs distortion compensation on the input signal z[n] according to the second distortion compensation characteristic to generate an output signal y[n], and outputs the output signal y[n].

[0175] The processor 331 determines whether the update timing for the first distortion compensation characteristic has been reached (step S305). The first update process is performed at a low frequency. Therefore, the interval between updates is set to a relatively long time.

[0176] When the update timing has not been reached (step S305 is "No"), the process returns to step S302, the processor 331 performs the second update process (step S302), the first distortion compensation circuit 310 performs the first distortion compensation process (step S303), and the second distortion compensation circuit 320 performs the second distortion compensation process (step S304). For example, for each sampling period f s The second update process is performed. For each sampling period fs A first distortion compensation process and a second distortion compensation process are performed.

[0177] When the update timing has been reached ("Yes" in step S305), the process returns to step S301, and the processor 331 performs the first update processing. For example, for a sampling period of 1 / f s The first update process is performed every cycle of several tens to several hundreds times the length of [s].

[0178] The first update process S301 and the second update process S302 may be similar to, for example, Figure 5 and Figure 7 The processes of the first update process and the second update process shown in FIG.

[0179] By repeatedly performing the above operation, the first distortion compensation characteristic is updated at a low frequency, while the second distortion compensation characteristic is updated at a high frequency. s A first distortion compensation process and a second distortion compensation process are performed.

[0180] Fig.18 3 is a block diagram showing another example of the configuration of the distortion compensation apparatus 300. In this example, the update unit 330 is implemented as a wired logic circuit such as an FPGA or an ASIC (Application Specific Integrated Circuit), rather than a computer.

[0181] The updating unit 330 includes a partial circuit for performing a first updating process for updating the first distortion compensation coefficient 334a and a partial circuit for performing a second updating process for updating the second distortion compensation coefficient 334b. The first updating process is performed based on the sampling data 335 indicating the output z[n] of the amplifier 50, and the second updating process is performed based on, for example, a part of the sampling data 335. The sampling data 335 obtained by the distortion compensation device 300 is stored in the sampling data storage unit of the updating unit 330.

[0182] The number of the second distortion compensation coefficients 334b ​​is smaller than the number of the first distortion compensation coefficients 334a. Therefore, the processing load for calculating the second distortion compensation coefficients 334b ​​is smaller than the processing load for calculating the first distortion compensation coefficients 334a. In the update process, the first distortion compensation coefficients 334a are calculated at a low frequency, while the second distortion compensation coefficients 334b ​​are calculated at a high frequency.

[0183] [4. Appendix]

[0184] It should be noted that the embodiments disclosed herein are only illustrative and not restrictive in all aspects. The scope of the present invention is defined by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all improvements within the scope.

[0185] Reference Symbols List

[0186] 100 Wireless Communicator

[0187] 20,300 Distortion Compensation Equipment

[0188] 30,22C Digital to Analog Converter

[0189] 36 Coupler

[0190] 40 Upconverter

[0191] 50 Power Amplifier

[0192] 60 Antenna

[0193] 70, 471, 472 Downconverter

[0194] 80 Analog-to-digital converter

[0195] 21A, 22A, A First predistorter

[0196] 21B, 22B, B Second predistorter

[0197] 210, 310 first distortion compensation circuit

[0198] 211, 331 processors

[0199] 212, 332 memory

[0200] 213 First Update Unit

[0201] 214,333 Coefficient Update Procedure

[0202] 215a, 334a First distortion compensation coefficient

[0203] 215b, 219b, 335 sampling data

[0204] 217, 320 Second distortion compensation circuit

[0205] 218 Second Update Unit

[0206] 219a, 334b ​​Second distortion compensation coefficient

[0207] 221 First nonlinear compensation unit

[0208] 222 Second nonlinear compensation unit

[0209] 231 First memory effect compensation unit

[0210] 232 Second memory effect compensation unit

[0211] 330 Update Unit

[0212] 401 First Filter

[0213] 402 Second filter

[0214] 411, 412 Anti-aliasing filter

Claims

1. A distortion compensation device, comprising: a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; as well as An updating unit, the updating unit being configured to update the second distortion compensation characteristic, wherein: The first distortion includes nonlinear distortion and memory effect distortion, The second distortion is a distortion whose time variation is faster than that of the first distortion, and The updating unit updates the second distortion compensation characteristic at a frequency higher than an updating frequency of the first distortion compensation characteristic.

2. The distortion compensation device according to claim 1, wherein: The second distortion includes at least one of the nonlinear distortion and the memory effect distortion.

3. The distortion compensation device according to claim 1 or 2, wherein: The first distortion compensation characteristic is specified by a first characteristic formula of a predetermined order, and The second distortion compensation characteristic is specified by a second characteristic formula, and the order of the second characteristic formula is lower than that of the first characteristic formula.

4. The distortion compensation device according to claim 1 or 2, wherein: The first distortion compensation circuit outputs an output signal having a first frequency bandwidth, and The second distortion compensation circuit outputs an output signal having a second frequency bandwidth narrower than the first frequency bandwidth.

5. The distortion compensation device according to claim 1 or 2, wherein: The updating unit includes a first updating unit configured to update the first distortion compensation characteristic; and a second updating unit configured to update the second distortion compensation characteristic; The first updating unit updates the first distortion compensation characteristic based on a first monitor signal obtained from an output signal of the amplifier, The second updating unit updates the second distortion compensation characteristic based on a second monitor signal obtained from the output signal of the amplifier, and A frequency bandwidth of the second monitoring signal is narrower than a frequency bandwidth of the first monitoring signal.

6. A wireless communicator, comprising: an amplifier configured to amplify a signal having a radio frequency; a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion generated in an output of the amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion generated in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; as well as An updating unit, the updating unit being configured to update the second distortion compensation characteristic, wherein: The first distortion includes nonlinear distortion and memory effect distortion, The second distortion is a distortion whose time variation is faster than that of the first distortion, and The updating unit updates the second distortion compensation characteristic at a frequency higher than an updating frequency of the first distortion compensation characteristic.

7. The wireless communicator of claim 6, further comprising: a first filter configured to convert a monitoring signal obtained from an output signal of the amplifier into a first monitoring signal; as well as a second filter configured to convert the monitoring signal into a second monitoring signal, the frequency bandwidth of the second monitoring signal being narrower than the frequency bandwidth of the first monitoring signal, wherein The updating unit comprises: a first updating unit configured to update the first distortion compensation characteristic based on the first monitoring signal output from the first filter, and A second updating unit configured to update the second distortion compensation characteristic based on the second monitor signal output from the second filter.

8. A predistorter, the predistorter being connected to an external distortion compensation circuit, the external distortion compensation circuit being configured to compensate for a first distortion generated in an output of an amplifier, the predistorter comprising: a distortion compensation circuit having a distortion compensation characteristic for compensating for a second distortion different from the first distortion among the distortions generated in the output of the amplifier; as well as An updating unit, the updating unit being configured to update the distortion compensation characteristic, wherein: The first distortion includes nonlinear distortion and memory effect distortion, The second distortion is a distortion whose time variation is faster than that of the first distortion, and The updating unit updates the distortion compensation characteristic at a frequency higher than an updating frequency of the external distortion compensation circuit.

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