Method for manufacturing thick dielectric films using stress control

Abstract

A method of fabricating a thick crack-free dielectric film on a wafer for device fabrication is disclosed herein. A stress release pattern is fabricated in an oxide layer of the wafer surrounding a plurality of device regions. The stress release pattern includes a plurality of recesses periodically spaced apart along at least one direction. The plurality of recesses interrupts a continuous film during dielectric film deposition to prevent cracks from forming in the dielectric film and propagating into the device regions. Thus, a thick crack-free dielectric film can be obtained in the device regions formed by patterning the dielectric layer. Furthermore, conditions of the dielectric film deposition process can be adjusted to ensure the quality of the deposited dielectric film. Moreover, a plurality of deposition processes can be performed to deposit a thick crack-free dielectric film.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 973,277, filed September 27, 2019, entitled “METHOD FOR FABRICATING THICK DIELECTRIC FILMS USING STRESS CONTROL,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the fabrication of integrated devices requiring stress control. More specifically, this disclosure relates to the fabrication of devices on a crack-free, thick stoichiometric silicon nitride (Si3N4) film deposited on a silicon wafer coated with silicon dioxide. Background Technology

[0004] Silicon-based photonic integrated circuits, utilizing the strong optical third-order nonlinearity and field enhancement in strongly confined structures of silicon-based materials, have recently attracted research and development interest for realizing energy-efficient optical nonlinearities and quantum sources on-chip. Among the three conventional silicon complementary metal-oxide-semiconductor (CMOS) materials (i.e., silicon, silicon dioxide, and silicon nitride), silicon nitride exhibits lower linear and nonlinear optical absorption losses compared to silicon, and a third-order optical nonlinearity one order of magnitude larger than that of silicon dioxide. This is in contrast to SiN deposited via plasma-enhanced chemical vapor deposition. x In comparison, stoichiometric silicon nitride (i.e., Si3N4) deposited via low-pressure chemical vapor deposition (LPCVD) offers lower material absorption loss in the 1550 nm communication band due to the lower NH bond content at approximately 1520 nm, where the absorption peak is located. Therefore, for the 1550 nm communication band, Si3N4 is superior to SiN. x Considering the low loss, Si3N4 optical microring resonators have shown performance exceeding 10. 7 It achieves a high-quality (Q) factor and realizes nonlinear optical parametric oscillations with sub-milliwatt threshold power.

[0005] In the field of silicon photonics, it has been observed that Si3N4 films with thicknesses exceeding 700 nm are required to design waveguide dispersion for optical nonlinear frequency conversion. However, thick Si3N4 films deposited by LPCVD exhibit large tensile stresses, which tend to lead to crack formation throughout the wafer. This typically limits the film thickness to less than 400 nm.

[0006] To grow thick Si3N4 films of about 910 nm, researchers have developed a temperature cycling method along with a hand-scribed trench to stop the crack propagation into the about 50 mm x 50 mm central device area. Deposition of films with thicknesses exceeding 400 nm is performed in multiple cycles, with temperature cooling to room temperature and pulling the wafer out of the furnace between each cycle. However, this process is not effective in stopping the crack once it is formed within the device area. It is also likely that a silicon oxynitride layer is formed when the wafer is exposed to air between cycles.

[0007] A recently developed photonic Damascene process utilizes an additive manufacturing process, where Si3N4 is deposited after etching a negative pattern of waveguides in the oxide layer. The waveguides are surrounded by a carefully designed dense filler pattern on the underlying oxide layer. A 1.5 pm thick Si3N4 film for waveguide-based devices has been demonstrated. However, the photonic Damascene process is not a standard CMOS process and imposes an additional chemical mechanical polishing (CMP) step for forming the Si3N4 device. The CMP process can potentially induce mechanical shock that can form cracks and hinder the fabrication of large area devices such as disk resonators. In addition, local deviations in the CMP removal rate impose a limit on the good control of the device height.

[0008] Another crack-free process for depositing LPCVD nitride-based films on 6-inch and 8-inch wafers requires rotating the wafer by 45° between film deposition to redistribute the uniaxial stress. The film deposition is performed in two steps, with 365 nm thick Si3N4 films deposited in each step. Each deposition process is performed at 780 °C, and the latter deposition is cooled to about 630 °C for 20 minutes. This fabrication method enables relatively thick crack-free Si3N4 films to reach a thickness of 730 nm. However, rotating the wafer by 45° within the furnace is a non-standardized process.

[0009] There is a need to address these or other issues related to the deposition of thick crack-free dielectric films. SUMMARY

[0010] Fabrication of various types of semiconductor devices requires the fabrication of thick crack-free dielectric films on silicon wafers. The present disclosure provides a solution for fabricating large area, thick crack-free dielectric films on silicon dioxide substrates for the fabrication of devices and circuits.

[0011] In a first aspect of the disclosure, a method of fabricating a dielectric film on a wafer is described. The method includes the steps of fabricating a predetermined pattern in an oxide layer of the wafer to define a plurality of device regions on a top surface of the wafer, depositing a dielectric film on the oxide layer, and patterning the dielectric film to form a plurality of devices in the device regions. The predetermined pattern includes a plurality of recesses that surround each device region.

[0012] In some embodiments, the plurality of recesses includes a first set of linear recesses extending along a first direction and periodically or quasi-periodically spaced along a second direction. Further, the plurality of recesses can include a second set of linear recesses extending along the second direction and spaced along the first direction. Further, the second direction can be orthogonal to the first direction.

[0013] In some embodiments, a width of each linear recess of the predetermined pattern is greater than twice a target thickness of the dielectric film.

[0014] In some embodiments, a thickness of the dielectric film is less than a depth of the plurality of recesses in the oxide layer.

[0015] In some embodiments, each device region is spaced apart from the predetermined pattern by a predetermined spacing, and the predetermined spacing is at least 1 micron.

[0016] In some embodiments, the plurality of recesses includes an array of square recesses. Each square recess is spaced apart from other square recesses in the array by at least a minimum spacing distance.

[0017] In some embodiments, the plurality of recesses includes an array of cross-shaped recesses. Each of the cross-shaped recesses is spaced apart from other cross-shaped recesses in the array by at least a minimum spacing distance, the minimum spacing distance determined by a lithography resolution.

[0018] In some embodiments, the method further includes the step of fabricating a plurality of trenches at an edge of the wafer outside of an optical exposure area surrounding the plurality of device regions. Additionally, the plurality of trenches can include a grid of linear cross-recesses scribed in a surface of the wafer.

[0019] In some embodiments, the dielectric film is a silicon nitride (Si3N4) film.

[0020] In some embodiments, depositing the dielectric film on the oxide layer includes depositing a Si3N4 film in a single deposition process using low pressure chemical vapor deposition (LPCVD) in a deposition chamber maintained at a temperature of at least 700 degrees Celsius (°C) during a portion of the single deposition process. The Si3N4 film deposited during the single deposition process has a thickness of at least 400 nanometers (nm). In some embodiments, the temperature of the deposition chamber is maintained at 750 o Celsius (°C) during a portion of the single deposition process. The Si3N4 film deposited during the single deposition process has a thickness of at least 400 nanometers (nm). In some embodiments, the temperature of the deposition chamber is maintained at 750o C to 800 o C, and the thickness of the Si3N4 film deposited during the single deposition process is between 700 nm to 950 nm.

[0021] In some embodiments, depositing the dielectric film on the oxide layer further comprises: depositing the Si3N4 film multiple times in a deposition chamber using low pressure chemical vapor deposition (LPCVD), the deposition chamber being maintained at a temperature of at least 700 o C during a portion of the multiple consecutive deposition processes. Between each deposition run, the ambient atmosphere of the deposition chamber is primarily a nitrogen (N2) atmosphere between subsequent deposition processes of the multiple consecutive deposition processes. In some embodiments, the ambient atmosphere of the deposition chamber can be primarily an argon (Ar) atmosphere. The ambient atmosphere should prevent oxidation of the dielectric film, and thus, can only contain trace amounts of oxygen (O2) at most.

[0022] In some embodiments, the method further comprises the step of depositing an upper cladding layer on top of the dielectric film. In some embodiments, the upper cladding layer is a low temperature oxide (LTO) layer.

[0023] In a second aspect of the present disclosure, a method of fabricating a dielectric film on a wafer of semiconductor material is disclosed. The method comprises the steps of: depositing a first layer of dielectric on an oxide layer of the wafer; fabricating a predetermined pattern in the first layer of dielectric of the wafer to define a plurality of device regions on a top surface of the wafer; and depositing a second layer of dielectric on top of the first layer of dielectric to increase the thickness of the dielectric film. The predetermined pattern comprises a plurality of recesses, the plurality of recesses surrounding each device region, and each recess of the plurality of recesses extending into the oxide layer.

[0024] In some embodiments, fabricating the predetermined pattern further comprises the step of etching the predetermined pattern in the first layer of dielectric to a depth extending into the oxide layer.

[0025] In some embodiments, the first layer of dielectric and the second layer of dielectric comprise silicon nitride (Si3N4).

[0026] In some embodiments, the first layer of dielectric having a thickness of less than 450 nanometers (nm) is deposited by low pressure chemical vapor deposition (LPCVD).

[0027] In some embodiments, the maximum thickness of the first layer of dielectric is adjusted by varying deposition parameters of an LPCVD deposition chamber.

[0028] In some embodiments, the method further comprises the step of patterning the dielectric film. The dielectric film comprises the first layer of dielectric film and the second layer of dielectric film to form a plurality of devices in the device regions.

[0029] In a third aspect of the disclosure, a semiconductor wafer on which a plurality of devices are fabricated is described. The semiconductor wafer includes: a semiconductor substrate; an oxide layer including a predetermined pattern formed therein to define a plurality of device regions on a top surface of the wafer; and a dielectric film formed in at least one device region to have a thickness of at least 400 nanometers (nm). The predetermined pattern includes a plurality of recesses surrounding each device region. The plurality of devices are formed in the device regions by patterning the dielectric film.

[0030] In some embodiments, the semiconductor wafer further includes a cladding layer formed on top of the dielectric film. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figures 1A-1F A process flow for fabricating thick, crack-free stoichiometric silicon nitride (Si3N4) films according to an embodiment is shown.

[0032] Figure 2A A one-dimensional recess pattern for stress relaxation according to an embodiment is shown.

[0033] Figure 2B A two-dimensional recess pattern for stress relaxation according to an embodiment is shown.

[0034] Figures 3A-3C Three exemplary stress release patterns according to an embodiment are shown.

[0035] Figures 4A-4C A relationship between the depth of a recess pattern and the thickness of a Si3N4 film according to an embodiment is shown.

[0036] Figure 5A A top view of a stress release pattern around a device on a substrate according to an embodiment is shown.

[0037] Figure 5B A cross-sectional view of a selected region of the stress release pattern of Figure 5A according to an embodiment is shown.

[0038] Figure 5C A cross-sectional view of a selected region of the stress release pattern of Figure 5A according to an embodiment is shown.

[0039] Figure 6 A device patterned on a die on a wafer according to an embodiment is shown.

[0040] Figure 7 Variations in furnace temperature and dielectric film thickness in an LPCVD deposition process according to an embodiment are shown.

[0041] Figure 8Wavelength vs. refractive index measured using ellipsometer for a control Si3N4 film is shown in accordance with an embodiment.

[0042] Figures 9A-9B Resonant transmission spectra measured from a waveguide-coupled Si3N4 microdisk resonator fabricated from a Si3N4 film in accordance with an embodiment is shown.

[0043] Figures 10A-10C A process flow for fabricating a crack-free dielectric film using two deposition processes in accordance with an embodiment is shown. DETAILED DESCRIPTION

[0044] Fabrication of various types of semiconductor devices requires fabrication of thick crack-free dielectric films on silicon wafers. One example of a specific application of such films is the fabrication of integrated photonic devices and optical circuits on stoichiometric silicon nitride (Si3N4) films with a thickness of about 1 micron (pm) for nonlinear optical and quantum optics experiments on a chip. For example, photonic devices for dispersion engineering applications can require Si3N4 films of more than 700 nm. Highly confined Si3N4 waveguides typically require a thickness of more than 700 nm to obtain anomalous dispersion at a wavelength of 1550 nm. Si3N4 whisper gallery mode (WGM) microdisks typically require a Si3N4 thickness of greater than 800 nm to obtain an anomalous dispersion WGM transverse magnetic mode (TM). However, thick Si3N4 films deposited by LPCVD exhibit large tensile stress, which tends to form cracks across the wafer. This typically limits the film thickness to less than 400 nm in order to obtain reasonable device yield.

[0045] This disclosure describes a method for fabricating a large-area, crack-free Si3N4 film on a silicon substrate for manufacturing devices and integrated optical paths. A key step in stress control is patterning a predetermined stress-relief pattern prior to Si3N4 film deposition. The stress-relief pattern is densely arranged around the device region. The stress-relief pattern is designed with periodic recesses or steps of high spatial frequency to interrupt the dielectric film during deposition. Strict adherence to the periodicity of the stress-relief pattern is not necessary. For example, some locations of the stress-relief pattern may have different spacing or different linewidths. The key is to provide sufficient interruption for the deposited film. This interruption prevents the accumulation of tensile stress and prevents crack propagation into the device region. The stress-relief pattern is fabricated in an undercoat layer, followed by Si3N4 film deposition. Additionally, trenches can be defined around the wafer periphery and / or on the outer side immediately adjacent to the device region to further prevent crack propagation from the wafer edge to the center of the wafer near the device region. Deposition conditions (e.g., deposition rate, chamber temperature, etc.) can be used to modulate the deposition process to ensure high-quality dielectric film. Furthermore, Si3N4 films can be deposited at high temperatures using low-pressure chemical vapor deposition (LPCVD) to reduce the NH bond content in the Si3N4 film caused by hydrogen in the reactant gas. Some applications, such as waveguides and microcavities (at approximately 1520 nm), benefit from the reduction in optical absorption due to NH bonds. Additionally, a hard mask layer can be deposited after the dielectric film deposition to serve as an etching mask and prevent delamination of the thick dielectric film. The methods disclosed herein include complementary metal-oxide-semiconductor (CMOS) compatible fabrication processes that can be readily implemented as conventional CMOS processes for commercial applications.

[0046] The fabrication process described in this paper offers at least the following advantages. First, the thickness of the Si3N4 film deposited by LPCVD can be increased, for example, achieving at least 1 μm in a single deposition process. Second, the deposited Si3N4 film can achieve crack-free device regions in 60% of a 4-inch wafer. Third, areas as large as several square millimeters (mm²) can be formed in the device region. 2 The continuous region allows for virtually any device design, including but not limited to waveguides, ring and disk structures, and polygonal block structures. Fourth, by utilizing an additional top cladding layer as an etch hard mask and protective layer, the thick film, after deposition and before subsequent patterning of the device, can last for at least six months without delamination or further cracking or crack propagation.

[0047] Figures 1A-1F A process flow for manufacturing a thick, crack-free, stoichiometric silicon nitride (Si3N4) film, according to an embodiment, is shown.

[0048] At step 150, as Figure 1AAs shown, fabrication begins with a substrate comprising a silicon (Si) layer 102 and a silicon dioxide (SiO2) layer 104. In this embodiment, the silicon wafer is thermally oxidized to form a silicon dioxide layer on the silicon substrate. The substrate may be a 4" silicon wafer having a thermal oxide layer of 3 μm to 4 μm as an undercoat. It should be understood that various substrates of different sizes can be used for fabrication, such as 4", 6", 8" or 12" wafers, or even a portion of a silicon wafer.

[0049] At step 155, as Figure 1B As shown, a predetermined pattern 106 is fabricated on the substrate. A device region 108 and the predetermined pattern 106 are fabricated (e.g., patterned in the SiO2 layer 104). The predetermined pattern 106 surrounds the device region 108. The fabrication of the predetermined pattern 106 can be performed through a series of steps: (1) spin-coating photoresist and curing the photoresist; (2) patterning by photolithography; (3) developing the pattern; (4) fabricating the pattern by etching or deposition; and (5) removing the photoresist. The photoresist can be positive or negative. Patterning can be performed using various photolithography techniques depending on the feature size, production volume, cost, and design complexity. For example, patterning can be performed using aligner, stepper, and / or scanner photolithography. Exposure can be performed using light sources of various wavelengths, such as mercury lamps at 436 nm (or "g-line"), 405 nm (or "h-line"), or 365 nm (or "i-line"), 248 nm krypton fluoride lasers, or 193 nm argon fluoride lasers. In one embodiment, patterning is performed using i-line lithography on an ASML 365 nm stepper. The stepper has a field of view of 15 mm × 15 mm and a scaling factor of 5. On a 4" wafer, the total exposure area can be 75 mm × 75 mm, comprising 5 × 5 optical exposure areas. Figure 1B As shown, the pattern is created by etching the oxide layer 104. A C4F8 / H2-based etching gas can be used to etch the oxide layer to a depth several hundred nanometers thicker than the target Si3N4 film. In one embodiment, the pattern depth 120 can be approximately 1.2 μm to accommodate a dielectric film up to approximately 1 μm thick. Trenches can be formed on the outer side of the device region 108 and the predetermined pattern 106 prior to film deposition.

[0050] At step 160, as Figure 1CAs shown, a Si3N4 film 116 (also referred to as a dielectric film 116) is deposited on the substrate. The dielectric film 116 can be uniformly deposited on the SiO2 layer 104. For example, a 950 nm thickness of Si3N4 film 116 can be deposited in a single process using LPCVD. The LPCVD process is set at approximately 780°C in a single deposition process. A slow deposition rate of 24 to 28 A / min can be employed to mitigate stress in the Si3N4 film 116.

[0051] Optionally, at step 165, as shown, a low temperature oxide (LTO) layer 110 can be deposited on the substrate. The LTO layer 110, having a thickness of 700 nm, can be deposited on top of the dielectric film 116. The LTO layer 110 can be used as an etch hard mask for the Si3N4 device. In addition, the LTO layer 110 can help prevent delamination of the dielectric film 116 at the edge. Figure 1D

[0052] At step 170, as shown, a device pattern 112 can be fabricated on the substrate. The device pattern 112 is defined on the LTO layer 110 by patterning. For example, a photoresist is spun on the wafer, the device pattern 112 is formed by photolithography, and the dielectric film 116 and / or the LTO layer 110 of the non-device area 108 is removed by etching. The patterning step can be performed by i-line photolithography. The LTO hard mask and Si3N4 device can then be etched using reactive gases based on C4F8 / H2 / He and SF6 / C4F8. The remaining LTO hard mask is removed by a buffered oxide etch (BOE). Thus, the device pattern 112 is exposed for subsequent processes. It will be appreciated that a device is formed in the film 116 after etching, but unlike the prior art Damascene process, the device is not formed by filling into the underlying oxide 104 film. This allows devices of more sizes and types to be made with precise control of height, and avoids the CMP step of the Damascene process. Figure 1E

[0053] At step 175, as shown, the device 112 formed on the substrate is coated with an LTO layer 114. The LTO layer 114 can be deposited on the entire substrate. The device 112 coated with the LTO layer 114 can be used for dispersion management. After LTO deposition, a high temperature annealing process can be performed to minimize H-bond absorption around 1520 nm. The annealing can be performed for several hours in a nitrogen ambient at 1150°C. Other types of inert gases, such as argon, can be used in the annealing process. The oxygen content in the inert gas ambient atmosphere is very low, so that the dielectric layer can be prevented from oxidizing during the annealing process. In addition, a gas containing hydrogen should be avoided to prevent the formation of hydrogen bonds in the dielectric film. Figure 1F

[0054] ​​​Stress relief patterns are designed to ensure crack-free device regions after the deposition of a dielectric layer. The stress relief pattern can be highly symmetrical along at least one line of symmetry. Periodic design of the stress relief pattern facilitates scaling and repetition. Alternatively, the stress relief pattern can be locally adjusted to optimize the interruption of the deposited dielectric film. For example, portions of the stress relief pattern can be tailored to have higher spatial frequencies and / or wider linewidths. Note that periodic patterns are disclosed below for illustrative purposes. However, this does not preclude the existence of aperiodic or quasi-periodic stress relief patterns. Figures 2A-2B The concept of using periodic recesses of 200 and 250 in one dimension to interrupt the membrane is shown.

[0055] like Figure 2A As shown, the line space pattern is distributed in a two-dimensional coordinate system 202. Lines 204 can be linearly concave along the x-axis and periodically spaced along the y-axis. The internal tensile stress is relaxed in a stress relaxation direction 214, where the continuity of the membrane is interrupted along the y-axis. Assume that a crack appears at the initial point 206. The crack propagates along direction 208. The abrupt change in the concavity along the stress relaxation direction 214 can disrupt the driving force of the crack. Therefore, the crack can stop propagating at the termination point 212. On the other hand, the continuity of the membrane along the x-axis is not interrupted, so that the membrane is subjected to principal stress 210 along the x-axis.

[0056] Figure 2B An orthogonal intersecting grid pattern 250 is depicted. Recessed lines 204 are distributed along the y-axis and x-axis, causing the continuity of the film to be interrupted along the y-axis and x-axis or diagonally. Therefore, stress can be released in all in-plane stress relaxation directions 214. The characteristic dimensions of the stress relief pattern 250 are the recessed pattern width 252, represented by 'a', and the edge-to-edge distance 254 of the ridge, represented by 'b'. The characteristic dimensions a and b can be on the order of 1 micrometer to tens of micrometers. The smaller the values ​​of a and b, the better the film is interrupted, thus allowing for better stress relief results. On the other hand, in some embodiments, a should be at least slightly greater than twice the thickness of the dielectric film. Otherwise, the deposited film can fill the recesses after conformal deposition. The lower limit of b is limited by the lithographic resolution. In one embodiment, the lower limit of b can refer to the minimum spacing distance, which can be calculated from the pixel size of multiple lithographic resolutions.

[0057] Patterns with high spatial symmetry and moderately high modulation frequencies can reasonably and uniformly release stress effectively. Two-dimensional periodic recessed pattern modulation with high spatial symmetry and high spatial frequency can uniformly release film stress in all in-plane directions. Furthermore, portions of the recessed pattern can be fine-tuned according to the spatial frequency and / or linewidth of the recessed pattern to locally enhance interruptions. The recessed pattern is etched slightly deeper than the target dielectric film thickness to completely release the dielectric film stress.

[0058] Furthermore, high spatial frequencies can help minimize the recovery of crack driving forces. The crack driving force needs to be reduced to a level suitable for crack resistance. Abruptly changing steps or recesses can disturb the crack driving force. Therefore, multiple periodically changing steps can prevent the crack from recovering its driving force in the overstress membrane. The design of relative displacement between adjacent rows or columns helps to interrupt crack propagation between alternating rows and columns.

[0059] Furthermore, the design parameters of the stress relief pattern (e.g., a and b) can be adjusted according to the actual size of the device region to obtain optimal results. Reducing the fill ratio of the stress relief pattern helps to enlarge the device region. Additionally, in some embodiments, a contact lithography aligner can be used to define the stress relief pattern only at the edge of the wafer to further enlarge the device region.

[0060] Figures 3A-3C Three stress relief pattern examples conforming to design standards according to some implementation methods are illustrated schematically.

[0061] Figure 3A A checkerboard-shaped stress relief pattern 300 is depicted. The periodic squares 304 are concave. The stress relief pattern 300 is symmetrical about four lines of symmetry 306. According to the reference coordinate system 302, the four lines of symmetry are 0 with respect to the x-axis. o 45 o 90 o and 135 o The width 308 of the recessed square 304 is represented by 'a', while the lateral distance 310 between two nearest recessed squares 304 is represented by 'b'. According to some embodiments, the pattern can be modified into other variations. For example, the recessed squares 304 in even-numbered rows can be rotated 45°. In another example, the recessed squares 304 in odd-numbered rows can have different sizes than the squares in even-numbered rows. In yet another example, the recessed shapes in odd-numbered rows can be squares, while the recessed shapes in even-numbered rows can be circles. The feature dimensions 'a' and 'b' can vary by a few micrometers in different rows and / or columns.

[0062] Figure 3B A stress relief pattern 330 depicts periodic crosses 332. Each cross 332 is concave in shape. (The last sentence appears to be incomplete and possibly contains errors.) Figure 3A Similar to pattern 300 shown, this periodic pattern 330 is also symmetrical about four lines of symmetry, which are 0 with respect to the x-axis. o 45 o 90 o and 135 oThe width 336 of the horizontal leg of each cross 332 is the same as the width 334 of the vertical leg of each cross 332, and the width 334 / 336 is denoted by a, while the lateral distance 338 between the nearest crosses 332 is denoted by b. It should be understood that in other embodiments, the feature size b can be measured from the center of each cross 332 to the center of the adjacent cross 332, and the feature size a of the vertical leg can be different compared to the horizontal leg. Variations of the pattern 330 can be Figure 3C the pattern 360 shown, where the crosses 362 in the even rows are rotated 45° relative to the crosses 332 in the odd rows. By rotating the crosses 362 in the even rows, the symmetry of the pattern is maintained. In the pattern 360 in Figure 3C the pattern 360, the minimum distance 364 / 368 between the nearest crosses is denoted by b.

[0063] Figure 4A A cross-sectional view 400 of a dielectric film 406 deposited on a patterned lower cladding layer 404 (SiO2layer 404) is shown, according to one embodiment. The substrate includes a silicon layer 402 and a SiO2layer 404. A stress release pattern is fabricated in the SiO2layer 404, where the pattern includes periodic recesses 418. The feature sizes of the recesses are a width 414 denoted by a, a depth 408 denoted by d, and a distance between two adjacent recesses 412 denoted by b. The feature size b can be a few microns in order to provide sufficient interruption for the dielectric film. A Si3N4layer is uniformly deposited on top of the patterned lower cladding layer 404. The thickness 410 of the deposited dielectric film 406 is denoted by c. In some embodiments, the thickness 410 of the dielectric film 406 is about 1 μm. After deposition, the recesses 418 are filled with Si3N4, the width 414 of the recesses 418 shrinks by 2c, and the two edges of the recesses 418 are rounded or slanted upward. The width 414 (a) of the recesses 418 should be larger than 2c in order to avoid the recesses 418 being filled. Depending on the relationship between the thickness 410 (c) and the depth 408 (d), the edges of the recesses 418 will exhibit different results after the dielectric film 406 is deposited. Figures 4B-4C The area 416 including the recesses is described in detail in Figures 4B-4C The results of the recesses 418 after the film 406 is deposited under different conditions are depicted.

[0064] As shown in Figure 4B When the depth 408 (d) > thickness 410 (c), the recesses 414 in the substrate sufficiently interrupt the continuity of the dielectric film 406 in the in-plane direction during deposition. As shown in Figure 4CAs shown, when the depth 408 (d) < the thickness 410 (c), the depth 408 of the recess 414 is not sufficient to interrupt the continuity of the dielectric film 406 in the in-plane direction during the deposition process in the substrate. Therefore, to achieve the best result, the depth 408 (d) should be greater than or equal to the thickness 410 (c).

[0065] A dense array of stress release patterns can be arranged around each device in the device region. Figure 5A A portion of a wafer 500 containing a device region 502 surrounded by a stress release pattern 504 is shown. The state of the wafer 500 corresponds to Figure 1E The step 170 shown. Figure 5A The device 502 depicted in is a waveguide-coupled microdisk, which includes a straight waveguide and a disk. There is a gap between the straight waveguide and the disk, and the gap is on the order of a few hundred nanometers (nm). It will be understood that the device 502 is depicted for illustrative purposes, and the particular type and / or arrangement of the device is not intended to be limiting, i.e., other types of devices are also contemplated to be within the scope of the present disclosure. In one embodiment, a dense array of chessboard-like stress release patterns 504 is arranged around the device region 502. The chessboard-like patterns 504 can be easily stacked and densely arranged around the device 502, and the entire stress release region can be scaled. In this embodiment, the device region 502 can have a feature size in the range from tens of nanometers to a few millimeters. In other words, the device region 502 can have a footprint (denoted by f) as large as a few square millimeters. The squares of the stress release patterns 504 are recessed. The stress release patterns 504 and the device region 502 need to be spaced apart by a spacing 506 (denoted by a feature size e) of at least a few microns. For example, e can be 30 pm. A region 520 including the chessboard-like patterns 504 is selected, and the selected region 520 is subjected to a first lithography process to form a first mask 510. Figure 5B The region 520 is shown in. The first mask 510 is shown in. Figure 5C A cross-sectional view along the dashed line 530 is shown in.

[0066] Figure 5B An enlarged view of the selected region 520 is depicted to show the basic elements of the chessboard-like patterns 504. The width 522 of each square of the pattern 504 is denoted by a, while the ridge spacing 524 between the recessed squares of the pattern 504 is denoted by b. According to some embodiments, a and b can be a few microns. In an embodiment, each square of the pattern 504 is 5 pm x 5 pm, while the ridge spacing 524 is 2 pm. It will be understood that in other embodiments, the elements of the pattern 504 can be rectangular, such that the width and height of each element are not uniform.

[0067] As shown in, the first mask 510 is used to form a first dielectric film 512 on the wafer 500. Figure 5CAs shown, device region 502 has a coverage area 532 of several square millimeters. The spacing 506 between device region 502 and stress relief pattern 504 is e, where e can be at least 1 micrometer. The thickness 536(c) of the dielectric layer can be less than 1 μm. The depth 538 of the recess in SiO2 layer 534 is greater than the thickness 536 of the dielectric layer (i.e., d is greater than c).

[0068] According to some implementation methods, devices can be fabricated on a wafer. Crack-free regions can be defined by photolithographically written regions. Figure 6 The illustration shows a photolithographic writing area 606 on a 4-inch wafer 600 using a stepper in one embodiment. The stepper has a field of view of 15mm × 15mm and a scaling factor of 5. Due to wafer maneuverability, a few millimeters from the edge of the wafer 600 cannot be used for device fabrication. According to one embodiment, on a 4" wafer 600, the total photolithographic writing area 606 is 75mm × 75mm, which includes 5×5 optical exposure areas 604 (dashed squares) with the same design. The optical exposure areas 604 at the four corners are partially patterned and lack sufficient stress-relief patterns, and are therefore excluded. The remaining 21 optical exposure areas in the solid-line area 608 contain device areas and sufficient stress-relief patterns, occupying approximately 60% of the wafer area. It should be noted that an optical exposure area 604 may contain one or more devices. The optical exposure areas 604 on the wafer 600 may be associated with one or more reticles (or masks). In other words, the optical exposure areas 604 of the wafer 600 may have the same design or may have different designs.

[0069] Before depositing the dielectric film, trenches can be defined outside the photolithographic writing region 606. For example... Figure 6 As shown, grid trenches 610 are defined at the edge of the wafer. The trenches can be arbitrarily scribed manually or automatically at the edge using a diamond scribing tool or other methods known in the art. The trenches prevent cracks formed at the wafer edge from propagating to the device region. The trench spacing can be several millimeters. It should be noted that stress-relief patterns can be patterned across the entire wafer by extending the writing area of ​​the photolithography tool, thus eliminating the need to define trenches at the wafer edge (i.e., since the stress-relief patterns perform the function of trenches at the wafer edge, the step of defining these trenches can be omitted).

[0070] Si3N4 films can be deposited in a single deposition process at approximately 780°C using LPCVD, achieving a film thickness of approximately 950 nm. Two precursor gases, SiH2Cl2 (DCS) and NH3, can be used for Si3N4 film deposition at flow rates of 25 sccm and 150 sccm, respectively. Figure 7 Figure 700 illustrates the variations in furnace temperature and deposited Si3N4 film thickness during a single deposition process. The horizontal axis 702 represents time in minutes (min) (i.e., the duration of a single deposition). The first vertical axis 704 represents temperature in degrees Celsius (°C), while the second vertical axis 706 represents thickness in micrometers (μm). The first solid line 708 in Figure 700 represents the variation in furnace temperature. The second solid line 710 represents the variation in Si3N4 film thickness during deposition. At time t... o At time t1712, the furnace temperature is 400°C and increases at a rate of approximately 10°C / min. At time t1714, the furnace temperature reaches 780°C, and the dielectric film begins to grow. Between time t1714 and time t2716, the furnace temperature remains stable at 780°C, and the dielectric film continues to grow at a controlled rate. Note that deposition can be performed at different temperatures (between t1 and t2) with a deposition temperature of at least 700°C. At time t2716, deposition stops, and at time t3718, the furnace temperature drops to the predetermined temperature. In this embodiment, a deposition rate of 24 to 28 Å / min is used for Si3N4 film deposition. A slow deposition rate helps to alleviate tensile stress in the Si3N4 film. The above parameters for dielectric film deposition can be varied depending on different reactor conditions.

[0071] The deposition of Si3N4 films using LPCVD can be performed in two or more consecutive processes without pulling the wafer out of the deposition chamber (e.g., furnace). Between each deposition process, the wafer is held in the deposition chamber in an N2 atmosphere at approximately 400°C. As defined herein, the N2 atmosphere primarily consists of nitrogen (by weight), but trace amounts of other gases, such as carbon dioxide, methane, or oxygen, are permitted. However, the combined weight of other gases should not exceed 2% of the weight of the atmosphere in the deposition chamber. Other inert atmospheres, such as argon (Ar), can be used. It is important to maintain a small amount of oxygen to prevent oxidation in the dielectric layer. Furthermore, the use of hydrogen-containing gases should be avoided to minimize the chance of hydrogen bonding formation in the dielectric film.

[0072] Devices manufactured by the methods disclosed herein have the following characteristics. The refractive index of a control film of Si3N4 is measured for one or more wavelengths to calibrate the quality of the LPCVD deposition. A control film of Si3N4 of thickness about 300 nm is deposited by LPCVD. The measurement is performed by an ellipsometer. Figure 8 A graph 800 representing the relationship between the refractive index (n) and the wavelength (λ) of a stoichiometric film is shown. In the graph 800, the vertical axis 802 represents the refractive index, while the horizontal axis 804 represents the wavelength. The curve 806 represents the relationship between n and λ. At about 1550 nm, the refractive index measured for a control film of Si3N4 of 300 nm thickness is about 1.94, which is consistent with a stoichiometric film. Thus, the LPCVD deposition process used to manufacture the device is of good quality.

[0073] In an embodiment, the exemplified device is a waveguide-coupled Si3N4 microdisk resonator. The microdisk resonator has a radius of 920 μιη and includes a 910 nm thick Si3N4 film and a 700 nm thick LTO upper cladding layer. A 1550 nm wavelength laser wavelength scanning tool using known techniques is used to characterize the throughput-transmission spectra of the waveguide-coupled Si3N4 microdisk resonator. Figures 9A-9B The measurement results are shown in FIG. 9. The vertical axis 902 represents the normalized transmitted optical power (dB), while the horizontal axis 904 represents the wavelength (nm). The measurement results are represented by 906. In Figure 9A In FIG. 9, the free spectral range (FSR) between the two consecutive transmitted optical intensity minima of the same horizontal mode is represented by 908. The measurement results show that the FSR is about 0.2 nm. In Figure 9B In FIG. 9, the solid line 910 represents a fitted curve to the measurement results. From the fitted curve, a linewidth 912 of 1.54 picometer (pm) is extracted. The microdisk resonator fabricated exhibits a resonator quality (Q) factor of about 1.0 x 10 6 .

[0074] The above disclosure describes the fabrication of a predetermined stress release pattern on the lower cladding layer after a single LPCVD deposition process to obtain a thick crack-free dielectric film. The fabrication process described can achieve Si3N4 films of more than 400 nm. Alternatively, the stress release pattern can be patterned between two LPCVD deposition processes.

[0075] Figures 10A-10C Key fabrication steps for implementing the fabrication process according to an embodiment are shown. In step 1000, as Figure 10AAs shown, a Si3N4 layer 1006 is first deposited on a substrate comprising a silicon layer 1002 and an unpatterned SiO2 lower cladding layer 1004. In this step 1000, a thin Si3N4 film having a thickness 1008 between 250 and 400 nm is deposited without forming cracks. In other embodiments, a Si3N4 film having a thickness less than 450 nm can be deposited in this step 1000. At step 1020, a stress release pattern is patterned on the Si3N4 film 1006, and a stress release pattern is fabricated by etching the pattern down to the lower cladding layer 1004. The etch depth 1010 needs to be a few hundred nanometers deeper than the target total thickness of the Si3N4 film to ensure sufficient stress relaxation. Subsequently, at step 1030, the remaining target Si3N4 film 1006 is deposited. The actual upper thickness 1012 of the deposited Si3N4 film can be adjusted according to the conditions of the furnace. Figure 10B As shown, a Si3N4 layer 1006 is first deposited on a substrate comprising a silicon layer 1002 and an unpatterned SiO2 lower cladding layer 1004. In this step 1000, a thin Si3N4 film having a thickness 1008 between 250 and 400 nm is deposited without forming cracks. In other embodiments, a Si3N4 film having a thickness less than 450 nm can be deposited in this step 1000. At step 1020, a stress release pattern is patterned on the Si3N4 film 1006, and a stress release pattern is fabricated by etching the pattern down to the lower cladding layer 1004. The etch depth 1010 needs to be a few hundred nanometers deeper than the target total thickness of the Si3N4 film to ensure sufficient stress relaxation. Subsequently, at step 1030, the remaining target Si3N4 film 1006 is deposited. The actual upper thickness 1012 of the deposited Si3N4 film can be adjusted according to the conditions of the furnace. Figure 10C As shown, a Si3N4 layer 1006 is first deposited on a substrate comprising a silicon layer 1002 and an unpatterned SiO2 lower cladding layer 1004. In this step 1000, a thin Si3N4 film having a thickness 1008 between 250 and 400 nm is deposited without forming cracks. In other embodiments, a Si3N4 film having a thickness less than 450 nm can be deposited in this step 1000. At step 1020, a stress release pattern is patterned on the Si3N4 film 1006, and a stress release pattern is fabricated by etching the pattern down to the lower cladding layer 1004. The etch depth 1010 needs to be a few hundred nanometers deeper than the target total thickness of the Si3N4 film to ensure sufficient stress relaxation. Subsequently, at step 1030, the remaining target Si3N4 film 1006 is deposited. The actual upper thickness 1012 of the deposited Si3N4 film can be adjusted according to the conditions of the furnace.

[0076] It should be understood that the arrangement of components shown in the drawings is for purposes of illustration, and other arrangements are possible. Other elements can be implemented in software, hardware, or a combination of software and hardware. Furthermore, some or all of these other elements can be combined, some can be omitted altogether, and additional components can be added, while still achieving the functionality described herein. Thus, the subject matter described herein can be embodied in many different variations, and all such variations are contemplated to be within the scope of the claims.

[0077] To facilitate understanding of the subject matter described herein, a number of aspects are described in the sequence of acts. The description of any sequence of acts is not intended to imply that the described ordering is the only ordering in which the acts can be performed. All method described herein can be performed in any suitable order, unless otherwise specified or otherwise clear from the context.

[0078] The use of the terms “a” and “an” and “the” and similar referents in the context of describing the subject matter (especially in the claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term “at least one” following a list of one or more items (for example, “at least one of A and B”) should be construed to mean one (A or B) of the items selected from the list or any combination of two or more of the items, unless otherwise indicated herein or clearly contradicted by context. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the scope of the sought protection is defined by the claims as appended and any equivalents thereof. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the subject matter and does not pose a limitation on the scope of the subject matter unless otherwise claimed. The use of the terms “based on” and other like phrases in the claims and written description is not intended to foreclose implementations of the subject matter where additional nexus, association, or functions are used in addition to, or instead of, those com- prised in the claims. Language in the specification should not be interpreted as indicating any unclaimed element as essential to the practice of the application.

Claims

1. A method for fabricating a dielectric film on a wafer, comprising: fabricating a predetermined pattern in an oxide layer of the wafer to form a plurality of device regions on a top surface of the wafer, wherein the predetermined pattern includes a plurality of recesses that surround each of the device regions; a plurality of spaced recesses includes an array of cross-shaped recesses, wherein cross-shaped recesses in even rows are rotated 45° relative to cross-shaped recesses in odd rows; depositing the dielectric film on the oxide layer; and patterning the dielectric film to form a plurality of devices in the device regions.

2. The method of claim 1, wherein, each linear recess of the predetermined pattern has a width that is greater than twice a target thickness of the dielectric film.

3. The method of claim 1, wherein, a thickness of the dielectric film is less than a depth of the plurality of recesses in the oxide layer.

4. The method of claim 1, wherein, each device region is spaced apart from the predetermined pattern by a predetermined spacing, and wherein the predetermined spacing is at least 1 micron.

5. The method of claim 1, wherein, each of the cross-shaped recesses is spaced apart from other cross-shaped recesses in the array by at least a minimum spacing distance, wherein the minimum spacing distance is determined by a lithography resolution.

6. The method of claim 1, wherein, the dielectric film is a Si3N4 film.

7. The method of claim 1, wherein, depositing the dielectric film on the oxide layer includes: depositing a Si3N4 film in a deposition chamber using low pressure chemical vapor deposition, the deposition chamber being maintained at a temperature of at least 700 degrees Celsius during a portion of a single deposition process, wherein a thickness of the Si3N4 film deposited during the single deposition process is at least 400 nanometers.

8. The method of claim 1, wherein, depositing the dielectric film on the oxide layer includes: depositing a Si3N4 film in a deposition chamber using low pressure chemical vapor deposition, the deposition chamber being maintained at a temperature of at least 700 degrees Celsius during a portion of a plurality of sequential deposition processes, wherein between each deposition process, an ambient atmosphere is maintained in the deposition chamber for a duration of time between a subsequent deposition process of the plurality of sequential deposition processes, and wherein the ambient atmosphere of the deposition chamber is an inert gas atmosphere for the duration of time.

9. The method of claim 8, the inert gas includes at least one of a nitrogen gas and an argon gas.

10. The method of claim 1, further comprising: depositing an upper cladding layer on top of the dielectric film.

11. A method for fabricating a dielectric film on a wafer of semiconductor material, comprising: depositing a first layer of dielectric on an oxide layer of the wafer; fabricating a predetermined pattern in the first layer of dielectric of the wafer to define a plurality of device regions on a top surface of the wafer, wherein the predetermined pattern includes a plurality of recesses that surround each of the device regions, and wherein each recess of the plurality of recesses extends into the oxide layer; a plurality of spaced recesses includes an array of cross-shaped recesses, wherein cross-shaped recesses in even rows are rotated 45° relative to cross-shaped recesses in odd rows; and depositing a second layer of dielectric on top of the first layer of dielectric to increase a thickness of the dielectric film after fabricating the predetermined pattern.

12. The method of claim 11, wherein, Fabricating the predetermined pattern further includes etching the predetermined pattern in the first layer of dielectric to a depth extending into the oxide layer.

13. The method of claim 11, wherein, The first layer of dielectric and the second layer of dielectric include Si3N4.

14. The method of claim 13, wherein, The first layer of dielectric has a thickness less than 450 nanometers deposited by low pressure chemical vapor deposition.

15. The method of claim 14, wherein, The maximum thickness of the first layer of dielectric is adjusted by varying deposition parameters of a low pressure chemical vapor deposition deposition chamber.

16. The method of claim 11, further comprising: patterning the dielectric film including the first layer of dielectric and the second layer of dielectric to form a plurality of devices in the device region.

17. A semiconductor wafer for fabricating a plurality of devices thereon, the semiconductor wafer comprising: a semiconductor substrate; an oxide layer including a predetermined pattern formed therein to define a plurality of device regions on a top surface of the wafer, wherein the predetermined pattern includes a plurality of recesses surrounding each device region; the plurality of spaced recesses including an array of cross-shaped recesses, wherein cross-shaped recesses in even-numbered rows are rotated 45° relative to cross-shaped recesses in odd-numbered rows; and a dielectric film formed in at least one device region to have a thickness of at least 400 nanometers, wherein a plurality of devices are formed in the device region by patterning the dielectric film.

18. The semiconductor wafer of claim 17, further comprising a cladding layer formed on top of the dielectric film.

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