Method for forming a semiconductor device

Abstract

An embodiment of the present invention provides a method for forming a semiconductor device. In the embodiment of the present invention, a sacrificial layer is formed above the dielectric layer. During the planarization process, the sacrificial layer protects the dielectric layer, obtaining a relatively flat dielectric layer and avoiding the occurrence of depressions on the surface of the dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for forming a semiconductor device. Background Art

[0002] With the continuous development of semiconductor manufacturing processes, the integration of semiconductor devices is getting higher and higher, and the feature size of semiconductor devices is gradually shrinking. However, the reliability of semiconductor devices still needs to be improved. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a method for forming a semiconductor device to improve the reliability of the semiconductor device.

[0004] The method for forming a semiconductor device according to an embodiment of the present invention includes:

[0005] Providing a front-end device layer, where the front-end device layer includes a dielectric layer;

[0006] Forming a sacrificial layer on the dielectric layer;

[0007] Patterning the dielectric layer and the sacrificial layer to form a plurality of holes exposing the front-end device layer;

[0008] Forming a barrier layer covering the sidewalls of each of the holes and the sacrificial layer;

[0009] Forming a conductive layer filling each of the holes on the barrier layer;

[0010] Planarizing the conductive layer to remove the conductive layer and the barrier layer on the sacrificial layer, forming a conductive via;

[0011] Removing the sacrificial layer; and

[0012] Forming an electrode layer covering the conductive via and the dielectric layer.

[0013] Further, the material of the sacrificial layer is amorphous silicon.

[0014] Further, the thickness of the sacrificial layer is 20 Å - 300 Å.

[0015] Further, after removing the sacrificial layer and before forming the electrode layer covering the holes and the dielectric layer, the method further includes:

[0016] Forming a protective layer covering the conductive via.

[0017] Further, the material of the conductive via is copper; the material of the protective layer is cobalt.

[0018] Further, the forming of the protective layer covering the conductive via specifically is:

[0019] A protective layer is formed on the conductive vias by a selective deposition process.

[0020] Further, the upper surface of the protective layer is flush or substantially flush with the upper surface of the dielectric layer.

[0021] Further, the method further includes:

[0022] Forming a plurality of discrete magnetic tunnel junction units on the electrode layer above each of the conductive vias;

[0023] Patterning the electrode layer.

[0024] Further, the magnetic tunnel junction unit includes a pinned layer, a barrier layer, and a free layer stacked in sequence.

[0025] Further, the semiconductor device is a magnetic random access memory.

[0026] In the embodiments of the present invention, by forming a sacrificial layer above the dielectric layer, during the planarization process, the sacrificial layer protects the dielectric layer, obtaining a relatively flat dielectric layer and avoiding the occurrence of depressions on the surface of the dielectric layer. Description of the Drawings

[0027] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0028] Figure 1 is a schematic structural diagram of an MRAM;

[0029] Figures 2 - 7 is a schematic diagram of each step of a method for forming a semiconductor device of a comparative example;

[0030] Figure 8 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0031] Figures 9 - 17 is a schematic diagram of the structure formed by each step of the method for forming a semiconductor device according to an embodiment of the present invention. Detailed Embodiments

[0032] The following describes the present invention based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. Those skilled in the art can fully understand the present invention without the description of these details. To avoid obscuring the essence of the present invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0033] In addition, those of ordinary skill in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0034] Unless the context clearly requires otherwise, the words such as "including", "comprising" and the like in the description of this application document shall be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to". In the description of the present invention, unless otherwise specified, the meaning of "multiple layers" is two or more layers.

[0035] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For ease of description, spatial relationship terms such as "beneath", "below", "under", "above", "on" etc. may be used herein to describe the relationship between one element or feature and another (some) element or feature as shown in the drawings.

[0036] Throughout the specification, reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily all refer to the same aspect. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more aspects of the present disclosure.

[0037] In the description of the present invention, unless otherwise specified, an integrated circuit generally means an integrated circuit component formed on a semiconductor substrate, whether or not the components are coupled together as a circuit or can be interconnected. Throughout the specification, the term "layer" is used in its broadest sense to include films, capping layers or the like, and a layer may include multiple sub-layers. In addition, reference to conventional techniques for forming thin films may include in-situ grown films. For example, in some embodiments, a controlled growth of an oxide of a desired thickness can be obtained by exposing a silicon surface to oxygen or to moisture in a heated chamber.

[0038] Conventional etching techniques known in the semiconductor manufacturing field for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide, or similar materials mentioned throughout the specification include, for example, wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical mechanical polishing process (Chemical Mechanical Polishing, CMP), and similar processes. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to specific deposition techniques should not be limited to those described. In some examples, two such techniques may be interchangeable. For example, stripping photoresist may include immersing the sample in a wet chemical bath or alternatively spraying the wet chemical directly onto the sample.

[0039] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which utilizes the special electrical properties of semiconductor materials to perform specific functions. It can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. Commonly used existing semiconductor devices include memories, such as static random access memory (Static Random-Access Memory, SRAM) and dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. Memories are an important part of a computer architecture and have a decisive impact on the speed, integration level, and power consumption of the computer. Magnetic random access memory (Magnetic Random Access Memory, MRAM) is a non-volatile memory technology and is being widely accepted by the industry as a mainstream data storage technology. It integrates a magnetoresistive device and a silicon-based selection matrix. Key attributes include non-volatility, low-voltage operation, durability for infinite read and write cycles, fast read and write operations, and easy integration as a backend technology. These characteristics make MRAM potentially replace many types of memories in various applications.

[0040] Generally speaking, MRAM includes multiple magnetic memory cells or an array of magnetic memory cells. Figure 1 is a schematic structural diagram of MRAM. As Figure 1 shown, the magnetic memory cell generally includes a front-end device layer 1, a first dielectric layer 2, a conductive layer 3, a first electrode layer 4, a second dielectric layer 5, a second electrode layer 6, and a magnetic tunnel junction (Magnetic Tunnel Junction, MTJ) 7. Multiple magnetic tunnel junction units 7 are electrically isolated from each other by the second dielectric layer 5. Among them, the first electrode layer 4 and the second electrode layer 6 each have a circuit pattern, and the circuit pattern is not shown in the figure. The conductive layer 3 and the first electrode layer 4 electrically connect the magnetic tunnel junction unit 7 to the MOS transistor in the front-end device layer 1 to form a complete MRAM.

[0041] Figures 2 - 7 It is a schematic diagram of each step of the method for forming a semiconductor device of a comparative example. Refer to Figures 2 - 7 , the method for forming a semiconductor device of the comparative example includes the following steps:

[0042] Step S100: Provide a front-end device layer 1.

[0043] Step S200: Form a dielectric layer 2 on the front-end device layer 1. The front-end device layer 1 includes various semiconductor components and interconnect structures, etc.

[0044] Step S300: Form a hole 3a in the dielectric layer 2 to expose the front-end device layer 1.

[0045] Step S400: Form a barrier layer 2a covering the bottom and side walls of the hole 3a.

[0046] Step S500: Form a conductive material layer 3b filling the hole on the barrier layer 2a.

[0047] Step S600: Planarize the conductive material layer 3b and the barrier layer 2a until the dielectric layer 2 is exposed. After the planarization process, the conductive material layer outside the hole 3a is removed to form a conductive layer 3.

[0048] Step S700: Form an electrode layer 4 on the conductive layer 3, the dielectric layer 2, and the barrier layer 2a.

[0049] Step S800: Form a plurality of magnetic tunnel junction units 7 on the electrode layer 4 above the conductive layer 3. The magnetic tunnel junction unit 7 includes a pinned layer 7a, a barrier layer 7b, and a free layer 7c stacked in sequence.

[0050] In the method for forming a semiconductor device of the comparative example, during the planarization process, the removal rate of the barrier layer 2a is lower than that of the conductive material layer 3b and the dielectric layer 2. As a result, after planarization, the barrier layer 2a forms relatively high antennae, while the dielectric layer 2 and the conductive layer 3 form depressions lower than the barrier layer 2a. The flatness of the electrode layer 4 and the pinned layer 7a, the barrier layer 7b, and the free layer 7c in the magnetic tunnel junction unit 7 formed in the subsequent process is poor. The poor flatness of the magnetic tunnel junction unit 7 has an adverse effect on the magnetic properties of the tunnel junction 7. In particular, various defects will be formed in the barrier layer 7b due to the poor flatness. MRAM mainly controls the magnetic moment directions of the pinned layer 7a and the free layer 7c to complete information writing. When there are defects in the barrier layer 7b between the pinned layer 7a and the free layer 7c, it may cause electrical connection between the pinned layer 7a and the free layer 7c, resulting in the failure of MRAM. At the same time, the conductive layer 3 will also have defects due to poor flatness and is easily corroded. The corrosion of the conductive layer 3 easily leads to time-dependent dielectric breakdown (TDDB) during the back end of line (BEOL) process. Therefore, the method for forming a semiconductor device of the comparative example results in very poor reliability of the semiconductor device.

[0051] In view of this, in order to improve the reliability of semiconductor devices, embodiments of the present invention provide a method for forming a semiconductor device. In the embodiments of the present invention, taking the formation of MRAM as an example for illustration, further, the method of the embodiments of the present invention is applied to form MRAM below the 10nm process node. It should be understood that the embodiments of the present invention can also be used to form other semiconductor devices. Figure 8 is a flowchart of the method for forming a semiconductor device according to an embodiment of the present invention. As Figure 8 shown, the method for forming a semiconductor device according to an embodiment of the present invention includes the following steps:

[0052] Step S100, providing a front-end device layer. The front-end device layer includes a dielectric layer.

[0053] Step S200, forming a sacrificial layer on the dielectric layer.

[0054] Step S300, patterning the dielectric layer and the sacrificial layer to form a plurality of holes exposing the front-end device layer.

[0055] Step S400, forming a barrier layer covering the sidewalls of each of the holes and the sacrificial layer.

[0056] Step S500, forming a conductive layer filling each of the holes on the barrier layer.

[0057] Step S600, planarize the conductive layer to remove the conductive layer and the barrier layer on the sacrificial layer, and form a conductive via hole.

[0058] Step S700, remove the sacrificial layer.

[0059] Step S800, form an electrode layer covering the conductive via hole and the dielectric layer.

[0060] In other alternative implementation manners, after step S700 and before step S800, the method further includes:

[0061] Step S700a, form a protective layer covering the conductive via hole.

[0062] After step S800, the method further includes:

[0063] Step S800a, form a magnetic tunnel junction layer on the electrode layer above each of the holes;

[0064] Step S800b, pattern the electrode layer.

[0065] Figures 9 - 17 It is a schematic diagram of the structure formed by each step of the method for forming a semiconductor device according to an embodiment of the present invention.

[0066] Reference Figure 9 , in step S100, provide a front-end device layer 10. The front-end device layer 10 includes a dielectric layer 12. Specifically, the front-end device layer 10 includes a substrate 11 and a dielectric layer 12 stacked in sequence

[0067] Specifically, the front-end device layer 10 provided in step S100 may be a single-crystalline silicon substrate, a single-crystalline germanium substrate, or a silicon-germanium single-crystalline substrate. Alternatively, the front-end device layer 10 may also be a silicon-on-insulator (SOI) substrate, a stacked silicon-on-insulator (SSOI), a stacked silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate with an epitaxial layer structure on silicon, a compound front-end device layer, or an alloy front-end device layer. The compound front-end device layer includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysproside, and the alloy front-end device layer includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. The SOI substrate includes a semiconductor layer (such as a silicon layer, a silicon-germanium layer, a carbon-silicon layer, or a germanium layer) disposed on an insulating material layer, and source devices and passive devices are provided in the semiconductor layer. The insulating material layer protects the active devices and passive devices disposed on the semiconductor layer. On the surface of the front-end device layer, several epitaxial interface layers or strain layers and other structures may also be formed to improve the electrical performance of the semiconductor device.

[0068] The material of the dielectric layer 12 can be silicon dioxide (SiO2), silicon oxynitride (SiON), or silicon oxycarbide (SiOC). In this embodiment, the material of the dielectric layer 12 is silicon dioxide.

[0069] Further, an etch stop layer is formed on the bottom surface of the dielectric layer 12. The material of the etch stop layer can be silicon nitride or nitrogen-doped silicon carbide (Nitrogen dopped Silicon Carbite, NDC). The etch stop layer can prevent over-etching of the substrate 11 during the etching of the dielectric layer, and better control the depth of the hole.

[0070] Reference Figure 9 , in step S200, a sacrificial layer 20 is formed on the dielectric layer 12.

[0071] Specifically, chemical vapor deposition (CVD) can be used to form the sacrificial layer 20, such as low temperature chemical vapor deposition (Low Temperature Chemical Vapor Deposition, LTCVD), plasma chemical vapor deposition process (Plasma Chemical Vapor Deposition, PCVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), rapid thermal chemical vapor deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), fluid chemical vapor deposition process (FluidChemical Vapor Deposition, FCVD).

[0072] The sacrificial layer 20 is used to protect the dielectric layer 12 during the subsequent planarization process. Therefore, the material of the dielectric layer is selected to have a removal rate less than that of the dielectric layer 12 during the planarization process. That is to say, the polishing liquid used in the planarization process has a high etch selectivity for the sacrificial layer 20. Specifically, the material of the sacrificial layer 20 can be silicon nitride (Si3N4) and amorphous silicon (a-Si), etc. In this embodiment, the material of the sacrificial layer 20 is amorphous silicon. Amorphous silicon has a high etch selectivity and is easy to be removed in the subsequent process, and is not likely to introduce contaminating particles. It can improve the formation efficiency of semiconductor devices and ensure the reliability of semiconductor devices at the same time.

[0073] The thickness of the sacrificial layer 20 can be 20 - 300 angstroms. In this embodiment, the thickness of the sacrificial layer 20 is about 50 angstroms.

[0074] Reference Figure 10 , in step S300, pattern the dielectric layer 12 and the sacrificial layer 20 to form a plurality of holes 30 exposing the front-end device layer 10.

[0075] Specifically, lithography can be selected to pattern the dielectric layer 12 and the sacrificial layer 20. A patterned photoresist layer is formed on the sacrificial layer 20. The photoresist layer does not cover the area to be etched, and then the area not covered by the photoresist layer is etched. The specific etching process can be dry etching or wet etching. Stop etching until the front-end device layer 10 is exposed. Finally, remove the photoresist layer.

[0076] Reference Figure 11 , in step S400, form a barrier layer 40 covering the sidewalls of each hole 30 and the sacrificial layer 20.

[0077] Specifically, the barrier layer 40 only covers the sidewalls and the bottom of the hole 30 and does not completely fill the hole. After the barrier layer 40 is formed, there is a certain space between the barrier layers 40 on the sidewalls of the hole 30, and a conductive layer will be filled in this space in subsequent processes to form a conductive via that plays an interconnection role in the semiconductor device.

[0078] The barrier layer 40 has good stability and insulation, and can play a role in blocking the diffusion of the metal layer. It is used to block the diffusion of atoms or ions of the subsequent formed conductive via, avoid the phenomenon of short circuit caused by atomic diffusion, and ensure the reliability of the semiconductor device. The material of the barrier layer 40 can specifically be one of cobalt (Co), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), and tantalum silicon nitride (TaSiN).

[0079] The process of forming the barrier layer 40 can be Physical Vapor Deposition (PVD) and Chemical Vapor Deposition, etc. The thickness of the barrier layer 40 can be 30 angstroms - 100 angstroms.

[0080] In an alternative implementation, a barrier layer 40 made of tantalum nitride is formed by physical vapor deposition process, and the thickness of the barrier layer 40 is about 50 angstroms.

[0081] Reference Figure 12 , in step S500, form a conductive layer 50 filling each hole on the barrier layer 40.

[0082] The lower end of the conductive layer 50 forms an electrical connection with the semiconductor device in the front-end device layer.

[0083] Specifically, the material of the conductive layer 50 can be a metal, alloy or compound with good conductivity, including: one or more of copper (Cu), iron (Fe), aluminum (Al) and tungsten (W). In this embodiment, the material of the conductive layer 50 is copper.

[0084] In an alternative implementation, the method for forming the conductive layer 50 may first form a seed layer on the structure formed in step S400 by physical vapor deposition. Then, an electroplating process is used to form a conductive material on the seed layer until a conductive layer 50 with an upper surface higher than the barrier layer 40 is formed.

[0085] In other alternative implementations, the method for forming the conductive layer 50 may also be chemical vapor deposition or physical vapor deposition, etc.

[0086] Such as Figure 12 As shown, since the surface of the hole is lower than the surface of the barrier layer in the area where no hole is formed, after the conductive layer 50 is formed, a certain depression will be formed on the upper surface of the area of the conductive layer 50 above the hole.

[0087] Refer to Figure 13 , in step S600, planarize the conductive layer 50 to remove the conductive layer 50 and the barrier layer 40 on the sacrificial layer 20, and form a conductive via 50a.

[0088] Specifically, a chemical mechanical polish (CMP) process is used to planarize the structure. The chemical mechanical polish is a process of achieving planarization during the alternating process of chemical reaction and mechanical friction. Specifically, it can be divided into the following two processes:

[0089] Chemical process: The chemical components in the polishing liquid react with the surface material of the semiconductor device to generate substances that are relatively easy to remove. For example, insoluble substances are converted into soluble substances, or hard substances are softened.

[0090] Physical process: The abrasive particles in the polishing liquid and the surface material of the semiconductor device undergo mechanical physical friction to remove the reaction products of the chemical reaction.

[0091] Specifically, a silicon oxide CMP process can be used. The polishing liquid is composed of a chemical solution and abrasive particles, and the abrasive particles can be silicon dioxide or aluminum oxide (Al2O3), etc.

[0092] Since the material of the conductive layer 50 is copper, the etching rate in the polishing liquid is relatively fast. Therefore, such as Figure 13As shown, the upper surface of the conductive via 50a formed after chemical mechanical polishing is lower than the upper surface of the sacrificial layer 20. The sacrificial layer 20 is etched at a relatively slow rate in the polishing liquid, which protects the dielectric layer 12 below the sacrificial layer 20. Therefore, compared with the formation method of the comparative example, the embodiment of the present invention forms a sacrificial layer 20 above the dielectric layer 12, obtaining a relatively flat dielectric layer, avoiding the situation in the comparative example where the surface of the dielectric layer is lower than the barrier layer during the planarization process, and the situation where the surface of the dielectric layer has depressions.

[0093] Reference Figure 14 , in step S700, the sacrificial layer 20 is removed.

[0094] Specifically, the sacrificial layer 20 can be removed by a wet etching process or a dry etching process. Further, the etching process has a high selectivity ratio for the dielectric layer 12 and the conductive via 50a.

[0095] In this embodiment, the sacrificial layer 20 is removed by a wet etching process. The etching solution is selected from 10%-30% TAMH solution or ammonia water. Using an alkaline etching solution can avoid the corrosion of the conductive via 50a.

[0096] Reference Figure 15 , in step S700a, a protective layer 60 covering the conductive via 50a is formed.

[0097] The upper surface of the protective layer 60 is flush or substantially flush with the upper surface of the dielectric layer 12. The protective layer 60 is used to fill the gap above the conductive via 50a, enabling the surface of the area above the hole to be substantially flat. At the same time, the protective layer 60 can protect the conductive via 50a, avoiding the corrosion of the conductive via 50a and preventing the diffusion of electrons in the conductive via 50a.

[0098] Specifically, the material of the protective layer 60 is cobalt, and forming the protective layer covering the conductive via specifically means forming a protective layer 60 on the conductive via 50a by a selective deposition process.

[0099] The selective deposition process specifically uses a chemical vapor deposition device or an atomic layer deposition (ALD) device, with a cobalt-containing material as the precursor, and the precursor includes cobalt carbonyl complex, cobalt amidinate compound, cobaltocene compound, diene cobalt complex, nitrosyl cobalt complex, its derivatives, its complexes, its plasmas, or its compositions.

[0100] The selective deposition process can form the protective layer 60 only above the conductive vias, without forming the protective layer material on the dielectric layer, ensuring the reliability of the semiconductor device.

[0101] The thickness of the protective layer 60 can be 50 - 150 angstroms. In this embodiment, the thickness of the protective layer 60 is about 100 angstroms.

[0102] Compared with the comparative example, in this embodiment, the protective layer 60 is formed on the conductive via 50a, preventing the conductive via 50a from being corroded, avoiding time-dependent breakdown in the backend process, and ensuring the reliability of the semiconductor device.

[0103] Reference Figure 16 , in step S800, an electrode layer 70 covering the conductive via 50a and the dielectric layer 12 is formed.

[0104] The electrode layer 70 is used to form an electrical connection with multiple subsequent magnetic tunnel junctions, enabling multiple magnetic tunnel junction units to form a complete semiconductor device together with the semiconductor structure in the substrate through the electrode layer 70 and the conductive via 50a. Further, the electrode layer 70 also covers the protective layer 60.

[0105] Forming the electrode layer 70 may include the following steps:

[0106] Step S801, depositing an electrode material layer.

[0107] Step S802, planarizing the electrode material layer to form the electrode layer 70.

[0108] Specifically, the material of the electrode layer 70 can be metals such as copper, iron, aluminum, tungsten, cobalt, and tantalum, or compounds such as titanium nitride, tantalum nitride, titanium silicon nitride, and tantalum silicon nitride. Since titanium nitride has good stability and good conductivity, in this embodiment, the material of the electrode layer 70 is titanium nitride.

[0109] Specifically, depositing the electrode material layer can use processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the electrode layer 70 is formed using physical vapor deposition.

[0110] In this embodiment, after forming the electrode material layer, the electrode material layer is planarized to obtain a flat electrode layer, ensuring the flatness of the subsequent magnetic tunnel junction units formed on the surface of the electrode layer 70.

[0111] Reference Figure 17 , in step S800a, magnetic tunnel junction units 80 are formed on the electrode layer 70 above each of the conductive vias 50a.

[0112] The magnetic tunnel junction unit 80 includes a pinned layer 81, a barrier layer 82, and a free layer 83 stacked in sequence. The pinned layer 81 and the free layer 82 may include magnetic materials such as nickel, iron, cobalt, or their alloys. Or may include composite magnetic materials such as permalloy, permendur, or cobalt iron or their alloys. In addition, other materials such as platinum (Pt), iridium (Ir), manganese (Mn), aluminum (Al), ruthenium (Ru), osmium (Os), or tantalum (Ta), or their alloys may also be included. The material of the barrier layer 82 may be a non-magnetic isolation material such as aluminum oxide or magnesium oxide (MgO).

[0113] Forming the magnetic tunnel junction layer 80 may include the following steps:

[0114] Step S801a: Deposit a pinned material layer, a barrier material layer, and a free material layer stacked in sequence.

[0115] The deposition process may be a process such as physical vapor deposition or chemical vapor deposition.

[0116] Step S802a: Pattern the pinned material layer, the barrier material layer, and the free material layer to form a plurality of discrete magnetic tunnel junction units 80.

[0117] The process of patterning the pinned material layer, the barrier material layer, and the free material layer may specifically adopt a photolithography process.

[0118] As Figure 17 shown, the pinned layer 81, the barrier layer 82, and the free layer 83 are all relatively flat. Especially the barrier layer in the magnetic tunnel junction unit is relatively flat. Compared with the comparative example, the defects in the barrier layer formed in this embodiment are greatly reduced, and good performance can be maintained. A good barrier layer can ensure the performance of the magnetic tunnel junction unit.

[0119] In step S800b, pattern the electrode layer.

[0120] The process of patterning the electrode layer may be a photolithography process.

[0121] In subsequent processes, other semiconductor structures such as an isolation layer and an interconnection structure are formed on the above structure, and packaging and testing are performed to form a complete MRAM.

[0122] In the embodiment of the present invention, by forming a sacrificial layer above the dielectric layer, during the planarization process, the sacrificial layer plays a protective role for the dielectric layer, obtaining a relatively flat dielectric layer, avoiding the occurrence of depressions on the surface of the dielectric layer. Furthermore, the flatness of the magnetic tunnel junction layer is improved, avoiding the formation of defects in the barrier layer of the magnetic tunnel junction, and enabling the magnetic tunnel junction layer to maintain good performance. The reliability of the semiconductor device is improved.

[0123] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: providing a front-end device layer, the front-end device layer including a dielectric layer; forming a sacrificial layer on the dielectric layer, the material of the sacrificial layer being amorphous silicon; patterning the dielectric layer and the sacrificial layer to form a plurality of holes exposing the front-end device layer; forming a barrier layer covering the sidewalls of each of the holes and the sacrificial layer; forming a conductive layer filling each of the holes on the barrier layer; planarizing the conductive layer to remove the conductive layer and the barrier layer on the sacrificial layer, forming a conductive via hole, wherein the etching rate of the sacrificial layer in the planarizing step is slower than that of the conductive layer to protect the dielectric layer; removing the sacrificial layer; forming a protective layer covering the conductive via hole; and forming an electrode layer covering the conductive via hole and the dielectric layer; wherein the protective layer is used to protect the conductive via hole from being corroded and prevent electron diffusion.

2. The method for forming a semiconductor device according to claim 1, wherein The thickness of the sacrificial layer is 20 Å - 300 Å.

3. The method for forming a semiconductor device according to claim 1, wherein, The material of the conductive via hole is copper; the material of the protective layer is cobalt.

4. The method for forming a semiconductor device according to claim 1 or 3, characterized in that, The forming of the protective layer covering the conductive via hole specifically is: forming a protective layer on the conductive via hole by using a selective deposition process.

5. The method for forming a semiconductor device according to claim 2, wherein, The upper surface of the protective layer is flush or substantially flush with the upper surface of the dielectric layer.

6. The method for forming a semiconductor device according to claim 1, wherein, The method further includes: forming a plurality of discrete magnetic tunnel junction units on the electrode layer above each of the conductive via holes; patterning the electrode layer.

7. The method for forming a semiconductor device according to claim 6, wherein the magnetic tunnel junction unit includes a pinned layer, a barrier layer, and a free layer stacked in sequence.

8. The method for forming a semiconductor device according to claim 1, wherein, The semiconductor device is a magnetic random access memory.

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