Segmented digital-to-analog converter

Abstract

A digital-to-analog converter receives a digital input, the digital input comprised of a first least significant bit, a second most significant bit, and a third intermediate bit. The digital-to-analog converter includes first, second, and third sub-digital-to-analog converters. The first sub-digital-to-analog converter receives the first least significant bit and includes first resistors each contributing a respective voltage to provide a first output. The second sub-digital-to-analog converter receives the second most significant bit and includes second resistors each contributing a respective voltage to provide a second output as an output of the digital-to-analog converter. The third sub-digital-to-analog converter is connected to the first sub-digital-to-analog converter to receive the first output and receives the third intermediate bit, and includes third resistors each contributing a respective voltage to provide a third output to the second sub-digital-to-analog converter. The first and third resistors each have a physical area less than each of the second resistors.

Description

Technical Field

[0001] This invention relates to a digital-to-analog converter (DAC). Specifically, this invention relates to a segmented resistive DAC (R-DAC). Background Technology

[0002] The basic requirements for digital-to-analog converters (DACs) are monotonicity and accuracy. Further advancements in DAC development have demanded high conversion speeds and low power consumption. Figure 1 This is a schematic diagram of an existing DAC with 3 sub-DACs. Figure 1 It is based on US Patent No. 10110244. Figure 3 Its teachings are introduced here in their entirety for reference. Figure 1 The DAC 100 includes sub-DACs 18, 32, and 16, and binary-to-thermometer code decoders 12, 30, and 14 coupled to each respective sub-DAC. The binary-to-thermometer code decoders 12, 30, and 14 receive a portion of the digital input D and provide a thermometer code vector T to the respective sub-DACs 18, 32, and 16. Each sub-DAC 18, 32, and 16 has a resistor array, with each resistor having a unit resistance R. A scaling resistor 29 is coupled between sub-DACs 18 and 32. Another scaling resistor 29 is coupled between sub-DACs 32 and 16. Each sub-DAC 18, 32, and 16 has a corresponding switch library 22, 34, and 20, which couples the resistors in the array to a high reference voltage V. refh or low reference voltage V refl Sub-DAC 18 further includes a termination resistor 24, which has a unit resistance R.

[0003] Figure 1 The resistors in the DAC have the same resistance value, which is easy to configure and avoids mismatch between sub-DACs. However, resistors with the same resistance value consume a relatively large area. Typically, a DAC implemented on a SoC (system on chip) has an area of ​​approximately 240,000 μm. 2 The size.

[0004] Advantageous is a digital-to-analog converter (DAC) with an efficient layout area while maintaining accuracy and monotonicity. Summary of the Invention

[0005] This summary is provided to illustrate selected simplified portions of the concepts detailed in the following detailed description. This summary is not intended to identify key or essential features of the claims, nor is it intended to limit the scope of the claims.

[0006] According to one embodiment, a digital-to-analog converter (DAC) is provided, configured to receive a binary digital input and convert the digital input into an analog signal. The binary digital input consists of the most significant bit, the least significant bit, and the remaining bits. The DAC includes:

[0007] The first binary-to-thermometer code decoder is configured to receive the least significant bit and convert the least significant bit into the first thermometer code bit.

[0008] The second binary-to-thermometer code decoder is configured to receive the most significant bit and convert the most significant bit into a second thermometer code bit.

[0009] A third binary-to-thermometer code decoder is configured to receive at least a portion of the remaining bits and convert the remaining bits into third thermometer code bits;

[0010] The first sub-digital-to-analog converter includes a plurality of first resistors and a plurality of first switches each connected to a corresponding first resistor, wherein each of the first resistors has a common first resistance; each of the first switches is configured to receive a corresponding bit of a first thermometer code bit, and is configured to be controlled by the corresponding bit to connect the corresponding first resistor to a high reference voltage or a low reference voltage.

[0011] The second sub-digital-to-analog converter includes a plurality of second resistors and a plurality of second switches each connected to a corresponding second resistor, wherein each of the second resistors has a common second resistance; each of the second switches is configured to receive a corresponding bit of a second thermometer code bit, and is configured to be controlled by the corresponding bit to connect the corresponding second resistor to a high reference voltage or a low reference voltage.

[0012] The third sub-digital-to-analog converter includes a plurality of third resistors and a plurality of third switches each connected to a corresponding third resistor, wherein each of the third resistors has a common third resistance; each of the third switches is configured to receive a corresponding bit of a third thermometer code bit, and is configured to be controlled by the corresponding bit to connect the corresponding third resistor to a high reference voltage or a low reference voltage.

[0013] The first and third resistors are smaller than the second resistor.

[0014] According to some implementation methods:

[0015] Each of the first resistors has a first terminal and a second terminal, the first terminal of the first resistor is connected to a corresponding first switch, and the second terminals of all the first resistors are connected together; and

[0016] The first sub-digital-to-analog converter further includes a first scaling resistor having a first terminal and a second terminal, the first terminal of the first scaling resistor being connected to the second terminal of the first resistor, and the second terminal of the first scaling resistor providing the output of the first sub-digital-to-analog converter.

[0017] According to some implementations, the resistance value of the first scaling resistor is (2) times that of the first resistor. L -1) / 2 L , where L is the number of least significant bits of the digital input received by the first binary-to-thermometer code decoder.

[0018] According to some implementation methods:

[0019] The first sub-digital-to-analog converter further includes a termination resistor having a first terminal and a second terminal, the first terminal of the termination resistor being connected to a low reference voltage, and the second terminal of the termination resistor being connected to the second terminal of the first resistor; and

[0020] The resistance of the terminating resistor is equal to that of the first resistor.

[0021] According to some implementation methods:

[0022] Each of the third resistors has a first terminal and a second terminal. The first terminal of the third resistor is connected to the corresponding third switch, and the second terminals of all the third resistors are connected together and connected to the output of the first sub-digital-to-analog converter; and

[0023] The third sub-digital-to-analog converter further includes a third scaling resistor having a first terminal and a second terminal, the first terminal of the third scaling resistor being connected to the second terminal of the third scaling resistor, and the second terminal of the third scaling resistor providing the output of the third sub-digital-to-analog converter.

[0024] According to some implementation methods: the resistance value of the third scaling resistor is the third resistor. Where S1 is the number of the remaining bits of the digital input received by the third binary-to-thermometer code decoder.

[0025] According to some implementation methods:

[0026] Each of the second resistors has a first terminal and a second terminal. The first terminal of the second resistor is connected to a corresponding second switch. The second terminals of all the second resistors are connected together to provide the output of the second sub-digital-to-analog converter.

[0027] The second sub-digital-to-analog converter further includes a second scaling resistor having a first terminal and a second terminal, the first terminal of the second scaling resistor being connected to the output of the third sub-digital-to-analog converter, and the second terminal of the second scaling resistor being connected to the second terminal of the second resistor.

[0028] According to some implementation methods, the resistance value of the second scaling resistor is the difference between the first resistor and the second resistor.

[0029] According to some implementations: the third binary-to-thermometer code decoder is configured to receive all the remaining bits.

[0030] According to some implementations, the digital-to-analog converter further includes:

[0031] A fourth binary-to-thermometer code decoder, wherein the third and fourth binary-to-thermometer code decoders collectively receive all the remaining bits, and collectively convert the remaining bits into third thermometer code bits; and

[0032] The fourth sub-digital-to-analog converter includes a plurality of fourth resistors and a plurality of fourth switches each connected to a corresponding fourth resistor, wherein each of the fourth resistors has a common fourth resistance; each of the fourth switches is configured to receive a corresponding bit of a third thermometer code bit from a fourth binary to thermometer code decoder, and is configured to be controlled by the corresponding bit to connect the corresponding fourth resistor to a high reference voltage or a low reference voltage.

[0033] According to some implementation methods:

[0034] The first sub-digital-to-analog converter is configured to provide a first output voltage in response to a first thermometer code bit;

[0035] The third sub-digital-to-analog converter is configured to receive a first output voltage and to provide a third output voltage in response to a third thermometer code bit received from a third binary-to-thermometer code decoder.

[0036] The fourth sub-digital-to-analog converter is configured to receive a third output voltage and to provide a fourth output voltage in response to a third thermometer code bit received from a fourth binary-to-thermometer code decoder; and

[0037] The second sub-digital-to-analog converter is configured to receive a fourth output voltage and provide a second output voltage as the output of the digital-to-analog converter.

[0038] According to some implementation methods:

[0039] Each of the fourth resistors has a first end and a second end. The first end of the fourth resistor is connected to the corresponding fourth switch, and the second ends of each fourth resistor are connected together.

[0040] The fourth sub-digital-to-analog converter further includes a fourth scaling resistor having a first terminal and a second terminal, the first terminal of the fourth scaling resistor being connected to the second terminal of the fourth scaling resistor, and the second terminal of the fourth scaling resistor providing a fourth output voltage.

[0041] According to some implementation methods: the resistance value of the fourth scaling resistor is the fourth resistor. Where S i It is the number of the remaining bits of the digital input received by the fourth binary-to-thermometer code decoder.

[0042] According to some implementations, the fourth resistor is equal to the third resistor.

[0043] According to some implementation methods, the third resistor is 1 / 2 to 1 / 8 of the second resistor.

[0044] According to one embodiment, a digital-to-analog converter (DAC) is provided, configured to convert a digital input into an analog output. The digital input consists of a first least significant bit, a second most significant bit, and a third intermediate significant bit. The DAC includes:

[0045] The first sub-digital-to-analog converter is configured to receive the first least significant bit via a first binary-to-thermometer code decoder. The first sub-digital-to-analog converter includes first resistors, each of which contributes a corresponding voltage to provide a first output in response.

[0046] The second sub-digital-to-analog converter is configured to receive the second most significant bit via a second binary-to-thermometer code decoder. The second sub-digital-to-analog converter includes second resistors, each contributing a corresponding voltage to provide a second output as the output of the digital-to-analog converter.

[0047] A third sub-digital-to-analog converter, connected to the first sub-digital-to-analog converter to receive the first output, and configured to receive a third intermediate valid bit via a third binary-to-thermometer code decoder, includes third resistors, each contributing a corresponding voltage to provide a third output to the second sub-digital-to-analog converter; wherein

[0048] The first resistor and the third resistor each have a smaller area than the second resistor.

[0049] According to some implementation methods: each of the first resistor and each of the third resistor has a resistance value that is smaller than that of each of the second resistor.

[0050] According to some implementation methods: the resistance value of each of the first resistor and each of the third resistor is 1 / 2 to 1 / 8 of the resistance value of each of the second resistor.

[0051] According to some implementation methods:

[0052] The first sub-digital-to-analog converter includes a first switch, each first switch being connected to a corresponding first resistor, and each first switch being configured to connect the corresponding first resistor to a high reference voltage or a low reference voltage in response to a bit of a first thermometer code vector obtained by the first binary-to-thermometer code decoder from the first least significant bit.

[0053] The second sub-digital-to-analog converter includes second switches, each second switch being connected to a corresponding second resistor. Each second switch is configured to connect the corresponding second resistor to a high reference voltage or a low reference voltage in response to a bit of the second thermometer code vector decoded from the second most significant bit by the second binary-to-thermometer code decoder; and

[0054] The third sub-digital-to-analog converter includes a third switch, each third switch being connected to a corresponding third resistor. Each third switch is configured to connect the corresponding third resistor to a high reference voltage or a low reference voltage in response to a bit of the third thermometer code vector obtained by the third binary-to-thermometer code decoder from the third intermediate valid bit.

[0055] According to some embodiments, the digital-to-analog converter further includes a fourth sub-digital-to-analog converter, which is connected to the third sub-digital-to-analog converter to receive a third output, and connected to the second sub-digital-to-analog converter to provide a fourth output to the second sub-digital-to-analog converter; wherein

[0056] The third sub-digital-to-analog converter and the fourth sub-digital-to-analog converter are configured to receive the third intermediate valid bit collectively via the third binary-to-thermometer code decoder and the fourth binary-to-thermometer code decoder, respectively;

[0057] The fourth sub-digital-to-analog converter includes a fourth resistor, each contributing a corresponding voltage to provide a fourth output; and

[0058] Each of the fourth resistors has a resistance value equal to that of each of the third resistors. Attached Figure Description

[0059] To enable a more concrete understanding of the foregoing contents of this invention, further detailed description of the invention can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. The accompanying drawings illustrate only typical embodiments of the invention, and since the invention can have other equally effective embodiments, the accompanying drawings should not be construed as limiting the scope of the invention. The drawings are drawn for ease of understanding rather than measurement of the invention. The benefits of the claimed inventive subject matter will be readily understood by those skilled in the art upon reading this description and in conjunction with the accompanying drawings. In the drawings, similar reference numerals are used to indicate similar elements, and:

[0060] Figure 1This is a schematic diagram of an existing DAC with three sub-DACs;

[0061] Figure 2 This is a schematic diagram of a digital-to-analog converter (DAC) according to one embodiment; and

[0062] Figure 3 This is a schematic diagram illustrating a more general segmented DAC according to one implementation. Detailed Implementation

[0063] Figure 2 This diagram illustrates a digital-to-analog converter (DAC) according to one embodiment of the present invention. The DAC 200 includes a first sub-DAC 210, a second sub-DAC 220, and a third sub-DAC 230, wherein the third sub-DAC 230 is connected between the first sub-DAC 210 and the second sub-DAC 220. The DAC 200 receives a binary digital input and converts the digital input into an analog output voltage V. out .like Figure 2 As shown, DAC 200 includes a first binary-to-thermometer decoder 240, a second binary-to-thermometer decoder 250, and a third binary-to-thermometer decoder 260. Each binary-to-thermometer decoder corresponds to a sub-DAC, whose function is to control the switch using the thermometer code bits decoded from the binary bits, thereby achieving the desired effect. Figure 1 The sub-DAC's resistor is coupled to a high reference voltage V in a similar manner as shown in the diagram. H or low reference voltage V L .

[0064] According to this embodiment, the first binary-to-thermometer code decoder 240 receives the first least significant bit (LSB) of the digital input and converts the first LSB into thermometer code to be further provided to the first sub-DAC 210. It is understood that the value of the binary bit of the digital input received by the binary-to-thermometer code decoder corresponds to the number of "1"s in the thermometer code provided by converting that digital input bit. For example, if the binary value is 2 bits, the decoder will convert that 2-bit value into a 3-bit thermometer code vector, and if the binary value is 3 bits, the thermometer code vector will be 7 bits. For example, if the binary input is "00", the converted thermometer code vector will be "000". Similarly, a binary input of "01" will provide a thermometer code vector of "100", a binary input of "10" will provide a thermometer code vector of "110", and a binary input of "11" will provide a thermometer code vector of "111". If the binary input is "001", the thermometer code vector is "1000000"; if the binary input is "100", the thermometer code vector is "1111000"; if the binary input is "110", the thermometer code vector is "1111110". That is, the binary-to-thermometer code decoder receives binary-formatted digital input data and provides vector bits, where the number of bits set to 1 is equal to the value in the digital input data, starting from 0.

[0065] In this embodiment, the first LSB of the digital input received by the first binary-to-thermometer decoder 240 is converted into a thermometer code vector and subsequently provided to the first sub-DAC 210. Similarly, the second binary-to-thermometer decoder 250 receives the second most significant bit (MSB) of the binary-encoded digital input, and the third binary-to-thermometer decoder 260 receives the third middle-significant bit (SB) of the binary-encoded digital input. It is readily understood that the LSB, SB, and MSB of the digital input are distinct from each other and collectively constitute the digital input. Thus, when the LSB and MSB are determined, the SB represents the remaining bits of the digital input and is provided to at least one sub-DAC other than the first binary-to-thermometer decoder 240 and the second binary-to-thermometer decoder 250. Accordingly, the first sub-DAC 210 includes a first switch 211 for receiving one bit of the thermometer code vector provided by the first binary-to-thermometer code decoder 240, the second sub-DAC 220 includes a second switch 221 for receiving one bit of the thermometer code vector provided by the second binary-to-thermometer code decoder 250, and the third sub-DAC 230 includes a third switch 231 for receiving one bit of the thermometer code vector provided by the third binary-to-thermometer code decoder 260.

[0066] The first sub-DAC 210 includes first resistors 212, each first resistor 212 having a first terminal 213 and a second terminal 214. The first terminal 213 of each first resistor 212 is connected to a corresponding first switch 211. The first switch 211 thus connects the first resistor 212 to a high reference voltage V according to the applied bit in the thermometer code vector provided by the first binary-to-thermometer code 240. H or low reference voltage V L Thus, each first resistor 212 contributes a corresponding voltage to the first output voltage of the first sub-DAC 210. The first sub-DAC 210 also includes a termination resistor 215 having a first terminal 216 connected to the second terminal 214 of the first resistor 212. The other terminal of the termination resistor 215 is connected to a low reference voltage V. L The first sub-DAC 210 includes a first scaling resistor 217 having a first terminal 218 and a second terminal 219, the first terminal 218 being connected to the second terminal 214 of the first resistor 212, and the second terminal 219 providing a first output voltage for the first sub-DAC 210.

[0067] Similarly, the third sub-DAC 230 includes third resistors 232, each having a first terminal 233 and a second terminal 234. The first terminal 233 of each third resistor 232 is connected to a corresponding third switch 231. The third switch 231 thus connects the third resistor 232 to a high reference voltage V according to the applied bit in the thermometer code vector provided by the third binary-to-thermometer code 260. H or low reference voltage V L Thus, each third resistor 232 contributes a corresponding voltage to the third output voltage of the third sub-DAC 230. The third sub-DAC 230 also includes a third scaling resistor 235 having a first terminal 236 and a second terminal 237, the first terminal 236 being connected to the second terminal 234 of the third resistor 232, and the second terminal 237 providing the third output voltage of the third sub-DAC 230.

[0068] Similarly, the second sub-DAC 220 includes second resistors 222, each having a first terminal 223 and a second terminal 224. The first terminal 223 of each second resistor 222 is connected to a corresponding second switch 221. The second switch 221 thus connects the second resistor 222 to a high reference voltage V according to the applied bit in the thermometer code vector provided by the second binary-to-thermometer code 250. H or low reference voltage V L Thus, each second resistor 222 contributes a corresponding voltage to the second output voltage of the second sub-DAC 220. The second sub-DAC also includes a second scaling resistor 225 having a first terminal 226 and a second terminal 227, the first terminal 226 being connected to the third sub-DAC 230, the second terminal 227 being connected to the second terminal 224 of the second resistor 222, and providing the second output voltage of the second sub-DAC 220.

[0069] According to this embodiment, the termination resistor 215 has a 2R L The resistance value is equal to the resistance value 2R of each of the first resistor 212 and the third resistor 232. L If the first binary-to-thermometer code decoder 240 receives a 4-bit binary code from the digital input, then the first scaling resistor 217 and the third scaling resistor 235 each have a resistance value that is 15 / 16 of the resistance value of each of the first resistor 212 and the third resistor 232, as follows: Therefore, the equivalent resistance of the first sub-DAC 210 as seen from the third sub-DAC 230 is equal to 2R. L The equivalent resistance of the third sub-DAC 230 as seen from the second sub-DAC 220 is equal to 2R. L On the other hand, each of the second resistors 222 has a 2RM The resistance value of this 2R M The resistance value is the same as the resistance value 2R of each of the first resistor 212 and the third resistor 232. L Based on Equation 2R M =α×2R L Proportional, where α will be described further later. The second scaling resistor 225 has 2R. M -2R L The resistance value is the difference between the resistance values ​​of the first resistor 212 and the second resistor 222.

[0070] It should be noted that the DAC 200 includes a first sub-DAC 210 for receiving digital inputs (LSB) and a second sub-DAC 220 for receiving digital inputs (MSB). Although in Figure 2 The diagram shows DAC 200 including a third sub-DAC 230 as an intermediate SB to receive digital input. In other embodiments, DAC 200 may include more sub-DACs similar to the third sub-DAC 230, wherein the number of switches and corresponding resistors therein is configurable to reflect the number of bits of the received digital input. Figure 3 This is a schematic diagram of a more general segmented DAC according to an embodiment of the present invention. The DAC 300 includes a first binary-to-thermometer code decoder 310 that receives an L-bit first LSB of the digital input and converts the L-bit first LSB into 2... L -1 bits of the first thermometer code vector T1. Accordingly, DAC 300 includes a first sub-DAC 320 connected to the first binary-to-thermometer code decoder 310 to receive bits of the first thermometer code vector T1, named... to Furthermore, the DAC 300 includes a second binary-to-thermometer code decoder 330, which receives the M-bit second MSB of the digital input and converts the M-bit second MSB into 2... M -1 bit second thermometer code vector T i+2 Accordingly, the DAC 300 includes a second sub-DAC 340 connected to the second binary-to-thermometer code decoder 330 to receive bits of the second thermometer code vector Ti+2, named to and Figure 2 Similarly, in the first sub-DAC 210, the first resistor 322 of the first sub-DAC 320 has a 2R resistor. L The first sub-DAC 320's termination resistor 324 also has a resistance value of 2R. L The resistance value. The first scaling resistor 326 of the first sub-DAC 320 has... The resistance value. And... Figure 2 Similarly, in the second sub-DAC 220, the second resistor 342 of the second sub-DAC 340 has a 2R M The resistance value, where the equation 2R applies. M =α×2R L The α value will be described further later. The second scaling resistor 344 of the second sub-DAC 340 also has a 2R value. M -2R L The resistance value, which is related to Figure 2 The second scaling resistor 225 in the second sub-DAC 220 is similar.

[0071] like Figure 3 As shown, the DAC 300 includes a third binary-to-thermometer code decoder 350 and a fourth binary-to-thermometer code decoder 370, which collectively receive a third intermediate SB, which is the remaining bits of the digital input excluding the first LSB and the second MSB. A third sub-DAC 360 and a fourth sub-DAC 380 are respectively connected to the third binary-to-thermometer code decoder 350 and the fourth binary-to-thermometer code decoder 370. The third binary-to-thermometer code decoder 350 is configured to receive the S1 bit of the third intermediate SB of the digital input and convert the received S1 bit into binary code. The third thermometer code vector T2, named to Each bit of the third thermometer code vector T2 is provided to the corresponding third switch of the third sub-DAC 360. Figure 2 Similarly, the third resistor 362 of the third sub-DAC 230 has a 2R value. L The resistor, and the third scaling resistor 364 of the third sub-DAC 360 have The resistance value. The fourth binary-to-thermometer code decoder 370 is configured to receive the digital input S. i The middle SB of the bit, and the S received i The binary code is decoded as follows: Thermometer code vector T i+1 Named to Each bit of the thermometer code vector Ti+1 is provided to the corresponding switch in the fourth sub-DAC 380. Figure 2 Similar to the third sub-DAC 230 and the aforementioned third sub-DAC 360, the fourth resistor 382 of the fourth sub-DAC 380 has a 2R value. L The resistance value, and the fourth scaling resistor 384 of the fourth sub-DAC 380 has a specific... The resistance value.

[0072] To maintain the monotonicity of a DAC, the resistor values ​​should remain stable so that changes in a single bit of the digital input are correctly transmitted to the output voltage. Resistor mismatch reflects the stability of the resistor value and its deviation from the design value. For example, for a DAC that receives a 4-bit binary input, the resistor mismatch should be less than [value missing]. This ensures that a change in one bit of the input is correctly transmitted to the output voltage. Each increase in the accuracy requirement translates into a halving of the mismatch requirement, meaning that the resistor mismatch should be reduced by half.

[0073] In DAC manufacturing, resistors are integrated with other components of the device; that is, they are "on-chip" rather than discrete components, thus occupying space on the integrated circuit (IC) chip. There is an inverse relationship between the physical area occupied by a resistor and its mismatch. Specifically, the mismatch is inversely proportional to the square root of the area: Where Area_R is the physical area consumed by the resistor, k is the slope factor, and δR is the resistor mismatch. A higher resistor mismatch allows for savings in resistor area. Based on the above, reducing the monotonicity requirement by one bit will reduce the resistor area requirement by a factor of 4 to a fraction of the original area. (Reference) Figure 2 In the illustrated implementation, when the first sub-DAC 210 and the third sub-DAC 230 each receive 4 bits of digital input, the second sub-DAC 220 requires at least 4 bits + 4 bits of precision, i.e., at least 8 bits of precision, to ensure that the second sub-DAC 220 can operate correctly when variations occur in the 8 bits input to the first sub-DAC 210 and the third sub-DAC 230. Preferably, in some implementations, the second sub-DAC 220 has 9 bits of precision, meaning that the second sub-DAC 220 includes one extra bit as design redundancy. However, for the third sub-DAC 230, only a maximum of 5 bits of precision is required. The area of ​​resistor 232 is configured as follows: Area_2R M This refers to the area of ​​the second resistor 222 in the second sub-DAC 220. The first resistor 212 and the termination resistor 215 in the first sub-DAC 210 can have the same configuration as the third resistor 232 in the third sub-DAC 230, which will save the area of ​​the resistors in the first sub-DAC 210 and the third sub-DAC 230 to as little as 1 / 256 of the area of ​​the second resistor 222 in the second sub-DAC 220.

[0074] More generally, refer to Figure 3As shown, the area of ​​each of the first resistor 322, the third resistor 362, and the fourth resistor 382 is equal to the area of ​​the second resistor 342. Where S1 is at least 1. Therefore, the resistance value of each of the first resistor 322, the third resistor 362, and the fourth resistor 382 is less than the resistance value of each of the second resistors 342. In some embodiments, the resistance value of a resistor is mainly determined by the area occupied by the resistor, as shown in the above equation 2R. M =α×2R L The factor α is at least 4. However, other fractional ratios may also be applied, for example, α is preferably between 2 and 8, which will not only save resistor area for the sub-DAC receiving the LSB and intermediate SB, but also ensure accuracy.

[0075] refer to Figure 2 The DAC 200 may further include an operational amplifier (op-amp) 270 having a positive input 272 and a negative input 274. The positive input 272 is connected to the output of a second sub-DAC 220, and the negative input 274 is connected to the output 276 of the operational amplifier 270. The DAC 200 includes the op-amp 270 to operate as an unbuffered voltage-mode DAC. In other embodiments, the DAC 200 includes an alternative operational amplifier 280 instead of the op-amp 270. The op-amp 280 has a positive input 282, a negative input 284, and an output 286. The positive input 282 is connected to a reference voltage, which is a high reference voltage V. H and low reference voltage V L The average value is used to determine the negative input terminal 284, which is connected to the output of the second sub-DAC 220. The output terminal 286 is connected to the negative input terminal 284 via a feedback resistor 288. In this embodiment, the feedback resistor 288 has a resistance value of [value missing]. Of which 64 is 2 6 6 is the number of bits provided to the MSB of the second sub-DAC 220, and 2R M This is the resistance value of the second resistor 222 in the second sub-DAC 220. The DAC 200 includes the optional operational amplifier 280 to operate as a buffered voltage-mode DAC. Figure 2 In the diagram, the dashed lines between the third sub-DAC 230 and op-amps 270 and 280 show possible connections.

[0076] The DAC described in each embodiment includes a first sub-DAC to receive a thermometer code vector converted from the LSB of the digital input, and a second sub-DAC to receive a thermometer code vector converted from the MSB of the digital input. Further, the DAC includes at least one third sub-DAC connected between the first and second sub-DACs to receive a thermometer code vector converted from an intermediate SB of the digital input. Each of the first to third sub-DACs includes multiple switches to receive bits in the corresponding received thermometer code vector. Each of the first to third sub-DACs further includes multiple resistors, each resistor connected to a corresponding switch. The switches are controlled by bits in the thermometer code vector to connect the corresponding resistor to a high reference voltage or a low reference voltage. Each resistor in the first and third sub-DACs has a smaller resistance value than the resistor in the second sub-DAC. Thus, the resistors in the first and third sub-DACs consume less area while maintaining the monotonicity and accuracy of the DAC.

[0077] Implementations of various embodiments have been described herein with reference to specific examples shown. These examples were chosen to assist those skilled in the art in forming a clear understanding of and implementing the embodiments. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, and the scope of methods implemented according to one or more embodiments, are not limited to the exemplary examples shown. Rather, those skilled in the art will understand based on this specification that many other configurations, structures, and methods can be implemented according to the various embodiments.

[0078] It should be understood that, with regard to the various positional indications used in the foregoing description of the invention, such as top, bottom, upper, and lower, these indications are given only with reference to the corresponding drawings, and may instead have other positional relationships when the orientation of the device changes during manufacturing or operation. As stated above, those positional relationships are described for clarity only and are not intended to be limiting.

[0079] The foregoing description in this specification refers to specific embodiments and accompanying drawings, but the invention should not be limited thereto; rather, it should be defined by the claims. The described drawings are exemplary and not restrictive. In the drawings, for illustrative purposes, the dimensions of elements may be enlarged and may not be drawn to a specific scale. This specification should also include variations in the tolerances and properties of the elements, operating methods, and other aspects. Various weakened embodiments of the invention should also be included.

[0080] The term "comprising" as used in this description and claims does not exclude other elements or steps. Unless specifically indicated, when using singular forms such as "a" or "an" to refer to a definite or indefinite element, the plural of that element should be included. Therefore, the term "comprising" should not be construed as limited to the items listed thereafter, nor should it be construed as excluding other elements or steps; the scope of the description "the device comprises items A and B" should not be limited to a device that includes only elements A and B. This description indicates that, for the purposes of this description, only elements A and B of the device are relevant. Although coupling generally includes inductive connections, and connection generally means a connection via, for example, wires, the terms "connection," "coupled," and "coupled" used herein all indicate an electrical connection between coupled or connected elements and do not imply the absence of intermediate elements. In describing transistors and their connections, the terms gate, drain, and source are interchangeable with gate, drain, and source, as well as gate terminal, drain terminal, and source terminal.

[0081] For those skilled in the art, various specific modifications can be made without departing from the scope of the claims of this invention.

Claims

1. A digital-to-analog converter, characterized in that, The digital-to-analog converter is configured to receive binary digital input and convert the digital input into an analog signal, wherein the binary digital input consists of the most significant bit, the least significant bit, and the remaining bits; the digital-to-analog converter includes: The first binary-to-thermometer code decoder is configured to receive the least significant bit and convert the least significant bit into the first thermometer code bit. The second binary-to-thermometer code decoder is configured to receive the most significant bit and convert the most significant bit into a second thermometer code bit. A third binary-to-thermometer code decoder is configured to receive at least a portion of the remaining bits and convert the remaining bits into third thermometer code bits; The first sub-digital-to-analog converter includes a plurality of first resistors and a plurality of first switches each connected to a corresponding first resistor, wherein each of the first resistors has a common first resistance; each of the first switches is configured to receive a corresponding bit of a first thermometer code bit, and is configured to be controlled by the corresponding bit to connect the corresponding first resistor to a high reference voltage or a low reference voltage. The second sub-digital-to-analog converter includes a plurality of second resistors and a plurality of second switches each connected to a corresponding second resistor, wherein each of the second resistors has a common second resistance; each of the second switches is configured to receive a corresponding bit of a second thermometer code bit, and is configured to be controlled by the corresponding bit to connect the corresponding second resistor to a high reference voltage or a low reference voltage. The third sub-digital-to-analog converter includes a plurality of third resistors and a plurality of third switches each connected to a corresponding third resistor, wherein each of the third resistors has a common third resistance; each of the third switches is configured to receive a corresponding bit of a third thermometer code bit, and is configured to be controlled by the corresponding bit to connect the corresponding third resistor to a high reference voltage or a low reference voltage. The first and third resistors are smaller than the second resistor.

2. The digital-to-analog converter according to claim 1, characterized in that: Each of the first resistors has a first terminal and a second terminal, the first terminal of the first resistor is connected to a corresponding first switch, and the second terminals of all the first resistors are connected together; and The first sub-digital-to-analog converter further includes a first scaling resistor having a first terminal and a second terminal, the first terminal of the first scaling resistor being connected to the second terminal of the first resistor, and the second terminal of the first scaling resistor providing the output of the first sub-digital-to-analog converter.

3. The digital-to-analog converter according to claim 1, characterized in that: Each of the third resistors has a first end and a second end. The first end of the third resistor is connected to the corresponding third switch. The second ends of each third resistor are connected together and connected to the output of the first sub-digital-to-analog converter. as well as The third sub-digital-to-analog converter further includes a third scaling resistor having a first terminal and a second terminal, the first terminal of the third scaling resistor being connected to the second terminal of the third scaling resistor, and the second terminal of the third scaling resistor providing the output of the third sub-digital-to-analog converter.

4. The digital-to-analog converter according to claim 1, characterized in that: Each of the second resistors has a first end and a second end. The first end of the second resistor is connected to the corresponding second switch. The second ends of each second resistor are connected together to provide the output of the second sub-digital-to-analog converter. as well as The second sub-digital-to-analog converter further includes a second scaling resistor having a first terminal and a second terminal, the first terminal of the second scaling resistor being connected to the output of the third sub-digital-to-analog converter, and the second terminal of the second scaling resistor being connected to the second terminal of the second resistor.

5. The digital-to-analog converter according to claim 1, characterized in that, Further includes: A fourth binary-to-thermometer code decoder, wherein the third binary-to-thermometer code decoder and the fourth binary-to-thermometer code decoder collectively receive all the remaining bits and collectively convert the remaining bits into third thermometer code bits; as well as The fourth sub-digital-to-analog converter includes a plurality of fourth resistors and a plurality of fourth switches each connected to a corresponding fourth resistor, wherein each of the fourth resistors has a common fourth resistance; each of the fourth switches is configured to receive a corresponding bit of a third thermometer code bit from a fourth binary to thermometer code decoder, and is configured to be controlled by the corresponding bit to connect the corresponding fourth resistor to a high reference voltage or a low reference voltage.

6. The digital-to-analog converter according to claim 5, characterized in that: The first sub-digital-to-analog converter is configured to provide a first output voltage in response to a first thermometer code bit; The third sub-digital-to-analog converter is configured to receive a first output voltage and to provide a third output voltage in response to a third thermometer code bit received from a third binary-to-thermometer code decoder. The fourth sub-digital-to-analog converter is configured to receive a third output voltage and to provide a fourth output voltage in response to a third thermometer code bit received from a fourth binary-to-thermometer code decoder; and The second sub-digital-to-analog converter is configured to receive a fourth output voltage and provide a second output voltage as the output of the digital-to-analog converter.

7. The digital-to-analog converter according to claim 1, characterized in that: The third resistor is 1 / 2 to 1 / 8 of the second resistor.

8. A digital-to-analog converter, characterized in that, The digital-to-analog converter is configured to convert a digital input into an analog output. The digital input consists of a first least significant bit, a second most significant bit, and a third intermediate significant bit. The digital-to-analog converter includes: The first sub-digital-to-analog converter is configured to receive the first least significant bit via a first binary-to-thermometer code decoder. The first sub-digital-to-analog converter includes first resistors, each of which contributes a corresponding voltage to provide a first output in response. The second sub-digital-to-analog converter is configured to receive the second most significant bit via a second binary-to-thermometer code decoder. The second sub-digital-to-analog converter includes second resistors, each contributing a corresponding voltage to provide a second output as the output of the digital-to-analog converter. A third sub-digital-to-analog converter, connected to the first sub-digital-to-analog converter to receive the first output, and configured to receive a third intermediate valid bit via a third binary-to-thermometer code decoder, includes third resistors, each contributing a corresponding voltage to provide a third output to the second sub-digital-to-analog converter; wherein The first resistor and the third resistor each have a smaller area than the second resistor.

9. The digital-to-analog converter according to claim 8, characterized in that: Each of the first resistor and each of the third resistor has a resistance value that is less than that of each of the second resistor.

10. The digital-to-analog converter according to claim 8, characterized in that: The system further includes a fourth sub-digital-to-analog converter (ADC), which is connected to the third ADC to receive a third output, and connected to the second ADC to provide a fourth output to the second ADC; wherein The third sub-digital-to-analog converter and the fourth sub-digital-to-analog converter are configured to receive the third intermediate valid bit collectively via the third binary-to-thermometer code decoder and the fourth binary-to-thermometer code decoder, respectively; The fourth sub-digital-to-analog converter includes a fourth resistor, each of which contributes a corresponding voltage to provide a fourth output; as well as Each of the fourth resistors has a resistance value equal to that of each of the third resistors.

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