Analog-to-digital converter based on low-power programmable bandwidth continuous-time delta-sigma modulator

Abstract

The present invention discloses an analog-to-digital converter (ADC) based on a continuous time (CT) Δ‑∑ modulator (DSM) in a radio receive chain that supports multiple data rates in a power-efficient manner with a small chip area. The ADC utilizes a second-order loop filter with a single amplifier loop filter topology that uses a two-stage Miller amplifier with a feedforward path and a push-pull output stage. High bandwidth operation employs a "negative R" compensation scheme at the amplifier input. The negative R auxiliary function is disabled in low data rate applications. When the negative R auxiliary function is disabled, the loop filter resistor value is increased instead of only increasing the loop filter capacitor value to scale the noise transfer function (NTF), thereby limiting the required capacitor area and achieving low power operation. The NTF zero position is programmable, allowing the NTF zero position to be located near the intermediate frequency of different bandwidths to reduce the impact of DSM quantization noise on narrowband (low data rate) applications.

Description

Field of the Invention

[0001] The present invention relates to analog-to-digital converters. Background Art

[0002] Analog-to-digital converters can be found in a wide range of applications including the receive chain of a radio receiver. There are many different radio standards, such as Bluetooth Low Energy. TM , Zigbee TM and other proprietary standards. The data rates of these standards vary from sub-kilobits per second (kpbs) to several megabits per second (Mbps), such as 100 bps to 3 Mbps. It is desirable to provide a receive link analog-to-digital converter that can support these various data rates in a power-efficient and size-efficient manner. Summary of the invention

[0003] Therefore, in one embodiment, a method includes configuring an analog-to-digital converter (ADC) to operate at a first data rate or a second data rate, the second data rate being lower than the first data rate. To operate the ADC at the first data rate, a negative R compensation circuit is enabled at an input of an amplifier of a delta-sigma modulator. To operate the ADC at the second data rate, the negative R compensation circuit is disabled.

[0004] In another embodiment, an analog-to-digital converter (ADC) is provided that includes a delta-sigma modulator and a negative R compensation circuit coupled to one or more switches that respond to a first value of a control signal to enable the negative R compensation circuit to be coupled to an input of an amplifier of the delta-sigma modulator and respond to a second value of the control signal to disable the negative R compensation circuit.

[0005] In another embodiment, an analog-to-digital converter (ADC) includes a delta-sigma modulator and a negative R compensation circuit that is selectively enabled to provide a loop gain enhancement function for an amplifier of the delta-sigma modulator when enabled, and is configurable to enable a first data rate for data to be provided to the delta-sigma modulator and disable a second data rate for data to be provided to the delta-sigma modulator, the second data rate being lower than the first data rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0007] Figure 1 A high-level block diagram of the radio receive chain is shown.

[0008] Figure 2 A prior art second order (with two integrators) delta-sigma modulator suitable for use in a receive chain ADC is shown.

[0009] Figure 3 An embodiment of a second-order continuous-time (CT) delta-sigma modulator (DSM) based ADC having only a single amplifier is shown.

[0010] Figure 4 An embodiment of a second order continuous time (CT) delta-sigma modulator (DSM) based ADC with only a single amplifier providing loop gain enhancement at the amplifier input with a negative R auxiliary is shown.

[0011] Figure 5 The improvement in effective gain using a negative R auxiliary circuit is conceptually illustrated.

[0012] Figure 6 Conceptual illustration of the thermal noise impact of using a negative R auxiliary circuit.

[0013] Figure 7 The noise transfer function and the location of the zero associated with the noise transfer function are shown for different bandwidth configurations of the ADC.

[0014] Figure 8 Additional details of the negative R auxiliary circuit are shown, particularly the switches associated with enabling and disabling the circuit.

[0015] Fig. 9 The resistor DAC used in the DSM is illustrated.

[0016] Fig.10 A current steering DAC that can be used in a DSM is shown.

[0017] Fig.11 A high-level block diagram of a two-stage Miller amplifier with an additional feed-forward path is shown.

[0018] Fig. 12A A more detailed differential embodiment of a two-stage Miller amplifier with an additional feed-forward stage and a push-pull output stage is shown.

[0019] Fig. 12B A portion of setting the output common mode voltage of the second stage of an embodiment of a two-stage Miller amplifier with an additional feed-forward stage and a push-pull output stage is shown.

[0020] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0021] Figure 1A high-level block diagram of a receive (RX) chain 100 in a radio in which embodiments of the present invention may be utilized is shown. The receive chain includes an antenna 101, a passive network 103 (typically implemented as an RLC network), a low noise amplifier 105, a mixer 107 that provides analog data at an intermediate frequency (IF) to a programmable gain amplifier (PGA) 109. In addition to gain programmability, the PGA typically also includes filtering to attenuate unwanted blocking signals. The amplifier 109 provides the analog input signal to an analog-to-digital converter (ADC) 111, which in turn provides the digital signal to a digital signal processor 115 to process the received radio signal. The embodiments described herein utilize a low power and small chip area RX ADC that is suitable for a wide range of data rates, for example, from less than 1 kilobit per second (kbps) to 3 megabits per second (Mbps), without incurring a large amount of area and power overhead to handle the various data rates. This enables a single RX ADC to support a variety of standards, such as Bluetooth 4.0, Bluetooth 4.0, and other proprietary standards for various Internet of Things (IoT) applications. TM Low Energy (BLE), Zigbee TM and sub-GHz bands.

[0022] A typical RX ADC utilizes a delta-sigma modulator based analog-to-digital converter. Figure 2 A prior art second order (with two integrators) delta-sigma modulator 200 suitable for use with an RX ADC is shown. The DSM 200 includes two amplifiers 201 and 203 configured in a distributed feedback topology. The DSM 200 utilizes a resistive DAC such as resistive DAC 205.

[0023] Figure 3 An embodiment of an ADC 300 based on a second-order continuous time (CT) delta-sigma modulator (DSM) is shown, which helps provide a more power and space efficient ADC. The ADC 300 implements a second-order loop filter using only a single amplifier 301 to save area and power, and achieves the same Figure 2 The two amplifier topologies of the second order DSM based ADC 200 are shown to have identical signal and noise transfer functions. As the operation of delta-sigma modulator based ADCs is well understood, the conventional details of the operation of the DSM based ADC 300 are not described.

[0024] Figure 4Another embodiment of an ADC 400 based on a second order continuous time (CT) delta-sigma modulator (DSM) is shown, which provides a more power and space efficient ADC compared to ADC 200. Similar to ADC 300, ADC 400 implements a second order loop filter using only a single amplifier 401 to save area and power. The ADC uses amplifier 401, resistor R1 403, resistor R2 407, capacitor C1 405, and capacitor C2 409 to implement the functions of the first and second integrators of DSM 200. Since the implementation of the DSM-based ADC 400 is differential, similar capacitors and resistors are found to be coupled between the positive output of amplifier 401 and the negative input of amplifier 401. The DSM-based ADC 400 has the same Figure 2 The two amplifier topologies of the second-order DSM-based ADC 200 are shown to have identical signal and noise transfer functions.

[0025] The DSM-based ADC 400 provides loop gain enhancement at the amplifier input using a negative R auxiliary circuit 415. The negative R circuit is essentially an active impedance synthesis circuit whose output impedance is resistant to negative polarity in a small signal sense. Figure 4 4, negative R auxiliary circuit 415 is implemented using CMOS amplifiers shown as inverter 451 and inverter 453. The input and output of inverters 451 and 453 are connected to the low signal swing input virtual ground nodes (ixp and ixn) of amplifier 401. The output impedance of the inverter is nominally set to the negative value of the resistance of the parallel combination of input resistance Ri, 417 and feedback DAC resistor Rdac1, 421 (-Ri / / Rdac1). In one embodiment, when the clock rate (fs) (given by Figure 4 When Ph1 and Ph2 in FIG. 4 are reduced, the negative R circuit 415 is disabled because at low frequencies, the loop gain is already high and the negative R assist is not needed. By disabling the negative R assist circuit, the overall thermal noise floor can be reduced. This allows larger resistors to be used without an overall thermal noise penalty because the increased thermal noise of the larger resistors is offset by the elimination of the negative R noise effect. In other words, larger resistors increase noise, but there is still a noise budget with the negative R circuit disabled. As further described herein, using larger resistors helps keep the loop filter area of ​​the ADC low by limiting the increase in capacitors to, for example, 4x (for 8x NTF scaling) while keeping the thermal noise level essentially constant. Larger resistors also allow the use of lower current amplifiers, thereby reducing overall power consumption.

[0026] Figure 5 and 6The advantages (and disadvantages) of the negative R auxiliary circuit for a single-ended amplifier embodiment are conceptually illustrated. Assume that the amplifier has a finite gain of A(s). Figure 5 and 6 , α = 1 nominal value (meaning that the negative R value is set to -Ri / / Rdac1), and |Z fb / R in |>>1, where Z fb is the feedback network impedance. The gain is shown as When α = 1, the second term disappears, thereby increasing the effective gain of the amplifier. Distortion caused by the nonlinearity of the op amp is reduced. The noise of the op amp is attenuated at the expense of the negative R circuit noise. Figure 6 , input referred noise power density v 2 n，in It can be calculated as:

[0027] Where k is the Boltzmann constant, T is the Kelvin temperature, and Rin is the input resistance. Therefore, when α = 1, the thermal noise contribution (4kTR in (1+α)) roughly doubles. Note that and represent the amplifier input referred noise and the noise power density of the feedback network, respectively.

[0028] like Figure 4 As shown, the transfer function of a second-order loop filter with a single op amp is:

[0029]

[0030] And under the constraint of R1C1+R2C2=R1C2, the above equation can be expressed in the following form

[0031]

[0032] It has Figure 2 The two integrator loop filters shown have the same loop filter transfer function form. Note that the values ​​of the loop filter components are not the same in the implementation of ADC 200 and ADC 400.

[0033] For lower data rates, the delta-sigma modulator noise transfer function (NTF) is scaled proportionally to the data rate in discrete steps (e.g., 8 steps covering the data rate). NTF scaling is typically accomplished by capacitor scaling to keep the thermal noise floor unaffected (i.e., if the sampling frequency is reduced by a factor of K, the capacitor value is scaled up by a factor of K). This approach naturally results in a larger capacitor area required for low frequency operation. In an embodiment of the present invention, NTF scaling is accomplished by scaling of the clock frequency and scaling of the input resistor and capacitor values ​​of the DSM loop filter. In an embodiment, the ADC loop filter capacitor and input resistance values ​​are selected so that at high frequency operation (high data rate, high bandwidth (BW)), the thermal noise floor specification is matched when the negative R circuit 415 is present. When the sampling frequency is lower, the negative R auxiliary is not required, and the negative R auxiliary circuit is turned off, and the thermal impact of the negative R auxiliary circuit disappears. Therefore, if the input resistance value remains unscaled with the negative R auxiliary circuit turned off, the thermal base will drop (lower thermal noise density). This is true even though the noise contribution of the op amp increases because the op amp is designed so that its noise contribution is lower than that of the loop filter resistor.

[0034] When the negative R circuit is disabled, the embodiment increases the loop filter resistor values ​​(Ri, R1, R2, Rdac1), not just the loop filter capacitor values. In particular, when the negative R circuit is disabled, the resistance of the input resistor Ri 417 will increase, and the remaining loop filter resistor values ​​(R1 403, R2 407 and Rdac1) will be scaled with the same proportionality factor as Ri. This allows the capacitors in the loop filter (C1, C2) to increase by a smaller amount (reduced by resistor scaling), thereby requiring a smaller area for capacitor scaling. For high data rate applications, the increased resistance will increase thermal noise, but will not exceed the thermal noise floor. Similarly, the current requirements of the operational amplifier can be relaxed. Of course, if a lower thermal noise floor is desired at low data rates, if sufficient chip area has been allocated for the loop filter capacitor for scaling, NTF scaling can be achieved by scaling only the capacitance of the loop filter (while keeping the negative R circuit disabled). In general, the negative R circuit does not have to be turned on or completely disabled at a negative resistance value equal to the effective input impedance (-Ri / / Rdac1, i.e., α=1). Note that due to the inherent variability of the circuit, the negative resistance value is approximately equal to the effective input impedance. In an embodiment, when the selected sampling clock frequency (and corresponding data rate) is not at a maximum or close to a maximum level, the negative resistance value is set to an intermediate level (e.g., α=0.5 (-2×Ri / / Rdac1) for medium data rate applications). Therefore, in an embodiment, the negative R compensation circuit operates at an intermediate compensation level between full compensation and no compensation, for intermediate data rates between the maximum data rate and the data rate at which negative R compensation is disabled.

[0035] In addition to enabling / disabling negative R assist and NTF scaling, embodiments herein provide the ability to program the NTF zero position, allowing the NTF zero to be located near the IF for different bandwidths. This significantly reduces the impact of DSM quantization noise, especially for narrowband (low data rate applications). For example, at the maximum data rate (2Mbps in one application), the sampling clock frequency is approximately 320MHz, while the IF bandwidth is approximately 2.5MHz, making the oversampling rate (OSR) equal to 64. For this application, the intermediate frequency (IF) is located around 1.5MHz and the NTF zero is located near 1.6MHz. For lower data rates, the bandwidth can be, for example, 1.25MHz, centered around an IF of 0.75MHz. Therefore, the NTF zero can be programmed from 1.6MHz to 0.75MHz to coincide with the lower IF with a smaller bandwidth.

[0036] In an embodiment, the loop filter components (R1, C1, R2, C2), the input resistor Ri, and the sampling clock frequency (fs) are all programmable. As explained more fully herein, the various components can be programmed for NTF scaling, programming the NTF zero position, and enabling / disabling the negative R auxiliary circuit. Table 1 illustrates an example of programming the sampling frequency, filter component values, and input resistance for NTF scaling, and programming the NTF zero position. Specifically, Table 1 shows the scaling of the reference (mode 1) resistor, capacitor, sampling frequency, OSR, and BW in various operating modes. In an embodiment, in mode 1, the input resistor Ri=80KOhms, the loop filter components R1=5.4MOhms, R2=50KOhms, C1=C2=200fF, and the sampling frequency fs=320MHz. OSR=64, BW is 2500kHz. Therefore, for a sampling clock frequency of 40MHz, the bandwidth is 156.25kHz or 312.5kHz (modes 6 and 5), for a sampling clock frequency of 160MHz, the bandwidth is 625kHz or 1.25MHz (modes 4 and 2), and for a sampling clock frequency of 320MHz, the bandwidth is 1.25MHz or 2.5MHz (modes 3 and 1).

[0037] In modes 1 to 4, the negative R circuit is enabled and in modes 5 and 6, it is disabled. When the sampling frequency is halved in mode 2, capacitors C1 and C2 are doubled to scale the NTF accordingly while keeping the thermal noise floor unchanged. In mode 2, the bandwidth is also halved.

[0038] In Mode 3, the sampling rate fs is kept at the maximum level and R1 is increased by a factor of 4 to move the NTF zero to a lower frequency by a factor of 2 for lower data rate applications (bandwidth is reduced by a factor of 2). The reduction in bandwidth results in a doubling of the OSR. The increase in R1 moves the zero position to a lower frequency. This allows the zero to be positioned at a frequency that fits the bandwidth to reduce the DSM quantization noise.

[0039] Table 1

[0040]

[0041] refer to Figure 7 , the overall noise transfer function is shown in the larger graph 701, while the lower frequency details are shown in the inset graph 703. The NTF null position can be adjusted based on the RX intermediate frequency (IF) position and the signal bandwidth, assuming the bandwidth is centered around the IF. Figure 7where fs is the ADC sampling frequency. Curve 705 represents the NTF of the ADC configured with OSR=64 (e.g., Mode 1) and the null position at 706. For NTFs with different bandwidths, the null position can be shifted, as shown by curve 707, with the null position at 708. It can be seen that the null position can be shifted lower, which means a higher OSR (smaller bandwidth at the same sampling frequency), such as Mode 3 in Table 1. Given the bandwidth and IF, R1 (see Tables 1 and Figure 4 ) are configured to a higher resistance to move the null position to a more ideal location. Note that curve 705 corresponds to modes 1, 2, and 5 of Table 1, while curve 707 corresponds to modes 3, 4, and 6. Referring again to Table 1, in mode 4 where the sampling frequency is halved, C1 and C2 are doubled to maintain the same frequency normalized NTF shape and maintain the same thermal noise floor. R1 is increased by a factor of 4 to move the null to half the original null frequency to better match the NTF null position to the smaller bandwidth IF. In mode 4, the bandwidth is reduced by a factor of 4 or equivalently the OSR is doubled.

[0042] Mode 5 is the first mode where the negative R auxiliary circuit is disabled due to the lower data rate (1 / 8 sampling frequency of Mode 1 sampling frequency). To limit the scaling of capacitors C1 and C2, the resistance values ​​of the input resistor Ri, feedback DAC resistor Rdac1, and feedback network resistors R1 and R2 are doubled. Doubling the loop filter resistors (Ri, R1, R2, and Rdac1) allows limiting the scaling of C1 and C2 to 4 times to scale the NTF by 8 times and keep the thermal noise floor essentially constant. Doubling all resistor values ​​(Ri, Rdac1, R1, R2) simultaneously keeps the frequency normalized NTF shape unchanged. Similarly, in Mode 6, the negative R auxiliary circuit is disabled due to the lower data rate (1 / 8 sampling frequency of Mode 1 sampling frequency). To limit the scaling of capacitors C1 and C2, the resistance values ​​of the loop filter resistors Ri, Rdac1, and R2 are doubled. This allows limiting the scaling of C1 and C2 to 4x to keep the NTF thermal noise floor constant. Given a smaller bandwidth (1 / 16), R1 is scaled up by 8x (4x larger than the remaining loop filter resistors) to more closely match the NTF zero to the reduced frequency IF (the zero location is reduced by an additional factor of 2x).

[0043] The various programmable entries shown in Table 1 can be configured by writing the desired control signal values ​​to a non-volatile memory (NVM) and providing control signals to configure the various settings at power-up. Thus, for example, the NVM stores switch settings for the negative R circuit 415, the desired resistances for the adjustable resistors Ri, Rdac1, R1, and R2, the desired capacitances for the adjustable capacitors C1 and C2, and the desired sampling frequency. The NVM can be accessed after packaging via a serial interface ( Figure 4 The various circuit configurations may be programmed by the IC (not shown) or may be programmed before the assembly is shipped to the customer, or may be programmed by the customer. In other embodiments, the configuration is pin programmable or determined at power-up by writing to the integrated circuit to select the desired configuration.

[0044] The loop filter components are configured based on the required BW. The data rate determines the BW. For example, for a particular modulation scheme (e.g., FSK modulation index 0.5), a data rate of 1Mbps implies a bandwidth of approximately 1.5MHz. Once the bandwidth requirement for a given data rate and modulation scheme is known, the loop filter settings are adjusted to provide the most power efficient configuration. Typically, high data rate applications use modes 1 and 2, and very low data rate applications use modes 5 and 6, for example. Note that the loop filter configuration shown in Table 1 is given for a receive chain ADC for low IF applications, where the IF frequency is set to a relatively low frequency close to DC. However, typically, Figure 4 The ADC shown can also be used in a null IF receiver, where the desired signal is placed around DC (ie, IF=0).

[0045] Figure 8 Additional details of the negative R auxiliary circuit 415 are shown. Figure 4 and Figure 8 In the embodiment of , the negative R auxiliary circuit 415 is implemented as two inverters 451 and 453. The negative R auxiliary circuit is disabled by opening switch 801 in response to setting the control signal 803 to -R OFF, and the switch 801 is closed in response to setting the control signal 803 to -R ON to enable the negative R auxiliary circuit. When the switch is closed, the output of inverter 451 and the input of inverter 453 are coupled to node A, and the output of inverter 453 and the input of inverter 451 are coupled to node B, and when the switch is open, the output of the inverter is disconnected from nodes A and B. The current source 807 is also connected / disconnected to the inverter based on the -R ON / OFF control signal. Note that other switches can be used to isolate the transistor input from nodes A and B. Resistor R 809 sets the output common level of nodes A and B.

[0046] Although the core of the negative R circuit is implemented by two cross-coupled inverters 451 and 453, whose nodes A and B are connected to the differential virtual ground node of the amplifier ( Figure 4 ixp and ixn of amplifier 401 in FIG. 4 , but they should be considered as analog CMOS amplifiers with an output impedance of -1 / (gm1+gm2). Figure 5 , α=1 means that 1 / (gm1+gm2) is set equal to Rin. Figure 4 In the ADC configuration, α = 1 corresponds to 1 / (gm1 + gm2) = Ri / / Rdac1. Note that the current source 807 (see Figure 8 ) to set the value of α to another value (e.g. 0.5). This feature can be used to provide intermediate values ​​of negative R between fully on or off, for example for medium bandwidth settings or process calibration.

[0047] Reference again Figure 4 , digital-to-analog converters (DACs) 421, 423, 425, and 427 are implemented as resistor DACs, such as Fig. 9 Although a resistor DAC may be used, in other embodiments, a Fig.10 Note that if you use the current steering DAC Fig.10 If a current steering DAC is used, Iref is adjusted to scale Rdac for the different modes in Table 1.

[0048] Figure 4 The illustrated embodiment uses a single amplifier loop filter topology to reduce power consumption and die area. Fig.11 , an embodiment of a single amplifier 401 utilizes a two-stage Miller amplifier 1100 with an additional feed-forward path. For ease of illustration, Fig.11 The embodiment of is shown as a single-ended amplifier. The amplifier 1100 includes two stages 1101 and 1103 and a feed-forward stage 1105. Fig. 12A and 12B A more detailed differential embodiment of a two-stage Miller amplifier with a push-pull output stage for low power consumption is shown. Transistors M1a and M1b correspond to the first stage 1101, and transistors M2a and M2b correspond to the second stage 1103. The feedback stage transistors include M3a and M3b located between the input inn and the output outp (or inp and outn), where "p" represents a positive input or output and "n" represents a negative input or output. The push-pull stages of each example of the differential circuit are stages 1201a and 1201b. Capacitors 1203, 1205 and resistors 1207 and 1209 set the output common mode voltage of the first stage. Fig. 12B shows the circuit for setting the output common-mode voltage of the second stage. Note that Fig. 12BThe circuit portion shown has a node Vx 1215 coupled to the Fig. 12A The circuit portion shown. In one embodiment, the output common mode voltage is lower than the input common mode voltage. The M3 transistor can be implemented as a standard voltage threshold (SVT) transistor to increase the output swing compared to a low threshold voltage (LVT). Cc and Rc form a Miller compensation network for the two-stage amplifier.

[0049] In one or more embodiments, Figure 4 The amplifier 401 in the loop filter of the DSM ADC uses a Fig. 12A and 12B The current efficient two stage push-pull amplifier of the feed forward path is shown. For low bandwidth mode (low data rate) where the sampling frequency is low, the amplifier 1200 has sufficient loop gain without degrading the performance. In high bandwidth operation, in order to reduce the power consumption while mitigating the adverse effects of the limited gain of the amplifier used in the loop filter, a "negative R" compensation scheme is used.

[0050] Therefore, various aspects of a low power second order DSM based ADC have been described. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the appended claims. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for operating an analog-to-digital converter ADC, comprising: configuring the ADC to operate at a first data rate or a second data rate, the second data rate being lower than the first data rate; for operating the ADC at the first data rate, thereby enabling a negative R compensation circuit at an input of an amplifier of a delta-sigma modulator; as well as Used to cause the ADC to operate at the second data rate, thereby disabling the negative R compensation circuit.

2. The method according to claim 1, further comprising: With the negative R compensation circuit enabled, the compensation level of the negative R compensation circuit is set to an intermediate compensation level responsive to the first data rate being at an intermediate data rate between the second data rate and a maximum data rate, and the compensation level of the negative R compensation circuit is set to a high compensation level responsive to the first data rate being at a high data rate higher than the intermediate data rate, the high compensation level having a negative resistance value of the negative R compensation circuit that is approximately equal to the effective input impedance of the amplifier.

3. The method according to claim 1, further comprising: to operate the ADC at the first data rate with the negative R compensation circuit enabled, setting an input resistance coupled to a first input of the amplifier to a first resistance value, and setting a loop filter capacitance in a delta-sigma modulator of the ADC to a first capacitance value; as well as for operating the ADC at the second data rate with the negative R compensation circuit disabled, setting the input resistance to a second resistance value higher than the first resistance value, and setting the loop filter capacitance to a second capacitance value higher than the first capacitance value.

4. The method according to any one of claims 1 to 3, further comprising: By increasing the resistance value of the resistor of the loop filter of the delta-sigma modulator, a zero of the noise transfer function associated with the analog-to-digital converter is lowered.

5. The method according to any one of claims 1 to 3, further comprising: in, The delta-sigma modulator is a second-order sigma-delta modulator with a single operational amplifier.

6. The method according to claim 5, further comprising: in, The single operational amplifier is a two-stage Miller amplifier having a feed-forward path and a push-pull stage.

7. The method of claim 1 , further comprising configuring the analog-to-digital converter to operate at a sampling frequency of the delta-sigma modulator, the sampling frequency being between a first sampling clock frequency and a second sampling clock frequency, the second sampling clock frequency being eight times the first sampling clock frequency.

8. The method of claim 7, further comprising configuring the analog-to-digital converter to operate at a bandwidth within a bandwidth range between a first bandwidth and a second bandwidth, the second bandwidth being sixteen times greater than the first bandwidth.

9. The method according to claim 8, wherein: A higher sampling clock frequency is used with a first bandwidth and a lower sampling clock frequency is used with a second bandwidth, and the thermal noise level is maintained within approximately 0.2 dB on an ADC configured to operate at the first or second bandwidth, and the first bandwidth is higher than the second bandwidth.

10. The method according to any one of claims 1 to 3, further comprising: The ADC is operated in the receive path of the radio.

11. An analog-to-digital converter ADC, comprising: Delta-Sigma modulator; as well as A negative R compensation circuit is selectively enabled to provide a loop gain enhancement function for the amplifier of the delta-sigma modulator when enabled, and is configurable to be enabled for a first data rate of data to be provided to the delta-sigma modulator and disabled for a second data rate of data to be provided to the delta-sigma modulator, the second data rate being lower than the first data rate.

12. The analog-to-digital converter according to claim 11, further comprising: A first input resistor is coupled to the positive input terminal of the amplifier and can be configured to be set to a first resistance value when the negative R compensation circuit is enabled and to be set to a second resistance value when the negative R compensation circuit is disabled, and the second resistance value is higher than the first resistance value.

13. The analog-to-digital converter of claim 12, further comprising: The plurality of loop filter resistors are set to first respective resistance values ​​when the negative R compensation circuit is enabled, and the plurality of loop filter resistors are set to second respective resistance values ​​scaled up for the first respective resistance values ​​when the negative R compensation circuit is disabled.

14. The analog-to-digital converter according to claim 12, wherein: The loop filter capacitance of the delta-sigma modulator may be configured to have a first capacitance value when the negative-R compensation circuit is enabled, and a second capacitance value higher than the first capacitance value when the negative-R compensation circuit is disabled.

15. The analog-to-digital converter of claim 11, further comprising: a loop filter resistor coupled between the negative output terminal of the amplifier and the positive input terminal of the amplifier, and configured to have a first resistance value when a zero of a noise transfer function associated with the analog-to-digital converter is at a first frequency, and configured to have a second resistance value when the zero of the noise transfer function is at a second frequency lower than the first frequency, the second resistance value being higher than the first resistance value.

16. The analog-to-digital converter according to any one of claims 11 to 15, wherein: The delta-sigma modulator is a second-order sigma-delta modulator with a single operational amplifier.

17. The analog-to-digital converter according to claim 16, wherein: The delta-sigma modulator comprises: said single operational amplifier; a first capacitor coupled between a negative output terminal of the single operational amplifier and a positive input terminal of the single operational amplifier; a first resistor coupled in parallel with the first capacitor; a second capacitor and a second resistor, which are coupled in series between the negative output terminal of the single operational amplifier and the negative input terminal of the single operational amplifier; a third capacitor coupled between the positive output terminal of the single operational amplifier and the negative input terminal of the single operational amplifier; a third resistor and the third capacitor connected in parallel; and A fourth capacitor and a fourth resistor are coupled in series between the positive output terminal of the single operational amplifier and the positive input terminal of the single operational amplifier.

18. The analog-to-digital converter according to claim 16, wherein: The single operational amplifier is a two-stage Miller amplifier having a feed-forward path and a push-pull stage.

19. The analog-to-digital converter according to claim 16, wherein: The analog-to-digital converter can be configured to operate at a sampling frequency of the delta-sigma modulator, wherein the sampling frequency is between a first sampling clock frequency and a second sampling clock frequency, wherein the second sampling clock frequency is eight times the first sampling clock frequency, and wherein a bandwidth of the ADC can be configured to be between a first bandwidth and a second bandwidth, wherein the second bandwidth is sixteen times the first bandwidth.

20. An analog-to-digital converter ADC, comprising: Delta-Sigma modulator; as well as a negative R compensation circuit coupled to one or more switches responsive to a first value of a control signal to enable the negative R compensation circuit across an amplifier input of the delta-sigma modulator and responsive to a second value of the control signal to disable the negative R compensation circuit.

21. The analog-to-digital converter according to claim 20, wherein: The noise transfer function zero of the delta-sigma modulator is programmable.

22. An analog-to-digital converter according to any one of claims 20 to 21, wherein: When the negative R compensation circuit is enabled, in response to the data rate of the data provided to the Δ-Σ modulator being at an intermediate data rate, the compensation level of the negative R compensation circuit is set to an intermediate compensation level, the intermediate data rate being between a second data rate at which the negative R compensation circuit is disabled and a maximum data rate, and in response to the data rate being at a high data rate higher than the intermediate data rate, the compensation level of the negative R compensation circuit is set to a high compensation level, the negative resistance value of the negative R compensation circuit at the high compensation level being approximately equal to the effective input impedance of the amplifier, and the negative resistance value of the intermediate compensation level being higher than the effective input impedance.

23. The analog-to-digital converter of claim 22, further comprising: A current source in the negative R compensation circuit may be configured to provide a first current value for the intermediate compensation level and to provide a second current level for the high compensation level.

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