A network element active-standby clock alignment method, a mainboard, a backup board and a network element device

Abstract

The embodiment of the application provides a network element master / standby clock alignment method, a master board, a standby board and a network element device, the master board comprises a first SETS chip, a first PLL and a fourth PLL connected with the first SETS chip respectively; the standby board comprises a second SETS chip, a second PLL and a third PLL connected with the second SETS chip respectively; the first PLL of the master board issues a modulated master board clock signal based on the first SETS chip, and sends the modulated master board clock signal to the standby board through a backboard; the second PLL of the standby board demodulates the master board clock signal to the second SETS chip, and sends the modulated standby board clock signal back to the fourth PLL of the master board through the third PLL; then the first PLL of the master board phase detects the master board clock signal and the standby board clock signal demodulated by the fourth PLL, and finally performs phase compensation on the standby board; the path delay is measured in real time with high precision through modulation loopback measurement, and the clock time of the master / standby is ensured to have high precision in any scenario.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to but is not limited to the technical field of communication, in particular to but is not limited to a network element master / standby board switching clock alignment method, a master board, a standby board and a network element device. BACKGROUND

[0002] The rapid development of Internet and mobile Internet application, currently, a plurality of countries in the world have competed to develop 5G network technology, China and the European Union have invested a large amount of funds and research and development strength for this purpose. It is expected that 5G commercial services will be launched in 2020. According to the 5G promotion work deployment proposed by the Ministry of Industry and Information Technology and the 5G commercial plan of the three major operators, China will carry out large-scale test networking in 2018, and on this basis, 5G network construction will be started in 2019, and commercial services will be officially launched as soon as 2020.

[0003] In the use scene of 5G bearing, higher requirements are put forward for data transmission delay and jitter; the precision can be improved by increasing the frequency of the punch clock, which is one direction. Communication equipment generally adopts backup for the main single board to improve the reliability of the equipment, and the clock is a very important part of the communication equipment, so the backup working mode is adopted in the design of the communication equipment clock. Once the main clock fails, the standby clock immediately replaces the main clock to provide timing signals for the communication equipment. The switching of the main clock and the standby clock should try to ensure that there is no impact on the business (such as business instantaneous interruption, error code, etc. generated during switching), therefore, in any case, it is necessary to ensure that the phase of the main clock and the standby clock is aligned during the switching of the main clock and the standby clock, otherwise the equipment will generate error code or even business interruption.

[0004] In the main / standby system, how to ensure the high precision of the clock time in the main / standby switching scene is often considered less, which cannot meet the higher requirements of the bearing network business in the future 5G system. For example, in the current OTN system, the main / standby switching cannot prevent the logic of the hot plug driving device from being unable to achieve accurate delay control, and for other reasons, only the difference between the main clock and the standby clock on each slot business board can be measured manually, and the compensation is made on the standby master, the precision can be at most + / - 1 counting period, and real-time dynamic measurement cannot be achieved, resulting in that the business cannot be lossless during switching. SUMMARY

[0005] The network element master / standby switching clock alignment method, the master board, the standby board and the network element device provided by the embodiment of the present application mainly solve the problem that the clock time precision is not accurate in the main / standby switching in the related art, and the business is damaged during switching.

[0006] To solve the above technical problems, the embodiment of the present application provides a network element master / standby switching clock alignment method, which comprises the following steps:

[0007] The mainboard comprises a first synchronization equipment clock source (SETS) chip, a first PLL connected with the first SETS chip, and a fourth PLL connected with the first SETS chip.

[0008] The first PLL sends the modulated mainboard clock signal based on the first SETS chip to the backup board.

[0009] The fourth PLL receives the backup board clock signal sent by the backup board.

[0010] The first PLL performs phase discrimination on the mainboard clock signal and the backup board clock signal demodulated and sent by the fourth PLL, and sends a phase discrimination value to the backup board for phase compensation.

[0011] The embodiment of the application also provides a method for aligning a clock in a main / backup switching process of a network element, comprising the following steps:

[0012] The backup board comprises a second SETS chip, a second PLL connected with the second SETS chip, and a third PLL connected with the second SETS chip.

[0013] The second PLL receives the mainboard clock signal sent by the first PLL of the mainboard through a backboard, and sends the mainboard clock signal demodulated to the second SETS chip.

[0014] The third PLL sends the modulated backup board clock signal based on the second SETS chip.

[0015] The second SETS chip receives a phase discrimination value for phase compensation.

[0016] The embodiment of the application also provides a mainboard, which comprises a first SETS chip, a first PLL and a fourth PLL connected with the first SETS chip, and is used for implementing the steps of the method for aligning a clock in a main / backup switching process of a network element.

[0017] The embodiment of the application also provides a backup board, which comprises a second SETS chip, a second PLL and a third PLL connected with the second SETS chip, and is used for implementing the steps of the method for aligning a clock in a main / backup switching process of a network element.

[0018] The embodiment of the application also provides a network element device, which comprises the mainboard and the backup board.

[0019] The embodiment of the application has the following beneficial effects:

[0020] According to the network element mainboard clock switching alignment method, the mainboard, the backup board and the network element device provided by the embodiment of the present application, the mainboard comprises a first synchronization equipment clock source (SETS) chip, a first PLL connected with the first SETS chip, and a fourth PLL connected with the first SETS chip. The first PLL sends the modulated mainboard clock signal generated based on the first SETS chip to the backup board. The fourth PLL receives the backup board clock signal modulated and sent by the backup board. The first PLL performs phase discrimination on the mainboard clock signal and the backup board clock signal demodulated and sent by the fourth PLL, and sends the phase discrimination value to the backup board for phase compensation. The backup board comprises a second SETS chip, a second PLL connected with the second SETS chip, and a third PLL connected with the second SETS chip. The second PLL receives the mainboard clock signal sent by the first PLL of the mainboard through the backboard, demodulates the mainboard clock signal and sends it to the second SETS chip. The third PLL sends the modulated backup board clock signal generated based on the second SETS chip. The second SETS chip receives the phase discrimination value for phase compensation.

[0021] According to the network element mainboard clock switching alignment method provided by the embodiment of the present application, the modulated mainboard clock is sent by the first PLL of the mainboard in the circuit, and then the backup board demodulates the mainboard clock and sends it back to the mainboard. The first PLL of the mainboard calculates the phase difference between the mainboard clock and the backup board clock, and then performs phase compensation on the backup board. The path delay is measured in real time with high precision through modulation loopback measurement, so as to ensure the high precision of the clock time of the mainboard and the backup board in any scene.

[0022] Other features and corresponding advantages of the present application are described in the latter part of the specification, and it should be understood that at least part of the advantages become apparent from the description of the present application in the specification. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The principle diagram of the ordinary precision of the mainboard and the backup board clock switching time in the related art;

[0024] Figure 2 The principle diagram of the high precision of the mainboard and the backup board clock switching time in the embodiment one of the present application;

[0025] Figure 3 The flowchart of the mainboard clock processing in the embodiment one of the present application;

[0026] Figure 4 The flowchart of the backup board clock processing in the embodiment one of the present application;

[0027] Figure 5 The principle diagram of the high precision of the mainboard and the backup board clock switching time in the embodiment two of the present application;

[0028] Figure 6 A flowchart of a method for clock alignment in a master / standby switchover of a network element according to Embodiment Two of the present application;

[0029] Figure 7 A structural diagram of a master board according to Embodiment Three of the present application;

[0030] Figure 8 A structural diagram of a standby board according to Embodiment Three of the present application;

[0031] Figure 9 A structural diagram of a network element device according to Embodiment Three of the present application. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be made to the embodiments of the present application with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0033] Embodiment One:

[0034] In the related art, as shown in Figure 1 , Figure 1 is a principle diagram of normal precision of clock time in a master / standby switchover in the related art. In the circuit, 2-way uplink and downlink loops are used to realize clock time precision compensation. The master board sends out the master board clock through FPGA logic. The difference of 1PPS (pulse per second) of the master board and the standby board is measured manually, and compensation is made on the standby board. The compensation precision is at most + / - 1 counting period. The driver delay is not fixed, and real-time dynamic measurement cannot be realized, resulting in that the switchover service cannot be lossless.

[0035] As shown in Figure 2 , Figure 2 is a principle diagram of high precision of clock time in a master / standby switchover provided by the present application. The master board 20 includes a first synchronization device clock source SETS chip 201, a first PLL 202 connected with the first SETS chip 201, and a fourth PLL 203 connected with the first SETS chip 201. The standby board 30 includes a second SETS chip 301, a second PLL 302 connected with the second SETS chip 301, and a third PLL 303 connected with the second SETS chip 301. The master board 20 further includes a first FPGA 204 connected with the first SETS chip 201, and the standby board 30 further includes a second FPGA 304 connected with the second SETS chip 301. The master board 20 and the standby board 30 are connected through a backplane 40.

[0036] It should be noted that each PLL (phase-locked loop) on the master board and the standby board has PWM modulation (pulse width modulation) demodulation function and zero delay function, and each PLL can also realize phase discrimination function. The phase discrimination uses a separate ring, as shown in Figure 2As shown, in order to further improve the accuracy, in some embodiments, the output line can be fed back to the input, configured as an outer loop zero delay mode, in order to illustrate simply and clearly, Figure 2 Not shown; the first SETS 201 of the mainboard is configured as a lossless switching mode, and the second SETS 301 of the backup board is configured as a zero delay mode; in some embodiments, the PWM modulation of the first SETS 201 and the second SETS 301 also has a PWM modulation and demodulation function.

[0037] In the embodiment of the application, the length of the line from the first SETS chip 201 of the mainboard 20 to the first PLL 202 is a first length L1, the length of the line from the first PLL 202 to the backboard 40 is a second length L2, the length of the line from the backboard 40 to the fourth PLL 203 is a second length L2, the length of the line from the fourth PLL 203 to the first SETS chip 201 is a third length L3, and the length of the line from the fourth PLL 203 to the first PLL 202 is the sum of the first length and the third length L1+L3.

[0038] The mainboard 20 and the backup board 30 have symmetry, the length of the line from the backboard 40 to the second PLL 302 of the backup board 30 is a second length L2, the length of the line from the second PLL 302 to the second SETS chip 301 is a third length L3, the length of the line from the second SETS chip 301 to the third PLL 303 is a first length L1, the length of the line from the third PLL 303 to the backboard 40 is a second length L2, and the length of the line from the second PLL 302 to the third PLL 303 is the sum of the first length and the third length L1+L3. The length of the line from the backboard 40 is a fourth length L4, and the length of the line from the first SETS chip 201 to the first FPGA 204 is also a first length L1; the length of the line from the second SETS chip 301 to the second FPGA 304 is also a first length L1.

[0039] Based on Figure 2 The principle diagram of the high-precision master-slave switching clock of the application embodiment is shown, and the application embodiment provides a network element master-slave switching clock alignment method, as shown in Figure 3 The network element master-slave switching clock alignment method includes:

[0040] S301, the first PLL issues the modulated mainboard clock signal generated based on the first SETS chip to the backup board.

[0041] In the embodiment of the present application, the mainboard sends the mainboard clock signal modulated by PWM to the backup board, which can be the mainboard clock signal generated based on the first SETS chip and modulated by the first PLL with the PWM modulation function. Specifically, the first SETS chip generates the system clock of the mainboard, the first PLL receives the system clock of the mainboard, the first PLL modulates the system clock of the mainboard and the time TOD given by the logic to obtain the mainboard clock signal, and then the first PLL sends the mainboard clock signal with zero delay. Figure 2 The first FPGA in the figure gives the TOD through the SPI or I2C interface, and the logic gives the time TOD, so as to make the example clearer. Figure 2 The time TOD is not shown.

[0042] In some embodiments, the first SETS chip can also be modulated, and in this case, the first PLL only needs zero delay function. Specifically, the first SETS chip generates and modulates the mainboard clock signal, and the first PLL sends the mainboard clock signal with zero delay. For example, the first FPGA sends the TOD to the first SETS chip, the first SETS chip generates the system clock of the mainboard, and modulates the system clock and the TOD to obtain the mainboard clock signal.

[0043] S302, the fourth PLL receives the backup board clock signal modulated and sent by the backup board.

[0044] In the embodiment of the present application, the backup board sends the backup board clock signal modulated by PWM to the mainboard, and the fourth PLL of the mainboard receives the backup board clock signal through the backboard, demodulates the backup board clock signal to obtain the system clock of the backup board, and sends it to the first PLL with zero delay.

[0045] S303, the first PLL performs phase discrimination on the mainboard clock signal and the backup board clock signal demodulated and sent by the fourth PLL, and sends the phase discrimination value to the backup board for phase compensation.

[0046] The first PLL calculates the phase difference between the system clock of the backup board and the system clock of the mainboard, and the mainboard sends the phase difference to the backup board for phase compensation through TOD, that is, the first PLL of the mainboard performs phase discrimination, the path delay is (L1+2L2+L3+L4) during the main-backup switching, and the second SETS chip of the backup board performs phase compensation to complete the clock time alignment of the mainboard and the backup board.

[0047] Based on the high-precision principle diagram of the main-backup switching clock time as shown in Figure 2 The embodiment of the present application provides a network element main-backup switching clock alignment method, as shown in Figure 4 The network element main-backup switching clock alignment method comprises the following steps.

[0048] S401, the second PLL receives the mainboard clock signal issued by the first PLL of the mainboard through the backboard, and sends the mainboard clock signal after demodulation to the second SETS chip.

[0049] In the embodiment of the application, the second PLL demodulates the modulated mainboard clock signal and sends it to the second SETS chip. Specifically, the second PLL modulates the system clock of the mainboard and sends it to the second SETS chip with zero delay, and simultaneously sends it to the third PLL with zero delay. Because when the backup board becomes the mainboard, the system clock of the mainboard is sent to the third PLL for symmetry of the mainboard and the backup board. The TOD demodulated by the second PLL is sent to the second FPGA of the board through SPI / I2C, and the second FPGA is used to calculate the time of the board.

[0050] The second SETS chip generates the system clock of the backup board according to the system clock of the mainboard and sends it to the third PLL. The backup board also aligns the system clock generated by the second SETS chip with 8K and simultaneously sends the system clock with 8K to the third PLL.

[0051] S402, the third PLL issues the modulated backup board clock signal based on the backup board clock signal generated by the second SETS chip.

[0052] In the embodiment of the application, the third PLL can modulate the backup board clock signal. Specifically, the third PLL modulates the backup board clock signal according to the system clock of the backup board and the time TOD given by the logic and sends the backup board clock signal to the mainboard through the backboard. The time TOD given by the logic is the TOD given by the second FPGA in the mainboard through the SPI or I2C interface. In order to make the diagram clearer, Figure 2 the second FPGA in the mainboard is not shown. Figure 2

[0053] In some embodiments, the second SETS chip can also modulate the backup board clock signal, and in this case, the third PLL only needs zero delay function. Specifically, the second SETS chip generates and modulates the system clock of the backup board according to the system clock of the mainboard and sends it to the third PLL. For example, the second FPGA sends the TOD to the second SETS chip, the second SETS chip takes the system clock of the mainboard as the clock source, generates the system clock of the backup board, and modulates the system clock with the TOD to obtain the backup board clock signal. Then the mainboard receives the backup board clock signal and phase detects based on the backup board clock signal.

[0054] S403, the second SETS chip receives the phase detection value for phase compensation.

[0055] ​The first PLL of the mainboard performs phase discrimination to obtain a phase discrimination value, and the second SETS chip receives the phase discrimination value sent by the mainboard through TOD, and performs phase compensation according to the phase discrimination value.

[0056] The embodiment of the present application provides a network element master-slave switching clock alignment method, a PLL with PWM modulation and demodulation function is used in a circuit, a first PLL of a mainboard is used (or a zero delay driver is used) to replace existing ordinary precision logic to control downlink and uplink path symmetry, the first PLL phase discrimination is used to send and return clock phase difference, which is transmitted to a backup board through TOD, and delay compensation is performed on the backup board; compared with related technologies, the embodiment of the present application can accurately control line delay through PWM modulation in the case that there is only one path in the uplink and downlink loop, without manual intervention, realize real-time automatic clock time high-precision master-slave switching, realize real-time high-precision path delay measurement, ensure clock time high-precision of the master and the slave in any scene, and solve the problem of ordinary precision of existing master-slave switching clock time.

[0057] Embodiment three:

[0058] The embodiment of the present application provides a more specific network element master-slave switching clock alignment method, which illustrates clock time high-precision alignment of master-slave board switching, as shown in Figure 5 , Figure 5 The schematic diagram of master-slave switching clock time provided by the embodiment of the present application; as shown in Figure 6 , the network element master-slave switching clock alignment method comprises:

[0059] S601, the first SETS chip generates a system clock of the mainboard.

[0060] In the embodiment of the present application, the first SETS chip in the mainboard selects a clock source provided by the first FPGA logic, the first SETS is set to lossless switching mode, and the system clock of the mainboard is generated, the system clock of the mainboard includes a system clock (sys) and an 8K clock signal for synchronization, and the wiring length of the first SETS chip to the first FPGA and the first PLL is L1.

[0061] S602, the first PLL modulates the mainboard clock signal according to the system clock of the mainboard and the time TOD given by the logic.

[0062] The first FPGA gives TOD to the first PLL through an SPI or I2C interface, the first PLL performs PWM modulation on sys, 8K and TOD, and obtains the mainboard clock signal sys_8k_tod.

[0063] S603, the first PLL zero-delay sends the mainboard clock signal.

[0064] The first PLL modulates to obtain a mainboard clock signal sys_8k_tod, which is immediately sent to the backboard. The first PLL supports hot plug, and the wiring length is L2.

[0065] In S604, the second PLL receives the mainboard clock signal sent by the first PLL of the mainboard through the backboard.

[0066] The mainboard clock signal sys_8k_tod reaches the second PLL through the backboard, and the wiring length of the backboard is L4. The mainboard clock signal sys_8k_tod reaches the second PLL through the wiring with a length of L2.

[0067] In S605, the second PLL demodulates the system clock of the mainboard and sends it to the second SETS chip with zero delay and to the third PLL with zero delay.

[0068] The second PLL demodulates 8K (rck_8k) and sends it to the second SETS with zero delay and to the third PLL with zero delay. The wiring length is L3. Since the fourth PLL of the mainboard sends the system clock of the backup board to the first PLL, in order to ensure consistency between the mainboard and the backup board, the backup board sends the system clock of the mainboard to the third PLL. The mainboard TOD demodulated by the second PLL is sent to the second FPGA of the backup board through SPI / I2C.

[0069] In S606, the second SETS chip generates the system clock of the backup board according to the system clock of the mainboard and sends it to the third PLL.

[0070] The second SETS chip selects rck_8k as the clock source of the backup board and configures it in zero delay mode to generate the synchronous 8k and the system clock sys of the backup board, which are sent to the third PLL and the second FPGA. The second FPGA calculates the backup board time TOD according to the synchronous 8K and the system clock sys. The wiring length from the second SETS chip to the second FPGA and the second PLL is L1.

[0071] In S607, the third PLL modulates to obtain the backup board clock signal according to the system clock of the backup board and the time TOD given by the logic, and sends the backup board clock signal to the mainboard through the backboard.

[0072] The second FPGA sends the TOD to the third PLL through the SPI or I2C interface. The third PLL modulates the 8K, sys and TOD of the backup board through PWM to obtain the backup board clock signal sys_8k_tod. The wiring length from the third PLL to the backboard is L2.

[0073] In S608, the fourth PLL receives the backup board clock signal through the backboard and demodulates to obtain the system clock of the backup board, which is sent to the first PLL with zero delay.

[0074] The standby board clock signal returns to the main board through the backplane wire L4, is sent to the fourth PLL for demodulation to obtain the 8K (rck_8k) of the standby board, and is sent to the first PLL of the main board through the wire with the length L2+L3+L1.

[0075] In S609, the first PLL calculates the phase difference between the system clock of the standby board and the system clock of the main board, and sends the phase difference to the standby board through the time information TOD for phase compensation.

[0076] The first PLL completes the phase discrimination, and since there is no uncontrollable delay in the path, the whole path delay is (L2+L4+L2+L3+L1+L2+L2++L4+L3+L1), the path delay of the main board and the standby board switching is half of the whole path delay, i.e. (L1+2L2+L3+L4), the FPGA synchronization 8K delay of the main board and the standby board is half of the whole path delay, i.e. (L1+2L2+L3+L4), and the phase difference is (L1+2L2+L3+L4), which is sent to the standby board through the TOD, and the phase compensation is completed on the second SETS chip of the standby board, the alignment of the main system clock and the 8K is completed, and the high-precision clock time in the switching process of the main board and the standby board can be ensured.

[0077] In S610, the second SETS chip receives the phase discrimination value sent by the main board through the TOD, and performs phase compensation according to the phase discrimination value.

[0078] In the embodiment of the application, due to the symmetry of the main board and the standby board, when the main board becomes the standby board and the standby board becomes the main board, the situation is the same, and will not be described again. Figure 5

[0079] In the embodiment of the application, the PLL directly sends the backplane, when there are multiple slots, the PLL can send multiple slots through the zero-delay driver, and then the zero-delay selector selects the returned clock from the multiple slots, and measures the delay of each slot. In order to make the main board and the standby board switching clearer, Figure 5 The situation of each service board, the zero-delay driver and the zero-delay selector is not shown.

[0080] It is worth noting that since the path delay is controllable, in order to simplify the actual operation and application, the delay of the PCB wire and the like affected by the environment is ignored, the path delay from the main board to the standby board can be measured and directly compensated into the second SETS of the standby board, high-precision measurement is realized, i.e. the standby board can not use the return clock, and directly uses the hardware measurement method to calculate the path delay and compensate on the standby board.

[0081] ​The embodiment of the present application provides a kind of network element master backup clock alignment method, main and backup mutual sending channel uplink 1 way, downlink channel has 1 way, both to transmit clock, also guarantee the real-time alignment of time between main and backup, realize the high accuracy of main and backup clock time switching;On the clock channel of mainboard downlink, the system clock generated by the first SETS chip is aligned with 8K, the system clock is issued by time PWM modulation, and is sent to backup board through backplane, then the system clock and TOD information are demodulated on backup board;On the uplink channel of backup board, the system clock sent by the first SETS chip is selected, and the system clock generated by the second SETS chip is sent to the opposite mainboard through backplane, and the phase is judged at the input end of the first PLL, the path delay is measured in real time, and the path length is made equal on uplink and downlink, so that the path delay can be compensated in real time.

[0082] Embodiment three:

[0083] The embodiment of the present application provides a kind of mainboard, as shown in Figure 7 The first SETS chip, the first PLL and the fourth PLL are connected with the first SETS chip, and the first FPGA is connected with the first SETS chip, for realizing the steps of the network element master backup clock alignment method realized by the mainboard in each embodiment.

[0084] The embodiment of the present application provides a kind of backup board, as shown in Figure 8 The second SETS chip, the second PLL and the third PLL are connected with the second SETS chip, and the second FPGA is connected with the second SETS chip, for realizing the steps of the network element master backup clock alignment method realized by the mainboard in each embodiment.

[0085] The embodiment of the present application also provides a kind of network element device, as shown in Figure 9 The mainboard and the backup board are connected.

[0086] It can be seen that those skilled in the art should understand that all or some steps of the method disclosed above, the functions of the modules / units in the system and the device can be implemented as software (which can be realized by computer program code executable by a computing device), firmware, hardware and their appropriate combinations. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processor, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit.

[0087] Moreover, it is to be understood that the above description is intended to be illustrative, and not restrictive, of the present application. Many other

[0088] The above description is further to be understood that a variety of non- limiting changes in the method and apparatus disclosed herein will be apparent to one of ordinary skill in the art and can be made without departing from the scope of the present application.

Claims

1. A method for clock alignment during a master-backup switchover of a network element, comprising: a master board includes a first synchronization equipment clock source (SETS) chip, a first phase-locked loop (PLL) connected to the first SETS chip, and a fourth PLL connected to the first SETS chip; wherein the master board is connected to a backup board through a backplane; the backup board includes a second SETS chip, a second PLL connected to the second SETS chip, and a third PLL connected to the second SETS chip; wherein a wire length from the first SETS chip to the first PLL is the same as a wire length from the second SETS chip to the second PLL; a wire length from the first PLL to the backplane is the same as a wire length from the second PLL to the backplane; a wire length from the backplane to the fourth PLL is the same as a wire length from the backplane to the third PLL; and a wire length from the fourth PLL to the first SETS chip is the same as a wire length from the second SETS chip to the third PLL; the first PLL zero-delay issues a modulated master board clock signal based on the first SETS chip to the backup board; the fourth PLL receives a modulated backup board clock signal sent by the backup board through the backplane; the first PLL phase detects the modulated backup board clock signal sent by the fourth PLL and the master board clock signal, and sends a phase detection value to the backup board for phase compensation through time of day (TOD) information.

2. The method for clock alignment of a primary and a backup of a network element according to claim 1, wherein, the first PLL zero-delay issues a modulated master board clock signal based on the first SETS chip includes: the first SETS chip generates a system clock of the master board; the first PLL modulates the master board clock signal according to the system clock of the master board and a time TOD provided by logic; and the first PLL zero-delay issues the master board clock signal.

3. The method for clock alignment of a primary and a backup of a network element according to claim 1, wherein, the first PLL zero-delay issues a modulated master board clock signal based on the first SETS chip includes: the first SETS chip generates and modulates the master board clock signal; and the first PLL zero-delay issues the master board clock signal.

4. The method for clock alignment of a primary and a backup of a network element according to claim 1, wherein, the fourth PLL receives a modulated backup board clock signal sent by the backup board includes: the fourth PLL receives the backup board clock signal through the backplane; and the fourth PLL demodulates the backup board clock signal to obtain a system clock of the backup board, and zero-delay issues the system clock to the first PLL.

5. The method for clock alignment of a primary and a backup of a network element according to claim 4, c h a r a c t e r i z e d b y, the first PLL phase detects the modulated backup board clock signal sent by the fourth PLL and the master board clock signal, and sends a phase detection value to the backup board for phase compensation includes: the first PLL calculates a phase difference between the system clock of the backup board and the system clock of the master board; and the first PLL sends the phase difference to the backup board for phase compensation through TOD information.

6. The method of claim 1-5, wherein, The first SETS chip to the first PLL has a first length, the first PLL to the backplane has a second length; the backplane to the fourth PLL has a second length, the fourth PLL to the first SETS chip has a third length, and the fourth PLL to the first PLL has a sum of the first length and the third length.

7. A method for clock alignment during master-backup switching of a network element, comprising: The backup board includes a second SETS chip, a second PLL connected to the second SETS chip, and a third PLL connected to the second SETS chip; wherein the backup board is connected to the master board through a backplane; the master board further includes a first SETS chip, a first PLL connected to the first SETS chip, and a fourth PLL connected to the first SETS chip; wherein the first SETS chip to the first PLL has the same length as the second SETS chip to the second PLL; the first PLL to the backplane has the same length as the second PLL to the backplane; the backplane to the fourth PLL has the same length as the backplane to the third PLL; the fourth PLL to the first SETS chip has the same length as the second SETS chip to the third PLL; The second PLL receives the master board clock signal issued by the first PLL of the master board through the backplane with zero delay, demodulates the master board clock signal, and sends it to the second SETS chip; The third PLL issues the modulated backup board clock signal generated based on the second SETS chip with zero delay; The second SETS chip receives the phase detection value through time information TOD for phase compensation.

8. The network element primary / backup switchover clock alignment method as described in claim 7, characterized in that, The second PLL demodulates the master board clock signal and sends it to the second SETS chip, including: The second PLL demodulates the system clock of the master board, sends it to the second SETS chip with zero delay, and simultaneously sends it to the third PLL with zero delay; The second SETS chip generates the system clock of the backup board according to the system clock of the master board and sends it to the third PLL.

9. The method for clock alignment of a primary and a backup network element of claim 8, wherein, The third PLL issues the modulated backup board clock signal generated based on the second SETS chip, including: The third PLL modulates the backup board clock signal according to the system clock of the backup board and the time TOD provided by the logic, and sends the backup board clock signal to the master board through the backplane.

10. The method of claim 7, wherein the clock alignment is performed when the primary and backup network elements are switched. The third PLL issues the modulated backup board clock signal generated based on the second SETS chip, including: The second SETS chip generates and modulates the system clock of the backup board according to the system clock of the master board, and sends it to the third PLL.

11. The method of claim 7, wherein the clock alignment is performed when the primary and backup network elements are switched. The second SETS chip receives the phase detection value for phase compensation, including: The second SETS chip receives the phase detection value sent by the master board through TOD, and performs phase compensation according to the phase detection value.

12. The method of claim any one of claims 7-11, wherein, The backboard to the second PLL length is a second length, the second PLL to the second SETS chip length is a third length, and the second SETS chip to the third PLL length is the first length; The third PLL to the backboard length is a second length, and the second PLL to the third PLL length is the sum of the first length and the third length.

13. A main board, characterized by, The mainboard comprises a first SETS chip, a first PLL and a fourth PLL connected with the first SETS chip respectively; and the steps of the clock alignment method for the main / standby switching of the network element according to any one of the preceding claims 1-6.

14. A backup plate, characterized by The mainboard comprises a second SETS chip, a second PLL and a third PLL connected with the second SETS chip respectively; and the steps of the clock alignment method for the main / standby switching of the network element according to any one of the preceding claims 7-12.

15. A network element device, comprising: The mainboard comprises the mainboard according to claim 13, and the standby board according to claim 14.

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