The processor's filtered branch prediction architecture

Abstract

A branch predictor [110] of a processor [100] includes one or more prediction structures [112, 114, 116] that identify predicted branches, including predicted branch addresses and predicted branch directions. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information, and filters the selected structures so that the filtered structures are not used for branch prediction. Thus, the branch predictor reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.

Description

Background Art

[0001] Description of Related Technology

[0002] In order to improve processing efficiency, the processor may employ one or more predictive processing techniques. One type of predictive processing technique is called branch prediction, whereby the processor predicts the outcome of a branch instruction so that the processor can begin speculatively executing subsequent instructions along the predicted branch before the processing unit evaluates the branch instruction. To support branch prediction, the processor employs a branch target structure (referred to as a branch target buffer (BTB)) and a branch direction predictor. The BTB stores address information for predicted branches, while the branch direction predictor predicts whether a given branch is expected to be taken. However, conventional branch prediction structures consume an undesirable amount of power. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] By referencing the accompanying drawings, the present disclosure may be better understood, and its numerous features and advantages will be apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or identical items.

[0004] Figure 1 is a block diagram of a processor including a branch predictor with a filtered branch prediction structure according to some embodiments.

[0005] Figure 2 According to some embodiments Figure 1 A block diagram of a portion of a branch prediction module illustrating filtered accesses to a branch target buffer.

[0006] Figure 3 is a flow chart of a method of filtering accesses to a branch target buffer at a processor according to some embodiments.

[0007] Figure 4 According to some embodiments Figure 1 A block diagram of a portion of a branch prediction module illustrating filtered access to one or more branch direction tables.

[0008] Figure 5 is a flow chart of a method for filtering accesses to one or more branch direction tables based on table usage within a specified prediction period, according to some embodiments.

[0009] Figure 6 is a flow chart of a method of filtering accesses to one or more branch direction tables based on table usage according to a prediction of table usage, according to some embodiments. DETAILED DESCRIPTION

[0010] Figures 1 to 6A technique for reducing power consumption at a branch predictor of a processor is described. The branch predictor includes one or more prediction structures to identify predicted branches, including a predicted branch address and a predicted branch direction. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information, and filters the selected structures so that the filtered structures are not used for branch prediction. Thus, the branch predictor reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.

[0011] To illustrate, in some embodiments, the branch predictor includes two branch target buffers (BTBs) organized into levels, so that one of the BTBs is a level 1 (L1) BTB and the other is a level 2 (L2) BTB. The L2 BTB is larger than the L1 BTB but is slower to access than the L1 BTB. Conventionally, in order to identify the predicted branch address, the branch predictor accesses both the L1 and L2 BTBs at the processor for each acquired instruction address. However, for acquired instruction addresses that are likely to hit (i.e., be identified as stored therein) in the L1 BTB, concurrent access to the L2 BTB consumes power unnecessarily. In addition, in many cases, when a previously acquired instruction address that is in close spatial proximity in the virtual address space also hits in the L1 BTB, the acquired instruction address is more likely to hit in the L1 BTB. In other words, when the acquired instruction address has a relatively high spatial code locality, the L1 BTB hit is likely to increase. Therefore, using the techniques described herein, the branch predictor maintains a count of accesses to the same memory space region (referred to herein as a page), and when the count exceeds a threshold, suppresses accesses to the L2 BTB for addresses fetched in the corresponding memory page. Thus, the branch predictor reduces unnecessary accesses to the L2 BTB, thereby reducing dynamic power consumption at the processor.

[0012] As another example, in some embodiments, a branch predictor uses a basic predictor and multiple direction tables to predict branch directions, whereby each direction table is a tag table that independently predicts the direction of the predicted branch based on the history of the acquired instruction addresses stored in the direction table. For the acquired instruction address, the branch predictor identifies a set of tables that hit the tags associated with the acquired instruction address. The branch predictor combines the prediction generated by the basic predictor with the prediction from each of the identified sets of tables to generate a combined prediction. However, some of the prediction tables are unlikely to hit a given stream of acquired instruction addresses. Therefore, in order to reduce power consumption, the branch predictor predicts whether each direction table is predicted to hit within a specified time period, hit for a given instruction address, or a combination of the two. The branch predictor disables those direction tables that are predicted not to hit and are therefore unlikely to provide useful branch direction information. Thus, the branch predictor reduces the total number of accesses to the multiple direction tables, thereby reducing power without substantially reducing branch prediction accuracy.

[0013] Figure 1 A processor 100 is shown that includes a filtered branch prediction structure according to some embodiments. As used herein, a branch prediction structure is a filtered structure when its effect on branch prediction at the processor 100 can be selectively enabled and disabled. As further described herein, the processor 100 filters the branch prediction structure so that the structure does not affect branch prediction in one or more of a variety of ways, including inhibiting access to the structure, disabling the structure (e.g., placing the structure in a low-power state), or a combination thereof.

[0014] The processor 100 executes an instruction set (e.g., a computer program) on behalf of an electronic device to perform a specified task. In some embodiments, the processor 100 is incorporated into one of a variety of electronic devices, such as a desktop or laptop computer, a server, a game console, a smartphone, a tablet computer, etc. To support the execution of instructions, the processor 100 includes an instruction pipeline having an instruction fetch stage 102 and additional pipeline stages (not shown). The additional pipeline stages include a stage for decoding the fetched instructions into a set of operations, an execution stage for performing the decoded operations, and a retirement stage for retiring the executed instructions. It will be appreciated that in some embodiments, the processor 100 includes additional modules to support the execution of instructions, including one or more memory controllers, input / output controllers, memory structures (e.g., one or more caches), etc. In addition, it will be appreciated that in some embodiments, the processor 100 includes additional instruction pipelines. For example, in some embodiments, the processor 100 includes multiple processor cores, each of which has at least one instruction pipeline to execute the instruction set. Furthermore, in some embodiments, processor 100 includes additional processing units specifically designed to perform operations associated with particular tasks, such as one or more graphics processing units (GPUs) to perform operations associated with drawing, display, and other graphics operations.

[0015] return Figure 1 In the illustrated embodiment, instruction fetch stage 102 retrieves (fetches) instructions from instruction cache 103 based on instruction pointer 101. As will be appreciated by those skilled in the art, instruction pointer 101 is an address value that indicates the current instruction to be fetched and is modified by performing selected operations to modify the program flow of the instructions being executed. For example, in some embodiments, a branch instruction modifies instruction pointer 101 based on, for example, an evaluation of data specified by the branch instruction or an associated instruction.

[0016] To support high instruction fetch bandwidth, the processor 100 includes a branch predictor 110 that predicts whether a given fetch instruction corresponds to a branch instruction, predicts the direction of the given branch instruction (i.e., whether the given branch instruction will be taken), and predicts the target address of the given branch instruction (if the given branch instruction is predicted to be taken). The branch predictor 110 includes multiple modules and structures that support branch prediction, including an L1 BTB 112, an L2 BTB 114, a branch direction table 116, and a branch prediction control module 120. The branch prediction control module 120 manages the operation of the branch predictor 110, including enabling or disabling the branch prediction structure, suppressing access to the branch prediction structure, managing data stored at the branch prediction structure, and other management operations as further described herein.

[0017] L1 BTB 112 and L2 BTB 114 each include multiple entries, each entry corresponding to a different instruction pointer value predicted as a branch instruction. In at least one embodiment, branch prediction control module 120 manages the entries of L1 BTB 112 and L2 BTB 114 so that L2 BTB 114 serves as a victim buffer for L1 BTB 112. In some embodiments, L2 BTB 114 is a larger structure and contains more entries than L1 BTB 112. When branch prediction control module 120 evicts data from L1 BTB 112 based on a specified condition (such as new data being moved to L1 BTB 112), branch prediction control module 120 moves the evicted data to L2 BTB 114.

[0018] During each instruction cycle, the instruction fetch stage 102 provides the instruction pointer 101 to the branch predictor 110. In response, the branch prediction control module 120 determines whether the L1 BTB 112 includes an entry corresponding to the fetched instruction address indicated by the instruction pointer 101. In response to identifying that the entry corresponds to the received instruction pointer value (referred to as a BTB hit), the branch prediction control module 120 retrieves the branch target address (BTA) from the identified entry and provides the BTA to the instruction fetch stage 102.

[0019] In addition to accessing the L1 BTB 112 for each instruction address fetched, the branch prediction control module 120 selectively accesses the L2 BTB 114 based on whether the access to the L2 BTB 114 is expected to be productive (i.e., whether the access to the L2 BTB 114 is expected to result in a BTB hit). Figure 2 and Figure 3 As further described, the branch prediction control module 120 maintains a hit count at the L1 BTB 112 for fetched addresses corresponding to a specified region of virtual memory space, where the specified region is referred to herein as a memory page. It will be appreciated that the memory pages monitored by the branch prediction control module 120 may be different from the memory pages used for other operations at the processor 100, such as memory pages maintained by an operating system executing at the processor 100.

[0020] In response to receiving a fetched instruction address, the count for a given memory page being below a specified threshold, the branch prediction control module 120 identifies the memory page corresponding to the fetched instruction address and identifies the count corresponding to the identified memory page. In response to the count being below the threshold, the branch prediction control module 120 provides the fetched instruction address to the L2 BTB 114 and identifies whether the fetched instruction address hits in the L1 BTB 112. In response to a hit at the L2 BTB 114, the branch prediction control module 120 retrieves a branch target address (BTA) from the identified entry of the L2 BTB 114 and provides the BTA to the instruction fetch stage 102.

[0021] In response to determining that the count of the identified memory pages is above a specified threshold, the branch prediction control module 120 suppresses access to the L2 BTB 114 for the fetched instruction address by, for example, not providing the fetched instruction address to the L2 BTB 114. Thus, the branch prediction control module 120 ensures that the L2 BTB 114 is not accessed for the fetched instruction address that is predicted to hit in the L1 BTB 112, thereby reducing power consumption at the processor 100.

[0022] In addition to providing a BTA to the fetch stage 102, the branch predictor 110 also provides a branch direction prediction for each predicted branch instruction, where the branch direction prediction indicates whether the branch is predicted to be taken or not taken. To support prediction of branch direction, the branch predictor 110 includes a branch direction table 116. In at least one embodiment, the branch direction table 116 forms at least a portion of a tagged geometric length (TAGE) predictor, where each individual table (e.g., tables 117, 118) is a partially tagged predictor table that stores a global history of fetched instruction addresses forming a geometric progression. In addition, each table stores a different history depending on the corresponding geometric progression of the table. Each entry of the table stores: a useful bit indicating whether the corresponding entry is predicted to be useful in branch prediction; a counter for tracking a deviation value of the branch direction; and a tag indicating the virtual address associated with the entry.

[0023] The branch prediction control module manages the data stored at each of the branch direction tables 116. In at least one embodiment, the branch prediction control module analyzes patterns of branch instructions executed at the processor 100 over time, including which branch instructions are taken and which are not taken, and updates the branch direction table 116 based on the identified patterns. In at least one embodiment, the branch prediction control module 120 analyzes executed instructions in blocks or sets (referred to herein as branch prediction windows) and accesses the branch direction table 116 over each branch prediction window. Based on the identified patterns, the branch prediction control module updates the offset value, useful bit, or flag associated with one or more entries, or a combination thereof.

[0024] In at least one embodiment, the branch direction table 116 is divided into two levels, designated as a level 1 (L1) table and a level 2 (L2) table. During a prediction window, the branch prediction control module 120 accesses both the L1 table and the L2 table to identify a direction prediction in response to one of the BTBs 112 and 114 indicating a branch within the prediction window. In some embodiments, the branch prediction control module 120 accesses each table using a tag generated based on a path history associated with the prediction window (e.g., a control flow history associated with instructions included in the prediction window). Each entry in the branch direction table 116 with a matching tag provides the deviation value stored at the corresponding entry to the branch prediction control module 120, which selects or combines the received deviation values according to a specified branch prediction algorithm. The specific branch prediction algorithm varies depending on the design and application of the processor 100.

[0025] In some cases, the path history within a given prediction window is such that one or more of the branch direction tables 116 do not store an entry corresponding to the generated tag or provide branch prediction information that does not improve the accuracy of the branch direction prediction generated by the branch prediction control module 120. These one or more branch prediction tables do not provide useful branch prediction information within a given prediction window or set of prediction windows, and therefore accesses to these branch prediction tables are referred to herein as "unproductive" reads. It will be appreciated that unproductive reads consume power in the processor 100 without substantially improving the accuracy of branch predictions. Therefore, as discussed herein with respect to Figures 4 to 6As further described, the branch predictor 110 selectively inactivates one or more of the branch direction tables 116 based on a predicted likelihood that the selected branch prediction table will result in an unproductive read. The inactive branch prediction tables are not accessed by the branch prediction control module 120 and, in some embodiments, are placed in a low-power state, thereby saving power. As further explained herein, the branch prediction control module 120 selects the branch prediction tables to be inactive in one or more of a variety of ways, such as based on the number of times each table is hit during a set of prediction windows, based on a history of patterns of hits to the branch direction tables 116, or a combination thereof.

[0026] Figure 2 According to some embodiments Figure 1 1 is a block diagram of a portion of the branch predictor 110 for managing filtering of accesses to the BTB 114. In the depicted example, the branch prediction control module includes a BTB access control module 230 and a page access table 225. The BTB access control module 230 controls access to the L2 BTB 114 based on a received fetched instruction address (e.g., fetched address 211) and data stored in the page access table 225.

[0027] Page access table 225 includes a plurality of entries (e.g., entry 226), where each entry corresponds to a memory page (e.g., memory page 231). As noted above, in some embodiments, the memory pages (e.g., memory pages 231, 232) correspond to memory pages used by an operating system executing at processor 100. In other embodiments, memory pages 231, 232 do not correspond to memory pages used by an operating system. In some embodiments, the size of each of memory pages 231, 232 is configurable by a user or programmer of processor 100.

[0028] Each entry in the page access table 225 includes a memory page identifier field (e.g., identifier field 227 of entry 226) and an access count field (e.g., access count field 228 of entry 226). The memory page identifier field 227 stores an identifier of the memory page corresponding to the entry, and the access count field 228 stores the number of consecutive accesses to the memory page in the event of a miss in the L2 BTB 114, as further described below. In operation, the BTB access control module 230 manages the entries and fields of the page access table 225 and filters accesses to the L2 BTB 114 based on the access counts for the memory pages according to the page access table 225.

[0029] Figure 3A flowchart of a method 300 for filtering access to the L2 BTB 114 according to some embodiments is shown. At block 302, the BTB access control module 230 receives a fetched instruction address (e.g., fetched address 211). At block 304, the BTB access control module 230 identifies the memory page corresponding to the fetched address and determines whether the identified memory page has an entry in the page access table 225. If so, method flow moves to block 308 described below. If the identified memory page does not have an entry in the page access table 225, method flow moves to block 306, and the BTB access control module 230 allocates an entry in the page access table 225 for the identified memory page and sets the access count field of the allocated entry to an initial value (e.g., zero). In some cases, the access control module allocates an entry by replacing another entry using a specified replacement policy (such as a least recently used replacement policy). Method flow proceeds to block 308.

[0030] At block 308, the BTB access control module 230 determines whether the access count field of the identified memory page is greater than a threshold. If so, method flow moves to block 310, and the BTB access control module 230 filters access to the L2 BTB 114 by, for example, not providing the fetched instruction address to the L2 BTB 114. Method flow moves to block 311, and the BTB access control module 230 determines whether the L1 BTB 112 sends a BTA for the fetched instruction address to the L2 BTB 114. If not (i.e., the fetched instruction address has an L1 BTB miss), method flow returns to block 302. If the fetched instruction address has an L1 BTB hit, and the L1 BTB 112 sends a BTA for the fetched instruction address to the L2 BTB 114, method flow moves to block 321, and the BTB access control module 230 resets the access count field of the identified memory page to an initial value. Method flow returns to block 302.

[0031] Returning to block 308 , if the BTB access control module 230 determines that the access count for the identified memory page is at or below the threshold, the method proceeds to block 312 , and the BTB access control module 230 provides the fetched instruction address to the L2 BTB 114 to determine whether the L2 BTB 114 stores the BTA for the fetched instruction address. The method proceeds to block 314 .

[0032] At block 314, the L1 BTB 112 indicates a BTB hit or a BTB miss based on whether the L1 BTB 112 stores the BTA for the fetched instruction address. In response to a BTB hit at the L1 BTB 112, method flow moves to block 316, and the BTB access control module 230 maintains the access count for the identified memory page. Method flow returns to block 302.

[0033] Returning to block 314, if the L1 BTB 112 indicates a BTB miss, method flow moves to block 318, and the BTB access control module 230 determines whether the L2 BTB 114 has indicated a BTB hit for the fetched instruction address. In response to a hit in the L2 BTB 114 for the fetched instruction address, method flow moves to block 319, and the BTB access control module 230 resets the access count field for the identified memory page to an initial value. Method flow returns to block 302. If, at block 318, the L2 BTB indicates a BTB miss, method flow moves to block 320, and the BTB access control module increments the access count field for the identified memory page.

[0034] Figure 4 According to some embodiments Figure 1 1 is a block diagram of a portion of the branch predictor 110 for managing filtering of accesses to at least a subset of the branch direction tables 116. In the depicted example, the direction prediction tables are divided into two subsets: a set of L1 direction tables 442 (e.g., L1 direction tables 448 and 449) and a set of L2 direction tables 444 (e.g., L2 direction tables 446 and 447). The branch prediction control module 120 includes a direction table access control module 452 and a table usage history 455. The direction table access control module 452 identifies which of the L2 direction tables 444 will provide a prediction for a branch direction and records the identified L2 direction table in the table usage history 455. Additionally, the direction table access control module 452 identifies patterns in which the L2 direction tables 444 provide useful predictions based on the table usage history 455, and enables or disables access to selected ones of the L2 direction tables 444 based on the identified patterns.

[0035] By way of example, to determine a branch direction within a given prediction window, the branch prediction control module 120 accesses each of the L1 direction tables 442 and combines the direction predictions generated by the L1 direction tables 442 according to a specified branch direction algorithm to generate a direction prediction, designated for descriptive purposes as the "L1 direction prediction." Conventionally, the branch prediction control module 120 concurrently accesses each of the L2 direction tables 444 in a manner similar to the L1 direction table 442 to generate a separate and independent direction prediction, designated for descriptive purposes as the "L2 direction prediction." In the event of a conflict between an L1 direction prediction and an L2 direction prediction, the L2 direction prediction is typically selected because the L2 direction tables are larger, utilize more branch history, and are more accurate. They are also slower to access than the L1 prediction tables. However, as indicated above, within a given prediction window, only a subset of the L2 direction tables 444 are likely to provide a direction prediction. Thus, in at least one embodiment, direction table access control module 452 disables access to a selected subset of L2 direction table 444, thereby saving power without substantially reducing the accuracy of direction prediction.

[0036] Figure 5 and Figure 6 An example technique for identifying a subset of the L2 direction table 444 is shown at . Figure 5 , a flow chart illustrating a method 500 for identifying a subset of L2 direction tables 444 based on table usage over multiple prediction windows, according to some embodiments. At block 502, direction table access control module 452 uses table usage history 455 to identify usage of each of L2 direction tables 444 over N prediction windows, where N is an integer. Each set of N prediction windows is referred to herein as an "epoch." In at least one embodiment, direction table access control module 452 identifies a given L2 direction table as being used for a prediction window when there is a tag hit at the L2 direction table during the prediction window.

[0037] At block 504, the direction table access control module 452 identifies a directional misprediction rate at the branch predictor 110 during the period. In at least one embodiment, the misprediction rate is the number of branch directional mispredictions identified by the processor 100 during the period divided by N. The processor 100 identifies directional mispredictions using any of a variety of conventional misprediction identification techniques. Based on the branch misprediction rate, the direction table access control module 452 generates a control value that indicates one or more of: a level of directional mispredictions during the period, a rate of change in the directional misprediction rate, and whether the directional misprediction rate is increasing or decreasing.

[0038] For example, in some embodiments, the directional table access control module 452 generates a reference misprediction rate calculated for M periods, where M is an integer. For a certain period, the directional table access control module 452 calculates an error value based on the difference between the misprediction rate for that period and the reference misprediction rate. The directional table access control module 452 then uses a proportional-integral-derivative (PID) controller to calculate a control value based on the following three components: 1) a proportional component indicating the misprediction rate for the previous period; 2) an integer component indicating the sum of the error values for the previous period; and 3) a derivative component indicating the difference between the last two error values.

[0039] At block 506, the direction table access control module 452 determines the number of active L2 direction tables based on the control value calculated at block 504. For example, if the control value indicates that the misprediction rate is above a threshold or is increasing at a rate above the threshold, the direction table access control module 452 sets the number of active L2 direction tables to a relatively high number. In contrast, if the control value indicates that the misprediction rate is below a threshold or is increasing at a rate below the threshold, the direction table access control module 452 sets the number of active L2 direction tables to a relatively low number. Thus, the direction table access control module 452 maintains the misprediction rate within a specified tolerance.

[0040] At block 508, direction table access control module 452 selects a subset of L2 direction tables 444 that will be inactive based on the usage of each of L2 direction tables 444 during the previous period and based on the number of active L2 direction tables identified at block 506. For example, in some embodiments, direction table access control module 452 selects for the subset those L2 direction tables whose usage during the previous period was below a threshold. If the number of L2 direction tables selected for the subset would result in too few active L2 direction tables, as indicated by the required number calculated at block 506, the direction table access control module removes L2 direction tables from the subset until the required number is met. After selecting the subset of inactive L2 direction tables 444, direction table access control module 452 inhibits access to the selected subset during subsequent periods.

[0041] Figure 6A flow chart of a method 600 for identifying a subset of L2 direction tables 444 based on predicted table usage per period, according to some embodiments, is shown. With respect to method 600, it is assumed that direction table access control module 452 monitors the usage of each L2 direction table 444 during each prediction window and records the usage at table usage history 455. In at least one embodiment, direction table access control module records the usage pattern of each L2 direction table 444 for a specified period (such as a specified number of past prediction windows) by: storing a one at a corresponding bit position of the table entry if the corresponding L2 direction table has indicated a tag match; and storing a zero at the corresponding bit position if the L2 direction table has indicated a tag miss.

[0042] At block 602, the direction table access control module 452 accesses the table usage history 455 to profile the usage of the L2 direction table 444. In some embodiments, the direction table access control module 452 uses branch prediction techniques commonly used to predict branch directions to identify patterns. At block 604, based on the identified patterns, the direction table access control module 452 predicts, for each of the L2 direction tables 444, whether the corresponding table is expected to be used during the next prediction window. At block 606, the direction table access control module activates the L2 direction table predicted to be used at block 604 for the next prediction window. Therefore, during the next prediction window, the direction table access control module 452 only accesses those L2 direction tables that were activated. Thus, the direction table access control module conserves power while maintaining branch prediction accuracy. Method flow returns to block 602 for the next prediction window.

[0043] As disclosed herein, a method includes, in response to fetching a first instruction address for execution at a fetch stage of an instruction pipeline of a processor: identifying a first memory region including the first instruction address; identifying a first number of access misses to a first branch target buffer (BTB) for the first memory region; and, in response to the first number of access misses exceeding a threshold, suppressing access to the first BTB for the first instruction address. In one aspect, the method includes, in response to fetching the first instruction address, accessing a second BTB. In another aspect, the first BTB is a victim buffer of the second BTB. In yet another aspect, identifying the first number of accesses to the first memory region includes identifying the first number of accesses based on a table storing a plurality of access miss counts, each of the plurality of access miss counts being associated with a different memory region.

[0044] In another aspect, the method includes incrementing one of the plurality of counts in response to a first access miss at a first BTB. In yet another aspect, incrementing one of the plurality of counts includes incrementing one of the plurality of counts in response to a first access miss at the first BTB and a second access miss at a second BTB. In another aspect, the method includes resetting one of the plurality of counts in response to an access hit at the first BTB. In yet another aspect, the method includes resetting one of the plurality of counts in response to transferring a branch target address from the second BTB to the first BTB.

[0045] As disclosed herein, in some embodiments, a method includes: identifying a first usage history indicating usage of each of a first plurality of branch direction prediction tables within a first time period; selecting a first subset of the first plurality of branch direction prediction tables based on the first usage history; and suppressing access to the first subset of the first plurality of branch direction prediction tables within a prediction window of a branch predictor of a processor. In one aspect, identifying the first usage history includes: identifying the first usage history within a plurality of prediction windows of the branch predictor. In one aspect, selecting the first subset of the first plurality of branch direction prediction tables includes: determining a branch misprediction rate within the plurality of prediction windows; and selecting the first subset of the first plurality of branch direction prediction tables based on the first usage history and the branch misprediction rate. In another aspect, selecting the first subset of the first plurality of branch direction prediction tables includes: predicting a subset of the first plurality of branch direction prediction tables that is expected to be used during a subsequent prediction window of the branch predictor based on the first usage history; and selecting the first subset of the first plurality of branch direction prediction tables based on the predicted subset.

[0046] In one embodiment, a processor includes: an instruction pipeline including a fetch stage configured to fetch a first instruction address; and a branch predictor including: a first branch target buffer (BTB) configured to provide a branch target address to the instruction pipeline; a branch prediction control module configured to: identify a first memory region including the first instruction address; identify a first number of access misses to the first BTB for the first memory region; and, in response to the first number of access misses exceeding a threshold, suppress access to the first BTB for the first instruction address. In one aspect, the processor includes: a second BTB; and the branch prediction control module configured to access the second BTB in response to fetching the first instruction address. In another aspect, the first BTB is a victim buffer of the second BTB. In yet another aspect, the branch prediction control module is configured to: identify the first number of accesses based on a table storing a plurality of access miss counts, each of the plurality of access miss counts being associated with a different memory region.

[0047] In one aspect, the branch prediction control module is configured to increment one of the plurality of counts in response to a first access miss at the first BTB. In another aspect, the branch prediction control module is configured to increment one of the plurality of counts in response to a first access miss at the first BTB and a second access miss at the second BTB. In yet another aspect, the branch prediction control module is configured to reset one of the plurality of counts in response to an access hit at the first BTB. In yet another aspect, the branch prediction control module is configured to reset one of the plurality of counts in response to transferring a branch target address from the second BTB to the first BTB.

[0048] In some embodiments, a processor includes: a branch predictor, the branch predictor including: a first plurality of branch direction prediction tables configured to provide predictions of branch instruction directions; and a branch prediction control module configured to: identify a first usage history indicating usage of each of the first plurality of branch direction prediction tables within a first time period; select a first subset of the first plurality of branch direction prediction tables based on the first usage history; and suppress access to the first subset of the first plurality of branch direction prediction tables within a prediction window of the branch predictor. In one aspect, the branch prediction control module is configured to identify the first usage history by: identifying the first usage history within a plurality of prediction windows of the branch predictor.

[0049] In another aspect, the branch prediction control module is configured to select a first subset of the first plurality of branch direction prediction tables by: determining branch misprediction rates within a plurality of prediction windows; and selecting the first subset of the first plurality of branch direction prediction tables based on a first usage history and the branch misprediction rates. In yet another aspect, the branch prediction control module is configured to select the first subset of the first plurality of branch direction prediction tables by: predicting, based on the first usage history, a subset of the first plurality of branch direction prediction tables that is expected to be used during a subsequent prediction window of the branch predictor; and selecting the first subset of the first plurality of branch direction prediction tables based on the predicted subset.

[0050] In some embodiments, certain aspects of the above-described technology may be implemented by one or more processors of a processing system that executes software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that manipulate one or more processors to perform one or more aspects of the above-described technology when executed by one or more processors. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device (such as a flash memory, a cache, a random access memory (RAM), or one or more other non-volatile memory devices), etc. The executable instructions stored on the non-transitory computer-readable storage medium may be in the form of source code, assembly language code, object code, or other instruction formats that are interpreted or otherwise executed by one or more processors.

[0051] It should be noted that not all activities or elements described above in the general description are required, part of a specific activity or device may not be required, and one or more additional activities may be performed, or elements other than those described may be included. In addition, the order in which the activities are listed is not necessarily the order in which the activities are performed. Moreover, the concepts have been described with reference to specific embodiments. However, it will be understood by those skilled in the art that various modifications and changes may be made without departing from the scope of the present disclosure set forth in the appended claims. Therefore, the description and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0052] The benefits, other advantages and solutions to problems have been described above with reference to specific embodiments. However, the benefits, advantages, solutions to problems, and any features that may make any benefit, advantage or solution appear or become more prominent should not be construed as key, required or essential features of any or all of the claims. Furthermore, the specific embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners that will be apparent to those skilled in the art having the benefit of the teachings herein. No limitation is intended to the details of construction or design shown herein, except as described in the appended claims. Therefore, it is apparent that the specific embodiments disclosed above may be changed or modified, and all such variations are considered to be within the scope of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the appended claims.

Claims

1. A method comprising: maintaining a corresponding access count for each memory region in the plurality of memory regions; In response to fetching a first instruction address [211] for execution at a fetch stage [102] of an instruction pipeline of a processor [100]: identifying a first memory region from the plurality of memory regions including the first instruction address [231]; identifying, for the first memory region, a first number of access misses to a first branch target buffer (BTB) [114] based on the corresponding access count of the first memory region [228]; as well as In response to the first access miss number exceeding a threshold, access to the first BTB for the first instruction address is suppressed.

2. The method according to claim 1, further comprising: A second BTB is accessed in response to obtaining the first instruction address [112]. The method of claim 2 , wherein the first BTB is a victim buffer of the second BTB.

4. The method of claim 2, wherein: Identifying a first number of accesses for the first memory region includes identifying the first number of accesses based on a table [225] storing the access counts for the plurality of memory regions.

5. The method of claim 4, further comprising: One of the access counts is incremented in response to a first access miss at the first BTB.

6. The method of claim 5, wherein: Incrementing the one of the access counts includes incrementing the one of the access counts in response to the first access miss at the first BTB and a second access miss at the second BTB.

7. The method of claim 6, further comprising: The one of the access counts is reset in response to an access hit at the first BTB.

8. The method of claim 6, further comprising: The one of the access counts is reset in response to transferring a branch target address from the second BTB to the first BTB.

9. A method comprising: identifying a first usage history [455], the first usage history indicating usage of each of a first plurality of branch direction prediction tables over a first time period; selecting a first subset of the first plurality of branch direction prediction tables [444] based on the first usage history; as well as Access to the first subset of the first plurality of branch direction prediction tables is suppressed within a prediction window of a branch predictor [120] of the processor.

10. The method of claim 9, wherein identifying the first usage history comprises: The first usage history within a plurality of prediction windows of the branch predictor is identified.

11. The method of claim 10 , wherein selecting the first subset of the first plurality of branch direction prediction tables comprises: determining a branch misprediction rate within the plurality of prediction windows; as well as The first subset of the first plurality of branch direction prediction tables is selected based on the first usage history and the branch misprediction rate.

12. The method of claim 9, wherein selecting the first subset of the first plurality of branch direction prediction tables comprises: predicting a subset of the first plurality of branch direction prediction tables that is expected to be used during a subsequent prediction window of the branch predictor based on the first usage history [446, 447]; as well as The first subset of the first plurality of branch direction prediction tables is selected based on the predicted subset.

13. A processor [100], comprising: an instruction pipeline, the instruction pipeline comprising a fetch stage, the fetch stage configured to fetch [102] a first instruction address [211]; as well as A branch predictor [110], the branch predictor comprising: a first branch target buffer (BTB) [114] configured to provide a branch target address to the instruction pipeline; A branch prediction control module [120], the branch prediction control module being configured to: identifying a first memory region including the first instruction address from a plurality of memory regions [231], wherein a corresponding access count is maintained for each of the plurality of memory regions [228]; identifying a first number of access misses to the first BTB from the access count of the first memory region; and In response to the first access miss number exceeding a threshold, access to the first BTB for the first instruction address is suppressed.

14. The processor of claim 13, further comprising: Second BTB[112]; as well as The branch prediction control module is configured to access the second BTB in response to obtaining the first instruction address.

15. The processor of claim 14, wherein the first BTB is a victim buffer of the second BTB.

16. The processor of claim 14, wherein the branch prediction control module is configured to: A first number of accesses is identified based on a table [225] storing the access counts for the plurality of memory regions.

17. The processor of claim 16, wherein the branch prediction control module is configured to: One of the access counts is incremented in response to a first access miss at the first BTB.

18. The processor of claim 17, wherein the branch prediction control module is configured to: The one of the access counts is incremented in response to the first access miss at the first BTB and a second access miss at the second BTB.

19. The processor of claim 17, wherein the branch prediction control module is configured to: The one of the access counts is reset in response to an access hit at the first BTB.

20. The processor of claim 17, wherein the branch prediction control module is configured to: The one of the access counts is reset in response to transferring a branch target address from the second BTB to the first BTB.

21. A processor [100], comprising: A branch predictor [110], the branch predictor comprising: a first plurality of branch direction prediction tables [444] configured to provide predictions of branch instruction directions; and A branch prediction control module [120], the branch prediction control module being configured to: identifying a first usage history [455], the first usage history indicating usage of each of the first plurality of branch direction prediction tables over a first time period; selecting a first subset of the first plurality of branch direction prediction tables based on the first usage history; and Access to the first subset of the first plurality of branch direction prediction tables is suppressed within a prediction window of the branch predictor.

22. The processor of claim 21 , wherein the branch prediction control module is configured to identify the first usage history by: The first usage history within a plurality of prediction windows of the branch predictor is identified.

23. The processor of claim 22, wherein the branch prediction control module is configured to select the first subset of the first plurality of branch direction prediction tables by: determining a branch misprediction rate within the plurality of prediction windows; and The first subset of the first plurality of branch direction prediction tables is selected based on the first usage history and the branch misprediction rate.

24. The processor of claim 23, wherein the branch prediction control module is configured to select the first subset of the first plurality of branch direction prediction tables by: predicting, based on the first usage history, a subset of the first plurality of branch direction prediction tables that is expected to be used during a subsequent prediction window of the branch predictor; and The first subset of the first plurality of branch direction prediction tables is selected based on the predicted subset.

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