TSV as a pad

Abstract

Representative techniques and devices including process steps may be employed to mitigate the possibility of delamination of bonded microelectronic substrates due to metal expansion at the bonding interface. For example, through-silicon vias (TSVs) may be provided through at least one of the microelectronic substrates. The TSVs are exposed at the bonding interface of the substrates and serve as contact surfaces for direct bonding.

Description

[0001] Priority claims and cross-references to related applications

[0002] This application claims the benefit of U.S. Nonprovisional Application Nos. 16 / 439,360 and 2018, filed on June 12, 2019, and U.S. Provisional Application No. 62 / 684,505, filed on June 13, 2018, under 35 U.S.C. 119(e)(1), which are incorporated herein by reference in their entireties. Technical Field

[0003] The following description relates to integrated circuits ("ICs"). More specifically, the following description relates to manufacturing IC dies and wafers. Background Art

[0004] Microelectronic components typically include a thin flat plate of semiconductor material (such as silicon or gallium arsenide), which is generally referred to as a semiconductor wafer. The wafer can be formed to include multiple integrated chips or bare chips on the surface of the wafer and / or partially embedded in the wafer. The bare chips separated from the wafer are usually provided as separate, pre-packaged units. In some package designs, the bare die is mounted to a substrate or chip carrier, which is in turn mounted on a circuit panel such as a printed circuit board (PCB). For example, many bare chips are provided in packages suitable for surface mounting.

[0005] Packaged semiconductor dies can also be provided in a "stacked" arrangement, where one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements can allow several different dies and devices to be mounted within a single footprint on a circuit board, and can further facilitate high-speed operation by providing short interconnections between packages. Typically, the interconnection distance may be only slightly greater than the thickness of the die itself. In order to achieve interconnection within a stack of die packages, interconnect structures for mechanical and electrical connections can be provided on both sides (e.g., multiple faces) of each die package (except the topmost package).

[0006] Additionally, dies or wafers may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This may include: stacking layers of one or more dies, devices, and / or wafers on a larger base die, device, wafer, substrate, etc.; stacking multiple dies or wafers in a vertical or horizontal arrangement, and various combinations of both.

[0007] The die or wafers may be bonded in a stacked arrangement using a variety of bonding techniques including direct dielectric bonding, non-adhesive techniques such as ) or hybrid joining techniques (such as ), both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), Xperi Corporation. Bonding includes a spontaneous process that occurs under ambient conditions when two prepared surfaces are brought together (e.g., see U.S. Pat. Nos. 6,864,585 and 7,485,968, the contents of which are incorporated herein in their entirety).

[0008] The corresponding mating surfaces of the bonded dies or wafers typically include embedded conductive interconnect structures (which can be metal) or the like. In some examples, the bonding surfaces are arranged and aligned so that the conductive interconnect structures from the corresponding surfaces are connected during bonding. The connected interconnect structures form a continuous conductive interconnect (for signal, power, etc.) between the stacked dies or wafers.

[0009] There may be various challenges in achieving stacked die and wafer arrangements. When stacked die are bonded using direct bonding or hybrid bonding techniques, it is generally desirable that the surfaces of the die to be bonded are extremely flat, smooth, and clean. For example, typically, these surfaces should have very low variations (i.e., nanometer-scale variations) in surface topography so that these surfaces can fit tightly together to form a durable bond.

[0010] Double-sided dies can be formed and prepared for stacking and bonding, where both sides of the die will be bonded to other substrates or dies, such as in the case of multi-die-to-die or multi-die-to-wafer. Preparing both sides of the die includes processing (finishing) two surfaces to meet the dielectric roughness specification and the metal layer (e.g., copper, etc.) recess specification. For example, the conductive interconnect structure at the bonding surface can be slightly recessed, just below the insulating material of the bonding surface. The amount of recess below the bonding surface can be determined by the dimensional tolerance, specification or physical limitation of the device or application. The hybrid surface can be prepared to be bonded to another die, wafer or other substrate using a chemical mechanical polishing (CMP) process, etc.

[0011] Typically, when directly bonded surfaces comprising a combination of a dielectric layer and one or more metal features (e.g., an embedded conductive interconnect structure) are bonded together, the dielectric surfaces are first bonded at a lower temperature, and then the metal of the features expands as the metal is heated during annealing. The expansion of the metal causes the metal from the two bonded surfaces to join into a unified conductive structure (metal-to-metal bonding). Although both the substrate and the metal are heated during annealing, the coefficient of thermal expansion (CTE) of the metal relative to the CTE of the substrate generally indicates that at a particular temperature (e.g., ~300°C), the metal expands much more than the substrate. For example, the CTE of copper is 16.7, while the CTE of fused silica is 0.55, and the CTE of silicon is 2.56.

[0012] In some cases, the greater expansion of the metal relative to the substrate may be a problem for directly bonding stacked dies or wafers. If the metal pad is positioned above a through-silicon via (TSV), the expansion of the TSV metal may contribute to the expansion of the pad metal. In some cases, the combined metal expansion may result in local delamination of the bonding surface as the expanded metal rises above the bonding surface. For example, the expanded metal may separate the bonding dielectric surfaces of the stacked dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The detailed description is described with reference to the accompanying drawings. In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears. The use of the same reference numbers in different drawings indicates similar or identical items.

[0014] For the purposes of this discussion, the devices and systems shown in the figures are shown as having multiple components. As described herein, various implementations of devices and / or systems may include fewer components and still be within the scope of the present disclosure. Alternatively, other implementations of devices and / or systems may include additional components or various combinations of the described components and still be within the scope of the present disclosure.

[0015] Figure 1A A cross section of an example substrate with bond pads and TSVs is shown.

[0016] Figure 1B Shows Figure 1A A top view of an example substrate.

[0017] Figure 2 Cross-sections of two example bonded substrates with bond pads and TSVs, and example resulting delamination are shown.

[0018] Figure 3A A cross section of an example substrate is shown according to one embodiment, wherein at least one end of a TSV serves as a bonding surface.

[0019] Figure 3B According to an embodiment Figure 3A A top view of an example substrate.

[0020] Figure 4 Two example bonded substrate cross-sections are shown, wherein at least one end of a TSV serves as a bonding surface, according to one embodiment.

[0021] Figure 5 Cross-sections of two example substrates are shown, wherein at least one end of a TSV serves as a bonding surface, according to one embodiment.

[0022] Figure 6Cross-sections of two example substrates are shown according to one embodiment, wherein at least one end of a TSV serves as a bonding surface having a non-uniform surface.

[0023] Figures 7 to 13 A cross-section of an example substrate is shown with at least one end of a TSV as a bonding surface, illustrating example backside processing of the substrate, according to one embodiment.

[0024] Fig.14 A diagram showing example TSVs for thermal management of a die according to various embodiments.

[0025] Fig.15 is a text flow chart illustrating an example process for forming a microelectronic assembly to reduce or eliminate delamination of bonded substrates, according to one embodiment. Summary of the invention

[0026] Representative techniques and devices are disclosed, including process steps for preparing various microelectronic devices for bonding, such as for direct bonding without the need for adhesives. In various embodiments, techniques can be used to mitigate the possibility of delamination due to metal expansion, particularly when TSVs or bonding pads above the TSVs are present at the bonding surface of one or both devices to be bonded. For example, in one embodiment, the TSVs can extend partially or completely through the substrate of the device, and at least one end of the TSV is exposed at the bonding surface of the device. For example, the exposed end of the TSV is prepared and used as a bonding surface or in place of a bonding pad for the device.

[0027] When a surface preparation process such as CMP is used to prepare the bonding surface of the substrate, the exposed metal end of the TSV at the bonding surface may become recessed relative to the dielectric due to the softer material of the TSV relative to the dielectric material. A TSV of a larger diameter may become recessed to a greater extent (e.g., a deeper recess) than a TSV of a smaller diameter. In such an embodiment, the recessing of the end surface of the TSV provides space for metal expansion of the TSV during the heat anneal, which can reduce or eliminate delamination that may otherwise occur.

[0028] In various implementations, an example process includes providing a conductive via through a first substrate having a first bonding surface. The conductive via extends at least partially through the first substrate from the first bonding surface. The process includes exposing the conductive via from a surface opposite the first bonding surface, and forming a second bonding surface, wherein the conductive via is recessed at or relative to the second bonding surface.

[0029] In various embodiments, the process includes reducing or eliminating delamination of bonded microelectronic components by selecting conductive vias and using at least one end of the conductive vias as a bonding contact surface for direct bonding (eg, DBI).

[0030] Additionally or alternatively, the back side of the first substrate may also be processed for bonding.One or more insulating layers of preselected materials may be deposited on the back side of the first substrate to provide stress relief when the back side of the first substrate is to be directly bonded.

[0031] In addition, the conductive vias in the first substrate and other conductive vias can be used to conduct or transfer heat within the first substrate, and / or conduct or transfer heat away from the first substrate. In some implementations, the heat transfer conductive vias can extend partially or completely through the thickness of the first substrate and can include a thermally conductive barrier layer. In such examples, the barrier layer that is typically used around the conductive vias and tends to be thermally insulating can be replaced by a thermally conductive layer. In various implementations, some conductive vias can be used for signal transmission and heat transfer.

[0032] In one embodiment, a microelectronic assembly includes a first substrate having a front side and a back side, wherein the back side has a bonding surface including a non-conductive bonding layer and a conductive via. A second substrate has a front side and a back side, and the front side includes a non-conductive bonding layer and a conductive feature. The front side of the second substrate is directly bonded to the back side of the first substrate so that the conductive pad contacts the conductive feature. The exposed end of the conductive via includes a contact surface suitable for direct metal-to-metal bonding without intervening materials.

[0033] Various specific embodiments and devices are discussed with reference to electrical and electronic components and varying carriers. Although specific components (i.e., bare die, wafer, integrated circuit (IC) chip bare die, substrate, etc.) are mentioned, this is not intended to be limiting, but for ease of discussion and illustration. The techniques and devices discussed with reference to wafers, bare die, substrates, etc. are applicable to any type or number of electronic components, circuits (e.g., integrated circuits (ICs), hybrid circuits, ASICs, memory devices, processors, etc.), grouped components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), etc., which can be coupled to each other, to external circuits, systems, carriers, etc. Each of these different components, circuits, groups, packages, structures, etc. can be collectively referred to as "microelectronic components". For simplicity, unless otherwise specified, a component that is joined to another component will be referred to as a "bare die" herein.

[0034] This summary of the invention is not intended to give a complete description. The implementation is explained in more detail below using multiple examples. Although various implementations and examples are discussed here and below, additional implementations and examples are possible by combining the features and elements of each implementation and example.

[0035] Specific implementation method

[0036] Overview

[0037] refer to Figure 1A (cross-sectional profiles shown) and Figure 1B (Top view shown), patterned metal and oxide layers are often used as hybrid bonds, or The surface layer is provided on a die, wafer or other substrate (hereinafter referred to as "die 102"). A representative device die 102 can be formed using various techniques to include a base substrate 104 and one or more insulating or dielectric layers 106. The base substrate 104 can be composed of silicon, germanium, glass, quartz, a dielectric surface, a direct indirect bandgap semiconductor material, or an indirect bandgap semiconductor material or layer, or other suitable material. The insulating layer 106 is deposited or formed on the substrate 104 and can be composed of an inorganic dielectric material layer, such as an oxide, nitride, oxynitride, oxycarbide, carbide, carbonitride, diamond, diamond-like material, glass, ceramic, glass-ceramic, etc.

[0038] The bonding surface 108 of the device wafer 102 may include conductive features, such as contact pads 110, traces 112, and other interconnect structures, which are embedded, for example, in the insulating layer 106 and arranged so that the conductive features 110 from the corresponding bonding surfaces 108 of the opposing devices can be mated and coupled (if desired) during bonding. The coupled conductive features 110 can form a continuous conductive interconnect (for signal, power, etc.) between the stacked devices.

[0039] A damascene process (or similar) may be used to form embedded conductive features 110 in insulating layer 106. Conductive features 110 may be composed of metal (e.g., copper, etc.) or other conductive materials or combinations of materials, and include structures, traces, pads, patterns, etc. In some examples, prior to depositing the material for conductive features 110, a barrier layer may be deposited in a cavity for conductive features 110 such that the barrier layer is disposed between conductive features 110 and insulating layer 106. The barrier layer may be composed of, for example, tantalum or another conductive material to prevent or reduce diffusion of the material of conductive features 110 into insulating layer 106. After forming conductive features 110, the exposed surface of device wafer 102, including insulating layer 106 and conductive features 110, may be planarized (e.g., via CMP) to form a flat bonding surface 108.

[0040] Forming the bonding surface 108 includes machining the surface 108 to meet the dielectric roughness specification and the metal layer (e.g., copper, etc.) recess specification to prepare the surface 108 for direct bonding. In other words, the bonding surface 108 is formed to be as flat and smooth as possible with very small surface topography variations. Various conventional processes such as chemical mechanical polishing (CMP), dry etching, or wet etching can be used to achieve low surface roughness. These processes provide a flat, smooth surface 108 that results in reliable bonding.

[0041] In the case of a double-sided die 102, a patterned metal and insulating layer 106 with prepared bonding surfaces 108 may be provided on both sides of the die 102. The insulating layer 106 is typically highly planar (typically, roughness to the nanometer level), with the metal layer (e.g., embedded conductive features 110) at or just below the bonding surface 108. Typically, the amount of recess below the surface 108 of the insulating layer 106 is typically determined by dimensional tolerances, specifications, or physical limitations. The bonding surface 108 is typically prepared using a chemical mechanical polishing (CMP) step and / or other preparation steps for direct bonding with another die, wafer, or other substrate.

[0042] Some embedded conductive features or interconnect structures may include metal pads 110 or conductive traces 112 that extend partially into the dielectric substrate 106 below the prepared surface 108. For example, some patterned metal (e.g., copper) features 110 or 112 may be approximately 0.5 microns to 2 microns thick. The metal of these features 110 or 112 may expand during annealing as the metal is heated. Other conductive interconnect structures may include metal (e.g., copper) through-silicon vias (TSVs) 114 and the like that extend perpendicular to the bonding surface 108, partially or completely through the substrate 102, and include a large amount of metal. For example, depending on the thickness of the substrate 102, the TSVs 114 may extend approximately 50 microns. The metal of the TSVs 114 may also expand when heated. The pads 110 and / or traces 112 may or may not be electrically coupled to the TSVs 114, such as Figure 1A shown.

[0043] refer to Figure 2 , die 102 may be directly bonded to other die 102 having metal pads 110, traces 112, and / or TSVs 114, for example, without adhesive. If metal pads 110 are positioned above (overlapping and physically and electrically coupled to) TSVs 114, expansion of the TSV 114 metal may contribute to expansion of the pad 110 metal. In some cases, the combined metal expansion may result in local delamination 202 of the bonding surface at the location of the TSV 114 (or TSV 114 / pad 110 combination) as the expanded metal rises above the bonding surface 108. For example, the expanded metal may separate the bonded dielectric surfaces 108 of the stacked die 102.

[0044] Example Embodiments

[0045] refer to Figures 3A to 6 In various embodiments, techniques may be employed to mitigate the possibility of delamination due to metal expansion. For example, in one embodiment, Figure 3A and Figure 3B As shown in , the TSV 114 can extend through the base layer 104 of the die 102, and through one or more insulating layers 106, to at least one bonding surface 108. The end 302 (or both ends 302) of the TSV 114 can be exposed at the (multiple) bonding surface 108 of the die 102, and used as a contact surface for direct bonding (e.g., DBI). In other words, the contact surface 302 of the TSV can be exposed at the bonding surface through the dielectric layer 106, prepared (e.g., planarized, etc.), and can be used instead of a direct bonding pad (rather than a contact pad 110).

[0046] refer to Figure 4 In various implementations, when the die 102 is thermally annealed and the metal of the TSV 114 and the contact pad 110 expand, using the end surface 302 of the TSV 114 as the bonding surface can reduce or eliminate delamination of the bonded die 102. In this implementation, based on the volume of the TSV 114, the metal expansion of the TSV 114 can be taken into account. Therefore, the predetermined recess "d" (e.g., as shown in FIG. 1 ) in the end surface 302 of the TSV 114 is Figure 5 ) may be sufficient to provide space for material expansion of the TSV 114 .

[0047] In various embodiments, the TSV 114 used as a direct bonding contact structure may have a diameter that may be larger or smaller by a preselected amount than other TSVs 114 disposed elsewhere within the die 102. In one embodiment, the size of the TSV 114 is selected or formed by estimating the amount that the material of the TSV 114 will expand when heated to a preselected temperature (-300°) based on the volume of the material of the TSV 114 and the coefficient of thermal expansion (CTE) of the material of the TSV 114 and predicting the amount that the material of the TSV 114 will expand when heated to the preselected temperature.

[0048] refer to Figure 5 In one embodiment, the end 302 of the TSV 114 is planarized along with the bonding surface 108 of the dielectric layer 106, including recessing the end 302 of the TSV 114 to have a predetermined recess depth (“d”) relative to the bonding surface 108 based on the expansion of the material of the TSV 114 at a predetermined temperature. In other words, the recess depth is determined based on the volume of the material of the TSV 114 and the coefficient of thermal expansion (CTE) of the material of the TSV 114.

[0049] In one embodiment, the ends 302 of the TSVs 114 may be selectively etched (via acid etching, plasma oxidation, etc.) to provide a desired recess depth "d" (to accommodate predicted metal expansion). Figure 6 As shown in , the end 302 of the corresponding TSV 114 can be selected, formed or processed to have a non-uniform top surface as an expansion buffer. Figure 6 , the end surface 302 of the TSV 114 may be formed or selectively etched to be rounded, hemispherical, convex, concave, irregular, or otherwise non-planar to allow additional space 602 for material expansion.

[0050] The additional space 602 may be determined and formed based on the amount that the material of the TSV 114 will expand when heated. In various implementations, the end surface 302 of the TSV 114 may be formed to be non-uniform during deposition, or the end surface 302 of the TSV 114 may be etched, ground, polished, or otherwise made uneven after forming the TSV 114. In some cases, the end surface 302 of the TSV 114 may be made uneven during CMP of the bonding surface 108.

[0051] Additionally or alternatively, the dielectric 106 at the bonding surface 108 around the TSV 114 can be formed or shaped to allow space for metal expansion of the TSV 114. In one example, a CMP process can be used to shape the surface 108 of the dielectric 106 around the TSV 114, or in other examples, other processes can be used so that the dielectric 106 around the TSV 114 includes a recess or other gap that provides space for metal expansion. In one embodiment, the dielectric 106 can be recessed (e.g., using CMP) when the bonding surface 108 is prepared. In this embodiment, the TSV 114 and the dielectric 106 can be recessed at the same time (but at different rates). For example, the process can form corrosion in the dielectric 106 around the edge of the TSV 114 while recessing the metal TSV 114.

[0052] In various embodiments, TSV 114 is composed of copper, copper alloys, etc. In other embodiments, the material of TSV 114 can be varied to control metal expansion and potential delamination. For example, in some embodiments, TSV 114 can be composed of different conductive materials, which may have a lower CTE. In some embodiments, TSV 114 can be composed of a different conductive material (with a lower CTE) than contact pad 110. For example, TSV 114 can be composed of tungsten, alloys, etc.

[0053] In other embodiments, the volume of material of TSV 114 may be varied to control metal expansion and the likelihood of delamination. For example, in some embodiments, TSV 114 with a preselected material volume (e.g., a smaller material volume) may be used when allowed within design specifications. The preselection of the volume of TSV 114 may be based on the expected material expansion of TSV 114.

[0054] Return to reference Figure 4, after preparing the bonding surface 108 (e.g., by CMP), the die can be directly bonded to other dies 102, for example, without adhesive, the other die 102 having metal pads 110, traces 112, and / or TSVs 114. When the mating TSVs 114 of the opposing dies 102 are bonded to form a single conductive interconnect, the material of the TSVs 114 expands during the heated annealing. However, when sufficient predetermined recesses are provided as discussed, the metal expansion does not result in delamination of the bonding surface, because the expanded metal of the TSVs 114 does not exceed the space provided by the recesses at the end surfaces 302 of the TSVs 114.

[0055] For example, if the end surfaces 302 of the TSVs 114 are sufficiently recessed, the expanded metal of the TSVs 114 will fill the recess(es) without separating the bonded dielectric surfaces 108 of the stacked dies 102. When the bonding surfaces 108 of the dies 102 are prepared using a surface preparation process such as CMP, the TSVs 114 exposed at the bonding surfaces 108 may become recessed relative to the dielectric 106 (intentionally or unintentionally) due to the softness of the TSVs 114 (e.g., which may include copper) relative to the dielectric 106 (e.g., which may include oxide).

[0056] In various embodiments, the amount of recessing of the TSVs 114 may be predictable based on the surface preparation techniques used (e.g., the chemical composition used, the speed of the polishing equipment, etc.), the materials of the dielectric layer 106 and the TSVs 114, the spacing or density of the TSVs 114 (and the metal pads 110), and the size (e.g., area or diameter) of the TSVs 114. In embodiments, based on the desired recessing and the expected metal expansion of the TSVs 114, the area or diameter of the TSVs 114 (e.g., for a particular material) may be selected to avoid delamination of the bonded die 102. For example, in some cases, when increased recessing is desired, a larger diameter TSV 114 may be selected. This technique may result in reduced or eliminated delamination, as well as reliable mechanical coupling of the dielectric 106 and metal structures (e.g., TSVs 114) at the bonding surface 108, and reliable electrical continuity of the bonded metal structures.

[0057] Additional Embodiments

[0058] Figures 7 to 13An example of backside die 102 processing according to various embodiments is illustrated. In some implementations, where the dies 102 are stacked and directly bonded without an adhesive, the backside 702 of the die 102 may receive a different preparation than the topside bonding surface 108 when the backside 702 is prepared for direct bonding. Instead of forming the dielectric layer 106 on the backside 702 of the die 102, the backside 702 may be prepared differently to reduce process steps, reduce manufacturing costs, or for other reasons.

[0059] In one implementation, the backside 702 is prepared so that the TSVs 114 are exposed to be used as contact surfaces 302 for bonding to a conductive pad, interconnect, or other conductive bonding surface. The preparation may include depositing a thin layer of insulating material, and planarizing (e.g., via CMP) the backside 702 (which may include planarizing the insulating material and / or the base substrate 104) to expose the TSVs 114. However, in some cases, expansion of the material of the TSVs 114 during the heat anneal may cause the insulating material and / or the substrate 104 to become damaged.

[0060] In one embodiment, Figures 7 to 13 As shown in , one or more layers of material may be deposited on the back side 702 to act as stress relief to prevent or eliminate damage to the substrate 104 and the die 102. The layers of material may be planarized and otherwise prepared as bonding surfaces on the back side 702 of the die 102.

[0061] As in Figure 7 As shown in FIG. 1 , TSV 114 is disposed within die 102, lateral to bonding surface 108 of die 102. TSV 114 may initially extend beyond the surface of backside 702 of die 102. Diffusion barrier and oxide liner 704 surround TSV 114 to prevent diffusion of metal (e.g., copper) of TSV 114 into the material (e.g., silicon) of base substrate 104. In one embodiment, as shown in FIG. Figure 7 As shown therein, another diffusion barrier 706 is deposited on the surface of the backside 702 of the die 102. In one example, the diffusion barrier 706 includes a dielectric such as a nitride.

[0062] In various embodiments, one or more insulating layers are then deposited onto the backside 702 of the die 102 to prevent damage to the die 102 when the material of the TSV 114 expands. For example, a first layer 708 including a first low temperature dielectric such as an oxide may be deposited over the backside 702, including over the diffusion layer 706. The first oxide layer 708 may include a low temperature oxide bonding layer. For example, Figure 7Such a scenario is shown and includes contact pads 110 formed on the front side bonding surface 108 over TSVs 114 .

[0063] As in Figure 8 As shown, the back side 702 (including one or more insulating layers 708) is planarized (e.g., via CMP) to form a flat, smooth bonding surface for direct bonding. The remaining dielectric layer 708 can help with warpage control, balancing the front side of the die 102. The TSVs 114 are exposed by planarization, including the exposed contact surfaces 302 of the TSVs 114.

[0064] It is worth noting that when some types of low temperature oxides (e.g., silicon oxide, etc.) are used, the oxide may be less rigid and the TSV 114 may be prone to cracking during planarization. Once planarized, the oxide is more stable. When other types of low temperature oxides (e.g., TEOS, etc.) are used, the oxide may give better support to the TSV 114, but the oxide may also relax, making the area around the TSV 114 higher than the bonding surface (~1 to 10nm), which can cause direct bonding (e.g., DBI) problems. As a solution to this problem, such as Figure 7 As shown in FIG. 7 , a DBI bonding layer (eg, layer 708 ) is added on top of the TSVs 114 .

[0065] exist Figure 8 A second die 802 that is similar or identical to die 102 is also shown in dashed lines. Figure 8 The illustration of shows one example of a front-to-back direct bonding arrangement (without adhesive) in which the second die 802 is bonded (dielectric-to-dielectric) to the backside 702 of the first die 102 at the front side 108 of the second die 802. As shown, in this arrangement, the surface 302 of the exposed TSV 114 at the backside 702 of the first die 102 is bonded (metal-to-metal) to the conductive pad 110 at the second die 802. In alternative embodiments, the die 102 and the die 802 can be bonded front-to-front, or back-to-back.

[0066] In one embodiment, Figures 9 and 10 As shown in , multiple layers can be added to the back side 702 to reduce metal expansion stress at the TSV 114 and form a back side 702 bonding surface for the die 102. Fig. 9As shown in FIG. 1 , after depositing the first low temperature oxide layer 708 (which, in some implementations, also includes a bonding layer), the second dielectric layer 902 (which may include a low temperature oxide) may be deposited on the first layer 708. No barrier or bonding layer is required between the two oxide layers (708 and 902). In various implementations, the first layer 708 and the second layer 902 are composed of similar or identical (with varying thicknesses) materials. In other implementations, the first layer 708 and the second layer 902 are composed of different materials. The second oxide layer 902 may have residual stress properties similar to or different from those of the first layer 708 (e.g., the first layer 708 may be compressive and the second layer 902 may be tensile, or vice versa, or both the layer 708 and the layer 902 may be compressive or tensile with similar or different values). In alternative implementations, additional insulating layers may also be deposited on the first layer 708 and the second layer 902.

[0067] As in Fig.10 As shown, layer 708 and layer 902 are planarized (eg, CMP), exposing TSV 114 and end surface 302, which may function in place of a bond pad. In one implementation, a portion of second layer 902 may remain on die 102 for warpage control.

[0068] In some embodiments, Fig.11 As shown in , the end surface 302 at the back side 702 can be formed to have an uneven or non-uniform surface topography. For example, the end surface 302 can be selected, formed or processed to have a non-uniform surface topography as an expansion buffer. For example, referring to Fig.11 The end surface 302 of the TSV 114 may be formed or selectively etched to be rounded, hemispherical, convex, concave, irregular, or non-planar in some way to allow additional space 1102 for material expansion.

[0069] The additional space 1102 may be determined and formed based on a prediction of the amount that the material of the TSV 114 will expand when heated. In various implementations, the end surface 302 of the TSV 114 may be formed to be non-uniform during deposition, or may be etched, ground, polished, or otherwise made non-uniform after forming the TSV 114. In some cases, the end surface 302 of the TSV 114 may be made non-uniform during CMP of the backside 702 bonding surface.

[0070] Figure 12 to Figure 13 1 illustrates an example of processing the back side 702 of the die 102 when the offset contact pads 110 are disposed on the front side 108 according to various embodiments. Fig.12 and Fig.13, the offset contact pad 110 may be coupled to the TSV 114 using one or more traces 112, etc. As discussed above, after the diffusion barrier layer 706 is deposited over the backside 702, one or more oxide stressor layers (e.g., such as layer 708) may be deposited on the backside 702. When the stressor layer 708 is the last layer on the backside 702, the stressor layer 708 may also include a direct bonding layer.

[0071] like Fig.13 As shown in FIG, layer 708 is planarized to form a bonding surface and expose TSV 114 with a smooth contact surface 302. In an alternative embodiment, multiple stress layers may be deposited and planarized at backside 702 in preparation for direct bonding.

[0072] In other embodiments, alternative techniques may be used to reduce or eliminate delamination due to metal feature expansion and still remain within the scope of the present disclosure.

[0073] In various embodiments, such as in Fig.14 As shown, in addition to or in lieu of electrical signals, one or more of the TSVs 114 of a set of stacked dies 102 may be used to conduct heat. For example, in some cases, it may not be practical or possible to attach a heat sink (or other heat transfer device) to a die 102 in a set of stacked dies 102 to mitigate the heat generated by the die 102. In such cases, other techniques may be sought to transfer the heat (if desired).

[0074] In an embodiment, as in Fig.14 As shown in FIG. 1 , various configurations of TSVs 114 (including TSVs 114 that extend partially or completely through the die 102) may be employed to conduct heat away from the die 102 (or away from heat generating portions of the die 102). The TSVs 114 of one die 102 may be used in conjunction with the TSVs 114, contact pads 110, traces 112, etc., of a second die 102 to accomplish heat transfer from one die 102 to other die 102, etc. For high performance thermal conductivity, the TSVs 114 of the first die 102 may be directly bonded (e.g., DBI) to the TSVs 114, contact pads 110, traces 112, etc., of the second die 102.

[0075] In one implementation, some of the TSVs 114, contact pads 110, traces 112, etc. are floating or "dummy" structures that can be used for heat transfer. These structures can conduct heat from the high-power die 102 to another die 102 or substrate (as needed). The dummy contact pads 110 can be coupled to the via last or via mid thermal TSVs 114 for heat conduction.

[0076] In an embodiment, diffusion barrier layer 704 surrounds TSV 114 and may be thermally confining or thermally blocking, diffusion barrier layer 704 may be replaced by a diffusion barrier of a different material having a certain thermal conductivity, such as a metal or alloy barrier, etc.

[0077] Example Process

[0078] Fig.15 A representative process 1500 is illustrated for preparing various microelectronic components (e.g., such as die 102) for bonding (such as for direct bonding without adhesives) while reducing or eliminating the possibility of delamination due to metal expansion of embedded structures at the bonding surface. For example, through silicon vias (TSVs) at the bonding surface may cause delamination, particularly when coupled to contact pads, because the material of the TSVs and contact pads expands during heat annealing. The process is described with reference to FIGS. 1 to 3. Fig.14 .

[0079] The order in which the process is described is not intended to be construed as limiting, and any number of the described process blocks in the process may be combined in any order to implement the process or an alternative process. Additionally, individual blocks may be deleted from the process without departing from the spirit and scope of the subject matter described herein. In addition, the process may be implemented in any suitable hardware, software, firmware, or combination thereof without departing from the scope of the subject matter described herein. In alternative implementations, other technologies may be included in the process in various combinations and are still within the scope of the present disclosure.

[0080] In various implementations, a die, wafer, or other substrate ("substrate") is formed using various techniques to include a base substrate and one or more dielectric layers. In one implementation, at block 1502, process 1500 includes providing a conductive via (e.g., such as TSV 114) through a first substrate having a first bonding surface (e.g., such as bonding surface 108), the conductive via at least partially passing through the first substrate from the first bonding surface. In one implementation, the first via extends at least partially through the first substrate perpendicular to the first bonding surface. In one example, the first via extends through the first substrate to one or both surfaces of the first substrate.

[0081] At block 1504, the process includes exposing the conductive via from a surface opposite the first bonding surface. In one implementation, the process includes forming a recess in the exposed end of the conductive via, the recess extending to a predetermined depth below the second bonding surface. For example, during the bonding process, the recess compensates for expansion of the conductive via.

[0082] In one example, the process includes forming the exposed end of the conductive via such that an oblique gap exists between the conductive via and the second bonding surface. In various examples, the non-uniform topography creates space for via metal expansion during heat annealing.

[0083] At block 1506 , the process includes forming a second bonding surface having a conductive via recessed at or relative to the second bonding surface.

[0084] In one implementation, the process includes providing a second substrate and directly bonding the second bonding surface of the first substrate to the second substrate without an intervening adhesive. In one implementation, the process includes directly bonding the first substrate to the second substrate using a direct dielectric-to-dielectric non-adhesive bonding technique at the bonding surface of the first substrate.

[0085] In one implementation, the second substrate further includes a conductive via extending at least partially through the second substrate. In another implementation, the second substrate further includes a pad on the conductive via of the second substrate, the pad contacting the conductive via of the first substrate. In one embodiment, the conductive via of the first substrate is substantially aligned with the conductive via of the second substrate.

[0086] In an alternative implementation, the conductive via is configured to remove heat from the first substrate.

[0087] In various embodiments, some process steps may be modified or eliminated compared to those described herein.

[0088] The techniques, components and devices described herein are not limited to Figures 1A to 15 , and may be applied to other designs, types, devices, and configurations including those with other electronic components without departing from the scope of the present disclosure. In some cases, additional or alternative components, techniques, sequences, or processes may be used to implement the techniques described herein. Furthermore, the components and / or techniques may be arranged and / or combined in various combinations while producing similar or substantially the same results.

[0089] in conclusion

[0090] Although the implementations of the present disclosure have been described in language specific to structural features and / or methodological actions, it should be understood that these implementations are not necessarily limited to the specific features or actions described. Instead, the specific features and actions are disclosed as representative forms of implementing example devices and techniques.

Claims

1. A method of forming a microelectronic assembly, comprising: providing a first conductive via through a first substrate, the first substrate having a base layer and a first bonding surface, the first conductive via extending at least partially through the first substrate and having a buried first end; exposing the first end of the first conductive via from a surface opposite the first bonding surface; forming a second bonding surface at the surface opposite to the first bonding surface, the forming the second bonding surface comprising: forming a non-conductive surface at least partially defined by a non-conductive bonding layer, the non-conductive bonding layer having a dielectric layer and an insulator on the dielectric layer; polishing the non-conductive surface; and recessing an exposed first end of the first conductive via, wherein the dielectric layer extends along a portion of the conductive via and extends over the base layer; providing a second substrate including a second conductive via extending at least partially through the second substrate and a pad electrically coupled to the second conductive via; and The second bonding surface of the first substrate is bonded to the second substrate such that the second conductive via contacts the first conductive via.

2. The method of forming a microelectronic assembly of claim 1, wherein the recess compensates for expansion of the conductive via during a bonding process.

3. The method of forming a microelectronic assembly of claim 1 , wherein bonding the second bonding surface of the first substrate to the second substrate comprises: The second bonding surface of the first substrate is directly bonded to the second substrate without an adhesive interposed therebetween. 4 . The method of forming a microelectronic assembly as recited in claim 1 , wherein the pad is over the second conductive via, the pad contacting the first conductive via of the first substrate.

5. The method of forming a microelectronic assembly as claimed in claim 1, wherein the conductive vias of the first substrate are substantially aligned with the conductive vias of the second substrate.

6. The method of forming a microelectronic assembly according to claim 1, further comprising: The exposed end of the conductive via is formed such that an inclined gap exists between the conductive via and the second bonding surface.

7. A method of forming a microelectronic assembly, comprising: providing a first substrate having a base layer, a front side, and a back side, the back side having a bonding surface, the bonding surface comprising a non-conductive bonding layer, and an exposed conductive via recessed from the non-conductive bonding layer, the non-conductive bonding layer comprising a dielectric layer and an insulator on the dielectric layer, the dielectric layer extending along a portion of the conductive via and extending over the base layer; providing a second substrate having a front side and a back side, the front side including a non-conductive bonding layer and exposed pads; coupling the front side of the second substrate to the back side of the first substrate by contacting the non-conductive bonding layers of the first and second substrates; as well as coupling the exposed pad to the exposed conductive via by a thermal treatment step, Before coupling, the exposed pad is recessed below the non-conductive bonding layer of the second substrate to accommodate thermal expansion of the exposed pad and the conductive via.

8. A method of forming a microelectronic assembly as claimed in claim 7, wherein the non-conductive bonding layer of the first substrate comprises a diffusion barrier and an insulator on the diffusion layer, the insulator being activated as a bonding surface.

9. A method of forming a microelectronic assembly, comprising: providing a first substrate having a base layer, a front side surface, and a back side surface, the back side surface including a first non-conductive bonding layer and an exposed conductive via, the first non-conductive bonding layer including a dielectric layer and an insulator on the dielectric layer, the dielectric layer extending along a portion of the conductive via and extending over the base layer; providing a second substrate having a backside surface including a second non-conductive bonding layer and exposed conductive vias; coupling the second substrate to the first substrate by contacting the first non-conductive bonding layer and the second non-conductive bonding layer; as well as coupling the exposed conductive via of the first substrate and the exposed conductive via of the second substrate; as well as Heat is transferred from the first substrate to the second substrate via the conductive vias of the first substrate and the conductive vias of the second substrate.

10. The method of forming a microelectronic assembly as claimed in claim 9, wherein the via is configured to carry an electrical signal to or from an electrical device in the first substrate or the second substrate.

11. A microelectronic assembly comprising: a first substrate having a bonding surface, the bonding surface comprising a first non-conductive bonding layer and a first conductive via, the first conductive via being electrically insulated from the first substrate; as well as a second substrate including a second non-conductive bonding layer and a conductive pad coupled to a second conductive via, the second conductive via being electrically insulated from the second substrate and extending at least partially through the second substrate; wherein the second substrate is directly bonded to the first substrate such that the first conductive via contacts the conductive pad to create a signal path from the first conductive via through the second conductive via, and The conductive pad is offset from the second conductive via such that no portion of the second conductive via is disposed within a perimeter of the conductive pad in a plan view.

12. The microelectronic assembly of claim 11 , further comprising: One or more dielectric stress relief layers at the back side of the first substrate.

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