Method, apparatus and system for handling non-posted memory write transactions in a fabric

Abstract

In one embodiment, a system on a chip includes a first endpoint for issuing non-posted memory write transactions to a memory, and a peripheral component interconnect (PCI) based structure including control logic for directing the non-posted memory write transactions to the memory, receiving completions of the non-posted memory write transactions from the memory, and routing the completions to the first endpoint. Other embodiments are described and claimed.

Description

[0001] This application is a divisional application. The original application was a patent application submitted to the China Patent Office on May 28, 2019 (the international application date is November 20, 2017), with application number 201780073628.6, and the name of the invention is "Method, device and system for processing non-posted memory write transactions in a structure". Technical Field

[0002] Embodiments relate to communications, and more particularly, to communications in integrated circuits. Background Art

[0003] Mainstream processor chips in high-performance and low-power segments are increasingly integrating additional functions such as graphics, display engines, security engines, etc. Due to the different requirements of servers, desktops, mobile phones, embedded, ultra-mobile and mobile Internet device parts, such designs are highly segmented. Different markets seek to use a single-chip system-on-chip (SoC) solution that combines at least some of the processor core, memory controller, input / output controller and other segment-specific acceleration elements on a single chip. However, due to the difficulty in integrating different intellectual property (IP) blocks on a single die, the design that gathers these features appears very slowly. This is especially true because IP modules can have various requirements and design uniqueness, and may require many dedicated lines, communication protocols, etc. to enable them to be incorporated into SoCs. As a result, each SoC or other advanced semiconductor device developed requires a lot of design complexity and customization to merge different IP blocks into a single device. This is so because it is usually necessary to redesign a given IP block to adapt to the interface and signaling requirements of a given SoC.

[0004] Many computer systems and even integrated circuits within such systems include Peripheral Component Interconnect (PCI) technology, which provides rules for transactional communication and various protocols for handling data flows within the system. In a PCI ordered interconnect, producer-consumer (P / C) flows are handled using some well-defined semantics. Most notably, these semantics include: (1) writes from producers are always delivered, in that they are considered complete when sent by the source without receiving an explicit acknowledgment (also known as fire and forget transactions); and (2) the system ensures that writes have been processed to a global observation point before the consumer uses the data. These semantics implement the functional correctness of the PCI ordered interconnect. While this arrangement is effective, difficulties arise when non-PCI-based devices are incorporated into a system with a PCI ordered interconnect, as considerable complexity can arise in ensuring that these semantics are met. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a basic interconnect architecture according to an embodiment of the present invention.

[0006] Figure 2 is a block diagram of further details of an interconnect architecture according to an embodiment of the present invention.

[0007] Figure 3 is a high-level block diagram of a SoC according to an embodiment of the present invention.

[0008] Figure 4 is a block diagram of a system according to another embodiment of the present invention.

[0009] Figure 5 is a block diagram of a sideband interconnect according to an embodiment of the present invention.

[0010] Figure 6 is a block diagram of details of signaling that may be used for a sideband interface according to an embodiment of the present invention.

[0011] Figure 7 is a flow chart of a method according to an embodiment of the present invention.

[0012] Figure 8 is a flow chart of a method according to another embodiment of the present invention.

[0013] Fig. 9 is a block diagram of an exemplary system in which embodiments may be used.

[0014] Fig.10 is a block diagram of a representative computer system.

[0015] Fig.11 is a block diagram of a system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In various embodiments, integrated circuits such as processors, systems on chips (SoCs), and other integrated circuits that implement communication technologies based on protocols based on peripheral component interconnects (PCIs) are configured to implement additional transaction mechanisms, namely non-posted memory write transactions in these devices. This is true despite the fact that there is no PCI specification that supports the concept of non-posted memory write transactions. Note that in the embodiments described herein, certain fabrics and devices such as endpoints within the SoC may be configured to accommodate and handle these non-posted memory write transactions. However, many other components (such as other fabric instances, endpoints, and other devices of traditional types) may not be configured to handle these transactions. It should be understood that non-posted memory write transactions are transactions that are sent by a source and sent to a target memory or other storage device that the source considers to be incomplete until the source receives an acknowledgment, such as in the form of a completion that does not include data, indicating that the data of the transaction has been globally observed.

[0017] Note that, as used herein, the terms "PCI", "PCI-based" or "PCI-compatible" refer to components such as devices, structures, endpoints, etc. that comply with one or more PCI specifications, including, for example, PCI Local Bus Specification Version 3.0 (February 3, 2004) and / or PCI-Express (PCIe) Base Specification Version 3.1a (December 7, 2015), and transaction ordering rules that support such PCI specifications. More specifically, such PCI-compliant structures are therefore "PCI-ordered structures". Accordingly, as used herein, the terms "non-PCI", "non-PCI-based" or "non-PCI-compliant" are used to refer to components that do not comply with these specifications and do not follow the ordering rules of such specifications. Therefore, more specifically, these non-PCI structures are not PCI-ordered structures. As an example, non-PCI devices may include devices designed to comply with other communication protocols, including Advanced Microcontroller Bus Architecture (AMBA) type protocols, such as Advanced eXtensible Interface (AXI), Open Core Protocol (OCP) or other proprietary or non-proprietary protocols. For example, fabrics from vendors such as Arteris and Sonics may be considered non-PCI fabrics.

[0018] In various embodiments, the PCI sorting system is configured to support P / C sorting across multiple channels by enabling non-posted write transaction types to be supported on the primary interface of the structure. Non-posted write transactions comply with all PCI sorting rules and provide explicit confirmation semantics (e.g., completion by no data) required for non-posted write transactions. Such non-posted write transactions provide the scalability of ensuring P / C correctness across all channels in the PCI sorting structure without any additional capabilities in the rest of the system. It is also understood that the non-posted memory transactions described herein are for bulk data writes. Such write transactions contrast with non-posted input / output writes (IOWr) and configuration writes (CfgWr) transactions. However, these other non-posted transactions are fundamentally written to different spaces (not memories) and are limited in size to a single double word (DW). In contrast, the memory transactions described herein can reach a full PCI maximum payload size of 1024DW.

[0019] By supporting non-posted write transaction semantics within the master interface of the structure, non-posted write transactions from non-PCI-based intellectual property (IP) logic can be directly mapped to non-posted writes on the master interface. If the non-PCI IP logic uses multiple channels, all such channels are mapped 1:1 on the master interface without any additional custom changes. Therefore, non-PCI-based IP logic can be natively integrated into the structure that supports non-posted writes. Non-posted write transactions can also simplify the P / C handshake of traditional PCI-compliant IP logic that uses multiple channels for quality of service (QoS). In some embodiments, supporting such non-posted write semantics in the structure simplifies the overall logic complexity by eliminating customized cross-channel handshake technology.

[0020] Embodiments may be used in many different types of systems. As an example, the embodiments described herein may be used in conjunction with semiconductor devices, such as processors or other semiconductor devices that may be fabricated on a single semiconductor die. In a particular embodiment, the device may be a system on a chip (SoC) or other advanced processor or chipset that includes various homogeneous and / or heterogeneous processing agents, as well as additional components such as network components, such as routers, controllers, bridging devices, devices, memory, etc.

[0021] Some embodiments can be used in semiconductor devices designed according to given specifications, such as the Integrated System-on-Chip Structure (IOSF) specification released by semiconductor manufacturers such as Intel Corporation to provide a standardized on-die interconnect protocol for connecting intellectual property (IP) blocks within a chip, including SoCs. Such IP blocks can be of various types, including general-purpose processors, such as in-order or out-of-order cores, fixed function units, graphics processors, IO controllers, display controllers, media processors, etc. By standardizing the interconnect protocol, a framework for widely using IP agents in different types of chips is thus implemented. Therefore, semiconductor manufacturers can not only effectively design different types of chips in a variety of customer groups, but also enable third parties to design logic such as IP agents to be included in these chips through specifications. In addition, by providing multiple options for many aspects of the interconnect protocol, the reuse of the design is effectively adapted. Although embodiments are described herein in conjunction with the IOSF specification, it should be understood that the scope of the present invention is not limited thereto, and the embodiments can be used in many different types of systems.

[0022] Reference now Figure 1 , shows a block diagram of a basic interconnection architecture according to an embodiment of the present invention. Figure 1As shown, system 10 may be part of a system on a chip or any other semiconductor device, such as a highly integrated processor complex or an integrated IO hub, and includes a fabric 20 that serves as an interconnect between various components. In the illustrated embodiment, these components include IP agents 30 and 40, which may be independent IP blocks to provide various functions, such as computing capabilities, graphics capabilities, media processing capabilities, etc. Thus, in one embodiment, these IP agents are IP blocks or logic devices having interfaces that comply with the IOSF specification. As further seen, fabric 20 is also interfaced with bridge 50. Although for ease of illustration, the fabric 20 is not illustrated in FIG. Figure 1 Not shown in the embodiment of FIG. 5 , it is understood that the bridge 50 may be used as an interface with other system components (eg, on the same chip or on one or more different chips).

[0023] As will be further described below, Figure 1 Each element shown in, i.e., the fabric, IP agent, and bridge may include one or more interfaces to handle the communication of various signals. These interfaces may be defined in accordance with the IOSF specification, which defines the signals for communication on these interfaces, the protocols for information exchange between agents, the arbitration and flow control mechanisms for initiating and managing information exchange, the address decoding and translation capabilities supported, the messaging for in-band or out-of-band communication, power management, testing, verification, and debugging support.

[0024] The IOSF specification includes three independent interfaces that can be provided for each agent, namely the main interface, the sideband message interface, and the testability and debugging interface (Design for Test (DFT), Design for Debug (DFD) interface). According to the IOSF specification, the agent can support any combination of these interfaces. Specifically, the agent can support 0-N main interfaces, 0-N sideband message interfaces, and an optional DFx interface. However, according to the specification, the agent must support at least one of these three interfaces.

[0025] Fabric 20 may be a hardware element that moves data between different agents. Note that the topology of fabric 20 will be product specific. As an example, the fabric may be implemented as a bus, a layered bus, a cascaded hub, etc. Referring now to Figure 2 , a block diagram showing further details of the interconnection architecture according to an embodiment of the present invention. Figure 2As shown, the IOSF specification defines three different structures, namely the main interface structure 112, the DFx structure 114 and the sideband structure 116. The main interface structure 112 is used for all in-band communications between agents and memory, for example, between a host processor (such as a central processing unit (CPU) or other processor) and an agent. The main interface structure 112 can also enable communication of peer transactions between agents and supported structures. All transaction types including memory, input and output (IO), configuration, and in-band messaging can be transmitted through the main interface structure 112. Therefore, the main interface structure can be used as a high-performance interface for data transmitted between peers and / or communication with upstream components.

[0026] In various embodiments, the main interface structure 112 implements a split transaction protocol to achieve maximum concurrency. That is, the protocol provides a request phase, an authorization phase, and a command and data phase. In various embodiments, the main interface structure 112 supports three basic request types: post-type, non-post-type, and completion. Typically, a post-type transaction is a transaction that is considered to be completed by the source when it is sent by the source, and the source does not receive completion or other confirmation messages about the transaction. An example of such a post-type transaction can be a write transaction. On the contrary, the source does not consider that a non-post-type transaction is completed until a return message (i.e., completion) is received. An example of a non-post-type transaction is a read transaction, in which the source agent requests to read data. Therefore, the completion message provides the requested data.

[0027] In addition, the main interface structure 112 supports the concept of different channels to provide a mechanism for independent data streams in the entire system. As will be further described, the main interface structure 112 itself can include a master interface for initiating transactions and a target interface for receiving transactions. The main master interface can also be subdivided into a request interface, a command interface, and a data interface. The request interface can be used to provide control of transaction commands and data movement. In various embodiments, the main interface structure 112 can support PCI sorting rules and enumeration.

[0028] Accordingly, the sideband interface structure 116 can be a standard mechanism for transmitting all out-of-band information. In this way, dedicated lines designed for a given implementation can be avoided, enhancing the ability to reuse IP between various chips. Therefore, compared with IP blocks that use dedicated lines to handle out-of-band communications such as status, interrupts, power management, fuse allocation, configuration shadows, test modes, etc., the sideband interface structure 116 according to the IOSF specification standardizes all out-of-band communications, promotes modularization of IP reuse between different designs and reduces its verification requirements. Typically, the sideband interface structure 116 can be used to transmit non-performance-critical information rather than for performance-critical data transmission (which can usually be transmitted through the main interface structure 112).

[0029] like Figure 2 As further shown in , IP agents 130, 140 and 150 may each include a corresponding main interface, sideband interface and DFx interface. However, as described above, in some embodiments, each agent need not include each of these interfaces, and a given IP agent may include only a single interface.

[0030] Using the IOSF specification, various types of chips with various functions can be designed. Figure 3 , shows a high-level block diagram of a SoC according to an embodiment of the present invention. Figure 3 As shown, SoC 200 may include various components, all of which may be integrated on a single semiconductor die to provide various processing capabilities at high speed and low power, consuming a relatively small amount of occupied area. Figure 3 As shown, SoC 200 includes multiple cores 2050-205 n In various embodiments, cores 205 may be relatively simple in-order cores or more complex out-of-order cores. Alternatively, there may be a combination of in-order and out-of-order cores in a single SoC. As seen, cores 205 may be interconnected via coherent interconnect 215, which is also coupled to cache memory 210, such as a shared last level cache (LLC). Although the scope of the present invention is not limited in this respect, in one embodiment, coherent interconnect 215 may be based on Quick Path Interconnect (QPI) available from Intel Corporation, Santa Clara, California. TM specification.

[0031] like Figure 3 As further seen in FIG. 1 , the coherent interconnect 215 can communicate with a fabric 250 via a bridge 220, which can be an IOSF fabric. The coherent interconnect 215 can also communicate with an off-chip memory (for ease of illustration) via an integrated memory controller 215. Figure 3 250).

[0032] like Figure 3 As further seen in FIG. 2 , various components may be coupled to structure 250 , including a content processing module (CPM) 240 , which may be used to perform various operations such as security processing, cryptographic functions, etc. Additionally, a display processor 245 may be part of a media processing pipeline that renders video for an associated display.

[0033] As further seen, structure 250 may be further coupled to IP proxy 255. Although for ease of use in Figure 3In the embodiment of FIG. 2 , only a single agent is shown, but it should be understood that multiple such agents are possible in different embodiments. In addition, in order to achieve communication with other on-chip devices, the structure 250 can also be connected to the PCIe TM Controller 260 communicates with Universal Serial Bus (USB) controller 265, both of which can communicate with various devices according to these protocols. Figure 3 In the embodiment shown is a bridge 270, which can be used to communicate with additional components of other protocols, such as OCP or AMBA protocols. Figure 3 These particular components are shown in the embodiment of the present invention, but it should be understood that the scope of the present invention is not limited in this manner and that additional or different components may be present in different embodiments.

[0034] Furthermore, it should be understood that although Figure 3 , but the embodiments may also be implemented in a system where multiple chips communicate with each other via non-IOSF interfaces. Figure 4 , which is a block diagram of a system according to another embodiment of the present invention. Figure 4 As shown, the system may include SoC 200', which may include similar to the above Figure 3 200', and an IOSF fabric 290. As can be seen, fabric 290 may also be coupled to various controllers that communicate with off-chip devices, including PCIe 400, PCIe 400, and PCIe 400. TM Controller 292 , USB controller 294 and bridge 296 .

[0035] As described above, in various embodiments, all out-of-band communications may be via the sideband messaging interface. Figure 5 , shows a block diagram of a sideband interconnection according to an embodiment of the present invention. Figure 5 As shown, the sideband interface system 175 includes a plurality of routers 180 and 190, which are connected in Figure 5180 is coupled to a plurality of endpoints 186a-186e, and a router 190 is coupled to a plurality of endpoints 196x-196z.

[0036] Reference now Figure 6 , a block diagram showing details of signaling that can be used for a sideband interface according to an embodiment of the present invention. Figure 6 , the interconnection between router 180 and endpoint 186 is shown. As can be seen, router 180 can include target interface 181 and host interface 182. Generally, target interface 181 can be configured to receive input signals, while host interface 182 can be configured to transmit output signals. As can be seen, endpoint 186 also includes host interface 187 and target interface 188.

[0037] Figure 6 Also shown are details of various signaling that may be used for the sideband interface, including credit information, placement information, message end signaling, and data. Specifically, credit updates may be transmitted over the sideband interface as non-delivered credit update signals (NPCUP) and delivered credit update signals (PCCUP). Additionally, placement signals (NPPUT and PCPUT) may be provided. Furthermore, an end of message (EOM) signal may be transmitted. Finally, data may be transmitted via payload packets, which, in one embodiment, may be implemented over a byte-wide communication channel. Although in Figure 6 The embodiments of the present invention are shown in this particular implementation, but the scope of the present invention is not limited in this regard. Whenever the credit placement signal is high, it means that credits are being returned. Whenever the placement signal is high, it means that the payload (e.g., data) signal is valid. Whenever placement and EOM are high at the same time, it means that the current payload is the last payload of the message. Note that the interface can "place" both data payloads and credits in the same clock cycle.

[0038] In one embodiment, non-posted write transaction types may include different addressing modes, including 32-bit address non-posted memory write requests (NPMWr32) and 64-bit address non-posted memory write requests (NPMWr64). These non-posted writes may be configured to use a non-posted stream request type and will return a single completion (CPL) with no data as a response.

[0039] In some embodiments, multiple outstanding non-posted write requests may be allowed. If any ordering is required between posted and non-posted writes, the agent may be configured to wait for all outstanding non-posted memory write requests to complete before issuing any posted write requests. This semantics ensures consistency of the written data because a posted write may override a non-posted write according to the ordering rules. Non-posted memory writes may follow the same ordering rules as any other non-posted request, and also follow the same rules as any other memory transaction.

[0040] In an embodiment, non-posted writes may only be sent from the root complex if they are to a non-PCI based fabric or device. In all other PCI based fabrics (e.g., PCIe switch fabric or integrated device fabric), non-posted writes are not supported. In this case, non-posted write transactions to be routed to PCI based fabrics that do not support non-posted writes may be converted or terminated by the root complex or other fabric that is aware of non-posted write transactions.

[0041] For example, if the agent provides access to a legacy root complex integrated endpoint that does not support non-posted memory write requests, the fabric can simply return an unsupported request completion. Existing agents will not see any changes because the error handler in the main fabric can handle this completion.

[0042] In another example, the agent can provide access to structures that do not support non-posted memory writes. For example, when a PCIe root port can provide access to a PCIe hierarchical structure, a virtual root port can provide access to an integrated device structure or a legacy host structure that does not support non-posted memory writes, and the bridge agent can map non-posted memory write transactions to posted memory write transactions (e.g., MWr32 or MWr64) and generate completions to send to the original requestor. This ensures interoperability and backward compatibility.

[0043] Using the embodiments, third-party non-PCI-based IP logic can be more easily and flexibly integrated into PCI-based clients, servers, and devices. In addition, the embodiments can also simplify the design of PCI sorting structures that implement P / C sorting on multiple channels. By defining and supporting non-posted write transactions for all channels in supported structures and devices, IP logic with additional virtual channels for QoS does not have to add any additional handshakes to ensure correct processing. In this way, the embodiments described herein provide non-posted write transaction capabilities, which are naturally scalable mechanisms for P / C sorting across any channel. As a result, the embodiments can enhance scalability by supporting PCI and non-PCI IP logic that can implement complex QoS mechanisms.

[0044] Embodiments may provide an ordering rule that supports non-posted write transactions based on PCI ordering rules. For Table 1 below, the columns represent the first transaction issued, and the rows represent transactions issued subsequently. The table entry indicates the ordering relationship between two transactions.

[0045] Table 1

[0046]

[0047]

[0048] In Table 1: a posted request is a memory write request or a message request; a non-posted read request is a configuration read request, an I / O read request or a memory read request; a non-posted write request is a memory write request; an NPR (non-posted request) with data is a configuration write request, an I / O write request or an atomic operation request; a non-posted request is a read request or an NPR with data.

[0049] Each table entry indicates an ordering relationship between two transactions. The table entries are defined as follows: (1) Yes - the second transaction (row) must be allowed to pass the first (column) to avoid deadlock. In the event of blocking, the second transaction is required to pass the first transaction. Fairness is understood as preventing starvation. If there is no credit for the message type, the message will be blocked; (2) No - the second transaction (row) must not be allowed to pass the first (column) transaction; and (3) Yes / No - there is no requirement, so that the second transaction can optionally pass the first transaction.

[0050] Table 2 below provides an explanation of each entry in Table 1 above.

[0051] Table 2

[0052] A2a does not allow a posted request to override another posted request unless A2b applies.

[0053] A2b allows a Posted Request with RO set to pass over another Posted Request. If the two requester IDs are different, a Posted Request with IDO set is allowed to pass over another Posted Request.

[0054] A3 and A4 posted requests must be able to bypass non-posted requests to avoid deadlock.

[0055] A5a allows posted requests to bypass completion, but does not necessarily require the ability to bypass completion unless A5b applies.

[0056] A5b Inside a PCI Express to PCI / PCI-X bridge, where the PCI / PCI-X bus segment operates in traditional PCI mode, posted requests must be able to pass completion for transactions in the PCI Express to PCI direction to avoid deadlock.

[0057] B2a does not allow read or write requests to bypass posted requests unless B2b applies.

[0058] B2b allows a read or write request with IDO set to bypass a posted request if the two requestor IDs are different.

[0059] C2a NPRs with data are not allowed to pass post-style requests unless C2b applies.

[0060] C2b allows NPRs with data and RO set to bypass a post-style request. If the two requester IDs are different, then NPRs with data and IDO set are allowed to bypass a post-style request.

[0061] B3, B4,

[0062] C3 and C4 allow a non-posted request to bypass another non-posted request.

[0063] B5 and C5 allow non-posted requests to bypass completion.

[0064] D2a Unless D2b applies, a pass-through request may not be completed.

[0065] D2b Allows I / O or configuration write completions to bypass a posted request. Allows completions with RO set to bypass a posted request. Allows completions with IDO set to bypass a posted request if the completer ID of the completion is different from the requester ID of the posted request.

[0066] D3 and D4 completion must be able to jump over non-posted requests to avoid deadlock.

[0067] D5a allows completions with different transaction IDs to pass over each other.

[0068] D5b does not allow completions with the same transaction ID to pass over each other. This ensures that multiple completions associated with a single memory read request will maintain ascending address order.

[0069] Reference now Figure 7 , shows a flow chart of a method according to an embodiment of the present invention. Specifically, Figure 7The method 300 shown in is a method for generating a non-posted memory write transaction to be output from an agent such as an endpoint on a given channel, and arbitrating between multiple pending transactions in the agent. In this way, the method 300 can be performed by hardware circuits, software, firmware and / or a combination thereof of a given agent, such as an interface circuit, which may include an arbitrator to perform at least a portion of the method 300. As shown, the method 300 begins with selecting a non-posted write transaction present in a non-posted queue of an endpoint (block 310). As an example, the main interface of the agent (which may be a PCI-based IP logic configured to support non-posted memory write transactions or a non-PCI device with such support) can select the non-posted memory write transaction according to various arbitration techniques, such as round robin, priority-based arbitration, etc. Control is then passed to block 320, where a non-posted write transaction can be issued from the endpoint. As an example, the transaction can be issued to an upstream device on a given channel (e.g., a first channel), such as via direct communication to the structure or via an intermediate bridge or other device. At this point, this non-posted memory write transaction is outstanding and remains outstanding until completion is received to indicate global observation of the write transaction.

[0070] Still reference Figure 7 , additional operations may occur within the agent. As shown, at diamond 330, it may be determined whether there is a posted write transaction in the posted queue of the endpoint. If not, control is passed to diamond 340, where it may be determined whether there is an additional non-posted (read or write) transaction in the non-posted queue of the endpoint. If so, control returns to block 310, where the transaction may also continue to be sent from the agent. That is, one or more non-posted transactions may be issued while one or more non-posted write transactions are not completed (i.e., completion has not yet been received).

[0071] Still reference Figure 7 , conversely, if it is determined that there is a posted write transaction in the posted queue, control passes to diamond box 350 to determine whether a completion for the non-posted write transaction has been received in the endpoint. If not, this posted write transaction will be retained until such a completion is received. Therefore, as shown in the figure, when it is determined that a completion is received, control passes from diamond box 350 to box 360, where the posted write transaction can be selected for output and thus, at box 370, the posted write transaction is issued from the endpoint. Note that there is no further processing regarding the posted write transaction because no completion is subsequently received when the transaction is observed globally, because this posted write transaction is a fire-and-forget operation. It should be understood that although in Figure 7 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0072] Reference now Figure 8 , shows a flow chart of a method according to another embodiment of the present invention. More specifically, Figure 8 The method 400 shown in the embodiment can be performed by hardware circuits, software, firmware and / or a combination thereof. More specifically, the method 400 is a method for processing non-posted writes in a structure or other receiving device configured to support non-posted write transactions. Thus, in an embodiment, the method 400 can be performed by the control logic of the structure.

[0073] As shown, method 400 begins with receiving a non-posted write transaction in a structure from an endpoint (block 410). Note that in some cases, the endpoint may be directly coupled to the structure, while in other cases, there may be one or more intermediate devices, such as a bridge or other device coupled between the endpoint and the structure. Control is then passed to diamond block 420 to determine whether the non-posted write transaction is sent to a memory coupled to a device that is aware of non-posted writes. As described herein, such devices may include a variety of different PCI-based and non-PCI-based devices that are configured to support non-posted write transactions as described herein. If it is determined that the transaction is sent to a supported device, control is passed to block 430, where the non-posted write transaction is routed to the device. As an example, the transaction may be routed to a memory controller that is in turn coupled to the memory. In other cases, the transaction may be routed to one or more intermediate devices that are in turn coupled to the memory. In any case, control is passed to block 440, where a completion is received from the device to indicate that a non-posted memory write transaction has been globally observed. Thereafter, at block 450, the completion may be routed to the endpoint. Note that when this completion is received at the endpoint, the memory write transaction is completed from the endpoint's perspective and is therefore no longer outstanding, so posted write transactions or other transactions with ordering requirements with respect to this non-posted write transaction can proceed.

[0074] Still reference Figure 8, conversely, if it is determined that the non-posted write transaction is destined for a memory coupled to a device that is not aware of non-posted writes, control passes to diamond block 460, where the structure determines whether to allow the non-posted write transaction to be converted to a posted write transaction. This determination can be based on whether the structure is able to convert the transaction. If not allowed, control passes to block 470, where the transaction can be terminated. In some cases, an unsupported message can be sent back to the requestor as a completion. Conversely, if it is determined that the conversion is allowed, control passes to block 480, where the transaction can be converted to a posted write transaction and routed to the device. Further, it should be understood that the structure can generate a completion and send the completion back to the endpoint to enable the endpoint to complete its non-posted memory write transaction (block 490). Note that the completion can be generated at the last possible location, such as before the egress on a port connected to an agent that does not support non-posted memory write transactions. It should be understood that although in Figure 8 The embodiments are shown at this high level, but many variations and alternatives are possible.

[0075] Reference now Fig. 9 , a block diagram of an exemplary system in which an embodiment may be used is shown. Fig. 9 In the illustration of , system 1300 may be a mobile low power system such as a tablet, 2:1 tablet, tablet phone device or other convertible or standalone tablet system. As shown, SoC 1310 is present and may be configured to operate as an application processor of the device. SoC 1310 may include agents and structures to support non-posted memory write transactions within the PCI context as described herein.

[0076] Various devices may be coupled to the SoC 1310. In the illustrated illustration, the memory subsystem includes flash memory 1340 and DRAM 1345 coupled to the SoC 1310. Additionally, a touchpad 1320 is coupled to the SoC 1310 to provide display capabilities and user input via touch, including providing a virtual keyboard on the display of the touchpad 1320. To provide a wired network connection, the SoC 1310 is coupled to an Ethernet interface 1330. A peripheral hub 1325 is coupled to the SoC 1310 to enable interfacing with various peripheral devices, such as may be coupled to the system 1300 via any of a variety of ports or other connectors.

[0077] In addition to the internal power management circuits and functions within the SoC 1310, the PMIC 1380 is coupled to the SoC 1310 to provide platform-based power management, for example, based on whether the system is powered by the battery 1390 or AC powered via the AC adapter 1395. In addition to power management based on the source, the PMIC 1380 can also perform platform power management activities based on environmental and usage conditions. Further, the PMIC 1380 can communicate control and status information to the SoC 1310 to cause various power management operations within the SoC 1310.

[0078] Still reference Fig. 9 To provide wireless capabilities, the WLAN unit 1350 is coupled to the SoC 1310 and in turn to the antenna 1355. In various embodiments, the WLAN unit 1350 may provide communications according to one or more wireless protocols.

[0079] As further shown, a plurality of sensors 1360 may be coupled to SoC 1310. These sensors may include various accelerometers, environmental and other sensors, including user gesture sensors. Finally, an audio codec 1365 is coupled to SoC 1310 to provide an interface to an audio output device 1370. Of course, it should be understood that although in Fig. 9 Although shown in this particular embodiment, many variations and alternatives are possible.

[0080] Reference now Fig.10 , shows a block diagram of a representative computer system, such as a notebook computer, an Ultrabook TM or other small systems. In one embodiment, processor 1410 includes a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing element. In the illustrated embodiment, processor 1410 serves as a main processing unit and a central hub for communicating with many of the various components of system 1400, and may include power management circuits as described herein. As an example, processor 1410 is implemented as a SoC and may include agents and structures that support non-posted memory write transactions as described herein. In one embodiment, processor 1410 communicates with system memory 1415. As an illustrative example, system memory 1415 is implemented by multiple memory devices or modules to provide a given amount of system memory.

[0081] To provide persistent storage of information such as data, applications, one or more operating systems, and the like, mass storage 1420 may also be coupled to processor 1410. In various embodiments, to enable thinner and lighter system designs and to improve system responsiveness, the mass storage may be implemented via an SSD, or may be implemented using primarily a hard disk drive (HDD) with a small amount of SSD storage acting as an SSD cache to enable non-volatile storage of contextual state and other such information during a power-off event so that a fast power-up can occur when restarting system activity. Fig.10 As shown, flash memory device 1422 may be coupled to processor 1410, for example, via a serial peripheral interface (SPI). The flash memory device may provide non-volatile storage for system software, including basic input / output software (BIOS) and other firmware for the system.

[0082] Various input / output (I / O) devices may be present in system 1400. Fig.10 Specifically shown in the embodiment of FIG. 1 is a display 1424, which may be a high-definition LCD or LED panel, which further provides a touch screen 1425. In one embodiment, the display 1424 may be coupled to the processor 1410 via a display interconnect, which may be implemented as a high-performance graphics interconnect. The touch screen 1425 may be coupled to the processor 1410 via another interconnect, which may be an I 2 C interconnection. Fig.10 As further shown in FIG. 14 , in addition to the touch screen 1425, user input by touch may also be performed via a touch pad 1430, which may be configured within the housing and may also be coupled to the same I as the touch screen 1425. 2 C interconnection.

[0083] For perceptual computing and other purposes, various sensors may be present within the system and may be coupled to the processor 1410 in different ways. Certain inertial and environmental sensors may be coupled to the processor 1410 through the sensor hub 1440 (e.g., via I 2 C interconnect) is coupled to processor 1410. Fig.10 In the illustrated embodiment, these sensors may include an accelerometer 1441, an ambient light sensor (ALS) 1442, a compass 1443, and a gyroscope 1444. Other environmental sensors may include one or more thermal sensors 1446, which in some embodiments are coupled to the processor 1410 via a system management bus (SMBus) bus.

[0084] See also Fig.10, various peripherals can be coupled to the processor 1410 via a low pin count (LPC) interconnect. In the embodiment shown, various components can be coupled through an embedded controller 1435. These components can include a keyboard 1436 (e.g., coupled via a PS2 interface), a fan 1437, and a thermal sensor 1439. In some embodiments, a touchpad 1430 can also be coupled to the EC 1435 via a PS2 interface. In addition, a security processor such as a trusted platform module (TPM) 1438 can also be coupled to the processor 1410 via the LPC interconnect.

[0085] System 1400 can communicate with external devices in various ways (including wirelessly). Fig.10 In the illustrated embodiment, there are various wireless modules, each of which may correspond to a radio device configured for a specific wireless communication protocol. One way to wirelessly communicate over short distances such as near field may be via NFC unit 1445, which may communicate with processor 1410 via SMBus in one embodiment. Note that via this NFC unit 1445, devices that are close to each other may communicate.

[0086] like Fig.10 As further seen in the figure, additional wireless units may include other short-range wireless engines, including WLAN unit 1450 and Bluetooth TM Unit 1452. Using WLAN unit 1450, Wi-Fi can be implemented TM Communication via Bluetooth TM Unit 1452, can perform short-range Bluetooth TM Communication. These units can communicate with the processor 1410 via a given link.

[0087] Additionally, for example, wireless wide area communications according to cellular or other wireless wide area protocols may occur via WWAN unit 1456, which in turn may be coupled to a subscriber identity module (SIM) 1457. Additionally, to enable the receipt and use of location information, a GPS module 1455 may also be present. Fig.10 In the illustrated embodiment, WWAN unit 1456 and an integrated capture device such as camera module 1454 may communicate via a given link.

[0088] To provide audio input and output, an audio processor may be implemented via a digital signal processor (DSP) 1460, which may be coupled to the processor 1410 via a high definition audio (HDA) link. Similarly, the DSP 1460 may communicate with an integrated coder / decoder (CODEC) and amplifier 1462, which in turn may be coupled to an output speaker 1463, which may be implemented within the chassis. Similarly, the amplifier and CODEC 1462 may be coupled to receive audio input from a microphone 1465, which in one embodiment may be implemented via a dual array microphone (e.g., a digital microphone array) to provide high quality audio input for voice activated control of various operations within the system. Note also that audio output may be provided from the amplifier / CODEC 1462 to a headphone jack 1464. Although in Fig.10 Although these specific components are shown in the embodiments described above, it should be understood that the scope of the present invention is not limited thereto.

[0089] Embodiments may be implemented in many different system types. Fig.11 , which is a block diagram of a system according to an embodiment of the present invention. Fig.11 As shown, the multiprocessor system 1500 is a point-to-point interconnect system and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Fig.11 As shown, each of processors 1570 and 1580 can be a multi-core processor, including first and second processor cores (i.e., processor cores 1574a and 1574b and processor cores 1584a and 1584b), although there may be more cores in the processor. Each processor can include a PCU (1575, 1585) or other power management logic to perform processor-based power management. Such a processor can be further configured to handle non-posted memory write transactions within the PCI context described herein.

[0090] Still reference Fig.11 , the first processor 1570 also includes a memory controller hub (MCH) 1572 and point-to-point (PP) interfaces 1576 and 1578. Similarly, the second processor 1580 includes an MCH 1582 and PP interfaces 1586 and 1588. Fig.10 As shown, MCH 1572 and 1582 couple the processors to respective memories, namely memory 1532 and memory 1534, which may be part of system memory (e.g., DRAM) locally attached to the respective processors. First processor 1570 and second processor 1580 may be coupled to chipset 1590 via PP interconnects 1562 and 1564, respectively. Fig.11As shown, chipset 1590 includes PP interfaces 1594 and 1598 .

[0091] In addition, the chipset 1590 includes an interface 1592 to couple the chipset 1590 with the high performance graphics engine 1538 via the PP interconnect 1539. Accordingly, the chipset 1590 may be coupled to the first bus 1516 via an interface 1596. Fig.10 As shown, various input / output (I / O) devices 1514 may be coupled to first bus 1516, as well as a bus bridge 1518 coupling first bus 1516 to a second bus 1520. In one embodiment, various devices may be coupled to second bus 1520 including, for example, a keyboard / mouse 1522, communication devices 1526 and a data storage unit 1528 such as a disk drive or other mass storage device which may include code 1530. Additionally, an audio I / O 1524 may be coupled to second bus 1520. Embodiments may be incorporated into other types of systems including, for example, smart cell phones, tablet computers, netbooks, Ultrabooks, and the like. TM etc. mobile devices.

[0092] The following examples relate to other embodiments.

[0093] In one example, a SoC is formed with a semiconductor die including: a plurality of agents including a first endpoint that issues non-posted memory write transactions to a memory; and a structure for coupling the plurality of agents, the structure including a host interface having a plurality of channels, the structure including a PCI-based structure including control logic for directing the non-posted memory write transactions to the memory, receiving completions of the non-posted memory write transactions from the memory, and routing the completions to the first endpoint.

[0094] In an example, the first endpoint waits for a receive completion before issuing a posted write transaction to ensure write data consistency.

[0095] In the example, the completion does not include data.

[0096] In an example, the fabric receives a non-posted memory write transaction via a first channel of a first endpoint and directs the non-posted memory write transaction to memory via a first channel of the fabric mapped to the first channel of the first endpoint.

[0097] In an example, the first endpoint issues a second non-posted memory write transaction while the non-posted memory write transaction is outstanding.

[0098] In an example, the first endpoint waits to receive a second completion of a second non-posted memory write transaction before issuing the posted write transaction to ensure write data consistency.

[0099] In an example, the first endpoint includes non-PCI logic to natively support non-posted write transactions.

[0100] In an example, the fabric includes an integrated system-on-chip fabric, wherein a protocol of the integrated system-on-chip fabric does not natively support non-posted memory write transactions.

[0101] In an example, the fabric converts a non-posted memory write transaction to a posted write transaction and sends the posted write transaction to a PCI-based fabric that does not support non-posted memory write transactions.

[0102] In an example, the fabric forwards the non-posted memory write transaction to a second fabric comprising a non-PCI based fabric that natively supports the non-posted memory write transaction.

[0103] In an example, the structure prevents a non-posted memory write transaction from passing a posted write transaction.

[0104] In another example, a method includes: sending a non-posted memory write transaction from an endpoint of a SoC to a host structure of the SoC to enable the host structure to direct the non-posted write transaction to a memory coupled to the SoC, the endpoint comprising a PCI-based endpoint, the host structure supporting PCI sorting rules; when the posted write transaction is present in a posted queue of the endpoint, determining whether the endpoint has received a completion of the non-posted memory write transaction; and blocking sending the posted write transaction from the endpoint to the host structure until it is determined that the endpoint has received the completion of the non-posted memory write transaction.

[0105] In an example, the method further comprises sending a second non-posted memory write transaction from the endpoint to the host fabric before the endpoint receives completion of the non-posted memory write transaction.

[0106] In an example, the method further comprises sending a plurality of non-posted memory write transactions from the endpoint to the host fabric while one or more previous non-posted memory write transactions sent by the endpoint are outstanding.

[0107] In an example, the method further includes sending a second non-posted memory write transaction from a second endpoint of the SoC to the host fabric, the second endpoint comprising non-PCI based IP logic, and the host fabric comprising a PCI based fabric configured to support the non-posted memory write transaction.

[0108] In an example, the method further includes: receiving a second non-posted memory write transaction from the requestor in the endpoint; converting the second non-posted memory write transaction to a posted write transaction and sending the posted write transaction to a second structure coupled to the endpoint, the second structure comprising a PCI-based structure that is not configured to support non-posted memory write transactions; and sending a completion of the second non-posted memory write transaction to the requestor.

[0109] In another example, a computer readable medium comprising instructions is used to perform the method of any of the above examples.

[0110] In another example, a computer readable medium including data is used by at least one machine to fabricate at least one integrated circuit to perform the method of any of the above examples.

[0111] In another example, an apparatus includes means for performing the method of any of the above examples.

[0112] In yet another example, a system includes: a SoC and a memory coupled to the SoC. The SoC may include: one or more cores to execute instructions; a coherent interconnect coupled to the one or more cores; a memory controller coupled to the coherent interconnect; a plurality of agents including: a first endpoint to issue a non-posted memory write transaction, the first endpoint including a PCI-based endpoint; a second non-PCI-based endpoint to issue a second non-posted memory write transaction; and a structure to couple at least some of the plurality of agents, the structure including control logic for directing at least the first non-posted memory write transaction to the memory, receiving a first completion of the first non-posted memory write transaction, and routing the first completion to the first endpoint.

[0113] In an example, the second endpoint includes third party IP logic.

[0114] In an example, the fabric forwards the second non-posted memory write transaction to a second fabric, the second fabric comprising a non-PCI based fabric.

[0115] In an example, the first endpoint issues another non-posted memory write transaction while the first non-posted memory write transaction is not completed, and refrains from issuing posted write transactions until the first endpoint receives the completion and another completion of the other non-posted memory write transaction.

[0116] In yet another example, an apparatus includes: a module for sending a non-posted memory write transaction from an endpoint to a host structure to enable the host structure to direct the non-posted write transaction to a memory, the endpoint comprising a PCI-based endpoint, the host structure supporting PCI ordering rules; a module for determining whether the endpoint has received a completion of the non-posted memory write transaction; and a module for preventing a posted write transaction stored in a posted queue of the endpoint from being sent from the endpoint to the host structure until the endpoint has received the completion of the non-posted memory write transaction.

[0117] In an example, the apparatus further comprises means for sending a second non-posted memory write transaction from the endpoint to the host fabric before the endpoint receives completion of the non-posted memory write transaction.

[0118] In an example, the apparatus further comprises means for sending a plurality of non-posted memory write transactions from the endpoint to the host fabric while one or more previous non-posted memory write transactions sent by the endpoint are outstanding.

[0119] In an example, the apparatus further comprises means for sending a second non-posted memory write transaction from the second endpoint to the host fabric, the second endpoint comprising non-PCI based IP logic, and the host fabric comprising a PCI based fabric configured to support the non-posted memory write transaction.

[0120] In an example, the apparatus further comprises: means for receiving a second non-posted memory write transaction received in the endpoint from the requestor; means for converting the second non-posted memory write transaction into a posted write transaction and sending the posted write transaction to a second structure coupled to the endpoint, the second structure comprising a PCI-based structure not configured to support non-posted memory write transactions; and means for sending completion of the second non-posted memory write transaction to the requestor.

[0121] It will be appreciated that various combinations of the above examples are possible.

[0122] Note that the terms "circuit" and "circuitry" are used interchangeably herein. As used herein, these terms and the term "logic" are used to refer to analog circuits, digital circuits, hardwired circuits, programmable circuits, processor circuits, microcontroller circuits, hardware logic circuits, state machine circuits, and / or any other type of physical hardware components, alone or in any combination. Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices, and on the contrary, other embodiments may involve other types of devices for processing instructions, or one or more machine-readable media including instructions, which, in response to being executed on a computing device, cause the device to perform one or more methods and techniques described herein.

[0123] Embodiments may be implemented in code and may be stored on a non-transitory storage medium having instructions stored thereon, which may be used to program a system to execute the instructions. Embodiments may also be implemented in data and may be stored on a non-transitory storage medium, which, if used by at least one machine, causes at least one machine to manufacture at least one integrated circuit to perform one or more operations. Further embodiments may be implemented in a computer-readable storage medium including information, which, when manufactured into a SoC or other processor, is used to configure the SoC or other processor to perform one or more operations. Storage media may include, but are not limited to, any type of disk, including a floppy disk, an optical disk, a solid-state drive (SSD), a compact disk read-only memory (CD-ROM), a rewritable compact disk (CD-RW), and a magneto-optical disk, a semiconductor device such as a read-only memory (ROM), a random access memory (RAM) (such as a dynamic random access memory (DRAM), a static random access memory (SRAM)), an erasable programmable read-only memory (EPROM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a magnetic card or an optical card, or any other type of medium suitable for storing electronic instructions.

[0124] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the present invention.

Claims

1. A computing device, include: a device coupled to the memory; as well as a peripheral component interconnect (PCI)-compatible fabric for coupling an endpoint and the device, the PCI-compatible fabric comprising control circuitry for receiving a non-posted memory write transaction from the endpoint, directing the non-posted memory write transaction to the device, receiving a completion of the non-posted memory write transaction from the device, and routing the completion to the endpoint.

2. The computing device according to claim 1, further comprising: include: the endpoint for sending the non-posted memory write transaction to the PCI-compatible structure; as well as The memory.

3. The computing device according to claim 1, in, The non-posted memory write transaction includes a 32-bit address.

4. The computing device according to claim 1, in, The non-posted memory write transaction includes a 64-bit address.

5. The computing device according to claim 1, in, The completion is a completion without data.

6. The computing device according to claim 1, in, The means is for preventing the non-posted memory write transaction from passing a first posted write transaction.

7. The computing device according to claim 1, in, The apparatus is configured to cause a second non-posted memory write transaction to pass over a second posted write transaction, wherein the second non-posted memory write transaction includes a set of relaxed ordering attributes.

8. The computing device according to claim 1, in, The means is for optionally enabling the non-posted memory write transaction to bypass a non-posted read transaction.

9. At least one computer-readable storage medium having stored thereon instructions which, when executed by a machine, cause the machine to: receiving a non-posted memory write transaction from an endpoint in a peripheral component interconnect (PCI) compliant fabric arranged to couple the endpoint and a device associated with a memory; directing the non-posted memory write transaction from the PCI-compatible fabric to the device; receiving a completion of the non-posted memory write transaction from the device in the PCI-compatible fabric; as well as The completion is routed to the endpoint.

10. The computer-readable storage medium according to claim 9, in, The computer-readable storage medium also has stored thereon instructions that, when executed by the machine, cause the machine to receive the non-posted memory write transaction having a 32-bit address.

11. The computer-readable storage medium according to claim 9, in, The computer-readable storage medium also has stored thereon instructions that, when executed by the machine, cause the machine to receive the non-posted memory write transaction having a 64-bit address.

12. The computer-readable storage medium according to claim 9, in, The computer-readable storage medium also has stored thereon instructions that, when executed by the machine, cause the machine to receive the completion including a completion without data.

13. The computer-readable storage medium according to claim 9, in, The computer-readable storage medium also has stored thereon instructions that, when executed by the machine, cause the machine to prevent the non-posted memory write transaction from passing over a first posted write transaction.

14. The computer-readable storage medium according to claim 9, in, The computer-readable storage medium also has stored thereon instructions that, when executed by the machine, cause the machine to cause a second non-posted memory write transaction to pass over a second posted write transaction, wherein the second non-posted memory write transaction includes a relaxed set of ordering attributes.

15. A computing system, include: An endpoint for issuing non-posted memory write transactions to a memory; a device coupled to the memory; Central processing unit; as well as a peripheral component interconnect (PCI) compliant fabric coupled to the central processing unit and for coupling the endpoint and the device, the PCI compliant fabric including control circuitry for processing the non-posted memory write transactions from the endpoint and routing completions of the non-posted memory write transactions from the device to the endpoint.

16. The computing system of claim 15, in, The non-posted memory write transaction includes a 32-bit address.

17. The computing system of claim 15, in, The non-posted memory write transaction includes a 64-bit address.

18. The computing system of claim 15, in, The completion is a completion without data.

19. The computing system of claim 15, in, The system is for preventing the non-posted memory write transaction from passing a first posted write transaction.

20. The computing system of claim 15, in, The system is for causing a second non-posted memory write transaction to pass over a second posted write transaction, wherein the second non-posted memory write transaction includes a set of relaxed ordering attributes.

21. The computing system of claim 15, in, The system is configured to optionally enable the non-posted memory write transaction to bypass a non-posted read transaction.

22. An endpoint, include: intellectual property (IP) logic to issue a non-posted memory write transaction to a memory via a fabric, wherein the endpoint is to receive a completion of the non-posted memory write transaction; a buffer for storing transactions including the non-posted memory write transactions; as well as An arbiter is coupled to the buffer, wherein the arbiter is used to select and output the non-posted memory write transaction.

23. The endpoint according to claim 22, in, The IP logic is to issue the non-posted memory write transaction including a 64-bit address.

24. The endpoint of claim 22, in, The endpoints include Peripheral Component Interconnect Express (PCIe) based endpoints.

25. A computing system, include: Central Processing Unit (CPU); as well as a root complex coupled to the CPU, wherein the root complex includes at least one root port for receiving a non-posted memory write transaction from an endpoint, directing the non-posted memory write transaction to a memory, receiving a completion of the non-posted memory write transaction, and routing the completion to the endpoint.

26. The computing system of claim 25, further comprising a structure coupled to the root complex, in, The structure includes a plurality of virtual channels.

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