Semiconductor device including thick metal layer

Abstract

A semiconductor device is provided, comprising a plurality of intermediate interconnects and a plurality of intermediate plugs disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnect, a second upper plug, and a second upper interconnect are disposed in the upper insulating layer. Each of the plurality of intermediate interconnects has a first thickness. The first upper interconnect has a second thickness greater than the first thickness. The second upper interconnect has a third thickness greater than the first thickness. The third thickness is 2 to 100 times the first thickness. The second upper interconnect comprises a material different from that of the second upper plug.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0122357, filed on October 2, 2019, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Devices and methods consistent with example embodiments relate to a semiconductor device having a thick metal layer and a method of forming the semiconductor device. Background Art

[0003] Semiconductor devices have various interconnects. Reducing the cross-sectional area of ​​interconnects to increase integration density leads to problems such as increased interconnect resistance and reduced signal transmission rates. The materials used for interconnects and the methods used to form them significantly impact the mass production efficiency and reliability of semiconductor devices. Summary of the Invention

[0004] Example embodiments of the inventive concepts are directed to providing a semiconductor device having improved current driving capability and a high signal transmission rate, and a method of forming the semiconductor device.

[0005] According to example embodiments, the disclosure relates to a semiconductor device, the semiconductor device including: an interlayer insulating layer disposed on a substrate; a plurality of intermediate interconnections disposed in the interlayer insulating layer; a plurality of intermediate plugs disposed in the interlayer insulating layer and disposed between the plurality of intermediate interconnections; an upper insulating layer disposed on the interlayer insulating layer; a first upper plug disposed in the upper insulating layer and connected to one of the plurality of intermediate interconnections, the one intermediate interconnection having a first thickness; a first upper interconnection disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness; a second upper plug disposed in the upper insulating layer on the first upper interconnection; a second upper interconnection disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; and an opening configured to pass through the upper insulating layer to expose a portion of the second upper interconnection, wherein the third thickness is in a range of 2 times to 100 times the first thickness, and wherein the second upper interconnection includes a material different from that of the second upper plug.

[0006] According to example embodiments, the disclosure relates to a semiconductor device comprising a plurality of semiconductor chips sequentially stacked on a printed circuit board (PCB), wherein at least one of the plurality of semiconductor chips comprises: a lower insulating layer disposed on a substrate; a memory cell disposed in the lower insulating layer; an interlayer insulating layer disposed on the lower insulating layer; a plurality of intermediate interconnections disposed in the interlayer insulating layer; a plurality of intermediate plugs disposed in the interlayer insulating layer and disposed between the plurality of intermediate interconnections; an upper insulating layer disposed on the interlayer insulating layer; a first upper plug disposed in the upper insulating layer and connected to one of the plurality of intermediate interconnections, the one intermediate interconnection having a first thickness. degree; a first upper interconnection disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness; a second upper plug disposed in the upper insulating layer and disposed on the first upper interconnection; a second upper interconnection disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; a bump disposed on the upper insulating layer, the bump extending into the upper insulating layer and contacting the second upper interconnection; and a through-electrode extending into the substrate and connected to the plurality of intermediate interconnections, wherein the third thickness is in a range of 2 times to 100 times the first thickness, and wherein the second upper interconnection comprises a material different from a material of the second upper plug.

[0007] According to example embodiments, the disclosure relates to a semiconductor device comprising: a relay substrate; a microprocessor disposed on the relay substrate; a buffer chip disposed on the relay substrate; and a plurality of semiconductor chips sequentially stacked on the buffer chip, wherein at least one of the plurality of semiconductor chips comprises: a lower insulating layer disposed on the substrate; a memory cell disposed in the lower insulating layer; an interlayer insulating layer disposed on the lower insulating layer; a plurality of intermediate interconnections disposed in the interlayer insulating layer; a plurality of intermediate plugs disposed in the interlayer insulating layer and disposed between the plurality of intermediate interconnections; an upper insulating layer disposed on the interlayer insulating layer; a first upper plug disposed in the upper insulating layer and connected to one of the plurality of intermediate interconnections , the one intermediate interconnect having a first thickness; a first upper interconnect, disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness; a second upper plug, disposed in the upper insulating layer and disposed on the first upper interconnect; a second upper interconnect, disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; a bump, disposed on the upper insulating layer, the bump extending into the upper insulating layer and contacting the second upper interconnect; and a through-electrode extending into the substrate and connected to the plurality of intermediate interconnects, wherein the third thickness is in a range of 2 times to 100 times the first thickness, and wherein the second upper interconnect comprises a material different from a material of the second upper plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concept.

[0009] Figures 2 to 4 It shows Figure 1 Magnified view of a portion of.

[0010] Figures 5 to 8 is a cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concept.

[0011] Figure 9 and Figure 10 It shows Figure 5 A magnified view of a portion of the .

[0012] Figures 11 to 13 is a cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concept.

[0013] Figure 14 and Figure 15 is a cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concept.

[0014] Figure 16 It shows Figure 14 and Figure 15 Magnified view of a portion of.

[0015] Figures 17 to 21 are cross-sectional views for illustrating a method of forming a semiconductor device according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0016] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown.In the drawings, like reference numerals refer to like elements throughout.

[0017] Figure 1 is a cross-sectional view illustrating a semiconductor device according to example embodiments of the inventive concept. Figure 2 and Figure 3 It shows Figure 1 An enlarged view of part II, Figure 4 It shows Figure 1 A semiconductor device according to an embodiment of the inventive concept may include a thick top metal (TTM).

[0018] Reference Figure 1A semiconductor device according to an embodiment of the inventive concept may include a substrate 21, a lower insulating layer 30, memory cells MC, contact spacers 38, through electrodes 39, an interlayer insulating layer 40, a plurality of intermediate interconnections 45, a plurality of intermediate plugs 47, an upper insulating layer 50, a plurality of first upper plugs 61, a plurality of first upper interconnections 65, a plurality of second upper plugs 71, a plurality of second upper interconnections 75, an opening 55W, a base insulating layer 91, and protruding electrodes 93. The upper insulating layer 50 may include a first group 53 and a second group 55.

[0019] In an example embodiment, the plurality of second upper interconnects 75 may be a thick top metal (TTM). The memory cell MC may include a dynamic random access memory (DRAM) cell, a static RAM (SRAM) cell, a flash memory cell, a magnetoresistive RAM (MRAM) cell, a phase change RAM (PRAM) cell, a ferroelectric RAM (FeRAM) cell, a resistive RAM (RRAM) cell, or a combination thereof. For example, the memory cell MC may include a DRAM cell.

[0020] The substrate 21 may include a semiconductor substrate such as a single crystal silicon wafer. The lower insulating layer 30 may cover one surface of the substrate 21. For example, the lower surface of the lower insulating layer 30 may contact the upper surface of the substrate 21. The base insulating layer 91 may be disposed on the other surface of the substrate 21. For example, the upper surface of the base insulating layer 91 may contact the lower surface of the substrate 21. The substrate 21 may be disposed between the lower insulating layer 30 and the base insulating layer 91. The memory cell MC may be disposed in the lower insulating layer 30. The memory cell MC may be electrically connected to at least a corresponding one of the plurality of intermediate interconnects 45.

[0021] The interlayer insulating layer 40 may be disposed on the lower insulating layer 30. A plurality of intermediate interconnects 45 and a plurality of intermediate plugs 47 may be disposed in the interlayer insulating layer 40. The plurality of intermediate plugs 47 may be disposed between the plurality of intermediate interconnects 45, electrically connecting the plurality of intermediate interconnects 45. The through-electrode 39 may extend into the substrate 21, the lower insulating layer 30, and the base insulating layer 91. For example, the upper surface of the through-electrode 39 may be coplanar with the upper surface of the lower insulating layer 30, and the lower surface of the through-electrode 39 may be coplanar with the lower surface of the base insulating layer 91. The protruding electrode 93 may be disposed on the base insulating layer 91. For example, the upper surface of the protruding electrode 93 may contact the lower surface of the base insulating layer 91. The through-electrode 39 may pass through the substrate 21, the lower insulating layer 30, and the base insulating layer 91, and may contact one selected from the plurality of intermediate interconnects 45 and the protruding electrode 93. The through-electrode 39 may be electrically connected to the plurality of intermediate interconnects 45. A contact spacer 38 may be disposed between the through-electrode 39 and the substrate 21. An upper surface of the contact spacer 38 may be coplanar with an upper surface of the lower insulating layer 30, and a lower surface of the contact spacer 38 may be coplanar with a lower surface of the substrate 21. A diameter of the through electrode 39 may be in the range of about 1 μm to about 20 μm.

[0022] Each of the through-electrode 39, the plurality of intermediate interconnects 45, the plurality of intermediate plugs 47, and the protruding electrode 93 may include a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, or a combination thereof. Each of the through-electrode 39, the plurality of intermediate interconnects 45, the plurality of intermediate plugs 47, and the protruding electrode 93 may include copper (Cu), tungsten (W), aluminum (Al), nickel (Ni), tin (Sn), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. For example, each of the through-electrode 39, the plurality of intermediate interconnects 45, and the plurality of intermediate plugs 47 may include a Cu layer.

[0023] A first group 53 of upper insulating layer 50 may be disposed on interlayer insulating layer 40. A plurality of first upper plugs 61, a plurality of first upper interconnects 65, and a plurality of second upper plugs 71 may be disposed in first group 53. The plurality of first upper plugs 61 may contact corresponding ones of the plurality of intermediate interconnects 45. The plurality of first upper interconnects 65 may be disposed on the plurality of first upper plugs 61. For example, the lower surfaces of the plurality of first upper interconnects 65 may contact the upper surfaces of the plurality of first upper plugs 61. The plurality of second upper plugs 71 may be disposed on the plurality of first upper interconnects 65. For example, the lower surfaces of the plurality of second upper plugs 71 may contact the upper surfaces of the plurality of first upper interconnects 65. A second group 55 may be disposed on first group 53 of upper insulating layer 50. For example, the lower surface of the second group 55 may contact the upper surface of the first group 53. A plurality of second upper interconnects 75 may be disposed in second group 55. The plurality of second upper interconnects 75 may contact the plurality of second upper plugs 71. The openings 55W may pass through the second group 55 of the upper insulating layer 50. At least some of the plurality of second upper interconnections 75 may be exposed at the bottom of the openings 55W.

[0024] Each of the plurality of first upper plugs 61, the plurality of first upper interconnections 65, the plurality of second upper plugs 71, and the plurality of second upper interconnections 75 may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, or a combination thereof. Each of the plurality of first upper plugs 61, the plurality of first upper interconnections 65, the plurality of second upper plugs 71, and the plurality of second upper interconnections 75 may include W, Al, Ni, Sn, Ti, TiN, Ta, TaN, WN, Cu, or a combination thereof.

[0025] In example embodiments, each of the plurality of first upper interconnections 65 and the plurality of second upper interconnections 75 may include a material different from that of the plurality of intermediate interconnections 45 and the plurality of intermediate plugs 47. Each of the plurality of first upper interconnections 65 and the plurality of second upper interconnections 75 may include a material different from that of the plurality of first upper plugs 61 and the plurality of second upper plugs 71. For example, each of the plurality of first upper interconnections 65 and the plurality of second upper interconnections 75 may include an Al layer, and each of the plurality of first upper plugs 61 and the plurality of second upper plugs 71 may include a W layer.

[0026] Each of the lower insulating layer 30, the contact spacer 38, the interlayer insulating layer 40, the upper insulating layer 50, and the base insulating layer 91 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. Each of the lower insulating layer 30, the contact spacer 38, the interlayer insulating layer 40, the upper insulating layer 50, and the base insulating layer 91 may include a single layer or a multilayer structure.

[0027] Reference Figure 1 and Figure 2The plurality of intermediate interconnects 45 may include a first intermediate interconnect 45A, a second intermediate interconnect 45B, a third intermediate interconnect 45C, and a fourth intermediate interconnect 45D. The plurality of intermediate plugs 47 may include a first intermediate plug 47A, a second intermediate plug 47B, and a third intermediate plug 47C.

[0028] The upper insulating layer 50 may include a first upper insulating layer 53A, a second upper insulating layer 53B, a third upper insulating layer 53C, a fourth upper insulating layer 53D, a fifth upper insulating layer 53E, a sixth upper insulating layer 55A, and a seventh upper insulating layer 55B. The first group 53 may include the first upper insulating layer 53A, the second upper insulating layer 53B, the third upper insulating layer 53C, the fourth upper insulating layer 53D, and the fifth upper insulating layer 53E. The second group 55 may include the sixth upper insulating layer 55A and the seventh upper insulating layer 55B.

[0029] Each of the plurality of first upper plugs 61 may include a first barrier layer 61A and a first conductive layer 61B. Each of the plurality of first upper interconnects 65 may include a second barrier layer 65A, a second conductive layer 65B, and a third barrier layer 65C. Each of the plurality of second upper plugs 71 may include a fourth barrier layer 71A and a third conductive layer 71B. Each of the plurality of second upper interconnects 75 may include a fifth barrier layer 75A, a fourth conductive layer 75B, and a sixth barrier layer 75C.

[0030] Multiple second intermediate interconnects 45B may be disposed on the first intermediate interconnect 45A. The first intermediate interconnect 45A may be in direct contact with the through-electrode 39. Multiple first intermediate plugs 47A may be disposed between the multiple second intermediate interconnects 45B and the first intermediate interconnect 45A. The multiple first intermediate plugs 47A may be in contact with the multiple second intermediate interconnects 45B and the first intermediate interconnect 45A. Multiple third intermediate interconnects 45C may be disposed on the multiple second intermediate interconnects 45B. The multiple second intermediate plugs 47B may be disposed between the multiple third intermediate interconnects 45C and the multiple second intermediate interconnects 45B. The multiple second intermediate plugs 47B may be in contact with the multiple third intermediate interconnects 45C and the multiple second intermediate interconnects 45B. Multiple fourth intermediate interconnects 45D may be disposed on the multiple third intermediate interconnects 45C. The multiple third intermediate plugs 47C may be disposed between the multiple fourth intermediate interconnects 45D and the multiple third intermediate interconnects 45C. The plurality of third intermediate plugs 47C may be in contact with the plurality of fourth intermediate interconnections 45D and the plurality of third intermediate interconnections 45C.

[0031] In an example embodiment, the first intermediate interconnect 45A may correspond to the bottommost layer of the plurality of intermediate interconnects 45. The plurality of fourth intermediate interconnects 45D may correspond to the topmost layer of the plurality of intermediate interconnects 45. Each of the plurality of fourth intermediate interconnects 45D may have a first thickness T1. The first intermediate interconnect 45A, each of the plurality of second intermediate interconnects 45B, and each of the plurality of third intermediate interconnects 45C may have a thickness substantially the same as the thickness of each of the plurality of fourth intermediate interconnects 45D. As used herein, the terms "thickness" and "height" may refer to the thickness or height measured in a direction perpendicular to the top surface of the substrate 21. When referring to an orientation, layout, position, shape, size, amount, or other metric, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, amount, or other metric, but are intended to include nearly identical orientation, layout, position, shape, size, amount, or other metric within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, terms described as "substantially the same," "substantially equal," or "substantially planar" may mean that they are completely identical, completely equal, or completely planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0032] In an example embodiment, the plurality of first intermediate plugs 47A may correspond to the lowest layer of the plurality of intermediate plugs 47. The plurality of third intermediate plugs 47C may correspond to the highest layer of the plurality of intermediate plugs 47. Each of the plurality of third intermediate plugs 47C may have a first height H1. The first height H1 may be substantially equal to the gap between the plurality of third intermediate interconnects 45C and the plurality of fourth intermediate interconnects 45D. Each of the plurality of first intermediate plugs 47A and the plurality of second intermediate plugs 47B may have a height substantially the same as the height of each of the plurality of third intermediate plugs 47C.

[0033] The fourth upper insulating layer 53D and the fifth upper insulating layer 53E may be sequentially stacked on the interlayer insulating layer 40. In example embodiments, the fourth upper insulating layer 53D may correspond to an etch stop layer. The fourth upper insulating layer 53D may include a material having an etch selectivity relative to the fifth upper insulating layer 53E. The fifth upper insulating layer 53E may include silicon oxide or a low-k dielectric, and the fourth upper insulating layer 53D may include silicon nitride, silicon oxynitride, silicon boronitride (SiBN), or silicon carbonitride (SiCN).

[0034] Each of the plurality of first upper plugs 61 may extend into the fifth upper insulating layer 53E and the fourth upper insulating layer 53D. For example, the upper surfaces of the plurality of first upper plugs 61 may be coplanar with the upper surface of the fifth upper insulating layer 53E, and the lower surfaces of the plurality of first upper plugs 61 may be coplanar with the lower surface of the fourth upper insulating layer 53D. A plurality of first upper interconnects 65 may be disposed on the fifth upper insulating layer 53E. For example, the lower surfaces of the plurality of first upper interconnects 65 may contact the upper surface of the fifth upper insulating layer 53E. Each of the plurality of first upper plugs 61 may pass through the fifth upper insulating layer 53E and the fourth upper insulating layer 53D and contact a corresponding one of the plurality of fourth intermediate interconnects 45D and a corresponding one of the plurality of first upper interconnects 65.

[0035] In example embodiments, the first barrier layer 61A may surround the side surfaces and bottom of the first conductive layer 61B. The first conductive layer 61B may include a W layer. The first barrier layer 61A may include a WN layer. The second conductive layer 65B may be disposed on the second barrier layer 65A. For example, the lower surface of the second conductive layer 65B may contact the upper surface of the second barrier layer 65A. The third barrier layer 65C may be disposed on the second conductive layer 65B. For example, the lower surface of the third barrier layer 65C may contact the upper surface of the second conductive layer 65B. The second conductive layer 65B may be disposed between the second barrier layer 65A and the third barrier layer 65C. The second conductive layer 65B may include a material different from that of the plurality of intermediate interconnects 45, the plurality of intermediate plugs 47, and the first conductive layer 61B. The second conductive layer 65B may include an Al layer. Each of the second barrier layer 65A and the third barrier layer 65C may include Ti, TiN, Ta, TaN, WN, or a combination thereof. One or both of the second barrier layer 65A and the third barrier layer 65C may be omitted.

[0036] In example embodiments, each of the plurality of first upper interconnects 65 may have a second thickness T2. The second thickness T2 may be greater than the first thickness T1. Each of the plurality of first upper plugs 61 may have a second height H2. The second height H2 may be greater than the first height H1. The second height H2 may be substantially equal to the gap between the plurality of fourth intermediate interconnects 45D and the plurality of first upper interconnects 65.

[0037] The first upper insulating layer 53A may be disposed on the fifth upper insulating layer 53E. For example, the lower surface of the first upper insulating layer 53A may contact the upper surface of the fifth upper insulating layer 53E. The first upper insulating layer 53A may cover the upper surface and side surfaces of the plurality of first upper interconnects 65. The second upper insulating layer 53B may be disposed on the first upper insulating layer 53A. For example, the lower surface of the second upper insulating layer 53B may contact the upper surface of the first upper insulating layer 53A. The second upper insulating layer 53B may correspond to a capping layer. The second upper insulating layer 53B may control outgassing of the lower layer during the annealing process. The third upper insulating layer 53C may be disposed on the second upper insulating layer 53B. For example, the lower surface of the third upper insulating layer 53C may contact the upper surface of the second upper insulating layer 53B.

[0038] In example embodiments, the first upper insulating layer 53A may include an oxide layer such as high-density plasma (HDP) oxide. The second upper insulating layer 53B may include a material different from that of the first upper insulating layer 53A. The second upper insulating layer 53B may include a nitride layer such as silicon nitride. The third upper insulating layer 53C may include a material different from that of the second upper insulating layer 53B. The third upper insulating layer 53C may include an oxide layer formed using tetraethyl orthosilicate (TEOS) or fluorinated tetraethyl orthosilicate (FTEOS).

[0039] Each of the plurality of second upper plugs 71 may extend into the third upper insulating layer 53C, the second upper insulating layer 53B, and the first upper insulating layer 53A. Each of the plurality of second upper interconnects 75 may be disposed on the third upper insulating layer 53C. For example, the lower surfaces of the plurality of second upper interconnects 75 may contact the upper surface of the third upper insulating layer 53C. Each of the plurality of second upper plugs 71 may pass through the third upper insulating layer 53C, the second upper insulating layer 53B, and the first upper insulating layer 53A and contact a corresponding one of the plurality of first upper interconnects 65 and a corresponding one of the plurality of second upper interconnects 75.

[0040] In example embodiments, the fourth barrier layer 71A may surround the side surfaces and bottom of the third conductive layer 71B. The third conductive layer 71B may include a W layer. The fourth barrier layer 71A may include a WN layer. The fourth conductive layer 75B may be disposed on the fifth barrier layer 75A. For example, the lower surface of the fourth conductive layer 75B may contact the upper surface of the fifth barrier layer 75A. The sixth barrier layer 75C may be disposed on the fourth conductive layer 75B. For example, the lower surface of the sixth barrier layer 75C may contact the upper surface of the fourth conductive layer 75B. The fourth conductive layer 75B may be disposed between the fifth barrier layer 75A and the sixth barrier layer 75C. The fourth conductive layer 75B may include a material different from that of the plurality of intermediate interconnects 45, the plurality of intermediate plugs 47, and the third conductive layer 71B. The fourth conductive layer 75B may include an Al layer. Each of the fifth barrier layer 75A and the sixth barrier layer 75C may include Ti, TiN, Ta, TaN, WN, or a combination thereof. One or both of the fifth barrier layer 75A and the sixth barrier layer 75C may be omitted. For example, the fifth barrier layer 75A may be omitted. In such an embodiment, the lower surface of the fourth conductive layer 75B may contact the upper surface of the third upper insulating layer 53C.

[0041] In example embodiments, each of the plurality of second upper interconnects 75 may have a third thickness T3. The third thickness T3 may be greater than the first thickness T1. The third thickness T3 may be in a range of 2 to 100 times the first thickness T1. The third thickness T3 may be greater than or equal to the second thickness T2. The third thickness T3 may be in a range of approximately 2 μm to approximately 10 μm. For example, the third thickness T3 may be approximately 2.5 μm.

[0042] In example embodiments, each of the plurality of second upper plugs 71 may have a third height H3. The third height H3 may be substantially equal to the gap between the plurality of first upper interconnects 65 and the plurality of second upper interconnects 75. The third height H3 may be greater than the first height H1. The third height H3 may be greater than or equal to the second height H2. The third height H3 may be in a range of approximately 0.5 μm to approximately 5 μm. For example, the third height H3 may be approximately 1.7 μm.

[0043] The sixth upper insulating layer 55A may be disposed on the third upper insulating layer 53C. For example, the lower surface of the sixth upper insulating layer 55A may contact the upper surface of the third upper insulating layer 53C. The sixth upper insulating layer 55A may cover the side surfaces and upper surfaces of the plurality of second upper interconnects 75. The seventh upper insulating layer 55B may be disposed on the sixth upper insulating layer 55A. An opening 55W may pass through the seventh upper insulating layer 55B and the sixth upper insulating layer 55A. Portions of the plurality of second upper interconnects 75 may be exposed at the bottom of the opening 55W. The seventh upper insulating layer 55B may include a material different from that of the sixth upper insulating layer 55A. For example, the seventh upper insulating layer 55B may include a nitride such as silicon nitride, and the sixth upper insulating layer 55A may include an oxide such as silicon oxide.

[0044] In an exemplary embodiment, the sixth upper insulating layer 55A may include an oxide layer such as HDP oxide. The seventh upper insulating layer 55B may include an oxide layer formed using TEOS or FTEOS. In an exemplary embodiment, the sixth upper insulating layer 55A may include an oxide layer formed using TEOS or FTEOS. The seventh upper insulating layer 55B may include an oxide layer such as HDP oxide.

[0045] Interconnection resistance can be reduced due to the configuration of the plurality of first upper plugs 61, the plurality of first upper interconnects 65, the plurality of second upper plugs 71, and the plurality of second upper interconnects 75. The configuration of the first upper insulating layer 53A, the second upper insulating layer 53B, and the third upper insulating layer 53C can improve interlayer insulation characteristics. The second upper insulating layer 53B can improve the electrical characteristics and reliability of the plurality of active / passive elements disposed in the lower insulating layer 30 and / or the interlayer insulating layer 40.

[0046] Reference Figure 1 and Figure 3 The second upper interconnection 75 may include a fourth conductive layer 75B and a sixth barrier layer 75C. The fourth conductive layer 75B may contact the plurality of second upper plugs 71. For example, a lower surface of the fourth conductive layer 75B may contact upper surfaces of the plurality of second upper plugs 71.

[0047] Reference Figure 1 and Figure 4 In example embodiments, the memory cell MC may include a DRAM cell. The memory cell MC may include a substrate 21, a first lower insulating layer 30A, a second lower insulating layer 30B, a device isolation layer 23, a gate dielectric layer 24, a plurality of gate electrodes 25, a gate capping layer 26, a plurality of source / drain regions 27, a bit plug 28, a bit line 29, a plurality of buried contact plugs 32, a plurality of bonding pads 33, a plurality of first electrodes 35, a capacitor dielectric layer 36, and a second electrode 37. The lower insulating layer 30 may include a first lower insulating layer 30A and a second lower insulating layer 30B.

[0048] The device isolation layer 23 may be formed in the substrate 21 using a shallow trench isolation (STI) technique. The upper surface of the device isolation layer 23 may be coplanar with the upper surface of the substrate 21. Each of the plurality of gate electrodes 25 may be disposed at a level lower than the upper end of the substrate 21. For example, the upper surfaces of the plurality of gate electrodes 25 may be at a level lower than the upper surface of the substrate 21. The gate dielectric layer 24 may surround the side surfaces and bottoms of the plurality of gate electrodes 25. The gate dielectric layer 24 may be disposed between the plurality of gate electrodes 25 and the substrate 21. A gate cap layer 26 may be disposed on the plurality of gate electrodes 25. A plurality of source / drain regions 27 may be disposed in the substrate 21 adjacent to the plurality of gate electrodes 25.

[0049] The gate dielectric layer 24, the plurality of gate electrodes 25, and the plurality of source / drain regions 27 may constitute a plurality of cell transistors. Each of the plurality of cell transistors may correspond to a recessed channel transistor. In example embodiments, each of the plurality of cell transistors may include a fin field effect transistor (finFET), a multi-bridge channel (MBC) transistor, a nanowire transistor, a vertical transistor, a recessed channel transistor, a three-dimensional (3D) transistor, a planar transistor, or a combination thereof.

[0050] The first lower insulating layer 30A may cover the device isolation layer 23, the gate capping layer 26, and the plurality of source / drain regions 27. A bit plug 28 and a bit line 29 may be disposed in the first lower insulating layer 30A. The bit line 29 may be disposed on the bit plug 28. The bit plug 28 may pass through the first lower insulating layer 30A and contact a corresponding one of the plurality of source / drain regions 27. A plurality of buried contact plugs 32 and a plurality of bonding pads 33 may be disposed in the first lower insulating layer 30A. Each of the plurality of bonding pads 33 may contact an upper surface of a corresponding one of the plurality of buried contact plugs 32. The upper surfaces of the plurality of bonding pads 33 may be coplanar with the upper surface of the first lower insulating layer 30A. Each of the plurality of buried contact plugs 32 may contact a corresponding one of the plurality of source / drain regions 27.

[0051] Multiple first electrodes 35 may be disposed on the multiple bonding pads 33. For example, the lower surfaces of the multiple first electrodes 35 may contact the upper surfaces of the multiple bonding pads 33. A capacitor dielectric layer 36 may be disposed on the multiple first electrodes 35. A second electrode 37 may be disposed on the capacitor dielectric layer 36. The multiple first electrodes 35, the capacitor dielectric layer 36, and the second electrode 37 may constitute multiple unit capacitors. Each of the multiple first electrodes 35 may correspond to a lower electrode of a unit capacitor. Each of the multiple first electrodes 35 may be referred to as a storage electrode. The second electrode 37 may correspond to an upper electrode of a unit capacitor. The second electrode 37 may be referred to as a plate electrode. The second lower insulating layer 30B may cover the second electrodes 37.

[0052] Each of the plurality of unit capacitors may include various 3D capacitors. For example, each of the plurality of first electrodes 35 may include a pillar structure, a cylindrical structure (eg, a single pillar storage (OCS) structure), or a combination thereof.

[0053] Each of the gate dielectric layer 24 and the capacitor dielectric layer 36 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof. Each of the plurality of gate electrodes 25, the bit plugs 28, the bit lines 29, the plurality of buried contact plugs 32, the plurality of bonding pads 33, the plurality of first electrodes 35, and the second electrode 37 may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof. Each of the device isolation layer 23, the gate cap layer 26, the first lower insulating layer 30A, and the second lower insulating layer 30B may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0054] Figures 5 to 8 is a cross-sectional view for describing a semiconductor device according to an embodiment of the inventive concept. Figure 9 and Figure 10 It shows Figure 5 A magnified view of a portion of the .

[0055] Reference Figure 5 , a semiconductor device according to example embodiments of the inventive concept may include a substrate 21, a lower insulating layer 30, an interlayer insulating layer 40, a plurality of intermediate interconnections 45, a plurality of intermediate plugs 47, an upper insulating layer 50, a first upper plug 61, a first upper interconnection 65, a second upper plug 71, a second upper interconnection 75, and an opening 55W.

[0056] In example embodiments, each of the plurality of intermediate interconnects 45 and the plurality of intermediate plugs 47 may be formed using a damascene process. Each of the plurality of intermediate interconnects 45 and the plurality of intermediate plugs 47 may have an inverted trapezoidal shape having an upper lateral width greater than its lower lateral width. Each of the first upper interconnect 65 and the second upper interconnect 75 may be formed using a patterning process. Each of the first upper interconnect 65 and the second upper interconnect 75 may have a trapezoidal shape having an upper lateral width less than its lower lateral width. Each of the first upper plug 61 and the second upper plug 71 may have an inverted trapezoidal shape having an upper lateral width greater than its lower lateral width.

[0057] Reference Figure 6, the test opening 155W may include a first opening 155W1 and a second opening 155W2. The second opening 155W2 may be connected to the bottom of the first opening 155W1. The first upper interconnect 65 may be exposed at the bottom of the second opening 155W2. The first opening 155W1 may pass through the seventh upper insulating layer 55B and the sixth upper insulating layer 55A. The second opening 155W2 may pass through the third upper insulating layer 53C, the second upper insulating layer 53B, and the first upper insulating layer 53A.

[0058] Reference Figure 7 , the first upper insulating layer 53A, the second upper insulating layer 53B, the third upper insulating layer 53C, the sixth upper insulating layer 55A, and the seventh upper insulating layer 55B may be sequentially stacked on the first upper interconnection 65. The first upper insulating layer 53A, the second upper insulating layer 53B, the third upper insulating layer 53C, the sixth upper insulating layer 55A, and the seventh upper insulating layer 55B may completely cover the first upper interconnection 65.

[0059] Reference Figure 8 , the sixth upper insulating layer 55A and the seventh upper insulating layer 55B may be sequentially stacked on the second upper interconnection 75. The sixth upper insulating layer 55A and the seventh upper insulating layer 55B may completely cover the second upper interconnection 75.

[0060] Reference Figure 9The third intermediate plug 47C may include a seventh barrier layer BM1 and a fifth conductive layer CM1. The seventh barrier layer BM1 may surround the side surfaces and bottom of the fifth conductive layer CM1. The fourth intermediate interconnect 45D may include an eighth barrier layer BM2 and a sixth conductive layer CM2. The eighth barrier layer BM2 may surround the side surfaces and bottom of the sixth conductive layer CM2. The eighth barrier layer BM2 may be interposed between the fifth conductive layer CM1 and the sixth conductive layer CM2. For example, the upper surface of the eighth barrier layer BM2 may contact the lower surface of the sixth conductive layer CM2, and the lower surface of the eighth barrier layer BM2 may contact the upper surface of the fifth conductive layer CM1. Each of the fifth conductive layer CM1 and the sixth conductive layer CM2 may include a Cu layer. Each of the seventh barrier layer BM1 and the eighth barrier layer BM2 may include Ti, TiN, Ta, TaN, or a combination thereof. Each of the first intermediate plug 47A and the second intermediate plug 47B may have a similar configuration to that of the third intermediate plug 47C. For example, each of the first and second intermediate plugs 47A and 47B may include a conductive layer and a barrier layer surrounding the side and bottom surfaces of the conductive layer. Each of the first, second, and third intermediate interconnects 45A, 45B, and 45C may have a configuration similar to that of the fourth intermediate interconnect 45D. For example, each of the first, second, and third intermediate interconnects 45A, 45B, and 45C may include a conductive layer and a barrier layer surrounding the side and bottom surfaces of the conductive layer.

[0061] Reference Figure 10The third intermediate plug 47C may include a ninth barrier layer BM and a fifth conductive layer CM1. The fourth intermediate interconnect 45D may include a ninth barrier layer BM and a sixth conductive layer CM2. The fifth conductive layer CM1 may be integrally formed with the sixth conductive layer CM2. The sixth conductive layer CM2 may be materially continuous with the fifth conductive layer CM1. Each of the fifth conductive layer CM1 and the sixth conductive layer CM2 may include a Cu layer. The ninth barrier layer BM may surround the bottom and side surfaces of the fifth conductive layer CM1 and the sixth conductive layer CM2. The ninth barrier layer BM may include Ti, TiN, Ta, TaN, or a combination thereof. Each of the first and second intermediate plugs 47A and 47B may have a configuration similar to that of the third intermediate plug 47C. For example, each of the first and second intermediate plugs 47A and 47B may include a conductive layer and a barrier layer surrounding the bottom and side surfaces of the conductive layer. Each of the first, second, and third intermediate interconnects 45A, 45B, and 45C may have a configuration similar to that of the fourth intermediate interconnect 45D. For example, each of the second and third intermediate interconnects 45B and 45C may include a conductive layer materially continuous with the conductive layers of the first and second intermediate plugs 47A and 47B, respectively, and a barrier layer surrounding the bottom and side surfaces of the conductive layer. The first intermediate interconnect 45A may include a conductive layer and a barrier layer surrounding the bottom and side surfaces of the conductive layer.

[0062] Figures 11 to 13 is a cross-sectional view for describing a semiconductor device according to example embodiments of the inventive concept.

[0063] Reference Figure 11 The semiconductor device according to example embodiments of the inventive concepts may include a substrate 21, a lower insulating layer 30, a memory cell MC, a contact spacer 38, a through electrode 39, an interlayer insulating layer 40, a plurality of intermediate interconnections 45, a plurality of intermediate plugs 47, an upper insulating layer 50, a plurality of first upper plugs 61, a plurality of first upper interconnections 65, a plurality of second upper plugs 71, a plurality of second upper interconnections 75, an opening 55W, a first bump 89, a base insulating layer 91, and a protruding electrode 93. The first bump 89 may include a pillar structure 85 and a solder 87. The pillar structure 85 may include a barrier layer 81, a seed layer 82, and a pillar 83.

[0064] The first bump 89 may have a diameter of about 1 μm to about 50 μm. The first bump 89 may have a height of about 1 μm to about 70 μm. In an embodiment, the first bump 89 may have a diameter of about 10 μm to about 50 μm. In an embodiment, the first bump 89 may have a diameter of about 1 μm to about 40 μm. In an embodiment, the first bump 89 may have a height of about 10 μm to about 70 μm. In an embodiment, the first bump 89 may have a height of about 1 μm to about 60 μm.

[0065] The pillar structure 85 may be disposed on the upper insulating layer 50. For example, the bottom surface of the pillar structure 85 may contact the upper surface of the upper insulating layer 50. The pillar structure 85 may extend into the second group 55 of the upper insulating layer 50. For example, the pillar structure 85 may extend below the upper surface of the second group 55. The pillar structure 85 may pass through the second group 55 and may contact the upper surface of a corresponding one of the plurality of second upper interconnects 75. The barrier layer 81 may include Ti, TiN, Ta, TaN, or a combination thereof. The seed layer 82 may be disposed on the barrier layer 81. The seed layer 82 may include Cu. The pillar 83 may be disposed on the seed layer 82. For example, the lower surface of the pillar 83 may contact the upper surface of the seed layer 82, and the lower surface of the seed layer 82 may contact the upper surface of the barrier layer 81.

[0066] The pillar 83 may include nickel (Ni), copper (Cu), aluminum (Al), silver (Ag), platinum (Pt), ruthenium (Ru), tin (Sn), gold (Au), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. For example, the pillar 83 may include a Ni layer.

[0067] Solder 87 may be provided on pillar structure 85. Solder 87 may include Sn, Ag, Cu, Ni, Au, or a combination thereof. For example, solder 87 may include a Sn-Ag-Cu layer. An interface metal layer may be further formed between pillar structure 85 and solder 87, but its description will be omitted for brevity.

[0068] Reference Figure 12 , a semiconductor device according to an example embodiment of the inventive concept may include a substrate 21, a lower insulating layer 30, a contact spacer 38, a through electrode 39, an interlayer insulating layer 40, a plurality of intermediate interconnections 45, a plurality of intermediate plugs 47, an upper insulating layer 50, a plurality of first upper plugs 61, a plurality of first upper interconnections 65, a plurality of second upper plugs 71, a plurality of second upper interconnections 75, an opening 55W, a first bump 89, a base insulating layer 91 and a protruding electrode 93.

[0069] Reference Figure 13, a semiconductor device according to an example embodiment of the inventive concept may include a substrate 21, a lower insulating layer 30, an interlayer insulating layer 40, a plurality of intermediate interconnections 45, a plurality of intermediate plugs 47, an upper insulating layer 50, a plurality of first upper plugs 61, a plurality of first upper interconnections 65, a plurality of second upper plugs 71, a plurality of second upper interconnections 75, an opening 55W and a first bump 89.

[0070] Figure 14 and Figure 15 is a cross-sectional view for describing a semiconductor device according to example embodiments of the inventive concept. Figure 16 It shows Figure 14 and Figure 15 The semiconductor device according to the embodiment of the inventive concept may include a hybrid memory cube (HMC), a high bandwidth memory (HBM), a double data rate fifth generation (DDR5) DRAM, or a combination thereof.

[0071] Reference Figure 14 , a semiconductor device according to an example embodiment of the inventive concept may include a printed circuit board (PCB) PC, a relay substrate IP, a plurality of semiconductor chips CP, BD, and MD1 to MD4, a plurality of bumps 89, 489, 589, and 689, an adhesive layer 95, and an encapsulant 96. The plurality of semiconductor chips CP, BD, and MD1 to MD4 may include a microprocessor CP, a buffer chip BD, and a plurality of memory chips MD1 to MD4. In an example embodiment, the plurality of memory chips MD1 to MD4 may be sequentially and vertically stacked on the buffer chip BD. The plurality of memory chips MD1 to MD4 may include memory chips corresponding to various combinations of numbers such as three, four, seven, eight, eleven, twelve, fifteen, sixteen, nineteen, or more.

[0072] The plurality of memory chips MD1 to MD4 may include a first memory chip MD1, a second memory chip MD2, a third memory chip MD3, and a fourth memory chip MD4. At least some of the plurality of memory chips MD1 to MD4 may include a plurality of through electrodes 39. The plurality of bumps 89, 489, 589, and 689 may include a plurality of first bumps 89, a plurality of second bumps 489, a plurality of third bumps 589, and a plurality of fourth bumps 689.

[0073] The PCB PC may include a rigid PCB, a flexible PCB, or a rigid-flexible PCB. The PCB PC may include a multilayer circuit board. The PCB PC may correspond to a package substrate or a motherboard. A plurality of fourth bumps 689 may be provided on the lower surface of the PCB PC. A relay substrate IP may be provided on the PCB PC. A plurality of third bumps 589 may be provided between the PCB PC and the relay substrate IP.

[0074] A plurality of semiconductor chips CP, BD, and MD1 to MD4 may be arranged on a relay substrate IP. The relay substrate IP may include a semiconductor substrate such as a silicon interposer. In an example embodiment, a microprocessor CP and a buffer chip BD may be arranged on the relay substrate IP. A plurality of second bumps 489 may be arranged between the microprocessor CP and the relay substrate IP and between the buffer chip BD and the relay substrate IP. The microprocessor CP may include various processors such as a graphics processing unit (GPU) or an application processor (AP). The buffer chip BD may include various elements such as a memory controller. The buffer chip BD may be connected to the microprocessor CP via the relay substrate IP and the plurality of second bumps 489.

[0075] A plurality of memory chips MD1 to MD4 may be sequentially stacked on the buffer chip BD. Each of the plurality of memory chips MD1 to MD4 may include a reference Figures 1 to 13 For example, each of the plurality of memory chips MD1 to MD4 may correspond to the reference Figures 1 to 13 1. The semiconductor device shown. In some embodiments, each of the plurality of memory chips MD1 to MD4 may include a plurality of first bumps 89. In example embodiments, an adhesive layer 95 may be provided between the plurality of memory chips MD1 to MD4 and between the first memory chip MD1 and the buffer chip BD. The adhesive layer 95 may include a non-conductive film (NCF).

[0076] A plurality of first bumps 89 may be provided between the plurality of memory chips MD1 to MD4 and between the first memory chip MD1 and the buffer chip BD. The plurality of first bumps 89 may extend into the adhesive layer 95. The plurality of first bumps 89 may pass through the adhesive layer 95. The plurality of memory chips MD1 to MD4 may be connected to the buffer chip BD via the plurality of first bumps 89 and the plurality of through electrodes 39. An encapsulant 96 may be provided on the buffer chip BD to cover the plurality of memory chips MD1 to MD4. The encapsulant 96 may include epoxy molding compound (EMC).

[0077] In an exemplary embodiment, the buffer chip BD may represent a master chip. Each of the plurality of memory chips MD1 to MD4 may represent a slave chip. In an exemplary embodiment, the first memory chip MD1 may represent a master chip. Each of the second memory chip MD2, the third memory chip MD3, and the fourth memory chip MD4 may represent a slave chip.

[0078] Reference Figure 15 , a semiconductor device according to example embodiments of the inventive concepts may include a plurality of memory chips MD1 to MD4 sequentially stacked on a package substrate PC2 .

[0079] The package substrate PC2 may include a PCB such as a rigid PCB, a flexible PCB, or a rigid-flexible PCB. The plurality of memory chips MD1 to MD4 may include a first memory chip MD1, a second memory chip MD2, a third memory chip MD3, and a fourth memory chip MD4. An adhesive layer 95 may be provided between the plurality of memory chips MD1 to MD4 and between the first memory chip MD1 and the package substrate PC2. The adhesive layer 95 may include NCF.

[0080] Multiple memory chips MD1 to MD4 can be connected to the package substrate PC2 via multiple first bumps 89 and multiple through electrodes 39. An encapsulant 96 can be provided on the package substrate PC2 to cover the multiple memory chips MD1 to MD4. The encapsulant 96 may include EMC. Multiple second bumps 489 can be provided on the lower surface of the package substrate PC2. In an exemplary embodiment, the first memory chip MD1 can represent a master chip. Each of the second memory chip MD2, the third memory chip MD3, and the fourth memory chip MD4 can represent a slave chip.

[0081] Reference Figure 16 The third memory chip MD3 may include a substrate 21, a lower insulating layer 30, a contact spacer 38, a through electrode 39, an interlayer insulating layer 40, a plurality of intermediate interconnections 45, a plurality of intermediate plugs 47, an upper insulating layer 50, a plurality of first upper plugs 61, a plurality of first upper interconnections 65, a plurality of second upper plugs 71, a plurality of second upper interconnections 75, a first bump 89, a substrate insulating layer 91 and a protruding electrode 93.

[0082] The second memory chip MD2 may include a configuration similar to that of the third memory chip MD3. The solder 87 of the third memory chip MD3 may adhere to the protruding electrode 93 of the second memory chip MD2. The solder 87 of the fourth memory chip MD4 may adhere to the protruding electrode 93 of the third memory chip MD3.

[0083] Figures 17 to 21 are cross-sectional views for describing a method of forming a semiconductor device according to an embodiment of the inventive concept.

[0084] Reference Figure 17 , a lower insulating layer 30 may be formed on the substrate 21. Contact spacers 38 and through electrodes 39 may be formed through the lower insulating layer 30 and the substrate 21. An interlayer insulating layer 40, a plurality of intermediate interconnections 45, and a plurality of intermediate plugs 47 may be formed on the lower insulating layer 30.

[0085] The plurality of intermediate interconnects 45 may include a first intermediate interconnect 45A, a plurality of second intermediate interconnects 45B, a plurality of third intermediate interconnects 45C, and a plurality of fourth intermediate interconnects 45D. The plurality of intermediate plugs 47 may include a plurality of first intermediate plugs 47A, a plurality of second intermediate plugs 47B, and a plurality of third intermediate plugs 47C. The plurality of intermediate interconnects 45 and the plurality of intermediate plugs 47 may be formed in the interlayer insulating layer 40. The first intermediate interconnect 45A may contact the through-electrode 39. The formation of the plurality of intermediate interconnects 45 and the plurality of intermediate plugs 47 may include a plurality of damascene processes.

[0086] A first group 53, a plurality of first upper plugs 61, and a plurality of first upper interconnections 65 may be formed on the interlayer insulating layer 40. The first group 53 may include a first upper insulating layer 53A, a second upper insulating layer 53B, a third upper insulating layer 53C, a fourth upper insulating layer 53D, and a fifth upper insulating layer 53E.

[0087] A fourth upper insulating layer 53D and a fifth upper insulating layer 53E may be sequentially stacked on the interlayer insulating layer 40. Each of the plurality of first upper plugs 61 may pass through the fifth upper insulating layer 53E and the fourth upper insulating layer 53D and may contact a corresponding one of the plurality of fourth intermediate interconnects 45D. Each of the plurality of first upper plugs 61 may include a first conductive layer 61B and a first barrier layer 61A configured to surround the side surface and bottom of the first conductive layer 61B.

[0088] A plurality of first upper interconnects 65 may be formed on the fifth upper insulating layer 53E. The formation of the plurality of first upper interconnects 65 may include a patterning process. At least one of the plurality of first upper interconnects 65 may contact the plurality of first upper plugs 61. Each of the plurality of first upper interconnects 65 may include a second barrier layer 65A, a second conductive layer 65B disposed on the second barrier layer 65A, and a third barrier layer 65C disposed on the second conductive layer 65B.

[0089] A first upper insulating layer 53A may be formed on the fifth upper insulating layer 53E. The first upper insulating layer 53A may cover the upper and side surfaces of the plurality of first upper interconnects 65. A second upper insulating layer 53B may be formed on the first upper insulating layer 53A. The second upper insulating layer 53B may correspond to a capping layer. The second upper insulating layer 53B may control degassing of lower layers during the annealing process. A third upper insulating layer 53C may be formed on the second upper insulating layer 53B. The upper surface of the third upper insulating layer 53C may be planarized.

[0090] In example embodiments, the first upper insulating layer 53A may include an oxide layer such as HDP oxide. The second upper insulating layer 53B may include a material different from that of the first upper insulating layer 53A. The second upper insulating layer 53B may include a nitride layer such as silicon nitride. The third upper insulating layer 53C may include an oxide layer formed using TEOS or FTEOS.

[0091] Reference Figure 18 A plurality of contact holes 71H may be formed through the third upper insulating layer 53C, the second upper insulating layer 53B, and the first upper insulating layer 53A using a patterning process. Upper surfaces of the plurality of first upper interconnections 65 may be exposed at the bottoms of the plurality of contact holes 71H.

[0092] Reference Figure 19 A plurality of second upper plugs 71 may be formed inside the plurality of contact holes 71H. Each of the plurality of second upper plugs 71 may include a third conductive layer 71B and a fourth barrier layer 71A surrounding a side surface and a bottom of the third conductive layer 71B.

[0093] Reference Figure 20 , a second upper interconnection 75 may be formed on the third upper insulating layer 53C, and the second upper interconnection 75 may contact the plurality of second upper plugs 71. The formation of the second upper interconnection 75 may include a patterning process. The second upper interconnection 75 may include a fifth barrier layer 75A, a fourth conductive layer 75B disposed on the fifth barrier layer 75A, and a sixth barrier layer 75C disposed on the fourth conductive layer 75B.

[0094] Reference Figure 21 , a sixth upper insulating layer 55A may be formed on the third upper insulating layer 53C. The sixth upper insulating layer 55A may cover the side surfaces and the upper surface of the second upper interconnection 75. A seventh upper insulating layer 55B may be formed on the sixth upper insulating layer 55A. An opening 55W may be formed through the seventh upper insulating layer 55B and the sixth upper insulating layer 55A. A portion of the second upper interconnection 75 may be exposed at the bottom of the opening 55W.

[0095] According to example embodiments of the inventive concept, the configuration of multiple intermediate interconnects, multiple first upper plugs, multiple first upper interconnects, multiple second upper plugs, and multiple second upper interconnects can significantly reduce interconnect resistance. The configuration of the first upper insulating layer, the second upper insulating layer, and the third upper insulating layer can improve interlayer insulation characteristics. The second upper insulating layer can improve the electrical characteristics and reliability of multiple active / passive components disposed in the lower insulating layer and / or the interlayer insulating layer. A semiconductor device having simplified processing, excellent current drive capability, and high signal transmission rate can be realized.

[0096] Although the embodiments of the inventive concept have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications may be made without departing from the scope of the inventive concept and without changing its essential features. Therefore, the embodiments described above should be considered in a descriptive sense only and not for purposes of limitation.

Claims

1. A semiconductor device, comprising: an interlayer insulating layer, disposed on the substrate; a plurality of intermediate interconnects disposed in the interlayer insulating layer; a plurality of middle plugs disposed in the interlayer insulating layer and between the plurality of middle interconnections; an upper insulating layer, disposed on the interlayer insulating layer; a first upper plug disposed in the upper insulating layer and connected to one of the plurality of intermediate interconnections, the one intermediate interconnection having a first thickness; a first upper interconnect disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness; a second upper plug disposed in the upper insulating layer on the first upper interconnect; a second upper interconnect disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; an opening configured to penetrate the upper insulating layer to expose a portion of the second upper interconnection; and a bump disposed on the upper insulating layer, extending into the opening and contacting the second upper interconnection, The upper surface of the second upper interconnection includes a first portion and a second portion, the first portion is covered by the upper insulating layer, and the second portion is exposed by the opening. wherein the upper insulating layer includes a first upper insulating layer, a second upper insulating layer, and a third upper insulating layer sequentially disposed between the first upper interconnection and the second upper interconnection, The first upper insulating layer contacts the upper surface of the first upper interconnection, and the third upper insulating layer contacts the lower surface of the second upper interconnection. wherein the third thickness is in a range of 2 to 100 times the first thickness, and The second upper interconnection includes a material different from a material of the second upper plug.

2. The semiconductor device according to claim 1, wherein The third thickness is greater than or equal to the second thickness.

3. The semiconductor device according to claim 1, wherein The third thickness is in the range of 2 μm to 10 μm.

4. The semiconductor device according to claim 1, in, Each of the plurality of intermediate plugs has a first height, wherein the first upper plug has a second height greater than the first height, and The second upper plug has a third height greater than the first height.

5. The semiconductor device according to claim 4, wherein The third height is greater than or equal to the second height. The semiconductor device according to claim 1 , wherein: Each of the first upper interconnection and the second upper interconnection includes a material layer different from a material layer of the plurality of intermediate interconnections.

7. The semiconductor device according to claim 6, in, The plurality of intermediate interconnects include a copper layer, and Wherein, the second upper interconnection comprises an aluminum layer.

8. The semiconductor device according to claim 6, wherein The first upper interconnection includes an aluminum layer.

9. The semiconductor device according to claim 6, wherein The second upper plug includes a tungsten layer.

10. The semiconductor device according to any one of claims 1 to 9, wherein The second upper plug passes through the first upper insulating layer, the second upper insulating layer, and the third upper insulating layer and contacts the first upper interconnection and the second upper interconnection.

11. The semiconductor device according to claim 10, in, The first upper insulating layer includes an oxide layer, Wherein, the second upper insulating layer includes a nitride layer, and Wherein, the third upper insulating layer includes an oxide layer. 12 . The semiconductor device according to claim 1 , further comprising a through-electrode extending into the substrate and connected to the plurality of intermediate interconnections.

13. The semiconductor device according to claim 12, wherein The through-electrode has a diameter of 1 μm to 20 μm.

14. The semiconductor device according to claim 1, further comprising: a lower insulating layer, disposed between the substrate and the interlayer insulating layer; as well as The memory cell is disposed in the lower insulating layer.

15. The semiconductor device according to claim 14, wherein The memory cell includes a dynamic random access memory cell, a static random access memory cell, a flash memory cell, a magnetoresistive random access memory cell, a phase change random access memory cell, a ferroelectric random access memory cell, a resistance random access memory cell, or a combination thereof.

16. A semiconductor device comprising a plurality of semiconductor chips sequentially stacked on a printed circuit board, in, At least one of the plurality of semiconductor chips comprises: a lower insulating layer, disposed on the substrate; a memory cell disposed in the lower insulating layer; an interlayer insulating layer, disposed on the lower insulating layer; a plurality of intermediate interconnects disposed in the interlayer insulating layer; a plurality of middle plugs disposed in the interlayer insulating layer and between the plurality of middle interconnections; an upper insulating layer, disposed on the interlayer insulating layer; a first upper plug disposed in the upper insulating layer and connected to one of the plurality of intermediate interconnections, the one intermediate interconnection having a first thickness; a first upper interconnect disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness; a second upper plug disposed in the upper insulating layer and on the first upper interconnection; a second upper interconnect disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; an opening configured to penetrate the upper insulating layer to expose a portion of the second upper interconnection; a bump disposed on the upper insulating layer, extending into the opening, and contacting the second upper interconnection; and a through-electrode extending into the substrate and connected to the plurality of intermediate interconnects, The upper surface of the second upper interconnection includes a first portion and a second portion, the first portion is covered by the upper insulating layer, and the second portion is exposed by the opening. wherein the upper insulating layer includes a first upper insulating layer, a second upper insulating layer, and a third upper insulating layer sequentially disposed between the first upper interconnection and the second upper interconnection, The first upper insulating layer contacts the upper surface of the first upper interconnection, and the third upper insulating layer contacts the lower surface of the second upper interconnection. wherein the third thickness is in a range of 2 to 100 times the first thickness, and The second upper interconnection includes a material different from a material of the second upper plug.

17. The semiconductor device according to claim 16, wherein The bumps have a diameter of 10 μm to 50 μm.

18. The semiconductor device according to claim 16, wherein The third thickness is greater than or equal to the second thickness.

19. The semiconductor device according to claim 16, in, Each of the plurality of intermediate plugs has a first height, wherein the first upper plug has a second height greater than the first height, and The second upper plug has a third height greater than the first height.

20. A semiconductor device, comprising: relay substrate; A microprocessor is provided on the relay substrate; A buffer chip is provided on the relay substrate; as well as Multiple semiconductor chips are sequentially stacked on the buffer chip. Wherein, at least one of the plurality of semiconductor chips comprises: a lower insulating layer, disposed on the substrate; a memory cell disposed in the lower insulating layer; an interlayer insulating layer, disposed on the lower insulating layer; a plurality of intermediate interconnects disposed in the interlayer insulating layer; a plurality of middle plugs disposed in the interlayer insulating layer and between the plurality of middle interconnections; an upper insulating layer, disposed on the interlayer insulating layer; a first upper plug disposed in the upper insulating layer and connected to one of the plurality of intermediate interconnections, the one intermediate interconnection having a first thickness; a first upper interconnect disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness; a second upper plug disposed in the upper insulating layer and on the first upper interconnection; a second upper interconnect disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; an opening configured to penetrate the upper insulating layer to expose a portion of the second upper interconnection; a bump disposed on the upper insulating layer, extending into the opening, and contacting the second upper interconnection; and a through-electrode extending into the substrate and connected to the plurality of intermediate interconnects, The upper surface of the second upper interconnection includes a first portion and a second portion, the first portion is covered by the upper insulating layer, and the second portion is exposed by the opening. wherein the upper insulating layer includes a first upper insulating layer, a second upper insulating layer, and a third upper insulating layer sequentially disposed between the first upper interconnection and the second upper interconnection, The first upper insulating layer contacts the upper surface of the first upper interconnection, and the third upper insulating layer contacts the lower surface of the second upper interconnection. wherein the third thickness is in a range of 2 to 100 times the first thickness, and The second upper interconnection includes a material different from a material of the second upper plug.

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