Integrated circuit and method for forming the same

Abstract

An integrated circuit and a method for forming the same, the integrated circuit comprising an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying the substrate. A first dielectric layer overlies the uppermost surface of the interconnect structure. The first dielectric layer has opposite sidewalls, the opposite sidewalls defining a groove. A first magnetic layer is disposed in the groove and conformally extends along the opposite sidewalls. A conductive wiring is disposed in the groove and overlies the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wiring. The second magnetic layer extends laterally from above a first sidewall of the opposite sidewalls to a second sidewall of the opposite sidewalls.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit and a method for forming the same. Background Art

[0002] An integrated circuit (IC) is an assembly of electronic components on a single piece of semiconductor material. A widely used electronic component in integrated circuits is the inductor. An inductor is a passive element that stores electrical energy in a magnetic field when an electric current flows through the inductor. Since any conductor of electric current has inductive properties, the design of inductors varies greatly. Inductors are multifunctional devices that can be used in, among other things, resistor-inductor (RL) filters, inductor-capacitor (LC) circuits, resistor-inductor-capacitor (RLC) circuits, power supplies, transformers, and many other circuit components. Summary of the invention

[0003] An embodiment of the present invention provides an integrated circuit, which includes a substrate, an interconnect structure, a first dielectric layer, a first magnetic layer, a conductive wiring, and a second magnetic layer. The interconnect structure has a plurality of metal layers disposed on the substrate. The first dielectric layer is disposed on the uppermost surface of the interconnect structure, wherein the first dielectric layer has opposite sidewalls defining a groove. The first magnetic layer is disposed in the groove and conformally extends along the opposite sidewalls. The conductive wiring is disposed in the groove and overlies the first magnetic layer. The second magnetic layer overlies the first magnetic layer and the conductive wiring, wherein the second magnetic layer extends laterally from above a first sidewall of the opposite sidewalls to a second sidewall of the opposite sidewalls.

[0004] An embodiment of the present invention provides an integrated circuit, which includes a substrate, an interconnect structure, a passivation layer, a first dielectric layer, a first etch stop layer, a first magnetic layer, a first conductive wiring and a second conductive wiring, a second dielectric layer and a second magnetic layer. The interconnect structure has a plurality of metal layers overlying the substrate. The passivation layer overlies the interconnect structure. The first dielectric layer has inclined opposite sidewalls, and the inclined opposite sidewalls define a groove overlying the passivation layer. The first etch stop layer extends along the top surface of the first dielectric layer and the inclined opposite sidewalls. The first magnetic layer overlies the first etch stop layer and is disposed in the groove. The first conductive wiring and the second conductive wiring are disposed in the groove and overlying the first magnetic layer, wherein the first conductive wiring and the second conductive wiring extend parallel to each other along a first direction parallel to the upper surface of the substrate. The second dielectric layer fills the groove and surrounds the first conductive wiring and the second conductive wiring. The second magnetic layer is disposed on the first magnetic layer and the second dielectric layer, wherein the first magnetic layer and the second magnetic layer surround the first conductive wire and the second conductive wire and extend laterally in a first direction along middle sections of the first conductive wire and the second conductive wire.

[0005] An embodiment of the present invention provides a method for forming an integrated circuit, which includes: forming an interconnect structure having multiple metal layers on a substrate; forming a passivation layer on the uppermost surface of the interconnect structure; forming a first dielectric layer on the passivation layer, wherein the first dielectric layer has sidewalls defining a groove; forming a first magnetic layer on the passivation layer, wherein the first magnetic layer is lined with the groove and extends above the top surface of the first dielectric layer; forming conductive wirings spaced apart from each other on the first magnetic layer; forming a second dielectric layer on the conductive wirings, wherein the second dielectric layer at least partially fills the grooves; and forming a second magnetic layer on the second dielectric layer and the first magnetic layer, wherein the second magnetic layer has a substantially flat upper surface extending continuously between the sidewalls of the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A cross-sectional view of some embodiments of an integrated circuit (IC) is shown that includes an inductor structure recessed into a first dielectric layer.

[0008] Figure 2 Shown along the cutting line A-A' Figure 1 Top views of some alternative embodiments of integrated circuits are shown.

[0009] Figure 3Cross-sectional views of some embodiments of an integrated circuit are shown that include an inductor structure recessed into a first dielectric layer and an input / output (I / O) structure electrically coupled to the inductor structure.

[0010] Figure 4 Show according to Figure 1 Cross-sectional views of integrated circuits illustrating some alternative embodiments of the integrated circuit are shown.

[0011] Figure 5 A cross-sectional view of an integrated circuit is shown, the integrated circuit including an inductor structure recessed into a first dielectric layer and overlying an interconnect structure.

[0012] Figures 6 to 15 Cross-sectional views of some embodiments of a first method of forming an inductor structure recessed into a first dielectric layer are shown.

[0013] Figure 16 to Figure 18 Cross-sectional views of some embodiments of a second method of forming an inductor structure recessed into a first dielectric layer are shown.

[0014] Fig.19 A method is shown in flow chart form that illustrates some embodiments of a method of forming an inductor structure recessed into a first dielectric layer. DETAILED DESCRIPTION

[0015] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] In addition, for ease of description, "first", "second", "third", etc. may be used herein to distinguish different elements of a figure or a series of figures. "First", "second", "third", etc. are not intended to describe corresponding elements, but are merely general identifiers. For example, the "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to the "first dielectric layer" described in conjunction with some embodiments, but may correspond to the "second dielectric layer" in other embodiments.

[0018] Some inductors are monolithically integrated on a semiconductor substrate. In some embodiments, the integrated inductor is formed in a back-end-of-the-line (BEOL) metal interconnect layer above the substrate. Since any conductor of electric current has inductive properties, the integrated inductor is implemented in various layouts (e.g., spiral inductors, planar spiral inductors, linear inductors, or coupled inductors). In addition, depending on the application, the integrated inductor may include, for example, a dielectric material core (e.g., an air core), a ferromagnetic core, or a ferrimagnetic core. For example, an integrated spiral inductor may include a magnetic core arranged in a first metal layer. The metal wiring may be wound around the magnetic core in a spiral pattern so that the metal wiring has multiple turns extending continuously around the magnetic core.

[0019] The challenge of the above-mentioned inductors is to provide consumers with inductors that precisely meet their needs. Consumers often design integrated circuits (ICs) that require inductors. These integrated circuits are designed to operate with specific inductances. Typically, integrated circuit manufacturers implement inductors into consumers' integrated circuits. However, since each specific integrated circuit application requires a specific inductor to optimize operation, manufacturers typically implement pre-designed inductors with specific inductances. This pre-designed inductor may have an inductance of a fixed value, which may be greater than / less than the inductance required by the consumer's integrated circuit. This difference in inductance may increase the total resistance of the consumer's integrated circuit and cause the consumer's integrated circuit to operate less than optimally. A partial solution to this challenge is to design an integrated circuit-specific inductor that can provide a variable inductance option when the integrated circuit requires an inductor.

[0020] In some embodiments, an integrated circuit-specific inductor overlies an etch stop layer, which overlies a passivation layer. The passivation layer overlies an internal connection structure. The integrated circuit-specific inductor includes two conductive wires extending parallel to each other along an upper surface of the etch stop layer, wherein the upper surface of the etch stop layer is substantially flat. A magnetic shielding structure continuously wraps around at least a middle section of the two conductive wires and is separated from the two conductive wires by a dielectric structure. The dielectric structure insulates the two conductive wires from each other and has an upper surface with a semicircular shape. The magnetic shielding structure includes a first magnetic layer located below a second magnetic layer. The first magnetic layer is disposed between the etch stop layer and the conductive wires, and the second magnetic layer conforms to the semicircular shape of the dielectric structure. Therefore, the top surface of the second magnetic layer is offset in a vertical direction relative to the upper surface of the etch stop layer by a relatively large step height (e.g., greater than 35 microns).

[0021] The challenges of the integrated circuit dedicated inductor described above relate to the manufacturing steps for forming the integrated circuit dedicated inductor and the relatively large step height. For example, during the manufacture of the inductor, an upper etch stop layer is formed on the first magnetic layer. Due to the shape of the first magnetic layer (e.g., a trapezoidal shape) and the short length of the sidewalls of the first magnetic layer, the upper etch stop layer may be delaminated with the first magnetic layer. This may cause delamination in the overlying structure and / or layer during subsequent processing steps, thereby causing failure of the integrated circuit dedicated inductor. In another example, since the conductive wiring is overlying on the top surface of the etch stop layer and the dielectric structure encloses the conductive wiring, it may be difficult to control the thickness and shape of the dielectric structure (e.g., due to the limitations of the tools used to make the integrated circuit). Therefore, the dielectric structure and the second magnetic layer may have a semicircular shape, which may cause the integrated circuit to have an undulated upper surface, thereby producing a relatively large step height (e.g., greater than 35 microns). This may reduce the ability to bond the bump structure of the integrated circuit (which overlies the conductive wiring and is electrically coupled to the conductive wiring) to an external device (e.g., an external integrated circuit). Additionally, this may reduce the number of IC-specific inductors that may be disposed over the interconnect structures and / or increase the time, complexity, and cost associated with fabricating the IC-specific inductors.

[0022] In some embodiments, the present disclosure relates to an integrated circuit inductor embedded in a dielectric structure, thereby alleviating problems associated with the manufacturing steps and reducing the step height (e.g., to less than 15 microns). A first dielectric layer overlies the interconnect structure. An etch stop layer overlies the upper surface of the first dielectric layer and lines a trench disposed in the first dielectric layer. A first magnetic layer also lines the trench above the etch stop layer and has a top surface extending above the top surface of the first dielectric layer. A conductive wire is disposed above the upper surface of the first magnetic layer in the trench, such that the top surface of the conductive wire is below the top surface of the first magnetic layer. A second dielectric layer surrounds the conductive wire and at least partially fills the trench. The second magnetic layer overlies the second dielectric layer and the first magnetic layer, such that the top surface of the second magnetic layer is substantially flat. The top surface of the second magnetic layer is offset in a vertical direction relative to the top surface of the etch stop layer by a relatively small step height (e.g., less than 15 microns). By forming at least a portion of the integrated circuit inductor (e.g., the conductive wiring and the first magnetic layer) in the trench of the first dielectric layer, the shape and / or size of the integrated circuit inductor can be more easily controlled. In addition, the step height of the integrated circuit inductor can be reduced. This, in part, improves the control of the shape and size of the integrated circuit inductor and / or reduces the time, complexity, and cost associated with making the integrated circuit inductor.

[0023] Figure 1A cross-sectional view of some embodiments of an integrated circuit (IC) 100 is shown that includes an inductor structure 109 recessed into a first dielectric layer 110 .

[0024] The integrated circuit 100 includes an interconnect structure 103 overlying a substrate 102. The substrate 102 may include one or more semiconductor devices (e.g., transistors, resistors, diodes, etc.) or portions of semiconductor devices. In some embodiments, the one or more semiconductor devices are disposed on / in the substrate 102 by a front-end-of-line (FEOL) process. For example, the semiconductor device may be a transistor, the transistor including a gate stack (e.g., a metal gate disposed on a high-k dielectric), the gate stack disposed on the substrate 102 and between source / drain regions disposed in the substrate 102.

[0025] In some embodiments, the interconnect structure 103 is formed by a back-end-of-line (BEOL) process. The interconnect structure 103 may include a plurality of conductive features, such as conductive contacts, conductive lines, and / or vias disposed in an inter-level dielectric (ILD) material. In some embodiments, the interconnect structure 103 may include a plurality of metal layers (e.g., metal layer 1, metal layer 2, etc.) disposed on top of each other. Each metal layer may include a conductive line, and a via may connect a conductive line of a first metal layer to a conductive line of a second metal layer.

[0026] The passivation layer 104 overlies the interconnect structure 103. In some embodiments, the passivation layer 104 is formed by a BEOL process. The passivation layer 104 may conformally line the uppermost surface of the interconnect structure 103. In some embodiments, the passivation layer 104 has a substantially flat top surface. The passivation layer 104 may be, for example, or may include silicon dioxide, silicon nitride, a polyimide compound, or other suitable materials. In some embodiments, some conductive lines connect the connection vias to contact pads (not shown) disposed in the passivation layer 104.

[0027] In some embodiments, the first dielectric layer 110 overlies the passivation layer 104 and has sidewalls defining the trench 110t. The first etch stop layer 114 overlies the upper surface of the first dielectric layer 110 and lines at least a portion of the trench 110t. In addition, the first etch stop layer 114 extends along the upper surface of the passivation layer 104 and along the sidewalls of the first dielectric layer 110. The first magnetic layer 112 overlies the first etch stop layer 114 and fills a portion of the trench 110t, wherein the first magnetic layer 112 conforms to the sidewalls of the first dielectric layer 110 defining the trench 110t. In some embodiments, the first magnetic layer 112 may be, for example, or may include a magnetic material, such as Cobalt Zirconium Tantalum (CZT), iron-nickel (NiFe) compound, or other suitable magnetic materials.

[0028] The first conductive wire 116a and the second conductive wire 116b are disposed in the trench 110t of the first dielectric layer 110 and overlying the first magnetic layer 112. In some embodiments, the first conductive wire 116a and the second conductive wire 116b define an inductor unit having an inductance value. The first conductive wire 116a and the second conductive wire 116b each include a conductive material, such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), Al-Cu compound, or any other suitable conductive material. In some embodiments, the first conductive wire 116a and the second conductive wire 116b may be a post-passivation copper interconnect (e.g., formed after BEOL processing and / or after the formation of the passivation layer 104).

[0029] In some embodiments, the barrier seed layer 118 overlies the first isolation layer 120, so that the barrier seed layer 118 and the first isolation layer 120 physically separate and electrically isolate the first conductive wire 116a and the second conductive wire 116b from the first magnetic layer 112. The second dielectric layer 115 is disposed in the trench 110t and surrounds the first conductive wire 116a and the second conductive wire 116b. In some embodiments, the second dielectric layer 115 is configured to electrically isolate the first conductive wire 116a and the second conductive wire 116b from adjacent conductive layers and / or structures (e.g., the first magnetic layer 112). The second isolation layer 128 overlies the second dielectric layer 115 and the first magnetic layer 112. The second etch stop layer 126 overlies the upper surface of the second isolation layer 128 and lines the upper surface of the second isolation layer 128. The second magnetic layer 124 overlies the second etch stop layer 126 and extends in the lateral direction above the first magnetic layer 112. In some embodiments, the second magnetic layer 124 may be, for example, or may include a magnetic material such as cobalt zirconium tantalum (CZT), iron-nickel (NiFe) compounds, or other suitable magnetic materials. The upper dielectric layer 122 overlies the second magnetic layer 124. In some embodiments, the upper dielectric layer 122 has a substantially flat upper surface. In some embodiments, the second magnetic layer 124 has a substantially flat upper surface and / or a substantially flat top surface (e.g., a flat upper surface within the tolerance of a chemical mechanical planarization (CMP) process or within the tolerance of an etching process). For example, in some embodiments, at any point, the height of the upper surface of the second magnetic layer 124 varies within a range of -50 angstroms and +50 angstroms relative to a level horizontal line 113, which is located between the substantially flat upper surface of the second magnetic layer 124 and the lower surface of the upper dielectric layer 122. In other embodiments, at any point, the height of the upper surface of the second magnetic layer 124 varies within a range of -25 angstroms to +25 angstroms relative to the contour level 113. In still other embodiments, at any point, the height of the upper dielectric layer 122 varies within a range of approximately +10% to -10% of the thickness of the upper dielectric layer 122 relative to the contour level 113.

[0030] During operation of the inductor structure 109, in some embodiments, when a first current i1 passes through the first conductive wiring 116a, the first conductive wiring 116a induces a first magnetic field 130. When a second current i2 passes through the second conductive wiring 116b, the second conductive wiring 116b induces a second magnetic field 132. Depending on the current flow direction of the first current i1 and / or the second current i2, the first magnetic field 130 and / or the second magnetic field 132 will be induced based on the "right-hand rule". For example, in some embodiments, the circuit is configured to provide the first current i1 through the first conductive wiring 116a so that the first current i1 flows out of the page (depicted by a black dot surrounded by a circle), and provide the second current i2 through the second conductive wiring 116b so that the second current i2 flows into the page (depicted by an X surrounded by a circle). Therefore, the first magnetic field 130 is induced around the first conductive wiring 116a, and the second magnetic field 132 is induced around the second conductive wiring 116b. Therefore, the inductor structure 109 has a measurable inductance. In some embodiments, the first magnetic layer 112 and the second magnetic layer 124 shield the first magnetic field 130 and the second magnetic field 132 to concentrate the magnetic flux of the inductor structure 109 near the first conductive wire 116a and the second conductive wire 116b.

[0031] Since the first conductive wiring 116a and the second conductive wiring 116b are disposed in the trench 110t, the substantially flat upper surface of the second magnetic layer 124 is offset in the vertical direction by a step height h1 relative to the top surface of the first etch stop layer 114. This facilitates easy design and fabrication of the shape and size of the second dielectric layer 115 and the second magnetic layer 124, thereby reducing the time and cost associated with forming the integrated circuit 100. Since the first magnetic layer 112 is lined with the trench 110t, delamination of the first magnetic layer 112 with the second isolation layer 128 and / or the second etch stop layer 126 is reduced. Therefore, delamination of the first magnetic layer 112 with adjacent layers can be reduced and / or eliminated, thereby improving the performance, endurance, and reliability of the inductor structure 109.

[0032] The step height h1 may be, for example, in the range of about 0 microns to 15 microns. In some embodiments, if the step height h1 is less than 0 microns, the second magnetic layer 124 may be disposed in a trench 110t defined in the first dielectric layer 110. This may improve the structural integrity of the inductor structure 109, but may also increase the complexity, cost, and time associated with the fabrication of the integrated circuit 100. In other embodiments, if the step height h1 is less than 15 microns and greater than 0 microns, the design and fabrication of the shape and size of the second magnetic layer 124 may be more easily achieved while preventing and / or mitigating delamination of the first magnetic layer 112. This may improve the structural integrity, reliability, and durability of the inductor structure 109.

[0033] Figure 2 Shown along the cutting line A-A' Figure 1 A top view 200 of some alternative embodiments of the integrated circuit 100 is shown. It should be noted that the examples of 202 and 206 are shown in FIG. Figure 3 is shown in cross section and in Figure 1 Not shown in FIG.

[0034] The second magnetic layer 124 continuously extends across the middle sections of the first conductive wiring 116a and the second conductive wiring 116b. Figure 1 112) is located directly below the second magnetic layer 124. The first conductive wire 116a extends from the first input / output (I / O) structure 202 of the inductor structure 109 to the second input / output structure 204. In some embodiments, the first conductive wire 116a extends continuously from the first input / output structure 202 to the second input / output structure 204 in a substantially straight line. In other embodiments, the first conductive wire 116a extends continuously from the first input / output structure 202 to the second input / output structure 204 in a helical pattern around the first magnetic layer 112. The second conductive wire 116b extends from the third input / output structure 206 of the inductor structure 109 to the fourth input / output structure 208. In some embodiments, the second conductive wire 116b extends continuously from the third input / output structure 206 to the fourth input / output structure 208 in a substantially straight line. In other embodiments, the second conductive wire 116 b extends continuously from the third input / output structure 206 to the fourth input / output structure 208 in a spiral pattern around the first magnetic layer 112 .

[0035] During operation of the inductor structure 109, the first current i1 flows from the first input / output structure 202 to the second input / output structure 204 through the first conductive wiring 116a, thereby inducing a first magnetic field ( Figure 1130). The second current i2 flows from the third input / output structure 206 to the fourth input / output structure 208 through the second conductive wiring 116b, thereby inducing a second magnetic field ( Figure 1 132). In some embodiments, Figure 2 As shown in , the first current i1 flows in a first direction, and the second current i2 flows in a second direction opposite to the first direction.

[0036] Figure 3 Show according to Figure 1 A cross-sectional view of an integrated circuit 300 is shown that illustrates some alternative embodiments of the integrated circuit 100 .

[0037] The interconnect buffer layer 310 overlies the passivation layer 104. In some embodiments, the interconnect buffer layer 310 may be, for example, or may include nitride, silicon nitride, oxide (e.g., silicon dioxide), or the like, and / or may have a thickness in the range of about 4.25 microns to 4.75 microns. The interconnect isolation layer 312 is disposed between the first etch stop layer 114 and the passivation layer 104. The interconnect isolation layer 312 may be, for example, or may include silicon nitride, silicon carbide, or the like. The first input / output structure 202 overlies the first conductive wiring 116a and directly contacts the upper surface of the first conductive wiring 116a (e.g., at Figure 3 The third input / output structure 206 overlies the second conductive wiring 116b and directly contacts the upper surface of the second conductive wiring 116b (as shown in FIG. Figure 3 As shown by the dotted line in Figure 2 As shown in the top view 200 of FIG. 1 , the first input / output structure 202 and the third input / output structure 206 are each laterally offset by a non-zero distance relative to the second magnetic layer 124. The first input / output structure 202 and the third input / output structure 206 each extend through the upper dielectric layer 122 to contact the first conductive wire 116a and the second conductive wire 116b, respectively.

[0038] In some embodiments, the first input / output structure 202 and the third input / output structure 206 each include a bonding structure dielectric layer 308, an upper bonding pad 306, and a solder bump 304. In some embodiments, the upper bonding pad 306 may be, for example, or may include copper, aluminum, gold, or the like. The solder bump 304 is configured to be bonded to and / or electrically coupled to the top conductive line and / or external bonding structure of an external integrated circuit. Therefore, the first input / output structure 202 and the third input / output structure 206 are configured to electrically couple the first conductive wire 116a and the second conductive wire 116b to an external integrated circuit.

[0039] The first conductive wire 116a includes a first conductive protrusion 116ap extending below the first magnetic layer 112 to the second input / output structure 204. The second conductive wire 116b includes a second conductive protrusion 116bp extending below the first magnetic layer 112 to the fourth input / output structure 208. The first conductive protrusion 116ap and the second conductive protrusion 116bp are each laterally offset relative to the first magnetic layer 112 and extend continuously through the interconnect buffer layer 310, the interconnect isolation layer 312, and the passivation layer 104. Therefore, the first conductive wire 116a and the second conductive wire 116b are electrically coupled to the second input / output structure 204 and the fourth input / output structure 208, respectively. The second input / output structure 204 and the fourth input / output structure 208 can each be configured as a lower bonding pad structure and can be, for example, or can include aluminum, copper, aluminum copper, or the like. The second input / output structure 204 and the fourth input / output structure 208 each contact the conductive interconnect wire 302. The conductive interconnect wire 302 is part of the interconnect structure 103 and is electrically coupled to a semiconductor device (eg, transistor) disposed on and / or within the substrate 102. The first conductive protrusion 116ap and the second conductive protrusion 116bp are sections of the first conductive wire 116a and the second conductive wire 116b, respectively.

[0040] In some embodiments, the substantially flat upper surface of the second magnetic layer 124 is offset by a step height h1 in the vertical direction relative to the top surface of the first etch stop layer 114. The upper surface of the first input / output structure 202 and / or the third input / output structure 206 is offset by a height h2 in the vertical direction relative to the top surface of the first etch stop layer 114. The height h2 is greater than the step height h1. In some embodiments, the height h2 is at least twice greater than the step height h1. Since the height h2 is greater than the step height h1, complications during the bonding process between the first input / output structure 202 and / or the third input / output structure 206 and other conductive structures (e.g., upper conductive wiring and / or external bonding structures) can be avoided. For example, in some embodiments, if the second magnetic layer 124 has a convex and / or semicircular upper surface with an increased step height h1 (e.g., approximately equal to and / or greater than the height h2), the shape and / or size of the second magnetic layer 124 may adversely affect and / or prevent the bonding process. In such an embodiment, the protrusion and / or the semicircular upper surface of the second magnetic layer 124 may cause delamination between the first input / output structure 202 and / or the third input / output structure 206 and another conductive structure, thereby causing a breakdown of the inductor structure 109. Therefore, by disposing the first magnetic layer 112 and / or the first conductive wiring 116a and the second conductive wiring 116b in the trench 110t of the first dielectric layer 110, the performance, structural integrity and reliability of the inductor structure 109 may be improved. In addition, this reduces the design and manufacturing complexity of the inductor structure 109.

[0041] Figure 4 Show according to Figure 1 A cross-sectional view of an integrated circuit 400 is shown that illustrates some alternative embodiments of the integrated circuit 100 .

[0042] The second dielectric layer 115 has a substantially flat top surface 115ts, which is disposed in a vertical direction above the top surface 112ts of the first magnetic layer 112. The second isolation layer 128 has a top surface 128ts disposed in a vertical direction above an upper surface 128us of the second isolation layer 128. The second etch stop layer 126 has a top surface 126ts located in a vertical direction above an upper surface 126us of the second etch stop layer 126.

[0043] Figure 5 Shown including Figure 1 A cross-sectional view of some embodiments of an integrated circuit 500 showing an embodiment of an inductor structure 109 is shown.

[0044] The integrated circuit 500 includes an interconnect structure 103 overlying a substrate 102. The substrate 102 may be, for example, or may include a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. A plurality of transistors 514 are disposed in and / or on the substrate 102. The transistors 514 may be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). The transistors 514 each include a source / drain region 510 disposed in the substrate 102 and laterally spaced apart from each other. A gate dielectric layer 506 overlies the substrate 102 between the source / drain regions 510, and a gate electrode 512 overlies the gate dielectric layer 506. In some embodiments, the gate electrode 512 may be, for example, or may include polysilicon or another suitable conductive material. The substrate 102 includes a first doping type (e.g., p-type), and the source / drain region 510 includes a second doping type (e.g., n-type) opposite to the first doping type. In addition, a sidewall spacer structure 508 is disposed along the sidewalls of the gate dielectric layer 506 and the gate electrode 512. The transistor 514 is disposed between the isolation structures 504, which extend from the upper surface of the substrate 102 to a point below the upper surface of the substrate 102. In some embodiments, the isolation structures 504 are configured as shallow trench isolation (STI) structures and include one or more dielectric materials (e.g., silicon dioxide).

[0045] The interconnect structure 103 includes an interconnect dielectric structure 503, an inner connecting hole 518, and an inner connecting wire 520. The inner connecting holes 518 and the inner connecting wire 520 are alternately stacked in the inner connecting dielectric structure 503. In some embodiments, the inner connecting dielectric structure 503 includes one or more interlayer dielectric (ILD) layers. The one or more ILD layers may be, for example, or may include oxides (e.g., silicon dioxide), low-k dielectric materials, combinations thereof, or the like. The inner connecting holes 518 and / or the inner connecting wire 520 may be, for example, each or may include copper, aluminum, tungsten, combinations thereof, or some other suitable conductive materials.

[0046] The passivation layer 104 overlies the interconnect structure 103. The passivation layer 104 may be, for example, or may include silicon dioxide, silicon nitride, a polyimide compound, or other suitable materials. In some embodiments, a plurality of bonding pad structures 522 are disposed in the passivation layer 104. Each bonding pad structure 522 may overlie the underlying interconnect wiring 520. Therefore, the bonding pad structure 522 is electrically coupled to the transistor 514 through the interconnect structure 103. In some embodiments, the bonding pad structures 522 may be, for example, each be or may include aluminum, copper, aluminum copper, or the like.

[0047] The first dielectric layer 110 is disposed on the passivation layer 104. At least a portion of the inductor structure 109 is disposed within a trench 110t defined by the first dielectric layer 110. This partially improves the structural integrity of the inductor structure 109 and reduces and / or eliminates the manufacturing complexity of the inductor structure 109.

[0048] Figures 6 to 15 Cross-sectional views 600 to 1500 illustrate some embodiments of a first method of forming an inductor structure recessed into a first dielectric layer according to the present disclosure. Figures 6 to 15 The cross-sectional views 600 to 1500 shown in FIG. 1 are described with reference to the method, however, it should be understood that Figures 6 to 15 The structure shown in is not limited to the method, but can be independent of the method. Figures 6 to 15 It is described as a series of actions, but it should be understood that these actions are not restrictive, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0049] like Figure 6 As shown in the cross-sectional view 600 of , a substrate 102 is provided. In some embodiments, the substrate 102 may include any type of semiconductor body (e.g., single crystal silicon, silicon germanium (SiGe), silicon on insulator (SOI), etc.). In some embodiments, a semiconductor device is formed in / on the substrate 102. For example, the semiconductor device may be a transistor including a gate stack (e.g., a metal gate disposed on a high-k dielectric), the gate stack being disposed on the semiconductor substrate 102 and between a source and a drain, while the source and the drain are disposed in the semiconductor substrate 102.

[0050] In some embodiments, the process of forming the semiconductor device includes forming a patterned photoresist layer (not shown) on the semiconductor substrate 102. The patterned photoresist layer can be formed, for example, by a spin-on process. The patterned photoresist layer can be patterned, for example, using a layout with multiple source / drain electrodes and can be patterned, for example, using photolithography. In some embodiments, the process of forming the source / drain of the semiconductor device includes performing ion implantation with the patterned photoresist in place and then stripping the patterned photoresist. In addition, in some embodiments, the gate can be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering or some other deposition or growth process with the patterned photoresist (not shown) in place and then stripping the patterned photoresist.

[0051] like Figure 7 As shown in the cross-sectional view 700 of , an interconnect structure 103 is formed on the semiconductor substrate 102 and the interconnect structure 103 directly contacts the semiconductor substrate 102. The interconnect structure 103 includes a plurality of conductive features, such as metal interconnect wiring and / or through holes for interconnecting the semiconductor device. In some embodiments, the plurality of conductive features are formed in a plurality of metal layers formed on top of each other. In some embodiments, the conductive features can be formed by a combination of photolithography and an applicable deposition or growth process (e.g., electrochemical plating (ECP), electroless plating, chemical vapor deposition or physical vapor deposition, sputtering, or some other deposition or growth process). The process may be, for example, part of a single damascene like process or a dual damascene like process. In some embodiments, after each metal layer is formed to form a substantially flat upper surface, a chemical mechanical polishing (CMP) process may be performed.

[0052] exist Figure 7 1 and 2 , after forming the interconnect structure 103, a passivation layer 104 is formed on the interconnect structure 103. The passivation layer 104 may include a dielectric material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), a polyimide compound, or other suitable materials. The passivation layer 104 may be formed, for example, by a deposition or growth process (e.g., CVD, PVD, or some other deposition or growth process).

[0053] like Figure 8As shown in the cross-sectional view 800 of , an interconnect buffer layer 310 is formed on the upper surface of the passivation layer 104. In some embodiments, the interconnect buffer layer 310 may be, for example, or may include nitride, silicon nitride, or the like. An interconnect isolation layer 312 is formed on the interconnect buffer layer 310. In some embodiments, the interconnect isolation layer 312 may be, for example, or may include silicon nitride, silicon carbide, or the like. A first dielectric layer 110 is formed on the interconnect isolation layer 312. The first dielectric layer 110 may be, for example, a polyimide compound, a polybenzoxazole compound, or any other suitable dielectric material and / or may be formed to a thickness in the range of about 16 microns to 20 microns. Subsequently, a patterning process is performed to form opposite sidewalls 110sw1, 110sw2 in the first dielectric layer 110, the opposite sidewalls 110sw1, 110sw2 defining the trench 110t in the first dielectric layer 110. In some embodiments, the process of patterning the first dielectric layer 110 includes: forming a mask layer (not shown) on the first dielectric layer 110; exposing the unmasked area of ​​the first dielectric layer 110 to one or more etchants to define the groove 110t; and performing a removal process to remove the mask layer. Subsequently, in some embodiments, a curing process may be performed on the first dielectric layer 110 to harden and / or strengthen the first dielectric layer 110. In some embodiments, the curing process may be, for example, or may include a pressure curing process, a thermal curing process, or any other suitable curing process. In some embodiments, the interconnect buffer layer 310, the interconnect isolation layer 312, and / or the first dielectric layer 110 may be deposited and / or grown by CVD, PVD, atomic layer deposition (ALD), or another suitable deposition process.

[0054] like Fig. 9As shown in the cross-sectional view 900 of , a first etch stop layer 114 is formed on the first dielectric layer 110 and the interconnect isolation layer 312. In some embodiments, the first etch stop layer 114 may be, for example, or may include a metal oxide, such as tantalum oxide, titanium oxide, another suitable etch stop material, or the like. In some embodiments, a method of forming the first etch stop layer 114 may include: forming a metal material (e.g., tantalum) on the first dielectric layer 110; and subsequently performing a thermal annealing process (e.g., using water (H2O)) to convert the metal material into a metal oxide. The first etch stop layer 114 may continuously line the trench 110t and / or may directly contact the opposite sidewalls 110sw1, 110sw2. A first magnetic layer 112 is formed on the first etch stop layer 114. The first magnetic layer 112 may be, for example, or may include cobalt zirconium tantalum (CZT), iron-nickel (NiFe) compounds, or other suitable magnetic materials and / or may have a thickness in the range of 3 microns to 10 microns. Subsequently, an etching process is performed on the first magnetic layer 112. In some embodiments, the etching process includes: forming a mask layer (not shown) on the first magnetic layer 112; performing a wet etching process on an unmasked area of ​​the first magnetic layer 112; and performing a removal process to remove the mask layer.

[0055] After performing the etching process on the first magnetic layer 112, the first etch stop layer 114 may be patterned. In some embodiments, patterning the first etch stop layer 114 may include: forming a mask layer (not shown) on the first etch stop layer 114; performing a dry etching process on an unmasked area of ​​the first etch stop layer 114; and performing a removal process to remove the mask layer. In some embodiments, the process of forming the first magnetic layer 112 includes depositing the first magnetic layer 112 by, for example, CVD, PVD, sputtering, or some other deposition or growth process. In other embodiments, the first etch stop layer 114 may be deposited and / or grown, for example, by CVD, PVD, ALD, or another suitable deposition process.

[0056] In some embodiments, by forming at least a portion of the first magnetic layer 112 in the trench 110t, delamination of the first magnetic layer 112 with the first etch stop layer 114, the first dielectric layer 110, and / or another layer can be reduced and / or eliminated. This can improve the structural integrity of the first magnetic layer 112 and any other layers / structures formed on the first magnetic layer 112. In addition, the aforementioned fabrication method can reduce the complexity and / or design of forming the first magnetic layer 112.

[0057] like Fig.10As shown in the cross-sectional view 1000 of FIG. 1 , a first isolation layer 120 is formed on the first magnetic layer 112. The first isolation layer 120 may be, for example, or may include a dielectric material, such as silicon dioxide, silicon nitride, a low-k dielectric, or some other suitable dielectric material. The first isolation layer 120 may be deposited or grown, for example, by CVD, PVD, ALD, or some other deposition or growth process. In some embodiments, the first isolation layer 120 conformally lines the surface of the first magnetic layer 112 and is disposed in the trench 110t.

[0058] exist Fig.10 10 , a barrier seed layer 118 is formed on the first isolation layer 120. The barrier seed layer 118 may be, for example, or may include copper, aluminum, gold, silver, alloys of the foregoing, or other suitable materials. The barrier seed layer 118 may be deposited or grown, for example, by CVD, PVD, sputtering, electrochemical plating, electroless plating, or some other deposition or growth process. In some embodiments, the barrier seed layer 118 conformally lines the surface of the first isolation layer 120 and is disposed in the trench 110 t.

[0059] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a first conductive wire 116 a and a second conductive wire 116 b are formed on the barrier seed layer 118 and the first conductive wire 116 a and the second conductive wire 116 b directly contact the barrier seed layer 118. In some embodiments, the first conductive wire 116 a and the second conductive wire 116 b are formed with a patterned photoresist layer 1102 in place. The patterned photoresist layer 1102 is formed on the barrier seed layer 118 by, for example, a spin coating process combined with a subsequent photolithography process to define an opening in the patterned photoresist layer 1102. The first conductive wire 116 a and the second conductive wire 116 b may, for example, each be or may include copper, aluminum, gold, silver, aluminum copper, alloys of the foregoing, or any other suitable conductive material. The first conductive wire 116a and the second conductive wire 116b can be deposited or grown, for example, by CVD, PVD, sputtering, electrochemical plating (ECP), electroless plating, or some other deposition or growth process. In other embodiments, the first conductive wire 116a and the second conductive wire 116b can each be deposited or grown in the opening of the patterned photoresist layer 1102 by ECP, wherein the barrier seed layer 118 acts as a seed layer, and the first conductive wire 116a and the second conductive wire 116b can be grown from the seed layer.

[0060] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , the patterned photoresist layer ( 114 ) is stripped from the barrier seed layer 118 by, for example, a wet etching or dry etching process. Fig.11 In some embodiments, the patterned photoresist layer ( Fig.11The stripping (shown in Figure 1102) also removes at least a portion of the barrier seed layer 118 and / or the first isolation layer 120 that is not covered by the first conductive wiring 116a and / or the second conductive wiring 116b. In other embodiments, subsequent etching and photolithography processes are performed to remove portions of the barrier seed layer 118 and the first isolation layer 120 that are laterally offset relative to the first conductive wiring 116a and / or the second conductive wiring 116b. In some embodiments, after the above-mentioned processing steps, the top surfaces of the first conductive wiring 116a and the second conductive wiring 116b are offset in the vertical direction relative to the top surface of the first etch stop layer 114 by a distance d1. In some embodiments, the distance d1 is non-zero. In other embodiments, the top surfaces of the first conductive wiring 116a and the second conductive wiring 116b are located below the top surface of the first etch stop layer 114. In some other embodiments, the top surfaces of the first conductive wire 116 a and the second conductive wire 116 b are located below the top surface of the first dielectric layer 110 .

[0061] like Fig.13 As shown in the cross-sectional view 1300 of , a second dielectric layer 115 is formed on the first conductive wiring 116a and the second conductive wiring 116b and the first magnetic layer 112. The second dielectric layer 115 conformally surrounds the first conductive wiring 116a and the second conductive wiring 116b and fills the remaining portion of the groove 110t. In some embodiments, the second dielectric layer 115 is configured to electrically isolate the first conductive wiring 116a and the second conductive wiring 116b from each other. The second dielectric layer 115 may be, for example, a polyimide compound, a polybenzoxazole compound, or any other suitable dielectric material. Subsequently, a patterning process is performed on the second dielectric layer 115. In some embodiments, the process of patterning the second dielectric layer 115 includes: forming a mask layer (not shown) on the second dielectric layer 115; exposing the unmasked area of ​​the second dielectric layer 115 to one or more etchants; and performing a removal process to remove the mask layer. Subsequently, in some embodiments, a curing process may be performed on the second dielectric layer 115 to harden and / or strengthen the second dielectric layer 115. In some embodiments, the curing process may be, for example, or may include a pressure curing process, a thermal curing process, or any other suitable curing process. In some embodiments, the second dielectric layer 115 may be deposited and / or grown by CVD, PVD, ALD, or another suitable deposition process. In some embodiments, the second dielectric layer 115 may have a substantially flat upper surface, which may be flush with the upper surface of the first magnetic layer 112. In some embodiments, the substantially flat upper surface of the second dielectric layer 115 may be formed by a patterning process (e.g., an etching process) and / or by a planarization process (e.g., a CMP process).

[0062] In some embodiments, by forming the second dielectric layer 115 in the trench 110t and along the inner sidewall and upper surface of the first magnetic layer 112, the shape and / or thickness of the second dielectric layer 115 can be more easily controlled. This can partially reduce the cost associated with forming the inductor structure ( Fig.15 109), and / or can improve the structural integrity of the first conductive wire 116a and the second conductive wire 116b.

[0063] like Fig.14 As shown in the cross-sectional view 1400 of , a second isolation layer 128 is formed on the second dielectric layer 115 and the first magnetic layer 112. The second isolation layer 128 may be, for example, or may include a nitride, silicon nitride, or another suitable dielectric material. A second etch stop layer 126 is formed on the second isolation layer 128. In some embodiments, the second etch stop layer 126 may be, for example, or may include a metal oxide, such as tantalum oxide, titanium oxide, another suitable etch stop material, or the like. In some embodiments, a method of forming the second etch stop layer 126 may include: forming a metal material (e.g., tantalum) on the second isolation layer 128; and subsequently performing a thermal annealing process (e.g., using water (H2O)) to convert the metal material into a metal oxide. In some embodiments, the second isolation layer 128 and / or the second etch stop layer 126 may be deposited or grown, for example, by CVD, PVD, ALD, or some other suitable deposition or growth process. In some embodiments, a subsequent etching process (e.g., a wet etching process and / or a dry etching process) (not shown) may be performed on the second isolation layer 128 and / or the second etch stop layer 126, wherein a portion of the above-mentioned layers in a region laterally offset relative to the first magnetic layer 112 may be removed.

[0064] like Fig.15 As shown in the cross-sectional view 1500 of , a second magnetic layer 124 is formed on the first etch stop layer 114 and the second etch stop layer 126 to form the inductor 109. The second magnetic layer 124 may be, for example, or may include cobalt zirconium tantalum (CZT), iron-nickel (NiFe) compound, or other suitable magnetic materials and / or may have a thickness in the range of 3 microns to 10 microns. Subsequently, an etching process is performed on the second magnetic layer 124. In some embodiments, the etching process includes: forming a mask layer (not shown) on the second magnetic layer 124; performing a wet etching process on the unmasked area of ​​the second magnetic layer 124; and performing a removal process to remove the mask layer. An upper dielectric layer 122 is formed on the second magnetic layer 124. The upper dielectric layer 122 may be, for example, or may include an oxide (e.g., silicon dioxide), a low dielectric constant dielectric material, another suitable dielectric material, or the like.

[0065] In some embodiments, the second isolation layer 128 and / or the second etch stop layer 126 are not etched and / or patterned until after the second magnetic layer 124 is formed (eg, see FIG. 1 ). Fig.14 ). In such an embodiment, the bottom surface of the second magnetic layer 124 extends along the upper surface 126u (not shown) of the second etch stop layer 126 or along the upper surface 128u (not shown) of the second isolation layer 128. In such an embodiment, after forming the second magnetic layer 124, a wet etching process may be performed on the second isolation layer 128 and / or the second etch stop layer 126 to remove portions of the above layers in a region laterally offset from the second magnetic layer 124.

[0066] Figure 16 to Figure 18 Cross-sectional views 1600 to 1800 illustrate some embodiments of a second method of forming an inductor structure recessed into a first dielectric layer according to the present disclosure. Figure 16 to Figure 18 The cross-sectional views 1600 to 1800 shown in FIG. 1 are described with reference to the method, however, it should be understood that Figure 16 to Figure 18 The structure shown in is not limited to the method, but can be independent of the method. Figure 16 to Figure 18 It is described as a series of actions, but it should be understood that these actions are not restrictive, because the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0067] like Fig.16 As shown in the cross-sectional view 1600, a second dielectric layer 115 is formed on the first conductive wiring 116a and the second conductive wiring 116b and the first magnetic layer 112. In some embodiments, Fig.16 The structure shown is Figures 6 to 12The second dielectric layer 115 conformally surrounds the first conductive wiring 116a and the second conductive wiring 116b and fills the remaining portion of the groove 110t. In some embodiments, the second dielectric layer 115 is configured to electrically isolate the first conductive wiring 116a and the second conductive wiring 116b from each other. The second dielectric layer 115 may be, for example, a polyimide compound, a polybenzoxazole compound, silicon nitride, tantalum oxide, or any other suitable dielectric material. Subsequently, a patterning process is performed on the second dielectric layer 115. In some embodiments, the process of patterning the second dielectric layer 115 includes: forming a mask layer (not shown) on the second dielectric layer 115; exposing the unmasked area of ​​the second dielectric layer 115 to one or more etchants; and performing a removal process to remove the mask layer. Subsequently, in some embodiments, a curing process may be performed on the second dielectric layer 115 to harden and / or strengthen the second dielectric layer 115. In some embodiments, the curing process may be, for example, or may include, a pressure curing process, a thermal curing process, or any other suitable curing process. In some embodiments, the second dielectric layer 115 may be deposited and / or grown by CVD, PVD, ALD, or another suitable deposition process. In some embodiments, the second dielectric layer 115 may have a substantially flat top surface 115ts, which is located vertically above the top surface 112ts of the first magnetic layer 112. In such embodiments, the substantially flat top surface 115ts of the second dielectric layer 115 may be achieved by a patterning process or by performing a planarization process (e.g., CMP) on the second dielectric layer 115.

[0068] like Fig.17As shown in the cross-sectional view 1700 of , a second isolation layer 128 is formed on the second dielectric layer 115 and the first magnetic layer 112. The second isolation layer 128 may be, for example, or may include nitride, silicon nitride, or another suitable dielectric material. The second isolation layer 128 may, for example, have a top surface 128ts, which is located above the upper surface 128us of the second isolation layer 128 in the vertical direction. A second etch stop layer 126 is formed on the second isolation layer 128. In some embodiments, the second etch stop layer 126 may be, for example, or may include a metal oxide, such as tantalum oxide, titanium oxide, another suitable etch stop material, or the like. In some embodiments, a method of forming the second etch stop layer 126 may include: forming a metal material (e.g., tantalum) on the second isolation layer 128; and then performing a thermal annealing process (e.g., using water (H2O)) to convert the metal material into a metal oxide. In addition, the second etch stop layer 126 has a top surface 126ts, which is located above the upper surface 126us of the second etch stop layer 126 in the vertical direction. In some embodiments, the second isolation layer 128 and / or the second etch stop layer 126 can be deposited or grown, for example, by CVD, PVD, ALD, or some other suitable deposition or growth process. In some embodiments, a subsequent etching process (e.g., a wet etching and / or a dry etching process) (not shown) can be performed on the second isolation layer 128 and / or the second etch stop layer 126, wherein a portion of the above-mentioned layer in a region that is laterally offset relative to the first magnetic layer 112 can be removed.

[0069] like Fig.18 As shown in the cross-sectional view 1800 of , a second magnetic layer 124 is formed on the first etch stop layer 114 and the second etch stop layer 126 to form the inductor 109. The second magnetic layer 124 may be, for example, or may include cobalt zirconium tantalum (CZT), iron-nickel (NiFe) compounds, or other suitable magnetic materials and / or may have a thickness in the range of 3 microns to 10 microns. Subsequently, an etching process is performed on the second magnetic layer 124. In some embodiments, the etching process includes: forming a mask layer (not shown) on the second magnetic layer 124; performing a wet etching process on the unmasked area of ​​the second magnetic layer 124; and performing a removal process to remove the mask layer. In addition, in the example Fig.15 The second isolation layer 128 and / or the second etch stop layer 126 are etched after forming the second magnetic layer 124 as shown and / or described in the drawings. An upper dielectric layer 122 is formed over the second magnetic layer 124. The upper dielectric layer 122 may be, for example, or may include, an oxide (e.g., silicon dioxide), a low-k dielectric material, another suitable dielectric material, or the like.

[0070] Fig.19A method 1900 of forming an inductor structure recessed into a first dielectric layer according to the present disclosure is shown. Although the method 1900 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from the order shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0071] At act 1902, an interconnect structure is formed over a substrate. The interconnect structure has a plurality of metal layers. Figure 7 Cross-sectional view 700 corresponding to some embodiments of act 1902 is shown.

[0072] At act 1904, a passivation layer is formed over the interconnect structure. A first dielectric layer is formed over the passivation layer. Figure 8 Cross-sectional view 800 corresponding to some embodiments of act 1904 is shown.

[0073] At act 1906, the first dielectric layer is patterned to define opposing sidewalls defining a trench extending through the first dielectric layer. Figure 8 A cross-sectional view 800 corresponding to some embodiments of act 1906 is shown.

[0074] At act 1908, a first etch stop layer is formed over the first dielectric layer, and the first etch stop layer lines the trench of the first dielectric layer. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1908 is shown.

[0075] At act 1910, a first magnetic layer is formed over the first etch stop layer, the first magnetic layer at least partially lining the trench and having a top surface disposed above the first dielectric layer. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1910 is shown.

[0076] At act 1912, a first spacer layer and a barrier seed layer are formed over the first magnetic layer. Fig.10 A cross-sectional view 1000 corresponding to some embodiments of act 1912 is shown.

[0077] At act 1914 , a first conductive wire and a second conductive wire are formed over the barrier seed layer and within the trench. Figure 11 to Figure 12 Cross-sectional views 1100 through 1200 corresponding to some embodiments of act 1914 are shown.

[0078] At act 1916, a second dielectric layer is formed over the first magnetic layer, thereby filling the remaining portion of the trench. The second dielectric layer surrounds the first conductive wire and the second conductive wire. Fig.13 and Fig.16 Cross-sectional views 1300 and 1600 corresponding to some embodiments of act 1916 are shown.

[0079] At act 1918, a second isolation layer and a second etch stop layer are formed over the second dielectric layer and the first magnetic layer. Fig.14 and Fig.17 Cross-sectional views 1400 and 1700 corresponding to some embodiments of act 1918 are shown.

[0080] A second magnetic layer is formed over the second etch stop layer at act 1920. The second magnetic layer extends in a lateral direction over the trench. Fig.15 and Fig.18 Cross-sectional views 1500 and 1800 corresponding to some embodiments of act 1920 are shown.

[0081] Thus, in some embodiments, the present disclosure is directed to an inductor structure that includes a magnetic layer surrounding a first conductive wire and a second conductive wire, wherein the first conductive wire and the second conductive wire are disposed within a trench defined by a dielectric layer.

[0082] In some embodiments, the present application provides an integrated circuit (IC), which includes: a substrate; an interconnect structure having a plurality of metal layers disposed on the substrate; a first dielectric layer disposed on an uppermost surface of the interconnect structure, wherein the first dielectric layer has opposite sidewalls defining a groove; a first magnetic layer disposed in the groove and conformally extending along the opposite sidewalls; a conductive wiring disposed in the groove and overlying the first magnetic layer; and a second magnetic layer overlying the first magnetic layer and the conductive wiring, wherein the second magnetic layer extends laterally from over a first of the opposite sidewalls to a second of the opposite sidewalls.

[0083] In the above integrated circuit of some embodiments, a top surface of the conductive wire is located below a top surface of the first magnetic layer in a vertical direction.

[0084] In the above integrated circuit of some embodiments, the upper surface of the second magnetic layer is substantially flat, and wherein the upper surface of the second magnetic layer extends continuously between outer sidewalls of the first magnetic layer.

[0085] In the above integrated circuit of some embodiments, a maximum distance between the opposite sidewalls of the first dielectric layer is smaller than a minimum width of the second magnetic layer.

[0086] In some embodiments of the above-mentioned integrated circuit, the distance between the relative side walls continuously increases from the bottom surface of the first dielectric layer to the top surface of the first dielectric layer, wherein the width of the first magnetic layer continuously increases in a direction from the bottom surface of the first dielectric layer to the top surface of the first dielectric layer.

[0087] In the above integrated circuit of some embodiments, the height of the second magnetic layer is smaller than the height of the first magnetic layer.

[0088] In the above integrated circuit of some embodiments, the height of the second magnetic layer is smaller than the height of the conductive wiring.

[0089] In some embodiments of the above-mentioned integrated circuit, it also includes: a second dielectric layer, which is arranged along the upper surface and sidewalls of the first magnetic layer, wherein the second dielectric layer surrounds the conductive wiring, and wherein the second dielectric layer contains the same material as the first dielectric layer.

[0090] In some embodiments, the present application provides an integrated circuit (IC), the integrated circuit comprising: a substrate; an interconnect structure having a plurality of metal layers overlying the substrate; a passivation layer overlying the interconnect structure; a first dielectric layer having inclined opposite sidewalls, the inclined opposite sidewalls defining a groove overlying the passivation layer; a first etch stop layer extending along a top surface of the first dielectric layer and the inclined opposite sidewalls; a first magnetic layer overlying the first etch stop layer and disposed in the groove; a first conductive wiring and a second conductive wiring disposed in the groove and overlying the substrate; On the first magnetic layer, wherein the first conductive wiring and the second conductive wiring extend parallel to each other along a first direction parallel to the upper surface of the substrate; a second dielectric layer filling the groove and enclosing the first conductive wiring and the second conductive wiring; and a second magnetic layer disposed on the first magnetic layer and the second dielectric layer, wherein the first magnetic layer and the second magnetic layer wrap around the first conductive wiring and the second conductive wiring and extend laterally in the first direction along the middle section of the first conductive wiring and the second conductive wiring.

[0091] In some embodiments of the above-mentioned integrated circuit, it also includes: a first input / output structure, directly contacting the first conductive wiring and arranged above the first conductive wiring, wherein the first input / output structure is laterally offset in a direction away from the second magnetic layer relative to the first side wall of the second magnetic layer; and a second input / output structure, directly contacting the first conductive wiring and arranged below the first conductive wiring, wherein the second input / output structure is arranged in the passivation layer, wherein the second input / output structure is laterally offset in another direction away from the second magnetic layer relative to the second side wall of the second magnetic layer, wherein the first side wall is opposite to the second side wall.

[0092] In some embodiments of the above-mentioned integrated circuit, a first height defined between a top surface of the first etch stop layer and a top surface of the second magnetic layer is less than half of a second height defined between the top surface of the first etch stop layer and a top surface of the first input / output structure.

[0093] In the integrated circuit of some embodiments, the first magnetic layer and the second magnetic layer include cobalt zirconium tantalum.

[0094] In some embodiments of the above-mentioned integrated circuit, the inclined opposite sidewalls of the first dielectric layer are laterally spaced between the inclined opposite sidewalls of the second magnetic layer, wherein the second magnetic layer has a substantially flat upper surface extending continuously between the inclined opposite sidewalls of the second magnetic layer.

[0095] In the integrated circuit of some embodiments, the first dielectric layer and the second dielectric layer include a polyimide compound or a polybenzoxazole compound.

[0096] In some embodiments of the above-mentioned integrated circuit, it also includes: an isolation layer overlying the first magnetic layer and the second dielectric layer; and a second etch stop layer overlying the isolation layer, wherein the isolation layer and the second etch stop layer are sandwiched between the first magnetic layer and the second magnetic layer.

[0097] In the above integrated circuit of some embodiments, the first conductive wire and the second conductive wire respectively include a protrusion, which extends into the passivation layer below the first magnetic layer and is electrically coupled to the metal layer in the interconnect structure.

[0098] In some embodiments, the present application provides a method for forming an integrated circuit (IC), the method comprising: forming an interconnect structure having multiple metal layers over a substrate; forming a passivation layer over the uppermost surface of the interconnect structure; forming a first dielectric layer over the passivation layer, wherein the first dielectric layer has sidewalls, the sidewalls defining grooves; forming a first magnetic layer over the passivation layer, wherein the first magnetic layer lines the grooves and extends over a top surface of the first dielectric layer; forming conductive wiring spaced apart from each other over the first magnetic layer; forming a second dielectric layer over the conductive wiring, wherein the second dielectric layer at least partially fills the grooves; and forming a second magnetic layer over the second dielectric layer and the first magnetic layer, wherein the second magnetic layer has a substantially flat upper surface extending continuously between the sidewalls of the first dielectric layer.

[0099] In the above-mentioned method of forming an integrated circuit in some embodiments, forming the first dielectric layer includes: depositing a dielectric material on the passivation layer, wherein the dielectric material includes a polyimide compound or a polybenzoxazole compound; patterning the dielectric material to form the sidewall defining the trench; and performing a curing process on the dielectric material.

[0100] In the above-mentioned method of forming an integrated circuit in some embodiments, forming the conductive wiring includes: forming an isolation layer on the first magnetic layer; forming a barrier seed layer on the isolation layer; forming a photoresist layer on the barrier seed layer, wherein the photoresist layer includes a wiring opening; and forming the conductive wiring in the wiring opening, wherein the conductive wiring is formed by an electrochemical plating process.

[0101] In the above-mentioned method of forming an integrated circuit in some embodiments, forming the first magnetic layer includes: depositing a magnetic material on the first dielectric layer, wherein the magnetic material comprises cobalt zirconium tantalum; forming a mask layer on the magnetic material; and performing a wet etching process on the magnetic material to remove unmasked areas of the magnetic material.

[0102] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, comprising: substrate; an interconnect structure having a plurality of metal layers disposed on the substrate; a first dielectric layer disposed on an uppermost surface of the interconnect structure, wherein the first dielectric layer has opposing sidewalls defining a trench; a first magnetic layer disposed within the trench and conformally extending along the opposing sidewalls; a conductive wiring disposed in the groove and overlying the first magnetic layer, wherein a top surface of the conductive wiring is located below a top surface of the first magnetic layer in a vertical direction; as well as A second magnetic layer overlies the first magnetic layer and the conductive wiring, wherein the second magnetic layer extends in a lateral direction from above a first sidewall of the opposite sidewalls to a second sidewall of the opposite sidewalls. 2 . The integrated circuit of claim 1 , wherein an upper surface of the second magnetic layer is flat, and wherein the upper surface of the second magnetic layer extends continuously between outer sidewalls of the first magnetic layer. 3 . The integrated circuit of claim 1 , wherein a maximum distance between the opposing sidewalls of the first dielectric layer is less than a minimum width of the second magnetic layer.

4. The integrated circuit of claim 1 , wherein a distance between the opposing side walls increases continuously from a bottom surface of the first dielectric layer to a top surface of the first dielectric layer, and wherein a width of the first magnetic layer increases continuously in a direction pointing from the bottom surface of the first dielectric layer to the top surface of the first dielectric layer. 5 . The integrated circuit of claim 1 , wherein a height of the second magnetic layer is smaller than a height of the first magnetic layer. 6 . The integrated circuit according to claim 5 , wherein the height of the second magnetic layer is smaller than the height of the conductive wiring.

7. The integrated circuit of claim 1 , further comprising: A second dielectric layer is disposed along the upper surface and sidewalls of the first magnetic layer, wherein the second dielectric layer surrounds the conductive wiring, and wherein the second dielectric layer comprises the same material as the first dielectric layer.

8. An integrated circuit comprising: substrate; an interconnect structure having a plurality of metal layers overlying the substrate; a passivation layer overlying the interconnect structure; a first dielectric layer having sloped opposing sidewalls defining a trench overlying the passivation layer; a first etch stop layer extending along the top surface of the first dielectric layer and the inclined opposing sidewalls; a first magnetic layer overlying the first etch stop layer and disposed in the trench; A first conductive wire and a second conductive wire are disposed in the groove and overlying the first magnetic layer, wherein the first conductive wire and the second conductive wire extend parallel to each other along a first direction parallel to the upper surface of the substrate; a second dielectric layer filling the trench and surrounding the first conductive wiring and the second conductive wiring; as well as A second magnetic layer is disposed on the first magnetic layer and the second dielectric layer, wherein the first magnetic layer and the second magnetic layer surround the first conductive wire and the second conductive wire and extend along middle sections of the first conductive wire and the second conductive wire in a lateral direction in the first direction.

9. The integrated circuit of claim 8, further comprising: a first input / output structure directly contacting the first conductive wiring and disposed above the first conductive wiring, wherein the first input / output structure is laterally offset relative to a first sidewall of the second magnetic layer in a direction away from the second magnetic layer; as well as A second input / output structure directly contacts the first conductive wiring and is arranged below the first conductive wiring, wherein the second input / output structure is arranged within the passivation layer, wherein the second input / output structure is laterally offset relative to a second side wall of the second magnetic layer in another direction away from the second magnetic layer, wherein the first side wall is opposite to the second side wall.

10. The integrated circuit of claim 9, wherein a first height defined between a top surface of the first etch stop layer and a top surface of the second magnetic layer is less than half of a second height defined between the top surface of the first etch stop layer and a top surface of the first input / output structure.

11. The integrated circuit of claim 8, wherein the first magnetic layer and the second magnetic layer comprise cobalt zirconium tantalum.

12. The integrated circuit of claim 8, wherein the inclined opposing sidewalls of the first dielectric layer are laterally spaced apart between the inclined opposing sidewalls of the second magnetic layer, wherein the second magnetic layer has a flat upper surface extending continuously between the inclined opposing sidewalls of the second magnetic layer. 13 . The integrated circuit of claim 8 , wherein the first dielectric layer and the second dielectric layer comprise a polyimide compound or a polybenzoxazole compound.

14. The integrated circuit of claim 8, further comprising: an isolation layer, overlying the first magnetic layer and the second dielectric layer; as well as A second etch stop layer is overlying the isolation layer, wherein the isolation layer and the second etch stop layer are sandwiched between the first magnetic layer and the second magnetic layer.

15. The integrated circuit of claim 8, wherein the first conductive wire and the second conductive wire respectively include a protrusion extending into the passivation layer below the first magnetic layer and electrically coupled to the metal layer in the interconnect structure.

16. A method of forming an integrated circuit, the method comprising: forming an interconnect structure having a plurality of metal layers over the substrate; forming a passivation layer over the uppermost surface of the interconnect structure; forming a first dielectric layer over the passivation layer, wherein the first dielectric layer has sidewalls defining a trench; forming a first magnetic layer over the passivation layer, wherein the first magnetic layer lines the trench and extends over a top surface of the first dielectric layer, wherein forming the first magnetic layer comprises depositing a magnetic material over the first dielectric layer, and forming a mask layer over the magnetic material; and performing a wet etching process on the magnetic material to remove unmasked areas of the magnetic material; forming conductive wirings spaced apart from each other on the first magnetic layer; forming a second dielectric layer over the conductive wiring, wherein the second dielectric layer at least partially fills the trench; as well as A second magnetic layer is formed over the second dielectric layer and the first magnetic layer, wherein the second magnetic layer has a planar upper surface extending continuously between the sidewalls of the first dielectric layer.

17. The method of forming an integrated circuit according to claim 16, wherein forming the first dielectric layer comprises: depositing a dielectric material on the passivation layer, wherein the dielectric material comprises a polyimide compound or a polybenzoxazole compound; patterning the dielectric material to form the sidewalls defining the trench; and A curing process is performed on the dielectric material.

18. The method of forming an integrated circuit according to claim 16, wherein forming the conductive wiring comprises: forming an isolation layer on the first magnetic layer; forming a barrier seed layer on the isolation layer; forming a photoresist layer over the barrier seed layer, wherein the photoresist layer includes wiring openings; as well as The conductive wiring is formed in the wiring opening, wherein the conductive wiring is formed by an electrochemical plating process.

19. The method of forming an integrated circuit of claim 16, wherein the magnetic material comprises cobalt zirconium tantalum.

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