Electronic Devices

Abstract

The present invention provides an electronic device, comprising a pixel array structure, a rewiring structure and a plurality of conductive through-hole structures. The pixel array structure comprises a plurality of signal lines. The rewiring structure overlaps with the pixel array structure and comprises a plurality of conductive lines. The plurality of conductive through-hole structures electrically connect the plurality of signal lines of the pixel array structure with the plurality of conductive lines of the rewiring structure. At least one of the plurality of conductive through-hole structures shares at least one conductive layer with the pixel array structure.

Description

Technical Field

[0001] The invention relates to an electronic device. Background Art

[0002] The driving circuit in the electronic device is usually arranged around the active area, and the signal line in the active area is electrically connected to the driving circuit through the peripheral circuit arranged outside the active area. The peripheral circuit occupies a certain wiring area, making it difficult for the electronic device to achieve a narrow frame design. In addition, as the size or resolution of the electronic device increases, it is easy to cause the resistance and capacitance load (RC loading) problem due to the excessive length of the peripheral circuit, which in turn affects the uniformity of the performance of the electronic device, such as causing poor uniformity of brightness or electrical performance. Summary of the invention

[0003] An embodiment of the present invention provides an electronic device, which helps to achieve a narrow frame design or improve the resistance and capacitance load problem.

[0004] An electronic device according to an embodiment of the present invention includes a pixel array structure, a rewiring structure, and a plurality of conductive via structures. The pixel array structure includes a plurality of signal lines. The rewiring structure overlaps with the pixel array structure and includes a plurality of conductive lines. The plurality of conductive via structures electrically connect the plurality of signal lines of the pixel array structure with the plurality of conductive lines of the rewiring structure. At least one of the plurality of conductive via structures shares at least one conductive layer with the pixel array structure.

[0005] In order to make the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0007] Figures 1 to 3 They are respectively a partial three-dimensional schematic diagram, a partial cross-sectional schematic diagram and a partial top view schematic diagram of an electronic device according to a first embodiment of the present invention;

[0008] Figures 4 to 6 They are partial top views of electronic devices according to second to fourth embodiments of the present invention respectively;

[0009] FIG. 7A to FIG. 7C They are Figure 6 A circuit diagram of shift register unit SR1 to shift register unit SR3;

[0010] Figure 8 and Fig. 9They are respectively a partial top view and a partial cross-sectional view of an electronic device according to a fifth embodiment of the present invention;

[0011] Fig.10 is a partial top view schematic diagram of an electronic device according to a sixth embodiment of the present invention;

[0012] Figures 11 to 13 They are partial cross-sectional schematic diagrams of electronic devices according to seventh to ninth embodiments of the present invention respectively;

[0013] Fig.14 and Fig.15 They are respectively a partial three-dimensional schematic diagram and a partial cross-sectional schematic diagram of an electronic device according to a tenth embodiment of the present invention;

[0014] Fig.16 and Fig.17 1 and 2 are respectively a partial cross-sectional schematic diagram and a partial top view schematic diagram of an electronic device according to an eleventh embodiment of the present invention.

[0015] Description of Figure Numbers

[0016] 1. 1A-1J: electronic devices;

[0017] 10, 10G, 10J: pixel array structure;

[0018] 10-1: first pixel array structure;

[0019] 10-2: second pixel array structure;

[0020] 100, 120, 120G: buffer layer;

[0021] 101: semiconductor layer;

[0022] 102: gate insulating layer;

[0023] 103: a first conductive layer;

[0024] 104, 121: first insulating layer;

[0025] 105: middle conductive layer;

[0026] 106, 123: second insulating layer;

[0027] 107: second conductive layer;

[0028] 108: third insulating layer;

[0029] 109: fourth insulating layer;

[0030] 109G: insulation layer;

[0031] 110: third conductive layer;

[0032] 110G, 110H: conductive layer;

[0033] 111: Stretchable electrodes;

[0034] 12. 12G: rewiring structure;

[0035] 122: first redistribution conductive layer;

[0036] 124: second redistribution conductive layer;

[0037] 1220, 1240, CL: wire;

[0038] 13, 13A-13G: conductive through-hole structure;

[0039] 13-1: first conductive via structure;

[0040] 13-2: second conductive via structure;

[0041] 13X: Simulate conductive via structure;

[0042] 16, 26: substrate;

[0043] 18, 28: component layer;

[0044] 20: driving circuit;

[0045] 22: Data demultiplexer;

[0046] 24: Gate drive circuit;

[0047] 30: Adhesion layer;

[0048] AE, AD1: active components;

[0049] BE: lower electrode;

[0050] C: capacitor;

[0051] CH: channel pattern;

[0052] CL-1: First conductor;

[0053] CL-2: Second lead;

[0054] CLK, XCLK, INPUT, OUTPUT, VGH, VGL: signal lines;

[0055] CP1, CP2: conductive patterns;

[0056] CT: Connector;

[0057] CV1-CV4, CV1A, CV1G, CV1H, CV4F, CV4G: conductive vias;

[0058] D1: first direction;

[0059] D2: second direction;

[0060] D3: third direction;

[0061] DE, DE1: drain;

[0062] DL: data line;

[0063] GE, GE1: gate;

[0064] MP: middle pattern;

[0065] PL: power line;

[0066] PE, PEG, PEH: pixel electrodes;

[0067] SE, SE1: source;

[0068] SL: scan line;

[0069] SP: sub-pixel;

[0070] SR1, SR2, SR3: shift register unit;

[0071] TE: upper electrode;

[0072] TP: top pattern;

[0073] θ: angle. DETAILED DESCRIPTION

[0074] The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only used with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used for illustration, not for limiting the present invention.

[0075] In the drawings, each figure shows the general characteristics of the methods, structures and / or materials used in a particular embodiment. However, these drawings should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative size, thickness and position of each film layer, region or structure may be reduced or enlarged, and / or some elements or film layers may be omitted.

[0076] The terms "first", "second", etc. mentioned in this specification or claims are only used to name different elements or distinguish different embodiments or ranges, and are not used to limit the upper or lower limit of the number of elements, nor to limit the manufacturing order or arrangement order of the elements. In addition, an element / film layer disposed on (or above) another element / film layer may include the case where the element / film layer is directly disposed on (or above) the other element / film layer, and the two elements / film layers are in direct contact; and the case where the element / film layer is indirectly disposed on (or above) the other element / film layer, and there are one or more elements / film layers between the two elements / film layers.

[0077] Figures 1 to 3 They are respectively a partial three-dimensional schematic diagram, a partial cross-sectional schematic diagram and a partial top view schematic diagram of an electronic device according to the first embodiment of the present invention. Figure 1 , the electronic device 1 may include a pixel array structure 10, a redistribution structure 12, and a plurality of conductive via structures 13, but is not limited thereto.

[0078] The pixel array structure 10 includes a plurality of signal lines, such as a plurality of scan lines SL and a plurality of data lines DL, but is not limited thereto. The plurality of scan lines SL and the plurality of data lines DL intersect with each other to define a plurality of sub-pixels SP. Each sub-pixel SP may include a scan line SL and a data line DL. However, the relative arrangement relationship of the scan lines SL, the data lines DL, and the sub-pixels SP or the number of the scan lines SL and the data lines DL included in each sub-pixel SP may be changed as required.

[0079] The rewiring structure 12 is arranged to overlap with the pixel array structure 10. In other words, the rewiring structure 12 and the pixel array structure 10 overlap with each other in the thickness direction (such as the third direction D3) of the electronic device 1. The rewiring structure 12 may include a plurality of conductive lines CL. Figure 1 As shown, the plurality of conductive lines CL of the redistribution structure 12 may at least partially overlap the plurality of signal lines (such as the data lines DL and the scan lines SL) of the pixel array structure 10, which is beneficial to maintaining the aperture ratio or light transmittance of the electronic device 1. Any embodiment of the present invention may be combined with the technical means described herein (i.e., the plurality of conductive lines CL may at least partially overlap the plurality of signal lines) without conflict, and will not be repeated below.

[0080] A plurality of conductive via structures 13 electrically connect a plurality of signal lines (such as a plurality of data lines DL) of the pixel array structure 10 with a plurality of conductive lines CL of the rewiring structure 12. Specifically, the conductive via structure 13 may include a plurality of conductive structures stacked and arranged in the thickness direction (such as the third direction D3) of the electronic device 1. One of the conductive via structures 13 may be connected to a corresponding signal line, and another of the conductive via structures 13 may be connected to a corresponding conductive line CL. In some embodiments, at least one conductive structure of the conductive via structure 13 and at least one conductive structure of the pixel array structure 10 may be patterned by the same conductive layer. In other words, at least one of the plurality of conductive via structures 13 may share at least one conductive layer with the pixel array structure 10.

[0081] In some embodiments, the electronic device 1 may further include a driving circuit 20. The driving circuit 20 overlaps the pixel array structure 10 and the redistribution structure 12, and the driving circuit 20 may be electrically connected to a plurality of signal lines (such as a plurality of data lines DL) of the pixel array structure 10 through a plurality of conductive lines CL of the redistribution structure 12 and a plurality of conductive via structures 13.

[0082] The multiple signal lines of the pixel array structure 10 can receive signals from the driving circuit 20 via the multiple wires CL of the rewiring structure 12 and the multiple conductive through-hole structures 13. The electronic device 1 does not need to set peripheral lines around the active area (the area where the multiple sub-pixels SP are located), which helps to achieve a full narrow frame design. In addition, as the size or resolution of the electronic device increases, a suitable signal transmission path can be provided by designing at least one of the conductive through-hole structure 13, the wire CL and the driving circuit 20 (such as size, number or position), which helps to improve the resistance and capacitance load problem. In some embodiments, the electronic device 1 can be applied to borderless mobile phones, borderless tablets or ultra-narrow desktop displays. In some embodiments, when the electronic device 1 has a high light transmittance requirement (such as applied to a transparent display), a miniature driving circuit 20 can be used to reduce the visibility of the driving circuit 20. In some embodiments, the electronic device 1 can also be applied to a replaceable display module of a large-size spliced ​​display.

[0083] Figure 1The conductive through-hole structure 13 is schematically shown in a rectangular frame, wherein each data line DL can be electrically connected to the driving circuit 20 through more than one conductive through-hole structure 13 (the upper and lower layers can be the same conductive through-hole or different conductive through-holes) and more than one conductive wire CL. In the architecture where one data line DL is electrically connected to multiple conductive through-hole structures 13, two conductive through-hole structures 13 electrically connected to the same data line DL can be respectively located in sub-pixels SP at opposite ends of the data line DL. However, the top view shape of the conductive through-hole structure 13, the number of conductive through-hole structures 13 electrically connected to each signal line, the number of conductive wires CL electrically connected to each signal line, or the position of multiple conductive through-hole structures 13 in the sub-pixel array can be changed as required, and other signal lines (such as multiple scan lines SL) in the pixel array structure 10 can also be electrically connected to the driving circuit 20 through multiple conductive through-hole structures 13 and multiple conductive wires CL.

[0084] In some embodiments, Figure 2 As shown, the electronic device 1 may further include a substrate 16 and a component layer 18. However, according to different requirements, the electronic device 1 may further include other components / layers or omit at least one of the above components / layers.

[0085] The substrate 16 is used to carry components, and the substrate 16 can be a hard substrate or a flexible substrate. For example, the material of the hard substrate is glass, wafer, quartz or other hard materials, and the material of the flexible substrate is polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyamide (PA), polyethylenenaphthalate (PEN), polyethyleneimine (PEI), polyurethane (PU), polydimethylsiloxane (PDMS), acrylic polymers such as polymethylmethacrylate (PMMA), ether polymers such as polyethersulfone (PES) or polyetheretherketone (PEEK), polyolefin, thin glass or other flexible materials, but not limited thereto.

[0086] The pixel array structure 10 may be disposed on a substrate 16. In some embodiments, Figure 2As shown, the pixel array structure 10 may include a buffer layer 100, a semiconductor layer 101, a gate insulating layer 102, a first conductive layer 103, a first insulating layer 104, an intermediate conductive layer 105, a second insulating layer 106, a second conductive layer 107, a third insulating layer 108, a fourth insulating layer 109 and a third conductive layer 110. However, according to different requirements, the pixel array structure 10 may adjust the relative position relationship of each element / film layer, or further include other elements / film layers or omit at least one of the above elements / film layers.

[0087] The buffer layer 100, the semiconductor layer 101, the gate insulating layer 102, the first conductive layer 103, the first insulating layer 104, the intermediate conductive layer 105, the second insulating layer 106, the second conductive layer 107, the third insulating layer 108, the fourth insulating layer 109 and the third conductive layer 110 are sequentially formed on the substrate 16. The manufacturing method, materials and relative arrangement relationship of the above-mentioned multiple layers can be configured according to requirements and are not limited here.

[0088] Figure 2 In the embodiment, the pixel array structure 10 may include four conductive layers, such as a first conductive layer 103, an intermediate conductive layer 105, a second conductive layer 107 and a third conductive layer 110. In some embodiments, based on conductivity or signal transmission efficiency considerations, the materials of the first conductive layer 103, the intermediate conductive layer 105 and the second conductive layer 107 may include metals, but are not limited thereto. In addition, based on aperture ratio or transmittance considerations, the material of the third conductive layer 110 may include a light-transmitting conductive material, but is not limited thereto. According to different requirements, the pixel array structure 10 may increase or decrease the number of conductive layers. For example, the pixel array structure 10 may not include the intermediate conductive layer 105, and the second conductive layer 107 may be disposed on the second insulating layer 106 (such as Fig.11 shown).

[0089] Figure 2 In the embodiment, the semiconductor layer 101 may be a patterned semiconductor layer and include a plurality of channel patterns CH ( Figure 2 Schematically shows a channel pattern CH). The first conductive layer 103 may be a patterned conductive layer and include a plurality of scan lines SL (refer to Figure 3 ), multiple gates GE ( Figure 2 Schematically shows a gate electrode GE), a plurality of lower electrodes BE ( Figure 2 Schematically shows a lower electrode BE) and a plurality of intermediate patterns MP ( Figure 2 In other words, the plurality of scan lines SL, the plurality of gate electrodes GE, the plurality of bottom electrodes BE and the plurality of middle patterns MP belong to the same layer. The middle conductive layer 105 may be a patterned conductive layer and include a plurality of top electrodes TE ( Figure 2Schematically shows one upper electrode TE). The second conductive layer 107 may be a patterned conductive layer and include a plurality of data lines DL (refer to Figure 3 ), multiple power lines PL (refer to Figure 3 ), multiple source electrodes SE ( Figure 2 Schematically shows a source electrode SE), multiple drain electrodes DE ( Figure 2 Schematically shows a drain electrode DE) and a plurality of upper layer patterns TP ( Figure 2 Schematically showing an upper pattern TP). In other words, the plurality of data lines DL, the plurality of power lines PL, the plurality of source electrodes SE, the plurality of drain electrodes DE and the plurality of upper patterns TP belong to the same layer. In other embodiments, the plurality of data lines DL and the plurality of power lines PL may belong to different layers. For example, the plurality of power lines PL may be manufactured together with the plurality of upper electrodes TE, that is, the plurality of power lines PL may belong to the same layer as the plurality of upper electrodes TE. The third conductive layer 110 may be a patterned conductive layer and include a plurality of pixel electrodes PE ( Figure 2 A pixel electrode PE is schematically shown.

[0090] The pixel array structure 10 may include a plurality of active elements AE ( Figure 2 An active element AE is schematically shown. Each active element AE may include a channel pattern CH, a gate GE, a source SE, and a drain DE, but is not limited thereto. Figure 2 As shown in FIG. 1 , the source electrode SE can be electrically connected to the corresponding channel pattern CH through a conductive via CV1 penetrating the gate insulating layer 102, the first insulating layer 104, and the second insulating layer 106. In addition, the drain electrode DE can be electrically connected to the corresponding channel pattern CH through another conductive via CV1. In addition, the drain electrode DE can also be electrically connected to the corresponding pixel electrode PE through a conductive via CV1A penetrating the third insulating layer 108 and the fourth insulating layer 109. However, the type of active element AE and the relative arrangement relationship of each element in the active element AE can be changed according to needs, and it is not limited to Figure 2 For example, the active element AE can be an amorphous silicon thin film transistor (a-Si TFT), a low temperature polysilicon (LTPS) thin film transistor, a high temperature polysilicon (HTPS) thin film transistor or an oxide thin film transistor (oxide TFT), but is not limited thereto.

[0091] The pixel array structure 10 may further include a plurality of capacitors C ( Figure 2A capacitor C is schematically shown. Each capacitor C may include a lower electrode BE and an upper electrode TE. In some embodiments, the upper electrode TE may be electrically connected to the corresponding source electrode SE through a conductive via CV2 penetrating the second insulating layer 106 .

[0092] Figure 3 The relative arrangement relationship between a plurality of signal lines (such as a plurality of scan lines SL, a plurality of data lines DL, and a plurality of power lines PL) and a plurality of sub-pixels SP in the pixel array structure 10 is schematically shown. Figure 3 As shown, each scan line SL may extend in the first direction D1, and a plurality of scan lines SL may be arranged in the second direction D2. The first direction D1 and the second direction D2 intersect with each other and are both perpendicular to the thickness direction of the electronic device 1 (such as the third direction D3). The first direction D1 and the second direction D2 may be perpendicular to each other, but are not limited thereto. Each data line DL may extend in the second direction D2, and a plurality of data lines DL may be arranged in the first direction D1. Each power line PL may extend in the second direction D2, and a plurality of power lines PL may be arranged in the first direction D1. As shown Figure 3 As shown, the plurality of data lines DL and the plurality of power lines PL may be alternately arranged in the first direction D1, but are not limited thereto. In other embodiments, the plurality of signal lines may further include wirings for other purposes, such as repair lines (not shown) or common electrode lines (not shown), but are not limited thereto.

[0093] Figure 3 Nine sub-pixels SP are schematically shown by thick solid lines. The nine sub-pixels SP are arranged in a rectangular array in the first direction D1 and the second direction D2. However, the number of sub-pixels SP and their arrangement can be changed according to requirements (such as the shape of the active area of ​​the electronic device 1). For example, multiple sub-pixels SP can also be arranged in a non-rectangular array (such as a circle, other polygons or irregular shapes, etc.). In some embodiments, each sub-pixel SP may include a scan line SL, a data line DL and a power line PL. However, the number of scan lines SL, the number of data lines DL and the number of power lines PL in each sub-pixel SP or the relative arrangement relationship between each sub-pixel SP and the corresponding signal lines can be changed according to requirements.

[0094] Please refer to Figure 2 , the device layer 18 can be disposed on the substrate 16 and overlap the pixel array structure 10 and the redistribution structure 12. In some embodiments, as Figure 2As shown, the component layer 18 may be disposed on a side of the pixel array structure 10 away from the substrate 16, for example, on the third conductive layer 110, but not limited thereto. In some embodiments, the component layer 18 may include a display medium layer, such as a liquid crystal layer or an electrophoretic layer, but not limited thereto. Correspondingly, the electronic device 1 may provide a display function. In other embodiments, the component layer 18 may include a photoelectric conversion layer. For example, the component layer 18 may include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a photo sensing element (photodiode, PD), but not limited thereto. Correspondingly, the electronic device 1 may provide a lighting function, a display function or a photo sensing function.

[0095] The redistribution structure 12 may be disposed on the substrate 16. In some embodiments, the pixel array structure 10 and the redistribution structure 12 are disposed on opposite surfaces of the substrate 16, but are not limited thereto. Figure 2 As shown, the redistribution structure 12 may include a buffer layer 120, a first insulating layer 121, a first redistribution conductive layer 122, a second insulating layer 123, and a second redistribution conductive layer 124. However, according to different requirements, the redistribution structure 12 may further include other elements / layers or omit at least one of the above elements / layers.

[0096] The buffer layer 120, the first insulating layer 121, the first redistribution conductive layer 122, the second insulating layer 123 and the second redistribution conductive layer 124 are, for example, sequentially formed on the substrate 16. For example, after forming the pixel array structure 10 and the device layer 18, the substrate 16 can be turned upside down, and the buffer layer 120, the first insulating layer 121, the first redistribution conductive layer 122, the second insulating layer 123 and the second redistribution conductive layer 124 are sequentially formed. The manufacturing method, materials and relative arrangement relationship of the above-mentioned multiple layers can be configured according to requirements, and are not limited here.

[0097] Figure 2 In the embodiment, the redistribution structure 12 may include two conductive layers, such as a first redistribution conductive layer 122 and a second redistribution conductive layer 124. In some embodiments, based on the consideration of conductivity or signal transmission efficiency, the materials of the first redistribution conductive layer 122 and the second redistribution conductive layer 124 may include metal, but are not limited thereto. According to different requirements, the redistribution structure 12 may increase or decrease the number of conductive layers.

[0098] The first redistribution conductive layer 122 may be a patterned conductive layer and include a plurality of conductive lines 1220 ( Figure 2 Schematically showing a conductive line 1220). The second redistribution conductive layer 124 may be a patterned conductive layer and include a plurality of conductive lines 1240 ( Figure 2 A conductive line 1240 is schematically shown). In some embodiments, the conductive line 1220 is electrically connected to the corresponding intermediate pattern MP by penetrating the first insulating layer 121, the buffer layer 120, the substrate 16, the buffer layer 100 and the gate insulating layer 102 through a conductive via CV4. The manufacturing method of the conductive via CV4 may include, for example, drilling (such as laser drilling, but not limited to), wet etching, dry etching, or dry-wet hybrid etching to form a through hole penetrating the first insulating layer 121, the buffer layer 120, the substrate 16, the buffer layer 100 and the gate insulating layer 102, and then when forming the first rewiring conductive layer 122, the material of the first rewiring conductive layer 122 is filled into the through hole. In addition, the conductive line 1240 can be electrically connected to the corresponding conductive line 1220 through a conductive via CV5 penetrating the second insulating layer 123.

[0099] In some embodiments, Figure 2 As shown, at least one of the multiple conductive via structures 13 of the electronic device 1 may include an upper pattern TP, a conductive via CV3, an intermediate pattern MP, and a conductive via CV4, but is not limited thereto. In other embodiments, the conductive via structure 13 may not include the intermediate pattern MP and the conductive via CV3, and the conductive via CV4 may further penetrate the first insulating layer 104 and the second insulating layer 106. In the case where the conductive via structure 13 includes the intermediate pattern MP and the conductive via CV3, the conductive via CV4 may not further penetrate the first insulating layer 104 and the second insulating layer 106, thereby helping to reduce the size of the conductive via CV4 (such as the thickness of the conductive via CV4 in the third direction D3) or reduce the manufacturing time, material usage, or manufacturing difficulty of the conductive via CV4.

[0100] In some embodiments, the upper pattern TP and the conductive via CV3 in the conductive via structure 13 can be manufactured together with the source SE, the drain DE, the conductive via CV1 and the conductive via CV2 in the pixel array structure 10, and the middle pattern MP in the conductive via structure 13 can be manufactured together with the gate GE and the lower electrode BE in the pixel array structure 10, that is, the conductive via structure 13 can share at least one conductive layer (such as the first conductive layer 103 and the second conductive layer 107) with the pixel array structure 10. On the other hand, the conductive via CV4 in the conductive via structure 13 can be manufactured together with the conductive wire 1220 of the redistribution structure 12, so the conductive via structure 13 can also share at least one conductive layer (such as the first redistribution conductive layer 122) with the redistribution structure 12.

[0101] The driving circuit 20 may be disposed on the second redistribution conductive layer 124 of the redistribution structure 12 and connected to the corresponding conductive wires 1240. The driving circuit 20 may include an integrated circuit, but is not limited thereto.

[0102] In each sub-pixel SP, the maximum size S of the conductive via structure 13 is, for example, determined by the conductive via with the largest thickness in the conductive via structure 13 (such as the conductive via CV4). In some embodiments, the maximum size S of the conductive via structure 13 (such as the maximum width of the conductive via CV4 in the first direction D1) may be greater than or equal to S1 and less than or equal to S2, that is, S1≤S≤S2. S1=2*d*cotθ+a1, and S2=(25400 / PPI)-a2. In the above formula, d is the thickness of the conductive via (such as the thickness of the conductive via CV4 in the third direction D3), and θ is the angle between the side wall surface of the conductive via at the narrow end and the contact surface at the narrow end outside the conductive via (refer to Figure 2 ), a1 is the contact width of the conductive via at the narrow end (e.g., the maximum contact width of the conductive via CV4 in the first direction D1), PPI is the sub-pixel density (sub-pixel per inch), and a2 is the line pitch of the conductive lines CL of the redistribution structure 12 (e.g., the maximum line pitch in the first direction D1). In some embodiments, a1≥2μm, and a2≥2μm.

[0103] Other embodiments of the electronic device of the present invention are described below with other drawings. In the following embodiments, the same or similar elements will use the same or similar reference numerals, and their redundant description will be omitted. In addition, the features of different exemplary embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made according to this specification or claims are still within the scope of this patent.

[0104] Figure 4 is a partial top view of an electronic device according to a second embodiment of the present invention. Figure 4 In the electronic device 1A, two adjacent rows of sub-pixels SP (such as Figure 4 The six sub-pixels SP on the left share a signal line (such as Figure 4 The middle power line PL), and the one signal line (such as Figure 4The power line PL in the middle is electrically connected to at least one conductive through-hole structure 13. The design of shared signal lines helps to reduce the number of conductive through-hole structures 13, thereby improving the aperture ratio or light transmittance of the electronic device 1A. In some embodiments, the conductive through-hole structure 13 may be arranged between four adjacent sub-pixels SP (as shown in the thick dotted box) to reduce the shielding rate of each of the four sub-pixels SP, but is not limited to this. In other embodiments, multiple signal lines (such as multiple power lines PL or multiple common electrode lines not shown) may also share one or more conductive through-hole structures 13, and the multiple signal lines may be electrically connected to each other through connecting lines (not shown) to reduce the number of conductive through-hole structures 13, thereby improving the aperture ratio or light transmittance of the electronic device 1A. Any embodiment of the present invention may be combined with the technical means described herein without conflict, and will not be repeated below.

[0105] Figure 5 is a partial top view of an electronic device according to a third embodiment of the present invention. Figure 5 , the electronic device 1B can utilize the circuit design of the data demultiplexer 22 to reduce the number of the conductive via structures 13, thereby increasing the aperture ratio or light transmittance of the electronic device 1B. Figure 5 Schematically showing that the gate electrodes GE1 of three active elements AD1 are electrically connected to the conductive via structures 13A respectively, so as to be electrically connected to the corresponding driving circuit (not shown) through the conductive via structures 13A, so that the active elements AD1 are turned on (or turned off) in sequence. The source electrodes SE1 of the active elements AD1 are electrically connected to the same conductive via structure 13, so as to receive data signals from the driving circuit (not shown) through the conductive via structure 13. The drain electrodes DE1 of the active elements AD1 are electrically connected to the data lines DL respectively, so as to transmit the data signals to the data lines DL. The number and configuration position of the data demultiplexer 22 can be determined according to the requirements and are not limited here.

[0106] Figure 6 is a partial top view schematically showing an electronic device according to a fourth embodiment of the present invention. FIG. 7A to FIG. 7C They are Figure 6 Please refer to the circuit diagram of the shift register unit SR1 to the shift register unit SR3. Figures 6 to 7C, the electronic device 1C also includes a gate driver circuit (Gate Driver on Array, GOA) 24. Compared with setting the gate driver circuit 24 at the periphery of the active area (the area where the multiple sub-pixels SP are located), by setting the gate driver circuit 24 in the active area and electrically connecting it to the drive circuit (not shown) through the conductive through-hole structure 13B to the conductive through-hole structure 13F, it is helpful to achieve a full narrow frame design. In some embodiments, the gate driver circuit 24 may include shift register units SR1 to SR3. Each of the shift register units SR1 to SR3 includes a signal line CLK, a signal line XCLK, a signal line INPUT, a signal line OUTPUT, a signal line VGH, and a signal line VGL. The signal line INPUT in the shift register unit SR1 is electrically connected to the drive circuit (not shown) through the conductive through-hole structure 13B. The signal line VGL and the signal line XCLK in the shift register unit SR2 are electrically connected to the drive circuit (not shown) through the conductive through-hole structure 13C and the conductive through-hole structure 13D, respectively. The signal line CLK and the signal line VGH in the shift register unit SR3 are electrically connected to the driving circuit (not shown) through the conductive via structure 13E and the conductive via structure 13F respectively. The number and configuration position of the shift register units can be determined according to the requirements and are not limited here.

[0107] Figure 8 and Fig. 9 They are respectively a partial top view and a partial cross-sectional view of an electronic device according to a fifth embodiment of the present invention. Figure 8 and Fig. 9 In the electronic device 1D, considering the processing uniformity or the visual uniformity of the electronic device 1D, the electronic device 1D may further include a plurality of simulated conductive via structures 13X. Each sub-pixel SP may be provided with, for example, at least one of a conductive via structure 13 and a simulated conductive via structure 13X. Figure 8 As shown, assuming that each sub-pixel SP is designed to include two conductive via structures, the two conductive via structures can be two conductive via structures 13, or a combination of a conductive via structure 13 and a simulated conductive via structure 13X, or two simulated conductive via structures 13X (not shown).

[0108] In some embodiments, Fig. 9As shown, at least one of the multiple simulated conductive via structures 13X may include an upper layer pattern TP, a conductive via CV3, and a middle pattern MP, that is, at least one of the multiple simulated conductive via structures 13X may share at least one conductive layer (such as the first conductive layer 103 and the second conductive layer 107) with the pixel array structure 10. In addition, the multiple simulated conductive via structures 13X may not be electrically connected to the multiple conductive lines CL of the redistribution structure 12.

[0109] Fig.10 FIG. 1 is a partial top view of an electronic device according to a sixth embodiment of the present invention. Fig.10 In the electronic device 1E, the pixel array structure further includes a plurality of stretchable electrodes 111. Part of the signal line (such as the scan line SL or the data line DL) may be formed by the stretchable electrode 111. For example, at least one of the plurality of stretchable electrodes 111 may be located at the junction of two adjacent sub-pixels SP and connect two parts of the same signal line (such as the scan line SL or the data line DL) located in the two adjacent sub-pixels SP. In other embodiments, the entire signal line (such as the scan line SL or the data line DL) may also be formed by the stretchable electrode 111. The stretchable electrode 111 has high stretchability and conductivity. For example, the material of the stretchable electrode 111 may include carbon-based nanomaterials, metal nanomaterials, or a combination thereof, but is not limited thereto.

[0110] Fig.11 is a partial cross-sectional schematic diagram of an electronic device according to a seventh embodiment of the present invention. Fig.11 In the electronic device 1F, the pixel array structure 10 is located between the redistribution structure 12 and the substrate 16, and the element layer 18 is located between the redistribution structure 12 and the pixel array structure 10. For example, the buffer layer 120 of the redistribution structure 12 can be disposed on the element layer 18, the third conductive layer 110, and the fourth insulating layer 109. In addition, in the conductive via structure 13, the conductive via CV4F penetrates the first insulating layer 121, the buffer layer 120, the fourth insulating layer 109, and the third insulating layer 108, and the opposite ends of the conductive via CV4F are respectively connected to the conductive wire 1220 and the upper pattern TP. The electronic device 1F can be applied to an embedded sensing display device, for example, but is not limited thereto.

[0111] Fig.11 The intermediate conductive layer 105 and the capacitor C are not shown. According to different requirements, the pixel array structure 10 of the electronic device 1F may include or exclude the intermediate conductive layer 105 and the capacitor C. Any embodiment of the present invention may be combined with the technical means described herein without conflict, and will not be repeated below.

[0112] Fig.12is a partial cross-sectional schematic diagram of an electronic device according to an eighth embodiment of the present invention. Fig.12 In the electronic device 1G, the redistribution structure 12G is located between the device layer 18 and the pixel array structure 10G.

[0113] In some embodiments, Fig.12 As shown, after the buffer layer 100 to the third insulating layer 108 of the pixel array structure 10G are sequentially formed on the substrate 16, the first insulating layer 121 to the second redistribution conductive layer 124 of the redistribution structure 12G may be formed successively, and then the driving circuit 20, the insulating layer 109G, the conductive layer 110G, the device layer 18 and the buffer layer 120G are sequentially formed. Under this architecture, the pixel array structure 10G may not include the fourth insulating layer 109 and the third conductive layer 110, and the redistribution structure 12G may not include the buffer layer 120. In addition, the first insulating layer 121 of the redistribution structure 12G is disposed on the third insulating layer 108 of the pixel array structure 10G. In the conductive via structure 13G, the conductive via CV4G penetrates the first insulating layer 121 and the third insulating layer 108, and the opposite ends of the conductive via CV4G are respectively connected to the conductive wire 1220 and the upper pattern TP. The insulating layer 109G of the electronic device 1G is disposed on the driving circuit 20 and the second insulating layer 123. The conductive layer 110G of the electronic device 1G is disposed on the insulating layer 109G. The conductive layer 110G may be a patterned conductive layer and include a plurality of pixel electrodes PEG ( Fig.12 One pixel electrode PEG is schematically shown. The pixel electrode PEG may be electrically connected to the wire 1220 through a conductive via CV1G penetrating the insulating layer 109G and the second insulating layer 123. The buffer layer 120G of the electronic device 1G is disposed on the element layer 18 and the conductive layer 110G.

[0114] Fig.13 FIG. 1 is a partial cross-sectional diagram of an electronic device according to a ninth embodiment of the present invention. Fig.13 In the electronic device 1H, the substrate 16 is located between the device layer 18 and the pixel array structure 10G. For example, the electronic device 1H may not include the insulating layer 109G, and the conductive layer 110H, the device layer 18 and the buffer layer 120G of the electronic device 1H may be sequentially disposed on the surface of the substrate 16 away from the pixel array structure 10G, wherein the pixel electrode PEH of the conductive layer 110H is electrically connected to the corresponding middle pattern MP through the conductive via CV1H penetrating the substrate 16 and the buffer layer 100 to the gate insulating layer 102.

[0115] Fig.14 and Fig.15 They are respectively a partial three-dimensional schematic diagram and a partial cross-sectional schematic diagram of an electronic device according to the tenth embodiment of the present invention. Fig.14 and Fig.15 The electronic device 1I includes a plurality of pixel array structures, such as a first pixel array structure 10-1 and a second pixel array structure 10-2. The first pixel array structure 10-1 is located between the second pixel array structure 10-2 and the rewiring structure 12. The plurality of wires of the rewiring structure 12 include a plurality of first wires CL-1 and a plurality of second wires CL-2. For the convenience of distinction, Fig.14 The first conductive wire CL-1 and the second conductive wire CL-2 are represented by solid lines of different line widths. The plurality of conductive through-hole structures include a plurality of first conductive through-hole structures 13-1 and a plurality of second conductive through-hole structures 13-2. For easy distinction, the areas where the first conductive through-hole structures 13-1 and the second conductive through-hole structures 13-2 are located are indicated by different background colors. The plurality of signal lines (such as the plurality of data lines DL) in the first pixel array structure 10-1 are electrically connected to the plurality of first conductive wires CL1 of the rewiring structure 12 through the plurality of first conductive through-hole structures 13-1, and the plurality of signal lines (such as the plurality of data lines DL) in the second pixel array structure 10-2 are electrically connected to the plurality of second conductive wires CL2 of the rewiring structure 12 through the plurality of second conductive through-hole structures 13-2. Fig.14 The schematic diagram shows that a plurality of first conductive lines CL1 and a plurality of second conductive lines CL2 are electrically connected to one driving circuit 20. Alternatively, the plurality of first conductive lines CL1 and the plurality of second conductive lines CL2 may be electrically connected to a plurality of driving circuits 20 (eg, Fig.15 shown).

[0116] Please refer to Fig.15 The first pixel array structure 10-1 and the components / film layers in the redistribution structure 12 and their relative arrangement relationship can be referred to above and will not be repeated here. The second pixel array structure 10-2 is disposed on the substrate 26 and may have a substantially similar structure to the first pixel array structure 10-1. Fig.15The second pixel array structure 10-2 does not show the intermediate conductive layer 105, the second insulating layer 106 and the capacitor C. However, according to different requirements, the pixel array structure 10-2 may include or exclude the intermediate conductive layer 105, the second insulating layer 106 or the capacitor C. The element layer 28 is disposed on the pixel electrode PE of the second pixel array structure 10-2. The element layer 28 and the element layer 18 can be used to provide different functions, such as two of the lighting function, the display function and the light sensing function, but are not limited thereto. For example, one of the element layer 28 and the element layer 18 may include, for example, a sub-millimeter light emitting diode array or a micro light emitting diode array to provide a lighting function, and the other of the element layer 28 and the element layer 18 may include, for example, a liquid crystal layer to provide a display function. As another option, one of the element layer 28 and the element layer 18 may include a liquid crystal layer, an electrophoretic layer, an organic light emitting diode array, a sub-millimeter light emitting diode array or a micro light emitting diode array to provide a display function, and the other of the element layer 28 and the element layer 18 may include, for example, a light sensing element array to provide a light sensing function.

[0117] In some embodiments, Fig.15 As shown, the first conductive via structure 13-1 may have Figure 2 The conductive through hole structure 13 of the first pixel array structure 10-1 is similar to that of the conductive through hole structure 13, that is, the first conductive through hole structure 13-1 may include an upper pattern TP, a conductive through hole CV3, an intermediate pattern MP and a conductive through hole CV4, but is not limited thereto. On the other hand, the second conductive through hole structure 13-2 may further include a conductive through hole CV1A, a conductive pattern CP2, a connector CT and a conductive pattern CP1 in addition to an upper pattern TP, a conductive through hole CV3, an intermediate pattern MP and a conductive through hole CV4. The conductive pattern CP2 may be formed together with the pixel electrode PE in the first pixel array structure 10-1, and the conductive pattern CP2 may be electrically connected to the upper pattern TP through the conductive through hole CV1A. The conductive pattern CP1 may be formed together with the pixel electrode PE of the second pixel array structure 10-2. After the second pixel array structure 10-2 and the element layer 28 are disposed on the substrate 26, the substrate 26 can be turned over so that the second pixel array structure 10-2 faces the first pixel array structure 10-1, and the first pixel array structure 10-1 is bonded to the second pixel array structure 10-2 through the bonding layer 30, and the conductive pattern CP1 is electrically connected to the conductive pattern CP2 through the connector CT. The connector CT includes, for example, a conductive glue or a welding member, but is not limited thereto.

[0118] Fig.16 and Fig.17 They are respectively a partial cross-sectional schematic diagram and a partial top view schematic diagram of an electronic device according to the eleventh embodiment of the present invention. Fig.16 and Fig.17 In the electronic device 1J, the pixel array structure 10J is, for example, a passive pixel array structure. In addition, the pixel array structure 10J may not include the power line PL, the active element AD, the capacitor C, the semiconductor layer 101 and the intermediate conductive layer 105, but is not limited thereto.

[0119] In one embodiment of the present invention, a plurality of signal lines of the pixel array structure can be connected to a plurality of wires of the rewiring structure through a plurality of conductive via structures, and then connected to a driving system end (such as a driving circuit) through the plurality of wires of the rewiring structure, so that the electronic device does not need to set up peripheral circuits, thereby facilitating the realization of a narrow frame or even a frameless design. In addition, as the size or resolution of the electronic device increases, a suitable signal transmission path can be provided by designing at least one of the conductive via structure, wire, and driving circuit (such as size, quantity, or position), thereby helping to improve the resistance and capacitance load problem.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims and their equivalents.

Claims

1. An electronic device, characterized in that: include: A pixel array structure including a plurality of signal lines; A rewiring structure, which is overlapped with the pixel array structure and includes a plurality of conductive lines; as well as a plurality of conductive via structures, electrically connecting the plurality of signal lines of the pixel array structure with the plurality of conductive lines of the rewiring structure, wherein at least one of the plurality of conductive via structures shares at least one conductive layer with the pixel array structure, The plurality of signal lines include a plurality of power lines and a plurality of data lines, the power lines and the plurality of data lines are electrically connected to different conductive through-hole structures, the pixel array structure further includes a plurality of sub-pixels, two adjacent rows of sub-pixels share a power line, the power line is electrically connected to at least one conductive through-hole structure, and the arrangement direction of each row of sub-pixels in the two adjacent rows of sub-pixels is parallel to the extension direction of the shared power line.

2. The electronic device according to claim 1, characterized in that: It also includes at least one of a data demultiplexer, a shift register unit, and a gate driving circuit.

3. The electronic device according to claim 1, characterized in that: Also includes: A plurality of simulated conductive via structures, wherein at least one of the plurality of simulated conductive via structures shares at least one conductive layer with the pixel array structure, and each sub-pixel is provided with a conductive via structure and at least one of the simulated conductive via structures.

4. The electronic device according to claim 1, characterized in that: The pixel array structure further includes a plurality of stretchable electrodes, at least one of which is located at a boundary between two adjacent sub-pixels and connects two parts of a same signal line located in the two adjacent sub-pixels.

5. The electronic device according to claim 1, characterized in that: Also includes: A substrate, wherein the pixel array structure and the redistribution structure are arranged on the substrate; as well as The component layer is arranged on the substrate and overlaps the pixel array structure and the redistribution structure.

6. The electronic device according to claim 5, characterized in that: The element layer includes a display medium layer or a photoelectric conversion layer.

7. The electronic device according to claim 5, characterized in that: The pixel array structure and the redistribution structure are respectively arranged on opposite surfaces of the substrate, and the multiple conductive through-hole structures penetrate the substrate to electrically connect the multiple signal lines of the pixel array structure with the multiple conductive lines of the redistribution structure, wherein the component layer is arranged on a side of the pixel array structure away from the substrate.

8. The electronic device according to claim 5, characterized in that: The pixel array structure is located between the redistribution structure and the substrate, and The component layer is located between the redistribution structure and the pixel array structure, or the redistribution structure is located between the component layer and the pixel array structure, or the substrate is located between the component layer and the pixel array structure.

9. The electronic device according to claim 1, characterized in that: The electronic device includes a plurality of the pixel array structures, the plurality of the pixel array structures include a first pixel array structure and a second pixel array structure, and the first pixel array structure is located between the second pixel array structure and the rewiring structure, The plurality of wires of the rewiring structure include a plurality of first wires and a plurality of second wires, the plurality of conductive via structures include a plurality of first conductive via structures and a plurality of second conductive via structures, and The multiple signal lines in the first pixel array structure are electrically connected to the multiple first wires of the rewiring structure through the multiple first conductive via structures, and the multiple signal lines in the second pixel array structure are electrically connected to the multiple second wires of the rewiring structure through the multiple second conductive via structures.

10. The electronic device according to claim 1, characterized in that: The at least one of the plurality of conductive via structures shares a first conductive layer and a second conductive layer in the pixel array structure with the pixel array structure.

11. The electronic device according to claim 1, characterized in that: Each signal line in the pixel array structure is electrically connected to a corresponding wire in the rewiring structure through at least one conductive through-hole structure.

12. The electronic device according to claim 1, characterized in that: The plurality of conductive lines of the redistribution structure at least partially overlap the plurality of signal lines of the pixel array structure.

13. The electronic device according to claim 1, characterized in that: Also includes: The driving circuit overlaps the pixel array structure and the rewiring structure, and the driving circuit is electrically connected to the plurality of signal lines of the pixel array structure through the plurality of wires of the rewiring structure and the plurality of conductive through-hole structures.

14. The electronic device according to claim 1, characterized in that: At least one conductive via structure among the plurality of conductive via structures satisfies: S1≤S≤S2; S1 = 2*d*cotθ + a1; and S2=(25400 / PPI)-a2, Wherein S is the maximum size of the at least one conductive via structure, d is the thickness of the conductive via with the largest thickness in the at least one conductive via structure, θ is the angle between the side wall surface of the conductive via with the largest thickness at the narrow end and the contact surface at the narrow end outside the conductive via, a1 is the contact width of the conductive via at the narrow end, PPI is the pixel density, and a2 is the line pitch of the conductive wires of the rewiring structure.

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