Generate vector predicate summary

Abstract

Devices and methods of operating such devices are disclosed. Vector processing circuitry performs data processing in a plurality of parallel processing channels, wherein the data processing is performed in a subset of the plurality of parallel processing channels, the subset being determined by set bit values ​​of a vector predicate. Predicate monitoring circuitry is responsive to the vector predicate and generates a predicate summary value based on the bit values ​​of the vector predicate. A first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition being true when the bit value of the vector predicate includes a set bit corresponding to a vector element at a higher index and an immediately following unset bit corresponding to a vector element at a lower index. A second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate. Thus, improved predicate-controlled vector processing is supported.

Description

Technical Field

[0001] The present technology relates to the field of data processing. Background Art

[0002] In a data processing device comprising vector processing circuitry performing data processing in a plurality of parallel processing channels, it may be arranged that data processing is selectively performed only in a subset of the plurality of parallel processing channels. Furthermore, control of such operation of the vector processing circuitry may be provided by means of vector predicates, which are typically provided as a plurality of bit values ​​corresponding to the number of the plurality of parallel processing channels, and which may be set to indicate whether a particular processing channel should be active. Thus, the vector processing circuitry may perform its data processing operations differently depending on a particular vector predicate received in association with an iteration of the vector processing, activating and deactivating processing channels depending on the bit values ​​of the vector predicate provided to control that iteration. Summary of the invention

[0003] At least some examples provide a device including: vector processing circuitry that performs data processing in a plurality of parallel processing lanes, wherein the data processing is performed in a subset of the plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and predicate monitoring circuitry that generates a predicate summary value based on the bit values ​​of the vector predicate in response to the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit values ​​of the vector predicate include a set bit corresponding to a vector element at a higher index followed by an unset bit corresponding to a vector element at a lower index, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

[0004] At least some examples provide a method including: performing vector data processing in a subset of a plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and generating a predicate summary value based on the bit values ​​of the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit values ​​of the vector predicate include a set bit corresponding to a vector element at a higher index followed by an unset bit corresponding to a vector element at a lower index, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

[0005] At least some examples provide an apparatus including: means for executing a vector data processing device in a subset of a plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and means for generating a predicate summary value based on the bit values ​​of the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit values ​​of the vector predicate include a set bit corresponding to a vector element at a higher index followed by an unset bit corresponding to a vector element at a lower index, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

[0006] At least some examples provide a computer program for controlling a host data processing device to provide an instruction execution environment, comprising: vector processing logic for performing data processing in a plurality of parallel processing channels, wherein the data processing is performed in a subset of the plurality of parallel processing channels, the subset being determined by set bit values ​​of a vector predicate; and predicate monitoring logic for generating a predicate summary value based on the bit values ​​of the vector predicate in response to the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit values ​​of the vector predicate include a set bit corresponding to a vector element at a higher index followed by an unset bit corresponding to a vector element at a lower index, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The techniques of the present disclosure will be further described, by way of example only, in conjunction with the embodiments of the disclosure shown in the accompanying drawings, which are to be read in conjunction with the following description, in which:

[0008] Figure 1 Schematically shows the overall layout of a data processing device in an example embodiment;

[0009] Figure 2A schematically illustrates vector processing of two source vectors to generate a destination vector, wherein only those channels are active for which corresponding bit values ​​of the vector predicates are set;

[0010] Figure 2B schematically illustrates a device according to an example embodiment;

[0011] Figure 3A schematically illustrates a predicate monitoring circuit for generating a predicate summary value representing a sparse condition in an example embodiment;

[0012] Figure 3B shows generation of a predicate summary value when a sparse condition is true in an example embodiment;

[0013] Figure 3Cshows the generation of the predicate summary value when the sparse condition is not true;

[0014] Figure 4A , 4B 4C and 4D show the generation of predicate digest values ​​for an example of a vector predicate resulting in four different possible predicate digest values ​​in a 2-bit example embodiment;

[0015] Figure 5A schematically illustrates a predicate monitoring circuit in an example embodiment arranged to generate a first predicate summary value and a second predicate summary value for two equal-sized portions of a vector predicate;

[0016] Figure 5B schematically illustrates a predicate monitoring circuit arranged to generate a first predicate summary value and a second predicate summary value for a first portion and a second portion of a vector predicate in an example embodiment;

[0017] Figure 6 schematically illustrates predicate monitoring circuitry arranged to generate a predicate summary value and a count of set bits in a vector predicate in one example embodiment;

[0018] Figure 7 schematically illustrates vector processing sampling circuitry associated with vector processing circuitry in an example embodiment and arranged to generate a vector instruction digest;

[0019] Figure 8 is a flow chart illustrating a series of steps taken by a method according to an example embodiment;

[0020] Fig. 9 is a flowchart showing a series of steps taken by a method according to an example embodiment; and

[0021] Fig.10 The implementation of the simulator in the example embodiment is schematically shown. DETAILED DESCRIPTION

[0022] In one example, a device is provided, including: vector processing circuitry that performs data processing in a plurality of parallel processing lanes, wherein the data processing is performed in a subset of the plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and predicate monitoring circuitry that generates a predicate summary value based on the bit values ​​of the vector predicate in response to the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit value of the vector predicate includes a set more significant bit followed by a less significant bit that is not set, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

[0023] The vector processing circuit of the device is arranged to perform data processing in multiple parallel processing channels controlled by the bit values ​​of vector predicates. Setting the bit value corresponding to the vector element at a given index causes the corresponding processing channel to be active for data processing, while not setting the bit corresponding to the specific vector element causes the corresponding processing channel to be inactive for data processing. A different vector predicate can be used for each vector processing instruction executed. When trying to understand and improve vector utilization, it is useful to capture predicate information related to predicate vector instructions. However, it is expensive to capture the entire vector predicate. Methods such as population counts or three-way indicators (showing that no bit / some bits / all bits are set) have limitations. For example, the inventors have realized that both population counts and three-way indicators cannot distinguish between continuous partial predicates (e.g., due to short loops in the program) and sparse predicates (e.g., due to tests in the program (perhaps a loop)). Such different reasons for using partial predicates may point to different practices for improving utilization. Therefore, when controlling the vector processing circuit by means of vector predicates in this way, it is useful to generate information related to the set bits and unset bits of the vector predicates. For example, this information may be collected over multiple iterations of a vector process (where each iteration may have a differently set vector predicate) in order to collect statistics about the manner in which the vector process controlled by the vector predicate is performed. In this case, it has been found useful to generate a predicate summary value so that it indicates whether a sparse condition is true for the vector predicate. The sparse condition is true when the bit value of the vector predicate includes a set bit corresponding to a vector element at a higher index followed by an unset bit corresponding to a vector element at a lower index. Conversely, the sparse condition is not true when this combination of a set bit at a higher index followed by an unset bit at a lower index does not hold. This may be, for example, because all bits of the vector predicate are set, because no bits of the vector predicate are set, or because such a particular bit combination is not found in the vector predicate.

[0024] In some embodiments, the first value of the predicate digest value indicates that the first value of the predicate digest value indicates that a strict subset of bit values ​​of the vector predicate are set, wherein the strict subset of set bits is not in a non-contiguous sequence including the least significant bit of the vector predicate. The first value of the predicate digest value thus corresponds to a strict subset of bit values ​​of the vector predicate that are set. Therefore, it should be understood that when a "strict subset" is mentioned here, this means that it corresponds to fewer than all bit values ​​of the vector predicate being set. This should be compared to the use of the term "subset of a plurality of parallel processing channels" used above to describe those channels that are activated, which means that when all bit values ​​of the vector predicate are set, all processing channels of a plurality of parallel processing channels of the vector processing circuit may be active. In addition, the first value of the predicate digest value indicates that the strict subset of set bits is not a contiguous sequence including the least significant bit of the vector predicate. Therefore, if the strict subset of set bits is a sequence of consecutive set bits, then for the first value of the predicate value digest to be generated, this cannot include the least significant bit of the vector predicate.

[0025] Conversely, in some embodiments, the second value of the predicate digest value indicates that a strict subset of the bit values ​​of the vector predicate are set in a consecutive sequence.

[0026] Furthermore, in some embodiments, the predicate monitoring circuit is responsive to the vector predicate to generate a predicate digest value having a second value when the continuous sequence includes the least significant bit of the vector predicate. Thus, when a strict subset of the bit values ​​of the vector predicate are set in the continuous sequence and the continuous sequence includes the least significant bit of the vector predicate, then the predicate monitoring circuit will generate the second value of the predicate digest value.

[0027] Additionally, other predicate digest values ​​may be defined, and in some embodiments, the predicate monitoring circuitry is responsive to the vector predicate to generate a predicate digest value having a third value of the predicate digest value when no bit values ​​of the vector predicate are set, and to generate a predicate digest value having a fourth value of the predicate digest value when all bit values ​​of the vector predicate are set.

[0028] It may be the case that these four values ​​are the only predicate digest values ​​of interest and this output can be efficiently represented in only a two bit value, so in some example embodiments the predicate monitoring circuitry is arranged to generate the predicate digest value as a 2-bit value.

[0029] In some example embodiments, the predicate digest values ​​are autologous. In other words, the particular bit patterns of the predicate digest values ​​that are selected to represent particular bit patterns within the vector predicates themselves satisfy the same rules as those that define the vector predicates. This property of the predicate digest values ​​may find various applications, for example, allowing at least one additional vector predicate to be combined with at least one predicate digest value in order to generate an additional predicate digest value, wherein the additional predicate digest value will then not only accurately represent the combination of the at least one additional vector predicate and the original predicate digest value, but actually represent the combination of the at least one additional vector predicate and the original vector predicate. Thus, various processing efficiencies may be achieved when summaries of multiple vector predicates are to be generated.

[0030] One particular selection of various values ​​for the predicate digest value that satisfies the homology property occurs in the following embodiment, wherein the third value of the predicate digest value is 00, wherein the second value of the predicate digest value is 01, wherein the first value of the predicate digest value is 10, and wherein the fourth value of the predicate digest value is 11.

[0031] In some embodiments, the predicate monitoring circuit may subdivide the vector predicate into at least two parts and generate a predicate summary value for each part. Thus, in some embodiments, the predicate monitoring circuit generates a first predicate summary value and at least one additional predicate summary value according to the bit values ​​of the vector predicate in response to the vector predicate, wherein the first predicate summary value and the at least one additional predicate summary value correspond to the first part and the at least one additional part of the vector predicate.

[0032] In some embodiments, the first portion and at least one further portion of the vector predicate are of the same size. In some embodiments, the first portion and at least one further portion of the vector predicate are of different sizes.

[0033] In addition to generating predicate summary values, the predicate monitoring circuitry may also generate other information related to the vector predicates. For example, in some embodiments, the predicate monitoring circuitry is also responsive to the vector predicates to generate a predicate count value indicating a count of set bits in the vector predicates.

[0034] The predicate monitoring circuitry may be arranged to return a predicate count value in response to various conditions, but in some embodiments the predicate monitoring circuitry is responsive to a count instruction to return a predicate count value indicative of a count of set bits in the vector predicate.

[0035] Thus, the count instruction may be a trigger that causes the predicate monitoring circuitry to return a predicate count value, and in some embodiments, the predicate monitoring circuitry may additionally return other information. For example, the predicate monitoring circuitry may further respond to the count instruction to return a predicate summary value.

[0036] Where the apparatus comprises vector processing circuitry, it may be useful to monitor the operation of the vector processing circuitry in various ways. Accordingly, in some embodiments, the apparatus further comprises vector processing sampling circuitry associated with the vector processing circuitry to generate vector instruction summaries for vector instructions executed by the vector processing circuitry, wherein the vector processing sampling circuitry comprises predicate monitoring circuitry.

[0037] The vector instruction digest may be generated according to various conditions, but in some example embodiments, the vector processing sampling circuitry is responsive to a sampling trigger condition to generate the vector instruction digest.

[0038] Generating a predicate digest value having at least one of a first value and a second value may be particularly meaningful in monitoring the operation of the vector processing circuit, and therefore, in some embodiments, the predicate monitoring circuit further comprises at least one counter for counting the occurrence of the generation of the predicate digest value having at least one of the first value and the second value. Therefore, statistical data may be collected based on the at least one counter.

[0039] In some such embodiments, the predicate monitoring circuit is responsive to a count summary trigger to output at least one value of at least one counter. Thus, the count summary trigger may be defined in various ways to access the value of at least one counter and utilize such statistical data.

[0040] In one example, a method is provided that includes: performing vector data processing in a subset of a plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and generating a predicate summary value based on the bit values ​​of the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit value of the vector predicate includes a set higher significant bit followed by an unset lower significant bit, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

[0041] In one example, an apparatus is provided that includes: means for performing vector data processing in a subset of a plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and means for generating a predicate summary value based on the bit values ​​of the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit value of the vector predicate includes a set more significant bit followed by an unset less significant bit, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

[0042] In one example, a computer program for controlling a host data processing device to provide an instruction execution environment is provided, the computer program comprising: vector processing logic to perform data processing in a plurality of parallel processing channels, wherein the data processing is performed in a subset of the plurality of parallel processing channels, the subset being determined by set bit values ​​of a vector predicate; and predicate monitoring logic to generate a predicate summary value based on the bit values ​​of the vector predicate in response to the vector predicate, wherein a first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition is true when the bit values ​​of the vector predicate include a set bit corresponding to a vector element at a higher index followed by an unset bit corresponding to a vector element at a lower index, and a second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate.

[0043] Some specific embodiments will now be described with reference to the accompanying drawings.

[0044] Figure 1 There is schematically shown a data processing apparatus 10 in which various examples of the techniques of the present disclosure may be embodied. The apparatus comprises data processing circuitry 12 which performs data processing operations on data items in response to sequences of instructions executed by it. These instructions are retrieved from a memory 14 accessed by the data processing apparatus and in a manner that will be familiar to those skilled in the art, for which purpose a fetch circuit 16 is provided. Furthermore, the instructions fetched by the fetch circuit 16 are passed to an instruction decoder circuit 18 which generates control signals arranged to control various aspects of the configuration and operation of the processing circuitry 12 and a set of registers 20 and a load / store unit 12. Typically, the data processing circuitry 12 may be arranged in a pipelined manner, but the details of this are not relevant to the techniques of the present disclosure. Those skilled in the art will be familiar with the various embodiments of the present invention. Figure 1 The general configuration shown in FIG. 1 is shown in FIG. 1 and further detailed description thereof is omitted for the sake of brevity only. Figure 1 As can be seen in the figures, the registers 20 each include storage means for a plurality of data elements, so that the processing circuitry may apply a data processing operation to a specified data element within a specified register, or may apply a data processing operation to a specified group of data elements (a "vector") within a specified register. In particular, the illustrated data processing apparatus relates to the execution of vectorized data processing operations, and in particular to the execution of vector instructions on the data elements stored in the registers 20, the execution of the vector instructions being dependent upon a vector predicate controlling which vector processing lane is active, which will be described in more detail below with reference to some specific embodiments. The data values ​​required by the data processing circuitry 12 when executing instructions, and the data values ​​resulting from these data processing instructions, are written to or read from the memory 14 via the load / store unit 22. It should also be noted that it is generally possible to Figure 1The memory 14 in FIG. 1 is considered as an example of a computer-readable storage medium on which instructions of the disclosed techniques may be stored as part of a predefined sequence of instructions ("program") and then executed by the processing circuit. However, the processing circuit may access such a program from a variety of different sources (e.g., RAM, ROM, etc.) via a network interface or the like.

[0045] Figure 2A A vector processing circuit is schematically shown, which may be present, for example, in Figure 1 1 and 2. The processing circuitry 12 of the device 10 shown is shown. Two source vector registers A and B are shown, from which elements are taken and form inputs to a specified operation "OP", the results of which are written to corresponding elements of the destination vector register. It is particularly noted that a vector predicate is also shown, and the setting of bits in the vector predicate controls which "lanes" are involved in the vector processing, i.e. which corresponding elements of the source and destination registers. In the example shown, three bits are set in the 8-bit vector predicate, so that three corresponding operations are performed on three corresponding pairs of elements taken from the source vector registers A and B, thereby generating three results for corresponding elements of the destination vector register. It should also be noted that in Figure 2A In the example of , an 8-element vector register and an 8-bit vector predicate are shown, but the techniques of this disclosure are in no way limited to a particular size of vector registers or vector predicates.

[0046] Figure 2B The apparatus 50 in one example embodiment is schematically shown. The apparatus 50 comprises a vector processing circuit 51 arranged to perform data processing in a plurality of parallel processing channels (e.g. Figure 2A 52) and for this purpose accesses the vector registers within register 52. Thus, source vector registers in register 52 are accessed to form inputs to data processing operations, and result values ​​resulting from these operations are written into destination vector registers in register 52. Vector predicates 53 are also shown as being retrieved from register 52 and passed to vector processing circuitry 51. It should be noted that this choice of illustration is intended to highlight the use of vector predicates 53, and that it is not necessary to store the vector predicates separately external to vector processing circuitry 51 and registers 52. However, this illustration helps to understand the nature of predicates 53 and their effect on vector processing circuitry 51 and the fact that this value is also received by predicate monitoring circuitry 54. Predicate monitoring circuitry 54 is arranged to receive vector predicates 53 and generate predicate summary values ​​55 based on the settings of bits in the vector predicates. Predicate summary values ​​55 may vary depending on the particular manner in which vector predicates 53 are processed, and therefore the processing performed by predicate monitoring circuitry 54 may vary. Different examples of this will be described below with reference to the following figures.

[0047] Figure 3A An example of a configuration of a predicate monitoring circuit 60 is schematically shown. The inputs for the circuit are provided by the elements of the vector predicate, in this example only four elements are shown for the sake of clarity of illustration. The predicate monitoring circuit 60 comprises a set of three NOT gates 61, 62, 63 and a set of AND gates 64, 65, 66. A final OR gate 67 combines the outputs from the three AND gates. The output is an example of a predicate summary value, which in this example corresponds directly to a "sparse condition" indicator. Figure 3A Inspection of the gate structure shows that for the sparse condition to be true, the bit values ​​of the vector predicate must be such that the bits corresponding to the vector elements at higher indices (in Figure 3A must be set, and immediately after (in Figure 3A In other words, the bits to the left of the vector predicate are considered "more significant" and the bits to the right of the vector predicate are considered "less significant", then the sparse condition requires that the bit value of the vector predicate contain a set more significant bit followed by a less significant bit that is not set (the output of OR gate 67 is 1). If this bit arrangement is not met, the sparse condition is not true (the circuit output of OR gate 67 is 0). Figure 3B shows an example setting of bits in a vector predicate for which the sparse condition is true, while Figure 3C An example of the setting of bits in a vector predicate for which the sparse condition is not true is shown.

[0048] Figures 4A-4D Another example configuration of a predicate summary generation circuit (as part of a predicate monitoring circuit) according to a 2-bit output configuration is shown, where each of the 4 possible bit patterns of the output represents a different recognition state of a set bit for a vector predicate. Figure 4A An example is shown where some (but not all) bits of the vector predicate are set, and the bits are consecutive starting from the lower (right-hand) end. Figure 4B An example is shown where some (but not all) bits are set, and the bits are sparse (not contiguous from the lower (right-hand) end). Figure 4C An example is shown where no bits are set. Figure 4D An example is shown where all bits are set. Figures 4A to 4D , also note that the particular 2-bit pattern (encoding) used has the property of being autological, i.e., the predicate digest values ​​have the same properties as the properties they indicate. In other words, in the example of 4A, the output "01" satisfies the definition according to which the output is generated, i.e., some but not all bits are set and the set bits are consecutive starting from the low end. Figure 4B, the output "10" satisfies the following definition: some bits are set, but sparsely (not continuous from the low end). Figure 4C The output of "00" satisfies the following definition: no bits are set. Figure 4D The output of "11" in satisfies the following definition: all bits are set. This property of the encoding has the additional advantage that predicate digest values ​​can be generated by applying the same predicate digest value generation rule to vector predicates, parts of vector predicates, or any concatenation of predicate digest values.

[0049] For example, the vector predicate 0001111100110011 has a predicate digest value of "10" (because it is sparse).

[0050] However, this vector predicate can also be split into two parts:

[0051] 00011111, which has a predicate digest value of "01" (due to a number of bits being set consecutively starting from the low end); and

[0052] 00110011, has a predicate digest value of "10" (because some bits are set, but sparse).

[0053] Concatenated, these two predicate digest values ​​give "0101", which is sparse by itself and produces a predicate digest value of "10".

[0054] Figure 5A The predicate monitoring circuit 80 is schematically shown, wherein the input of the vector predicate is divided into two parts, and for each part, a summary predicate value is generated by a corresponding summary generation circuit 81 and 82. Figure 5B A similar arrangement is schematically illustrated, where the input vector predicate is divided into multiple parts, for each part, a predicate summary value is generated, but Figure 5B The difference between the predicate monitoring circuit 90 of 5A and the predicate monitoring circuit 80 is that: Figure 5A The input vector predicate of the predicate monitoring circuit 80 in FIG. 8 splits the vector predicate into two equal-sized parts (in the example shown, each part is four elements of an 8-element vector), Figure 5B The predicate monitoring circuit 90 in FIG. 1 divides the vector predicate into two parts of different sizes (a 6-element part and a 2-element part in the example shown). Figure 5A and Figure 5B ,It should be noted that the summary generation circuit instances in each ,instance of the predicate monitoring circuit need not all be active, and ,thus predicate summary values ​​may be generated separately for ,subparts of the vector predicates.

[0055] Figure 6The apparatus 100 in one example embodiment is schematically shown. Here, the predicate monitoring circuit 102 includes not only the predicate summary value generation circuit 104, but also the count generation circuit 106. The summary generation circuit 104 is arranged to generate the predicate summary value 108 (as described above), while the count generation circuit 106 is arranged to generate the predicate count value 110, which indicates a count of the number of bits set in the vector predicate. The operation of the count generation circuit 106 may be optional, and in such an example, may be triggered by a count instruction received by the apparatus, for example as a Figure 1 108. The count instruction trigger may also be received by the predicate monitoring output control 112, which determines what the output of the predicate monitoring circuit will be. Thus, the predicate monitoring output control 112 receives the output of both the summary generation circuit 104 and the count generation circuit 106, namely the predicate summary value 108 and the predicate count value 110, respectively. Thus, for example, when the count generation circuit is inactive, the predicate monitoring output control may cause only the predicate summary value to be provided as output, whereas in response to a count instruction trigger, the predicate monitoring output control circuit 112 may additionally provide the predicate count value as part of the output.

[0056] Figure 7 Schematically, an apparatus 120 is shown in one example embodiment. A vector processing circuit 121 has associated vector processing sampling circuitry 122 provided, which is arranged to monitor the operation of the vector processing circuitry and to provide a vector instruction digest 127 to allow the operation of the vector processing circuitry to be understood. In particular, the vector processing sampling circuitry includes a predicate monitoring circuit 123, which may be configured in accordance with any of the examples described above. Capturing predicate information relating to vector predicates used in the operation of the vector processing circuitry 112 is useful to aid in understanding vector utilization. However, capturing the entire predicate for each vector operation performed is expensive, and for this reason the predicate monitoring circuitry 123 is arranged to generate predicate digest values ​​that constitute part or all of the vector instruction digest.

[0057] The predicate monitoring circuit also includes a counter 124, which is configured to count the occurrence of the generation of a specific predicate summary value. In this example, the counter 124 is provided as two counters to count the occurrence of the generation of a specific predicate summary value according to the Figures 4A-4DThe 2-bit configuration described above counts the occurrence of generation of predicate summary values. More specifically, the two counters provided count the occurrence of generation of predicate values ​​with output value "01" (i.e., when some but not all bits are set and they are continuous from the low end) and the occurrence of generation of predicate summary values ​​with value "10" (i.e., some bits are set but these bits are sparse (not continuous from the low end)). This enables the distinction between continuous partial predicates due to short loops and sparse predicates due to tests in loops. Capturing this information may point to different reasons for using vector predicates and may point to different action plans for improving utilization. Vector processing sampling 122 may be responsive to sampling trigger conditions 125, which may be defined differently depending on system requirements. However, in the example shown, the sampling trigger condition is met when at least one of the counters 124 reaches a threshold. In response thereto, the counters 124 generate count summaries 126, which may then form part of the vector instruction summary 127 used to form the output. This output may be used within device 120 or passed to another component of the system for analysis, storage, and / or action taken in response.

[0058] Figure 8 is a flow chart showing a sequence of steps taken by a method according to an example embodiment. The process can be considered to start at step 150, where it is determined whether there is a vector processing instruction to be executed. The method shown only involves such vector processing, so when not true, the process loops on itself at step 150. However, when true, the process proceeds to step 151, where it is determined whether the vector predicate has a set higher significant bit and a lower significant bit that is not set immediately thereafter. In other words, it is determined whether the bit value of the vector predicate includes a set bit corresponding to the vector element at the higher index and a non-set bit that is immediately thereafter corresponding to the vector element at the lower index. If true, a predicate summary value is generated with a first value at step 152, and if not true, a predicate summary value is generated with a second value at step 153. The first value and the second value can be, for example, "10" and "01" according to one of the examples given above. However, this particular encoding is not required. Finally, at step 154, the vector data processing defined by the instruction is performed in those channels that have set bits in the vector predicate. Then, the process returns to step 150.

[0059] Fig. 91 is a flow chart showing a sequence of steps taken according to an example embodiment. The process can be considered to start at step 160, where it is determined whether there are vector processing instructions to be executed. When this is not true, the process loops on itself at step 160. However, when this is true, the process proceeds to step 161, where it is determined whether the vector predicate has no bits set. If true, then at step 162, the predicate digest value is generated as "00". Otherwise, the process proceeds to step 163, where it is determined whether the vector predicate has all bits set. If true, then at step 164, the predicate digest value is output as "11". Otherwise, at step 165, it is determined whether the vector predicate has some but not all bits set, which are continuous from the lower index end (i.e., the least significant bit end of the vector predicate). If true, then at step 166, the predicate digest value is generated as "01". Otherwise, at step 167, the predicate digest value is generated as "10", indicating that some bits are set, but these bits are sparse, i.e., not continuous from the bottom end. Regardless of which path the predicate summary value is set via, flow then proceeds to step 168 where vector data processing is performed as defined by the vector processing instructions executed in those lanes that have set bits in the predicate. Flow then returns to step 160.

[0060] Fig.10 The simulator implementation that can be used is shown. Although the embodiments described earlier implement the present invention in terms of the apparatus and method for operating the specific processing hardware supporting the related technology, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented by using a computer program. Such computer programs are generally referred to as simulators, as long as such computer programs provide a software-based hardware architecture implementation. Various simulator computer programs include simulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the simulator implementation can be run on a host processor 230 that supports the simulator program 210, optionally on a host operating system 220. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments are provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but in some cases (such as when the native code of another processor is desired to be run for compatibility or reuse reasons), this approach may be reasonable. For example, the simulator implementation can provide an instruction execution environment with additional functions that are not supported by the host processor hardware, or provide an instruction execution environment that is generally associated with different hardware architectures. An overview of simulation is given in "Some Efficient Architectural Simulation Techniques" by Robert Bedichek, presented at the 1990 Winter USENIX Conference (pp. 53-63).

[0061] To the extent that embodiments have been previously described with reference to specific hardware constructs or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructs or features. For example, specific circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in simulated embodiments. In arrangements where one or more of the hardware elements mentioned in the foregoing embodiments are present on host hardware (e.g., host processor 230), some simulated embodiments may utilize the host hardware where appropriate.

[0062] The simulator program 210 may be stored on a computer-readable storage medium (which may be a non-transitory medium), and provides a program interface (instruction execution environment) to the target code 200, which is the same as the application program interface of the hardware architecture modeled by the simulator program 210. Therefore, the program instructions of the target code 200 (including vector processing instructions to be executed by the simulated vector processing circuit) can be executed in the instruction execution environment using the simulator program 210, and therefore, the host computer 230, which does not actually have the hardware features of the above-mentioned device examples, can simulate these features.

[0063] In general, apparatus and methods of operating such apparatus are disclosed. Vector processing circuitry performs data processing in a plurality of parallel processing lanes, wherein the data processing is performed in a subset of the plurality of parallel processing lanes determined by bit values ​​of set vector predicates. Predicate monitoring circuitry is responsive to the vector predicates to generate a predicate summary value based on the bit values ​​of the vector predicates. A first value of the predicate summary value indicates that a sparse condition of the vector predicate is true, the sparse condition being true when the bit value of the vector predicate includes a set bit corresponding to a vector element at a higher index and an immediately following unset bit corresponding to a vector element at a lower index. A second value of the predicate summary value indicates that the sparse condition of the vector predicate is not true. Thus, improved predicate-controlled vector processing is supported.

[0064] In this application, the phrase "configured to..." is used to indicate that an element of a device has a configuration that enables it to perform a defined operation. In this context, "configuration" refers to the arrangement or manner of interconnection of hardware or software. For example, a device may have dedicated hardware that provides a defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that the device elements need to be changed in any way to provide the defined operation.

[0065] Although illustrative embodiments have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes, additions and modifications may be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, the features of the dependent claims may be combined in various ways with the features of the independent claims without departing from the scope of the invention.

Claims

1. A data processing device, comprising: vector processing circuitry for performing data processing in a plurality of parallel processing lanes, wherein the data processing is performed in a subset of the plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and a predicate monitoring circuit, responsive to the vector predicate to generate a predicate summary value according to bit values ​​of the vector predicate, wherein a first value of the predicate digest value indicates that a sparse condition of the vector predicate is true when a bit value of the vector predicate includes a set bit corresponding to a vector element at a first index followed by an unset bit corresponding to the vector element at a second index, wherein the second index corresponds to a less significant bit in the vector predicate than the first index, And the second value of the predicate summary value indicates that the sparse condition of the vector predicate is not true. 2 . The apparatus of claim 1 , wherein the first value of the predicate digest value indicates that a strict subset of bit values ​​of the vector predicate are set, wherein the strict subset of bit values ​​is not a contiguous sequence that includes the least significant bits of the vector predicate.

3. An apparatus according to claim 1 or claim 2, wherein the second value of the predicate digest value indicates that a strict subset of bit values ​​of the vector predicate are set in a consecutive sequence. 4 . The apparatus of claim 3 , wherein the predicate monitoring circuit is responsive to the vector predicate to generate the predicate digest value having the second value when the continuous sequence includes a least significant bit of the vector predicate.

5. The apparatus of claim 1 , wherein the predicate monitoring circuit is responsive to the vector predicate to generate a predicate digest value having a third value of the predicate digest value when no bit values ​​in the vector predicate are set, and to generate a predicate digest value having a fourth value of the predicate digest value when all bit values ​​of the vector predicate are set.

6. An apparatus as claimed in claim 5, wherein the predicate monitoring circuit is arranged to generate the predicate digest value as a 2-bit value. The apparatus of claim 6 , wherein the predicate digest values ​​are homologous. 8 . The apparatus of claim 6 , wherein the third value of the predicate digest value is 00, wherein the second value of the predicate digest value is 01, wherein the first value of the predicate digest value is 10, and wherein the fourth value of the predicate digest value is 11.

9. The apparatus of claim 1 , wherein the predicate monitoring circuit is responsive to the vector predicate to generate a first predicate digest value and at least one further predicate digest value based on bit values ​​of the vector predicate, wherein the first predicate digest value and the at least one further predicate digest value correspond to a first portion and at least one further portion of the vector predicate.

10. The apparatus of claim 9, wherein the first portion and the at least one further portion of the vector predicate are of the same size.

11. The apparatus of claim 9, wherein the first portion and the at least one further portion of the vector predicate are of different sizes.

12. The apparatus of claim 1 or 2, wherein the predicate monitoring circuit is further responsive to the vector predicate to generate a predicate count value indicative of a count of set bits in the vector predicate.

13. Apparatus according to claim 12, wherein the predicate monitoring circuitry is responsive to a count instruction to return the predicate count value indicating a count of set bits in the vector predicate.

14. The apparatus of claim 13, wherein the predicate monitoring circuit is further responsive to the count instruction to return the predicate digest value.

15. Apparatus according to claim 1 or 2, comprising vector processing sampling circuitry associated with the vector processing circuitry to generate vector instruction summaries for vector instructions executed by the vector processing circuitry, wherein the vector processing sampling circuitry comprises the predicate monitoring circuitry.

16. The apparatus of claim 15, wherein the vector processing sampling circuitry is responsive to a sampling trigger condition to generate the vector instruction digest.

17. The apparatus of claim 1 or 2, wherein the predicate monitoring circuit further comprises at least one counter to count occurrences of generation of the predicate digest value having at least one of the first value and the second value.

18. The apparatus of claim 17, wherein the predicate monitoring circuit is responsive to a count summary flip-flop to output at least one value of the at least one counter.

19. A data processing method, comprising: performing vector data processing in a plurality of parallel processing lanes, wherein the data processing is performed in a subset of the plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; and In response to the vector predicate, generating a predicate summary value according to the bit values ​​of the vector predicate, wherein a first value of the predicate digest value indicates that a sparse condition of the vector predicate is true when a bit value of the vector predicate includes a set bit corresponding to a vector element at a first index followed by an unset bit corresponding to the vector element at a second index, wherein the second index corresponds to a less significant bit in the vector predicate than the first index, And the second value of the predicate summary value indicates that the sparse condition of the vector predicate is not true.

20. A computer program product for controlling a host data processing device to provide an instruction execution environment, comprising: vector processing logic to perform data processing in a plurality of parallel processing lanes, wherein the data processing is performed in a subset of the plurality of parallel processing lanes, the subset being determined by set bit values ​​of a vector predicate; as well as predicate monitoring logic for generating a predicate summary value in response to the vector predicate according to the bit values ​​of the vector predicate, wherein a first value of the predicate digest value indicates that a sparse condition of the vector predicate is true when a bit value of the vector predicate includes a set bit corresponding to a vector element at a first index followed by an unset bit corresponding to the vector element at a second index, wherein the second index corresponds to a less significant bit in the vector predicate than the first index, And the second value of the predicate summary value indicates that the sparse condition of the vector predicate is not true.

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