Semiconductor package with package-on-package (PoP) structure

Abstract

A semiconductor package having a package-on-package (PoP) structure is disclosed, in which a signal area and a power area are formed separately. The semiconductor package includes a lower semiconductor package and an upper semiconductor package on the lower semiconductor package. The upper semiconductor package includes: an upper package substrate; a memory chip located on the upper package substrate; a wire electrically connecting the memory chip to the upper package substrate; a power connector located on the upper semiconductor package; a signal connector located on the bottom surface of the upper package substrate; and an upper package molding material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0122969 filed on October 4, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to a semiconductor package. More particularly, example embodiments relate to a semiconductor package having a package on package (PoP) structure. Background Art

[0004] In the case of a semiconductor package with a PoP structure, the number of signal connectors can be increased to increase the bandwidth of data transmission between the upper semiconductor package and the lower semiconductor package of the PoP structure. In a conventional semiconductor package with a PoP structure, a power connector and a signal connector are arranged together in a limited space between the upper semiconductor package and the lower semiconductor package. In order to increase the bandwidth of data transmission, the size of a single terminal can be reduced, and the pitch between the terminals can be reduced. However, reducing the size of a single terminal and reducing the pitch between the terminals will lead to a non-wetting problem in which the terminals are disconnected from each other. Therefore, it is necessary to develop a semiconductor package structure that can not only increase the bandwidth of data transmission but also prevent poor contact. Summary of the invention

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide a semiconductor package with a PoP structure, wherein a power connector area and a signal connector area are formed separately from each other, so that the power connector is arranged on the top surface of the upper semiconductor package and the signal connector is arranged on the bottom surface of the upper semiconductor package, thereby increasing the size of a single solder ball, preventing and / or reducing the non-wetting problem that may occur when multiple signal connectors and power connectors are arranged in a limited space, thereby increasing the number of signal connectors, and thereby increasing the bandwidth of data transmission.

[0006] A semiconductor package with a PoP structure according to an embodiment of the present disclosure may include a lower semiconductor package and an upper semiconductor package located on the lower semiconductor package. The upper semiconductor package may include: an upper package substrate; a memory chip located on the upper package substrate; a wire electrically connecting the memory chip to the upper package substrate; a power connector located on the upper semiconductor package; a signal connector located on the bottom surface of the upper package substrate; and an upper package molding material.

[0007] A semiconductor package with a PoP structure according to another embodiment of the present disclosure may include a lower semiconductor package, an inserter located on the lower semiconductor package, and an upper semiconductor package located on the inserter. The upper semiconductor package may include: an upper package substrate; a memory chip located on the upper package substrate; a wire electrically connecting the memory chip to the upper package substrate; a power connector located on the upper semiconductor package; a signal connector located on the bottom surface of the upper package substrate; and an upper package molding material.

[0008] A semiconductor system with a PoP structure according to another embodiment of the present disclosure may include a lower board, an upper board, a lower semiconductor package located on the lower board, and an upper semiconductor package located on the lower semiconductor package. The lower semiconductor package may include: a lower package substrate; an application processor (AP) chip located on the lower package substrate; a lower package molding material located on the lower package substrate and on the AP chip; and a molded through-molding (TMV) located in the lower package molding material. The upper semiconductor package may include: an upper package substrate; a memory chip located on the upper package substrate; a wire electrically connecting the memory chip to the upper package substrate; a power connector located on the top surface of the upper semiconductor package; a power bump located on the power connector; a signal connector located on the bottom surface of the upper package substrate; and an upper package molding material. The gap between the bottom surface of the upper board and the top surface of the upper semiconductor package may be less than 300 μm. The gap between the bottom surface of the upper semiconductor package and the top surface of the lower semiconductor package may be less than 300 μm. A gap between a bottom surface of the lower semiconductor package and a top surface of the lower board may be less than 300 μm.

[0009] A semiconductor package with a PoP structure according to another embodiment of the present disclosure may include a lower semiconductor package and an upper semiconductor package located on the lower semiconductor package. The upper semiconductor package may include: an upper package substrate; a semiconductor chip located on the upper package substrate; an upper package molding material located on the upper package substrate and the semiconductor chip; a power connector located in the upper package molding material; and a signal connector located between the upper package substrate and the lower semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a side cross-sectional view of a semiconductor system according to an embodiment of the present disclosure.

[0012] Figure 2 is a side cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0013] Figure 3 is a side cross-sectional view of a lower semiconductor package according to an embodiment of the present disclosure.

[0014] Figure 4 is a top view of an upper semiconductor package according to an embodiment of the present disclosure.

[0015] Figure 5 is a side cross-sectional view of an upper semiconductor package according to an embodiment of the present disclosure.

[0016] Figure 6 is a top view of an upper semiconductor package according to an embodiment of the present disclosure.

[0017] Figure 7 is a side cross-sectional view of an upper semiconductor package according to an embodiment of the present disclosure.

[0018] Figure 8 is a top view of an upper semiconductor package according to an embodiment of the present disclosure.

[0019] Fig. 9 is a side cross-sectional view of an upper semiconductor package according to an embodiment of the present disclosure.

[0020] Fig.10 is a top view of an upper semiconductor package according to an embodiment of the present disclosure.

[0021] Fig.11 is a side cross-sectional view of an upper semiconductor package according to an embodiment of the present disclosure.

[0022] Fig.12 is a top view of an upper semiconductor package according to an embodiment of the present disclosure.

[0023] Fig.13 is a side cross-sectional view of an upper semiconductor package according to an embodiment of the present disclosure.

[0024] Fig.14 is a side cross-sectional view of a semiconductor system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Reference will now be made in more detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0026] Figure 1 is a side cross-sectional view of a semiconductor system 1 according to an embodiment of the present disclosure. Figure 1, the semiconductor system 1 according to an embodiment of the present disclosure may include a lower board 10, an upper board 20, a lower underfill 31, an upper underfill 32, a lower semiconductor package 100, an upper semiconductor package 200, and a package underfill 300. The lower semiconductor package 100 may include a solder 137 disposed on a bottom surface thereof (e.g., between the lower semiconductor package 100 and the lower board 10). The upper semiconductor package 200 may include a signal connector 260 disposed on a bottom surface thereof (e.g., between the upper semiconductor package 200 and the lower semiconductor package 100) and a power bump 270 disposed on a top surface thereof (e.g., between the upper semiconductor package 200 and the upper board 20).

[0027] The lower semiconductor package 100 and the upper semiconductor package 200 may be mounted between the lower board 10 and the upper board 20. The lower board 10 and the upper board 20 may connect the lower semiconductor package 100 and the upper semiconductor package 200 to an external circuit (not shown), and may support and protect the lower semiconductor package 100 and the upper semiconductor package 200 from external impact. For example, each of the lower board 10 and the upper board 20 may include a printed circuit board (PCB).

[0028] The lower board 10 and the upper board 20 may be two-layer mother boards. The lower board 10 and the upper board 20 may be configured as boards disposed parallel to each other at a constant interval, and each of the lower board 10 and the upper board 20 may be independently used as a mother board.

[0029] The lower semiconductor package 100 may be mounted on the lower board 10. The lower semiconductor package 100 may make contact (eg, electrically contact) with the lower board 10 via a solder 137 disposed on a bottom surface thereof.

[0030] The upper semiconductor package 200 may be disposed between the lower semiconductor package 100 and the upper board 20. The upper semiconductor package 200 may contact (e.g., electrically contact) the lower semiconductor package 100 via a signal connector 260 disposed on a bottom surface thereof, and may contact (e.g., electrically contact) the upper board 20 via a power bump 270 disposed on a top surface thereof.

[0031] The lower underfill 31 may be disposed between the lower board 10 and the lower semiconductor package 100. The lower underfill 31 may be located on and / or fix the solder 137 disposed on the bottom surface of the lower semiconductor package 100, and may support the lower semiconductor package 100 on the lower board 10.

[0032] The package underfill 300 may be disposed between the lower semiconductor package 100 and the upper semiconductor package 200. The package underfill 300 may be located on and / or fix the signal connector 260 disposed on the bottom surface of the upper semiconductor package 200, and may support the upper semiconductor package 200 on the lower semiconductor package 100.

[0033] The upper underfill 32 may be disposed between the upper board 20 and the upper semiconductor package 200. The upper underfill 32 may be located on and / or fix the power bumps 270 disposed on the top surface of the upper semiconductor package 200, and may support the upper board 20 on the upper semiconductor package 200.

[0034] Figure 2 4 is a side cross-sectional view of a semiconductor package 40 according to an embodiment of the present disclosure. Figure 2 , a semiconductor package 40 according to an embodiment of the present disclosure may include a lower semiconductor package 100, an upper semiconductor package 200, and a package underfill 300. In some embodiments, a power bump 270 may be disposed on a top surface of the upper semiconductor package 200, and a solder 137 may be disposed on a bottom surface of the lower semiconductor package 100. In some embodiments, the power bump 270 disposed on the top surface of the upper semiconductor package 200 may be omitted. In some embodiments, the semiconductor package 40 may be coupled to a lower board 10 and an upper board 20 to form a semiconductor system 1. As will be further described herein, embodiments of the present disclosure partially include improved configurations of the lower semiconductor package 100 and / or the upper semiconductor package 200.

[0035] Figure 3 is a side cross-sectional view of a lower semiconductor package 100 according to an embodiment of the present disclosure. Figure 3 , the lower semiconductor package 100 may include a through-mold (TMV) 110 , an application processor (AP) chip 120 (eg, a first semiconductor chip), chip bumps 125 , a lower package substrate 130 , solder 137 , and a lower package molding material 140 .

[0036] The TMV 110 may be disposed in the lower package molding material 140. The TMV 110 may be filled with a conductive material. It will be understood that "element A fills element B" (or similar language) as used herein means that element A is located in element B, but does not necessarily mean that element A completely fills element B. The lower end of the TMV 110 may contact the lower package substrate 130, and the upper end of the TMV 110 may contact the upper semiconductor package 200 (e.g., see FIG. 2 ). Figure 5) is in contact with a signal connector 260. The TMV 110 may provide a signal transmission path between the upper semiconductor package 200 and the lower semiconductor package 100.

[0037] The AP chip 120 may be mounted on the lower package substrate 130. The AP chip 120 may be electrically connected to the lower package substrate 130 via chip bumps 125.

[0038] The lower package substrate 130 may support the AP chip 120 and protect the AP chip 120 from external impact. For example, the lower package substrate 130 may include a printed circuit board (PCB) or a silicon plug-in. The AP chip 120 may be mounted on the top surface of the lower package substrate 130. The solder 137 may be provided on the bottom surface of the lower package substrate 130 (e.g., opposite to the AP chip 120 relative to the lower package substrate 130).

[0039] The lower package substrate 130 may include an internal signal wiring 131, an external signal wiring 133, and a lower package power wiring 135. The internal signal wiring 131 may electrically connect the TMV 110 to the AP chip 120. The internal signal wiring 131 may provide a connection between the AP chip 120 of the lower semiconductor package 100 and the upper semiconductor package 200 (see, for example, FIG. 2 ) within the semiconductor package 40. Figure 5 ) between the memory chip 210 (eg, the second semiconductor chip). The signal from the memory chip 210 of the upper semiconductor package 200 may be transmitted to the AP chip 120 via a path including the TMV 110, the internal signal wiring 131, and the chip bump 125.

[0040] The external signal wiring 133 may electrically connect the AP chip 120 to the solder 137 disposed on the bottom surface of the lower package substrate 130. The external signal wiring 133 may provide a path for (for example, when the lower semiconductor package 100 is Figure 1 and / or Figure 2 ) transmits a signal from the AP chip 120 of the lower semiconductor package 100 to the lower board 10 outside the semiconductor package 40.

[0041] The lower package power wiring 135 may electrically connect the AP chip 120 to the solder 137 disposed on the bottom surface of the lower package substrate 130. The lower package power wiring 135 may provide a path for receiving driving power for the lower semiconductor package 100 from the lower board 10. In some embodiments, the position of the lower package power wiring 135 and the position of the external signal wiring 133 may be interchanged.

[0042] The lower encapsulation molding material 140 may be disposed on the lower encapsulation substrate 130 and may be located on and / or cover the AP chip 120. The lower encapsulation molding material 140 may be a shell that is produced by a molding process and protects the AP chip 120 from the external environment. The lower encapsulation molding material 140 may include, for example, an epoxy molding compound (EMC). In some embodiments, the top surface of the AP chip 120 may not be covered by the lower encapsulation molding material 140 but may be exposed.

[0043] Figure 4 is a top view of an upper semiconductor package 200 according to an embodiment of the present disclosure, Figure 5 is a side cross-sectional view of an upper semiconductor package 200 according to an embodiment of the present disclosure. For example, Figure 5 Can be expressed Figure 4 FIG. 2 is a cross-sectional view of an upper semiconductor package 200. Figure 4 and Figure 5 , the upper semiconductor package 200 may include a memory chip 210 , a redistribution layer 215 , a wire 220 , a power connector 240 , an upper package substrate 250 , a signal connector 260 , and an upper package molding material 290 .

[0044] The memory chip 210 may be mounted on the upper package substrate 250. The memory chip 210 may include, for example, a dynamic random access memory (DRAM) chip. The memory chip 210 may include a lower memory chip 210B and an upper memory chip 210A stacked on the lower memory chip 210B. In some embodiments, the lower memory chip 210B may be located between the upper memory chip 210A and the upper package substrate 250. A redistribution layer 215 may be provided on the upper memory chip 210A.

[0045] The redistribution layer 215 may include a redistribution circuit disposed among and / or electrically connected to the power connector 240, the wire 220, and the memory chip 210. In some embodiments, the redistribution layer 215 may be included in the upper memory chip 210A.

[0046] The wire 220 can electrically connect the upper package substrate 250 to the memory chip 210. The wire 220 can include: signal wires 221A and 221B, which are connected to the signal wirings 251A and 251B in the upper package substrate 250; and power wires 223A and 223B, which are connected to the memory chip power wiring 255 in the upper package substrate 250.

[0047] The power connector 240 may be disposed on the top surface of the upper semiconductor package 200 while penetrating the upper package molding material 290. Driving power may be supplied to the memory chip 210 through the power connector 240. One end of the power connector 240 may contact the top surface of the memory chip 210 or the redistribution layer 215 disposed on the memory chip 210. The opposite end of the power connector 240 may be exposed upward on the upper package molding material 290, and (for example, when Figure 1 and / or Figure 2 When configured in the middle) can contact the power bump 270.

[0048] The upper package substrate 250 may support the memory chip 210 and protect the memory chip 210 from external impact. For example, the upper package substrate 250 may include a PCB or a silicon plug-in. The memory chip 210 may be mounted on the top surface of the upper package substrate 250. A signal connector 260 such as a solder ball may be provided on the bottom surface of the upper package substrate 250.

[0049] The upper package substrate 250 may include an upper chip signal wiring 251A, a lower chip signal wiring 251B, and a memory chip power wiring 255 .

[0050] The upper chip signal wiring 251A may electrically connect the signal wire 221A connected to the upper memory chip 210A to the signal connector 260. The upper chip signal wiring 251A may provide a path for transmitting a signal from the upper memory chip 210A to the AP chip 120 of the lower semiconductor package 100.

[0051] The lower chip signal wiring 251B may electrically connect the signal wire 221B connected to the lower memory chip 210B to the signal connector 260. The lower chip signal wiring 251B may provide a path for transmitting a signal from the lower memory chip 210B to the AP chip 120 of the lower semiconductor package 100.

[0052] The memory chip power wiring 255 may electrically connect the power conductive line 223A connected to the upper memory chip 210A to the power conductive line 223B connected to the lower memory chip 210B. The memory chip power wiring 255 may provide a path for supplying driving power to the lower memory chip 210B.

[0053] The signal connector 260 and the power bump 270 may include solder balls. The signal connector 260 may connect the upper semiconductor package 200 to the lower semiconductor package 100, or to the interposer 400 (eg, see Fig.14), and may provide a signal transmission path between the upper semiconductor package 200 and the lower semiconductor package 100. The power bump 270 may connect the upper semiconductor package 200 to the upper board 20, and may transmit driving power from the upper board 20 to the upper semiconductor package 200.

[0054] The upper package molding material 290 may be disposed on the upper package substrate 250, and may be located on and / or cover the memory chip 210 and the wire 220. The upper package molding material 290 may be a housing that is produced by a molding process and may protect the memory chip 210 and the wire 220 from the external environment. The upper package molding material 290 may include, for example, EMC.

[0055] Reference Figure 4 and Figure 5 , when the upper semiconductor package 200 is viewed from above, the power connector 240 may be disposed on the memory chip 210. Figure 5 , the power supply path to the upper memory chip 210A may include a power connector 240 and a redistribution layer 215. The power supply path to the lower memory chip 210B may include a power connector 240, a redistribution layer 215, a power conductor 223A connected to the upper memory chip 210A, a memory chip power wiring 255, and a power conductor 223B connected to the lower memory chip 210B.

[0056] Reference Figure 5 , a signal from the upper memory chip 210A may be transmitted to the lower semiconductor package 100 via a path including the redistribution layer 215, the signal wire 221A, the upper chip signal wiring 251A, and the signal connector 260. A signal from the lower memory chip 210B may be transmitted to the lower semiconductor package 100 via a path including the signal wire 221B, the lower chip signal wiring 251B, and the signal connector 260.

[0057] although Figures 2 to 5 Referring to the AP chip 120 and the memory chip 210, it will be understood that the present disclosure is not limited to these embodiments. In some embodiments, the lower semiconductor package 100 may include a first semiconductor chip 120, and the upper semiconductor package 200 may include a second semiconductor chip 210.

[0058] Figure 6 is a top view of an upper semiconductor package 200 according to an embodiment of the present disclosure, Figure 7 is a side cross-sectional view of an upper semiconductor package 200 according to an embodiment of the present disclosure. For example, Figure 7 Can be expressed Figure 6 FIG. 2 is a cross-sectional view of an upper semiconductor package 200. Figure 6 and Figure 7 , the memory chip 210 may include two chips arranged side by side at the same level. Figure 7 , each memory chip 210 may include a redistribution layer 215 disposed thereon.

[0059] Reference Figure 7 , the upper package substrate 250 may include a signal wiring 251. The signal wiring 251 may electrically connect the signal wire 221 connected to each memory chip 210 to the signal connector 260. The power supply path to each memory chip 210 may include a power connector 240 and a redistribution layer 215. The signal from each memory chip 210 may be transmitted to the lower semiconductor package 100 via a path including the redistribution layer 215, the signal wire 221, the signal wiring 251, and the signal connector 260. In some embodiments, the signal wire 221 may represent the wire 220 described with respect to the drawings.

[0060] Figure 8 is a top view of an upper semiconductor package 200 according to an embodiment of the present disclosure, Fig. 9 is a side cross-sectional view of an upper semiconductor package 200 according to an embodiment of the present disclosure. For example, Fig. 9 Can be expressed Figure 8 FIG. 2 is a cross-sectional view of an upper semiconductor package 200. Figure 8 and Fig. 9 , the memory chip 210 may include four chips arranged in a pinwheel pattern at the same level. In some embodiments, a corner of each of the four chips may be adjacent to a corner of each of the other three chips. Fig. 9 , each memory chip 210 may include a redistribution layer 215 disposed thereon.

[0061] Reference Fig. 9 , the upper package substrate 250 may include a signal wiring 251. The signal wiring 251 may electrically connect the signal wire 221 connected to each memory chip 210 to the signal connector 260. The power supply path to each memory chip 210 may include a power connector 240 and a redistribution layer 215. The signal from each memory chip 210 may be transmitted to the lower semiconductor package 100 via a path including the redistribution layer 215, the signal wire 221, the signal wiring 251, and the signal connector 260. In some embodiments, the signal wire 221 may represent the wire 220 described with respect to the drawings.

[0062] Fig.10 is a top view of an upper semiconductor package 200 according to an embodiment of the present disclosure, Fig.11is a side cross-sectional view of an upper semiconductor package 200 according to an embodiment of the present disclosure. For example, Fig.11 Can be expressed Fig.10 FIG. 2 is a cross-sectional view of an upper semiconductor package 200. Fig.10 and Fig.11 , the memory chip 210 may include two lower memory chips 210B disposed side by side and two upper memory chips 210A disposed side by side on the lower memory chips 210B. Each of the upper memory chips 210A may be stacked on the two lower memory chips 210B to cover at least a portion of each of the two lower memory chips 210B. Fig.11 , each of the upper memory chips 210A may include a redistribution layer 215 disposed thereon.

[0063] Reference Fig.11 , a power supply path to each of the upper memory chips 210A may include a power connector 240 and a redistribution layer 215. A power supply path to the lower memory chip 210B may include a power connector 240, a redistribution layer 215, a power conductor 223A connected to at least one of the upper memory chips 210A, a memory chip power wiring 255, and a power conductor (not shown) connected to the lower memory chip 210B.

[0064] Reference Fig.11 , a signal from each of the upper memory chips 210A may be transmitted to the lower semiconductor package 100 via a path including the redistribution layer 215 , the signal conductive line 221A, the signal wiring 251 , and the signal connector 260 .

[0065] Fig.12 is a top view of an upper semiconductor package 200 according to an embodiment of the present disclosure, Fig.13 is a side cross-sectional view of an upper semiconductor package 200 according to an embodiment of the present disclosure. For example, Fig.13 Can be expressed Fig.12 FIG. 2 is a cross-sectional view of an upper semiconductor package 200. Fig.12 and Fig.13 , when the upper semiconductor package 200 is viewed from above, the power connector 240 may be disposed on a portion of the upper semiconductor package 200 where the memory chip 210 is not disposed.

[0066] Reference Fig.13, the upper package substrate 250 may include an upper chip signal wiring 251A and a lower chip signal wiring 251B and an upper chip power wiring 255A and a lower chip power wiring 255B. The upper chip signal wiring 251A may electrically connect the upper chip signal wire 221A to the signal connector 260, and the lower chip signal wiring 251B may electrically connect the lower chip signal wire 221B to the signal connector 260. The upper chip power wiring 255A may electrically connect the upper chip power wire 223A to the power connector 240, and the lower chip power wiring 255B may electrically connect the lower chip power wire 223B to the power connector 240.

[0067] The power supply path to the upper memory chip 210A may include a power connector 240, an upper chip power wiring 255A, and an upper chip power conductor 223A. The power supply path to the lower memory chip 210B may include a power connector 240, a lower chip power wiring 255B, and a lower chip power conductor 223B.

[0068] The signal from the upper memory chip 210A may be transmitted to the lower semiconductor package 100 via a path including the upper chip signal wire 221A, the upper chip signal wiring 251A, and the signal connector 260. The signal from the lower memory chip 210B may be transmitted to the lower semiconductor package 100 via a path including the lower chip signal wire 221B, the lower chip signal wiring 251B, and the signal connector 260.

[0069] Fig.14 is a side cross-sectional view of a semiconductor system 1 ′ according to an embodiment of the present disclosure. Fig.14 , the semiconductor system 1′ may further include an insert 400. The insert 400 may be disposed on the lower semiconductor package 100. The insert 400 may be disposed between the upper semiconductor package 200 and the lower semiconductor package 100 to electrically connect the upper semiconductor package 200 to the lower semiconductor package 100. The insert 400 may include a TMV 110 (e.g., see FIG. 1 ) that may be partially inserted into the lower semiconductor package 100. Figure 3 ). The plug-in bump 410 in the lower semiconductor package 100 may include, for example, silicon, an organic substrate, or a printed circuit board (PCB), and may also include a redistribution layer. The plug-in bump 410 may include, for example, solder. A portion of the plug-in bump 410 may be inserted into the TMV 110 of the lower semiconductor package 100 (e.g., see Figure 3 ) and may be in contact with a conductive material disposed in the TMV 110.

[0070] In some embodiments, the first underpackaging filler 301 may be disposed between the lower semiconductor package 100 and the insert 400. The first underpackaging filler 301 may be located on the insert bump 410 disposed on the bottom surface of the insert 400 and / or fix the insert bump 410 disposed on the bottom surface of the insert 400. In some embodiments, the second underpackaging filler 302 may be disposed between the upper semiconductor package 200 and the insert 400. The second underpackaging filler 302 may be located on the signal connector 260 disposed on the bottom surface of the upper semiconductor package 200 and / or fix the signal connector 260 disposed on the bottom surface of the upper semiconductor package 200.

[0071] In some embodiments, a vertical gap between the bottom surface of the upper plate 20 and the top surface of the upper semiconductor package 200 may be less than 300 μm. In some embodiments, a vertical gap between the bottom surface of the upper semiconductor package 200 and the top surface of the lower semiconductor package 100 may be less than 300 μm. In some embodiments, a vertical gap between the bottom surface of the lower semiconductor package 100 and the top surface of the lower plate 10 may be less than 300 μm.

[0072] In some embodiments, the diameters of the solder 137 of the lower semiconductor package 100 , the signal connector 260 and / or the power bump 270 of the upper semiconductor package 200 , and / or the interposer bump 410 of the interposer 400 may be less than 350 μm.

[0073] As described above, in the semiconductor package 40 having a PoP structure according to an embodiment of the present disclosure or in the semiconductor system 1, 1' including the semiconductor package 40, the signal connector 260 and the power connector 240 of the upper semiconductor package 200 can be arranged in different corresponding spaces, thereby increasing space efficiency. That is, the signal connector 260 can be arranged on the bottom surface of the upper semiconductor package 200 to exchange signals with the lower semiconductor package 100, and the power connector 240 can be arranged on the top surface of the upper semiconductor package 200 to receive driving power for the upper semiconductor package 200 from the upper board 20 (which can be a two-layer motherboard). Therefore, it is possible to increase the number of signal connectors 260 without reducing the size of the bumps 260 and 270 for transmitting signals or power, thereby increasing the bandwidth of data transmission and preventing and / or reducing the non-wetting problem.

[0074] As is apparent from the above description, the present disclosure provides a semiconductor package having a PoP structure, wherein a power connector area and a signal connector area are formed separately from each other, so that the power connector is disposed on the top surface of the upper semiconductor package and the signal connector is disposed on the bottom surface of the upper semiconductor package. The semiconductor package having a PoP structure according to some embodiments of the present disclosure may be able to increase the size of a single solder ball. Therefore, the semiconductor package having a PoP structure according to some embodiments of the present disclosure may prevent and / or reduce the non-wetting problem that may occur when a plurality of signal connectors and power connectors are arranged in a limited space. In addition, the semiconductor package having a PoP structure according to some embodiments of the present disclosure may be able to increase the number of signal connectors, thereby increasing the bandwidth of data transmission.

[0075] Although the present disclosure has been specifically shown and described with reference to the exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that various changes in form and details may be made without departing from the scope of the present disclosure. Therefore, the above embodiments are interpreted in all aspects as illustrative and not restrictive.

Claims

1. A semiconductor package, comprising: a lower semiconductor package; as well as an upper semiconductor package located on the lower semiconductor package, Wherein, the upper semiconductor package comprises: an upper packaging substrate; A memory chip, which is located on the upper package substrate; A wire electrically connecting the memory chip to the upper package substrate; a power connector located on the upper semiconductor package; a signal connector located on a bottom surface of the upper package substrate; and an upper package molding material, which is located on the upper package substrate and covers the memory chip, The power connector penetrates the upper packaging molding material, one end of the power connector contacts the redistribution layer located on the memory chip, so that the power supply path of the memory chip includes the power connector and the redistribution layer, and the opposite end of the power connector is exposed upward on the upper packaging molding material.

2. The semiconductor package according to claim 1, wherein: The lower semiconductor package comprises: a lower package substrate; An application processor chip, which is located on the lower package substrate; a lower package molding material located on the lower package substrate and on the application processor chip; and a molded through piece located in the lower package molding material, and The lower package substrate includes internal signal wiring, external signal wiring and lower package power wiring.

3. The semiconductor package according to claim 2, wherein: The external signal wiring and / or the lower package power wiring electrically connects the application processor chip to solder on a bottom surface of the lower package substrate.

4. The semiconductor package according to claim 2, further comprising an inserter located between the lower semiconductor package and the signal connector, in, The plug-in includes a plug-in bump, and Wherein, the upper end of the molded through-piece contacts the plug-in protrusion.

5. The semiconductor package according to claim 1, wherein: The memory chip comprises a lower memory chip and an upper memory chip located on the lower memory chip, Wherein, the wires include signal wires and power wires, The upper package substrate includes upper chip signal wiring, lower chip signal wiring and memory chip power wiring. wherein the signal conductor is electrically connected to the upper memory chip, and The on-chip signal wiring electrically connects the signal wire to the signal connector.

6. The semiconductor package according to claim 1, wherein: The memory chip comprises a lower memory chip and an upper memory chip located on the lower memory chip, Wherein, the wires include signal wires and power wires, The upper package substrate includes upper chip signal wiring, lower chip signal wiring and memory chip power wiring. wherein the signal conductor is electrically connected to the lower memory chip, and The lower chip signal wiring electrically connects the signal wire to the signal connector.

7. The semiconductor package according to claim 1, wherein: The memory chip comprises a lower memory chip and an upper memory chip located on the lower memory chip, Wherein, the wires include signal wires and power wires, The upper package substrate includes upper chip signal wiring, lower chip signal wiring and memory chip power wiring. wherein the power conductor comprises a first power conductor electrically connected to the upper memory chip and a second power conductor electrically connected to the lower memory chip, and The memory chip power wiring electrically connects the first power conductor to the second power conductor.

8. The semiconductor package according to claim 1, wherein: The memory chip comprises a lower memory chip and an upper memory chip located on the lower memory chip, Wherein, the wires include signal wires and power wires, Wherein, the upper package substrate includes signal wiring and memory chip power wiring, wherein the signal wiring electrically connects the signal wire to the signal connector, and The memory chip power wiring electrically connects the power conductor to the power connector.

9. A semiconductor system comprising: Lower plate; upper plate; a lower semiconductor package located on the lower plate; as well as an upper semiconductor package located on the lower semiconductor package, Wherein, the lower semiconductor package comprises: a lower package substrate; An application processor chip, which is located on the lower package substrate; a lower package molding material located on the lower package substrate and on the application processor chip; and a molded through-piece located in the lower package molding material, Wherein, the upper semiconductor package comprises: an upper packaging substrate; A memory chip, which is located on the upper package substrate; A wire electrically connecting the memory chip to the upper package substrate; a power connector located on a top surface of the upper semiconductor package; a power bump located on the power connector; a signal connector located on a bottom surface of the upper package substrate; and an upper package molding material, which is located on the upper package substrate and covers the memory chip, wherein the power connector penetrates the upper package molding material, one end of the power connector contacts the redistribution layer located on the memory chip, so that the power supply path of the memory chip includes the power connector and the redistribution layer, and the opposite end of the power connector is exposed upward on the upper package molding material, wherein a gap between the bottom surface of the upper plate and the top surface of the upper semiconductor package is less than 300 μm, wherein a gap between a bottom surface of the upper semiconductor package and a top surface of the lower semiconductor package is less than 300 μm, and Wherein, a gap between a bottom surface of the lower semiconductor package and a top surface of the lower plate is less than 300 μm.

10. The semiconductor system according to claim 9, wherein: The lower package substrate includes internal signal wiring, external signal wiring and lower package power wiring, and The internal signal wiring electrically connects the molded through-hole to the application processor chip.

11. The semiconductor system according to claim 9, wherein: The lower package substrate includes internal signal wiring, external signal wiring and lower package power wiring, and The external signal wiring and / or the lower package power wiring electrically connects the application processor chip to solder on the bottom surface of the lower package substrate.

12. The semiconductor system according to claim 9, wherein: The memory chip comprises a lower memory chip and an upper memory chip located on the lower memory chip, Wherein, the wires include signal wires and power wires, and The upper package substrate includes upper chip signal wiring, lower chip signal wiring and memory chip power wiring.

13. The semiconductor system according to claim 12, wherein: The signal conductor is electrically connected to the upper memory chip, and The on-chip signal wiring electrically connects the signal wire to the signal connector.

14. The semiconductor system according to claim 12, wherein: The signal conductor is electrically connected to the lower memory chip, and The lower chip signal wiring electrically connects the signal wire to the signal connector.

15. The semiconductor system according to claim 12, wherein: The power conductor is electrically connected to the upper memory chip, and The memory chip power wiring electrically connects the power conductor to another power conductor electrically connected to the lower memory chip.

16. A semiconductor package, comprising: a lower semiconductor package; as well as an upper semiconductor package located on the lower semiconductor package, Wherein, the upper semiconductor package comprises: an upper packaging substrate; A semiconductor chip, which is located on the upper packaging substrate; an upper package molding material, which is located on the upper package substrate and the semiconductor chip; a power connector located in the upper package molding material; and a signal connector located between the upper package substrate and the lower semiconductor package, The power connector penetrates the upper package molding material, one end of the power connector contacts the redistribution layer located on the semiconductor chip, so that the power supply path of the semiconductor chip includes the power connector and the redistribution layer, and the opposite end of the power connector is exposed upward on the upper package molding material.

17. The semiconductor package according to claim 16, wherein: The semiconductor chip on the upper package substrate is a second semiconductor chip, Wherein, the lower semiconductor package comprises: a lower package substrate; A first semiconductor chip, which is located on the lower package substrate; a lower package molding material located on the lower package substrate and on the first semiconductor chip; and a molded through piece located in the lower package molding material, and The lower package substrate includes internal signal wiring, external signal wiring and lower package power wiring.

18. The semiconductor package according to claim 17, wherein: The external signal wiring and / or the lower package power wiring electrically connects the first semiconductor chip to solder on a bottom surface of the lower package substrate.

19. The semiconductor package according to claim 16, wherein: The semiconductor chip includes a lower semiconductor chip and an upper semiconductor chip located on the lower semiconductor chip, Wherein, the upper semiconductor package further includes signal wires and power wires, The upper package substrate includes upper chip signal wiring, lower chip signal wiring and memory chip power wiring. wherein the signal conductor is electrically connected to the upper semiconductor chip, and The on-chip signal wiring electrically connects the signal wire to the signal connector.

20. The semiconductor package according to claim 16, wherein The semiconductor chip includes a lower semiconductor chip and an upper semiconductor chip located on the lower semiconductor chip, Wherein, the upper semiconductor package further includes signal wires and power wires, The upper package substrate includes upper chip signal wiring, lower chip signal wiring and memory chip power wiring. wherein the signal conductor is electrically connected to the lower semiconductor chip, and The lower chip signal wiring electrically connects the signal wire to the signal connector.

Images