3D memory based processor

Abstract

A processor based on a three-dimensional memory includes a plurality of computing units, each of which includes a logic circuit (220) and adjacent first and second three-dimensional memory arrays (210, 230) stacked thereon, all peripheral circuits (15A, 15A', 17A) of the first three-dimensional memory array (210) and all peripheral circuits (15B, 15B', 17B) of the second three-dimensional memory array (230) are located outside the logic circuit (220) and surround it. The first and second three-dimensional memory arrays (210, 230) overlap with the logic circuit (220).

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201610083747.7 and application date February 13, 2016. Technical Field

[0002] The present invention relates to the field of integrated circuits, and more particularly to processors. Background Art

[0003] Processors need to perform various complex calculations. Conventional processors are only efficient for conventional addition and conventional multiplication, but other calculations require a large number of clock cycles to complete. For this reason, previous technologies proposed using a lookup table (LUT) to complete some calculations. For example, U.S. Patent 5,046,038 proposed using LUT to implement a divider, U.S. Patent 5,954,787 proposed using LUT to implement a trigonometric function calculator, and U.S. Patent 6,263,470 proposed using LUT to implement a Reed-Solomon decoder.

[0004] The following is a detailed description of using LUT to implement an index unit based on US Pat. No. 9,207,910. Figure 1A As shown, the exponential unit uses two LUTs 210 and 230. Among them, the log(x) value 240 of the input x can be found through LUT A 210, and then the log(x) value is multiplied by K in the multiplier 220, and the obtained product 250 can be used to find the exponential value 260 of x through LUT B 230. The patent also discloses a digital processor DSP 200X, which contains multiple parallel exponential units 200-1, 2001-2... 200-N, so that multiple inputs x1, x2... x can be calculated simultaneously. N The index of .

[0005] The above-mentioned processors using LUTs all face a common problem, that is, LUT 210, 230 all use SRAM storage elements, and SRAM must be formed on the substrate. Its storage element area is very large, occupying a large amount of substrate resources. Therefore, the array size of the LUT used in the prior art cannot be too large. As described in Patent 9,207,910, the size of a single LUT is generally limited to 32kb. Therefore, in the prior art, the input variables of the LUT can only be small word widths, which leads to limited improvement of the calculation speed by the LUT. When the processor uses a large number of parallel calculations, these LUTs need to be repeated many times, which requires a large amount of substrate area and increases the cost of the processor.

[0006] The processors in the prior art also face a problem. Since the logic circuits used for different types of calculations are very different, the time they take to complete these calculations is very different. For processors with multiple types of calculations, it is difficult to perform pipeline operations on these calculations. This is not conducive to the overall improvement of system performance. Based on the above difficulties, it is necessary to find a large-capacity, low-cost memory to store LUTs for the processor. Summary of the invention

[0007] The main purpose of the present invention is to provide a processor with better performance.

[0008] Another object of the present invention is to provide a processor with lower cost.

[0009] To achieve these and other purposes, the present invention provides a processor based on a three-dimensional printed memory (3D-P). 3D-P is a type of three-dimensional memory (3D-M), and the information stored in it is recorded in a non-electrical manner during the factory production process. This information is permanently fixed and generally cannot be changed after leaving the factory.

[0010] Since the 3D-P memory cell does not need to be electrically programmed, all the conductivity of its diode can be used to read the data stored in the memory cell. Therefore, compared with the programmable 3D-M, the read current of 3D-P can be increased by more than ten times. Therefore, the read delay of 3D-P is at the 10ns level. If a small array is used (i.e. the number of word lines is less than 1024), the read delay of 3D-P can be reduced to the ns level. Therefore, as a LUT memory, 3D-P can meet the speed requirements of the processor.

[0011] 3D-P uses a cross-point array with a storage element area of ​​4F 2 (F is the process feature size). In addition, with the adoption of three-dimensional integration (8 or more layers can be stacked), the capacity of 3D-P is much larger than that of SRAM (the area of ​​SRAM storage element is ~50F). 2 , which is ~100 times larger than 3D-P storage elements). After using 3D-P to store LUTs, a processor chip can store LUTs with a total data volume of up to 1Tb. This means that the processor can carry LUTs with very large word widths, which can greatly improve the performance of the processor.

[0012] More importantly, 3D-P is located on the substrate circuit. Except for its peripheral circuits, 3D-P basically does not occupy the substrate area. Therefore, 3D-P can be integrated on various logic circuits. Therefore, 3D-P will not only not increase the processor chip area, but also reduce the chip area. This is unimaginable for the existing technology. After using 3D-P as the carrier of LUT, there is another significant advantage: no matter how complex the calculation is, after using LUT, the calculation time of different types is structured, that is, their delays are basically integer multiples. This makes it easy to use pipeline operations for complex calculations.

[0013] Correspondingly, the present invention proposes a processor based on 3D-P, characterized in that it includes: a substrate, the substrate contains a substrate circuit, the substrate circuit includes at least one logic circuit and at least one peripheral circuit of the 3D-P; at least one imprinted storage layer stacked on the substrate, the information of the imprinted storage layer is entered during the factory production process, and the imprinted storage layer stores a LUT; the imprinted storage layer is coupled to the logic circuit through the peripheral circuit, and the logic circuit and the lookup table constitute a computing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A is a circuit block diagram of an exponential unit in the prior art; Figure 1B It is a digital processor based on the above index unit.

[0015] Figure 2 The figure is a cross-sectional view of a three-dimensional imprinting memory (3D-P).

[0016] Figure 3 is a circuit diagram of a 3D-P array in the memory layer 16A.

[0017] Figure 4 Comparison of the IV characteristics of the two 3D-P memory cells.

[0018] Figure 5 The graph is a relationship between the read delay of 3D-P and the number of array word lines n.

[0019] Figure 6 It is a 3D-P based index unit. The figure shows the top view of the substrate circuit (i.e. the 3D-P array has been removed).

[0020] Fig. 7A It is a circuit diagram of a GF adder; Figure 7B It is a 3D-P based GF adder. The figure is a top view of the substrate circuit (i.e. the 3D-P array has been removed).

[0021] Fig. 8A It is a DSP based on index unit; Figure 8BIt is a DSP based on multiple computing units.

[0022] Note that these drawings are only schematic diagrams and are not drawn to scale. For the sake of visibility and convenience, some sizes and structures in the drawings may be enlarged or reduced. In different embodiments, the same symbols generally represent corresponding or similar structures. DETAILED DESCRIPTION

[0023] Figure 2 It represents a three-dimensional imprint memory (3D-P). It contains a substrate circuit layer 0K and a plurality of storage layers 16A and 16B stacked thereon and stacked on each other. The substrate circuit layer 0K contains transistors 0t and interconnects 0i thereof. The transistors 0t are formed in a semiconductor substrate 0; the interconnects 0i are located above the substrate 0. In this embodiment, in order to ensure the speed of the substrate circuit 0K, the interconnects 0i contain 3 (or more than 3) interconnect layers 0M1-0M3. Each storage layer (such as 16A) contains a plurality of bit lines (such as 2a, along the y direction), word lines (such as 1a, along the x direction) and storage elements (such as 16Aaa). The storage layer (such as 16A) is coupled to the substrate 0 through contact channel holes (such as 1av). Here, the substrate circuit layer 0K contains the peripheral circuits of the 3D-P array.

[0024] Figure 2 Two types of 3D-P memory cells 16Aaa and 16Baa are also shown. Each memory cell contains a diode 14. The diode 12 has the following general characteristics: its resistance is small under the read voltage; when the applied voltage is less than the read voltage or is opposite to the read voltage, its resistance is large. The diode film can be a PiN diode or a metal oxide (such as TiO2) diode. The memory cell 16Baa is a low-resistance memory cell (generally referred to as a '1' memory cell); the memory cell 16Aaa is a high-resistance memory cell (generally referred to as a '0' memory cell). The high-resistance memory cell 16Aaa contains an additional insulating film (or high-resistance film) 12 than the low-resistance memory cell 16Baa. As a simple example, the insulating film 12 can be a layer of silicon dioxide film. Due to the presence of the high-resistance insulating film 12, the resistance of the high-resistance memory cell 16Aaa is much higher than that of the low-resistance memory cell 16Baa. The information stored in the 3D-P is entered during factory production and cannot be rewritten after leaving the factory.

[0025] Figure 3Circuit diagram of a 3D-P array in the memory layer 16A. In this figure, a diode indicates a low-resistance memory cell, and no diode indicates a high-resistance memory cell. All address lines in the array are continuous and do not share address lines with other memory arrays in the same memory layer. Accordingly, the 3D-P array has m bit lines and n word lines. In this embodiment, the number of word lines (n) is less than the number of bit lines (m); the bit lines are coupled to the X decoder 15, and the word lines are coupled to the Y decoder / readout circuit 17.

[0026] from Figure 2 and Figure 3 It can be seen that 3D-P uses a cross-point array, and its storage element area is 4F 2 (F is the process feature size). In addition, with the adoption of three-dimensional integration (8 or more layers can be stacked), the capacity of 3D-P is much larger than that of SRAM (the area of ​​SRAM storage element is ~50F). 2 , which is ~100 times larger than 3D-P storage elements). After using 3D-P to store LUTs, a processor chip can store LUTs with a total data volume of up to 1Tb. This means that the processor can carry LUTs with very large word widths, which can greatly improve the performance of the processor.

[0027] More importantly, 3D-P is located on the substrate circuit. Except for its peripheral circuits, 3D-P basically does not occupy the substrate area. Therefore, 3D-P can be integrated on various logic circuits. Therefore, 3D-P will not only not increase the processor chip area, but also reduce the chip area. This is unimaginable with existing technologies.

[0028] Figure 4 Compare the IV characteristics of two 3D-P memory cells ('0' and '1'). Since the memory cells of 3D-P are programmed non-electrically, the '0' and '1' memory cells have different physical / chemical forms ( Figure 2 16Aaa and 16Baa). In this example, the IV curves of the '0' and '1' memory cells are very different. The read of 3D-P is very different from the programmable 3D-M (i.e., 3D-W). Since the 3D-W memory cell needs to be programmed electrically, its read voltage and read current are subject to many restrictions. 3D-P does not need electrical programming, and it can use a larger read voltage V` read , its reading current I` read The read current is one order of magnitude larger than that of 3D-W. In other words, the read latency of 3D-P is one order of magnitude smaller than that of 3D-W. Considering that the read latency of 3D-W is on the order of 100ns, the read latency of 3D-P is on the order of 10ns (assuming the same memory array, 1k x 1k) (refer to the patent application "Computing System Based on Three-Dimensional Memory").

[0029] Figure 5This is a graph showing the relationship between the read latency of 3D-P and the number of word lines in the array n. The read latency of 3D-P is proportional to n. If the number of n is reduced from 1k to a lower 100 level (such as about 200), the read latency of 3D-P can be further reduced to the ns level. This speed enables 3D-P to meet the speed requirements of the processor as a LUT memory.

[0030] Figure 6 The exponential unit 200 based on 3D-P is shown in the top view of the substrate circuit (i.e., the 3D-P array has been removed). In the figure, the printed storage layer of LUT A 210 (the area filled with right diagonal lines) and the printed storage layer of LUT B 230 (the area filled with left diagonal lines) cover the multiplier 220. The input 270 selects the required logarithmic value through the X decoder 15A, 15A' of LUT A 210, and then the readout circuit 17A outputs the existing log (x) value 240. After being multiplied by K by the multiplier, the result 250 is sent to the X decoder 15B, 15B' of LUT B 230 to select the corresponding exponent value to obtain the final result 260. Note that both LUT A 210 and LUT B 230 have one side, and the substrate below them does not contain the peripheral circuit of 3D-P, which is convenient for the wiring of the multiplier 220.

[0031] Fig. 7A The circuit block diagram of a GF adder is shown in FIG. 300. The GF adder 300 is described in detail in U.S. Patent Application 2006 / 0123325A1. The polynomial multiplier 310 multiplies X and Y, and the first 7 bits 340 of the obtained product are sent to the LUT 320 for mod calculation. The last 8 bits 360 and the mod calculated value 350 are added in the adder 330 to obtain the final result Z.

[0032] Figure 7B This is a 3D-P based GF adder. The figure is a top view of the substrate circuit (i.e. the 3D-P array has been removed). Figure 6 Similarly, the multiplier 310 and the adder are covered by the 3D-P array 320. The 3D-P array has one side, and the substrate below does not contain the peripheral circuits of the 3D-P, which facilitates the interface between the substrate logic circuit and the outside world.

[0033] Fig. 8A It is a DSP 200X` based on index unit. It contains multiple parallel index units 200-1`, 2001-2`… 200-N`, all of which use 3D-P as the storage carrier of LUT and calculate multiple inputs x1, x2… x at the same time. N The index of . Figure 8BIt is a DSP 200Z` based on multiple computing units. It contains multiple computing units, including exponential unit 200`, GF multiplication unit 300, division unit 400`, etc. These computing units all use 3D-P as the storage carrier of LUT and perform parallel computing. After using 3D-P as the carrier of LUT, there is a significant advantage: no matter how complex the calculation is, after using LUT, the calculation time of different types is structured, that is, their delays are basically integer multiples. This makes it easy to use pipeline operations for complex calculations.

[0034] The 3D-P-based processor proposed in the present invention is widely used, and the computing units using it include: multiplication unit, division unit, trigonometric function unit, exponential unit, logarithmic unit, GF multiplication unit, error detection and correction ECC unit, encryption unit, decryption unit, or function unit (the function unit can use LUT to implement any function). It can be applied to various processors, including: central processing unit CPU, field programmable gate array FPGA, digital processor DSP, image processor GPU, video processor video processor, or communication processor modem, etc.

[0035] It should be understood that, without departing from the spirit and scope of the present invention, the form and details of the present invention can be modified, which does not hinder them from applying the spirit of the present invention. Therefore, except according to the spirit of the attached claims, the present invention should not be restricted in any way.

Claims

1. A processor comprising a plurality of computing units, wherein the plurality of computing units are located on the same semiconductor substrate (0), each computing unit being characterized by comprising: A logic circuit (220) located in the semiconductor substrate (0); A first three-dimensional imprinted storage array (210) and a second three-dimensional imprinted storage array (230) are adjacent to each other, the first three-dimensional imprinted storage array (210) and the second three-dimensional imprinted storage array (230) are both used to store a lookup table LUT and are stacked on the logic circuit (220), all peripheral circuits of the first three-dimensional imprinted storage array (210) are located in the semiconductor substrate (0) and constitute a first group of peripheral circuits, and all peripheral circuits of the second three-dimensional imprinted storage array (230) are located in the semiconductor substrate (0) and constitute a second group of peripheral circuits; The first group of peripheral circuits and the second group of peripheral circuits are both located outside the logic circuit (220) and surround the logic circuit (220); The first three-dimensional imprint storage array (210) and the second three-dimensional imprint storage array (230) both overlap with the logic circuit (220); The first three-dimensional imprint storage array (210) and the second three-dimensional imprint storage array (230) are both coupled to the logic circuit (220).

2. The processor according to claim 1, further characterized in that: At least one side of the first three-dimensional imprint storage array (210) does not contain peripheral circuits.

3. The processor according to claim 1, further characterized in that: The semiconductor substrate (0) below at least one side of the first three-dimensional imprinting memory array (210) does not contain peripheral circuits of the first three-dimensional imprinting memory array (210).

4. The processor according to claim 1, further characterized in that: At least one side of the second three-dimensional imprint storage array (230) does not contain peripheral circuits.

5. The processor according to claim 1, further characterized in that: The semiconductor substrate (0) below at least one side of the second three-dimensional imprinting memory array (230) does not contain peripheral circuits of the second three-dimensional imprinting memory array (230).

6. The processor according to claim 1, further characterized in that: The computing unit includes at least one multiplication unit, a division unit, a trigonometric function unit, an exponential unit, a logarithmic unit, a GF multiplication unit, an error detection and correction ECC unit, an encryption unit, a decryption unit, or a function unit.

7. The processor according to claim 1, further characterized in that: The processor is a central processing unit CPU, a field programmable gate array FPGA, a digital processor DSP, an image processor GPU, a video processor video processor, or a communication processor modem.

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