Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a device layer including first and second active patterns extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction intersecting the first direction on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer and including first and second lower wiring patterns extending in the first direction, on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction. The first upper wiring pattern is connected to the first upper via without being connected to the second upper via, and the second upper wiring pattern is connected to the second upper via without being connected to the first upper via.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0124784, filed on October 8, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0004] As semiconductor manufacturing technology has evolved, the height of the standard cells constituting semiconductor devices has decreased, as has the distance between adjacent patterns (e.g., the gate electrode pitch). This has resulted in increased design complexity. Increased integration complicates the routing process used for layout design, particularly wiring layer design. Summary of the Invention

[0005] The example embodiments provide semiconductor devices having structures capable of performing complex wiring layer designs with improved efficiency.

[0006] Example embodiments provide a method for manufacturing a semiconductor device capable of performing complex wiring layer designs with improved efficiency.

[0007] According to an example embodiment, a semiconductor device includes: a device layer including a first active pattern and a second active pattern, and a plurality of gate electrodes, the first active pattern and the second active pattern extending on a substrate in a first direction and adjacent to each other, the plurality of gate electrodes extending on the substrate in a second direction intersecting the first direction and crossing the first active pattern and the second active pattern; a lower wiring layer located on the device layer, including a first lower wiring pattern and a second lower wiring pattern, the first lower wiring pattern and the second lower wiring pattern extending in the first direction, respectively located on the first active pattern and the second active pattern, and connected to the plurality of gate electrodes; and an upper wiring layer located on the lower wiring layer, having a first upper via and a second upper via located on the first lower wiring pattern and the second lower wiring pattern, respectively, and a first upper wiring pattern and a second upper wiring pattern extending in the second direction. The first upper wiring pattern is connected to the first upper via but not to the second upper via, and the second upper wiring pattern is connected to the second upper via but not to the first upper via.

[0008] According to an example embodiment, a semiconductor device includes: a first active pattern and a second active pattern that extend in a first direction on a substrate and that are adjacent to each other; a plurality of first gate electrodes and a plurality of second gate electrodes that cross the first active pattern and the second active pattern and that extend in a second direction that intersects the first direction; an interlayer insulating film that is on the first active pattern and the second active pattern and the plurality of first gate electrodes and the plurality of second gate electrodes; a first lower wiring pattern and a second lower wiring pattern that extend in the first direction on the interlayer insulating film and that each connect to the plurality of first gate electrodes and the plurality of second gate electrodes; a dielectric film that is on the interlayer insulating film and the first lower wiring pattern and the second lower wiring pattern; a plurality of first upper vias and a plurality of second upper vias that are in the dielectric film and that connect to the first lower wiring pattern and the second lower wiring pattern, respectively; a plurality of first upper wiring patterns that extend in the first direction on the dielectric film, each of the plurality of first upper wiring patterns connecting to the plurality of first upper vias and not connecting to the plurality of second upper vias; and a plurality of second upper wiring patterns that extend in the second direction on the dielectric film, each of the plurality of second upper wiring patterns connecting to the plurality of second upper vias and not connecting to the plurality of first upper vias.

[0009] According to an example embodiment, a semiconductor device includes: a plurality of units that are on a substrate, and at least one unit of the plurality of units including: a first active pattern and a second active pattern that have different conductive types and that extend in a first direction; a plurality of gate electrodes that cross the first active pattern and the second active pattern and that extend in a second direction that intersects the first direction; a first lower wiring pattern and a second lower wiring pattern that are on the plurality of gate electrodes and that are configured to apply an electrical signal to the plurality of gate electrodes; a first upper via and a second upper via that are on the first lower wiring pattern and the second lower wiring pattern and that connect to the first lower wiring pattern and the second lower wiring pattern, respectively; and a plurality of upper wiring patterns that are on the first lower wiring pattern and the second lower wiring pattern, the plurality of upper wiring patterns including an input wiring pattern that connects to a first one of the first upper via and the second upper via and not to a second one of the first upper via and the second upper via.

[0010] According to an example embodiment, a method of manufacturing a semiconductor device includes the steps of constructing a layout of an integrated circuit including a standard cell layout, manufacturing a photomask using the layout, and forming a metal wiring and a via vertically connecting the metal wiring on a substrate using the photomask. The step of constructing the layout includes placing a standard cell according to pieces of design data defining the integrated circuit, wherein at least one of the standard cells includes a first active pattern and a second active pattern extending in a first direction and adjacent to each other, and a plurality of gate electrodes extending in a second direction intersecting the first direction and crossing the first active pattern and the second active pattern. The step of constructing the layout further includes wiring a first lower wiring pattern and a second lower wiring pattern connected to the plurality of gate electrodes in the at least one standard cell to have the first lower wiring pattern and the second lower wiring pattern with a plurality of available pin regions provided with pin regions overlapping in the second direction, predefining only a single pin region among the pin regions overlapping in the second direction, and placing an upper via in the predefined pin region and wiring an upper wiring pattern connected to the upper via and extending in the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a computer system for performing a semiconductor design according to some example embodiments of the inventive concepts;

[0013] Figure 2 is a flowchart illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts;

[0014] Figure 3 is a flowchart illustrating a layout design method according to some example embodiments of the inventive concepts;

[0015] Figures 4A-4C is a schematic layout illustrating a wiring process of a semiconductor device according to some example embodiments of the inventive concepts;

[0016] Figure 5 is a layout of a standard cell according to some example embodiments of the inventive concepts;

[0017] Figures 6A-6C is a cross-sectional view taken along line A-A', line B-B', and line C-C' of the standard cell of Figure 5

[0018] Figure 7 ​is a layout showing a lower wiring layer design of a semiconductor device according to some example embodiments of the inventive concept;

[0019] Figures 8A-8C is a cross-sectional view taken along Figure 7 lines A-A', B-B' and C-C' of the semiconductor device of

[0020] Figure 9 is a layout showing an upper wiring layer design of a semiconductor device according to some example embodiments of the inventive concept;

[0021] Figures 10A-10C is a cross-sectional view taken along Figure 9 lines A-A', B-B' and C-C' of the semiconductor device of

[0022] Figure 11 is a cross-sectional view of a semiconductor device according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0023] In the following, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, like drawing reference numerals can denote like elements or components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "on" another element, "attached" to another element, "connected" to another element, "coupled" to another element, "in contact" with another element, etc., it can be directly on, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on," "directly attached" to, "directly connected" to, "directly coupled" to, or "directly in contact" with another element, there are no intervening elements present. It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms since such elements are commonly known with other names. The terms of degree such as "substantially", "approximately" and "comprises / comprising" as used herein can allow for a degree of variability in amounts, dimensions, shapes, positions, etc. of one or more elements. As used herein, the term "exemplary" is used merely for

[0024] Figure 1 is a block diagram showing a computer system for performing a semiconductor design according to some example embodiments of the inventive concept.

[0025] Referring to Figure 1The computer system can include a central processing unit (CPU) 10, a working memory 30, an I / O device 50, and a storage device 70. The computer system can be a device configured to perform layout design according to some embodiments of the inventive concept. In some embodiments, the computer system can be equipped with various design and verification simulation programs.

[0026] The CPU 10 can be configured to execute computer readable program codes (e.g., application programs, an operating system, and device drivers) stored in the working memory 30 and / or the storage device 70. The CPU 10 can be configured to execute an operating system (OS) loaded in the working memory 30. The CPU 10 can be configured to execute various application programs (APs) that can be managed based on the OS. For example, the CPU 10 can be configured to execute a layout design tool 32 loaded in the working memory 30.

[0027] The operating system or the application programs can be loaded into the working memory 30. When the computer system is started, an OS image stored in the storage device 70 can be loaded into the working memory 30 based on a boot sequence. Various input / output operations of the computer system can be supported by the operating system. In a similar manner, the application programs can be loaded into the working memory 30 by a selection of a user or in order to provide basic services. The layout design tool 32 for layout design according to some example embodiments of the inventive concept can also be loaded into the working memory 30 from the storage device 70.

[0028] The layout design tool 32 can have a bias function that can be configured to change a shape and a position of a specific layout pattern different from a layout pattern defined by design rules. In addition, the layout design tool 32 can be configured to perform a design rule check (DRC) under a changed bias data condition (e.g., a changed shape and / or position of the layout pattern). The working memory 30 can be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM) or a non-volatile memory such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), or a NOR flash memory.

[0029] The working memory 30 can further include a simulation tool 34 configured to perform optical proximity correction (OPC) for designed layout data.

[0030] The I / O device 50 can control user input and output from a user interface device. For example, the I / O device 50 can include a keyboard or a display to receive information from a designer. Through the use of the I / O device 50, the designer can receive information about a semiconductor region or a data path that can need to be adjusted in operation characteristics. In addition, a process or a processing result of the simulation tool 34 can be displayed through the I / O device 50.

[0031] The storage device 70 can be provided as a storage medium of the computer system. The storage device 70 can store applications, an operating system image, and various types of data. The storage device 70 can be provided as a memory card (e.g., a multimedia card (MMC), an embedded multimedia card (eMMC), an SD, a MicroSD, etc.) or a hard disk drive (HDD). The storage device 70 can include a NAND type flash memory having a large storage capacity. In other embodiments, the storage device 70 can include a next-generation nonvolatile memory (such as a PRAM, an MRAM, a ReRAM, an FRAM, etc.) or a NOR flash memory.

[0032] The system interconnect 90 can be a system bus that provides a network inside the computer system. The CPU 10, the working memory 30, the I / O device 50, and the storage device 70 can be electrically connected to each other and exchange data through the system interconnect 90. However, the configuration of the system interconnect 90 is not limited to the above description of the example embodiments, and can also include an arbitration device for efficient management.

[0033] Figure 2 FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept.

[0034] Referring to Figure 2 , Figure 1 The computer system of FIG. 1 is used to perform a high-level design of a semiconductor integrated circuit (S110).

[0035] In some embodiments, the high-level design can include describing a design target integrated circuit in a high-level language of a computer language. For example, a high-level language such as a C programming language can be used. A circuit designed through the high-level design can be more specifically represented by a register transfer level (RTL) coding or simulation. For example, code generated through the register transfer level coding can be converted into a netlist and synthesized into an entire semiconductor device. The synthesized schematic circuit can be verified through a simulation tool, and can be accompanied by an adjustment process according to a verification result.

[0036] Then, a layout design for implementing a logically completed semiconductor integrated circuit on a silicon substrate can be performed (S120).

[0037] As described above, the layout design can be performed with reference to the schematic circuit or the corresponding netlist that is synthesized in the high-level design. The layout design can include a routing process of placing and connecting various standard cells provided in the cell library according to defined design rules.

[0038] The cell library for the layout design can further include information on operations, speed, and power consumption of the standard cells. The cell library for representing a circuit at a specific gate level as a layout can be defined in some layout design tools.

[0039] The layout design can include a process of defining shapes or sizes of layout patterns for forming transistors and metal wires (e.g., lower wiring layers and upper wiring layers) to be formed on a silicon substrate. For example, in order to form an inverter circuit on a silicon substrate, a layout pattern of appropriate inverter, such as a P-type metal oxide semiconductor (PMOS) transistor, an N-type metal oxide semiconductor (NMOS) transistor, an N-well (N-WELL), a gate electrode, and a metal wire to be formed thereon, can be appropriately placed.

[0040] To this end, an appropriate inverter can be searched for among inverters that have been defined in the cell library, and the appropriate inverter can be selected. In addition, routing can be performed on the selected and placed standard cells. Some of this series of processes can be automatically or manually performed by a layout design tool. In some embodiments, the placement and routing of the standard cells can be automatically performed using a separate place and route (place&routing) tool.

[0041] After the routing, verification of the layout can be performed to determine whether there are portions that violate design rules. Items to be verified can include a design rule check (DRC) that verifies whether the layout complies with design rules, an electrical rule check (ERC) that verifies that the correct operation is performed without internal disconnection, and a layout versus schematic (LVS) that verifies whether the layout matches the gate-level netlist.

[0042] During the layout design of a semiconductor device according to some example embodiments of the inventive concept, a cell library can be used, and in the cell library, when positions of each possible pin metal (also referred to as "upper via") selectable within a standard cell overlap in one direction, one of the pin metals is pre-defined.

[0043] By the pre-specification of the pin metal, design complexity can be improved and run time can be reduced, while block-level scaling can also be improved. Accordingly, when designing a highly integrated memory, the layout design tool 32 and / or the simulation tool 34 can be advantageously applied to a cell having high routing complexity. This will be described in detail with reference to Figure 3 and Figures 4A-4C This will be described in detail.

[0044] Referring back Figure 2 An optical proximity correction (OPC) process (S130) can be performed. A photolithography process can be used, and thus a layout pattern obtained by the layout design can be implemented on a silicon substrate. In this example, the optical proximity correction can be a technique for correcting distortion that can occur in the photolithography process. That is, through the optical proximity correction, distortion phenomena such as refraction or process effects caused by characteristics of light can be corrected during exposure using the layout pattern. When the optical proximity correction is performed, the shape and position of the designed layout pattern can be slightly changed.

[0045] In the layout design according to some example embodiments, pin metals that overlap in one direction are designated in advance, and thus additional run time for changing the positions of adjacent pin metals in the optical proximity correction process can not be generated.

[0046] Then, a photomask can be manufactured based on the layout changed through the optical proximity correction (S140). For example, the photomask can be manufactured using a thin film of chromium coated on a glass substrate in a manner of describing the layout pattern.

[0047] The manufactured photomask can be used to manufacture a semiconductor device (S150).

[0048] In a process of manufacturing a semiconductor device using the photomask, an exposure process and an etching process can be repeated in various ways. Through these processes, patterns of various shapes can be sequentially formed on a silicon substrate during the layout design. In some embodiments, various semiconductor processes are performed on a semiconductor device such as a wafer using a plurality of masks to form a semiconductor device in which an integrated circuit is implemented. For example, a process using a mask can refer to a patterning process that is part of a photolithography process. Through the patterning process, a desired pattern can be formed on a semiconductor substrate or a material layer.

[0049] The semiconductor processes can also include a deposition process, an etching process, an ion implantation process, a cleaning process, etc. In addition, the semiconductor processes can include a packaging process of mounting the semiconductor device on a printed circuit board (PCB) and sealing the semiconductor device with a sealing material, and can include a test process for the semiconductor device or a package thereof.

[0050] Figure 3 is a flowchart illustrating a layout design method according to some example embodiments of the inventive concept. Figures 4A-4C Placement and routing of a standard cell layout are illustrated, and is a plan view illustrating a standard cell layout according to some embodiments of the inventive concept.

[0051] Referring to Figure 3 and Figure 4AThe original standard cell layout can be configured using a layout design tool (S122).

[0052] The standard cell layout can include a layout of a lower wiring layer on a logic (or device layer) layout including logic transistors. Figure 4A The layout of the lower wiring layer on the logic layout is schematically shown.

[0053] For ease of explanation, the logic layout is schematically shown as a layout pattern defining a first active region AR1 and a second active region AR2. However, in some embodiments, the first active region AR1 and the second active region AR2 can be understood to respectively constitute a P-type metal-oxide-semiconductor field-effect transistor (P-MOSFET) and an N-type metal-oxide-semiconductor field-effect transistor (N-MOSFET) together with a gate electrode (not shown). The first active region AR1 and the second active region AR2 extend in a first direction D1 and can be separated from each other in a second direction D2.

[0054] The layout of the lower wiring layer is schematically shown as a first lower wiring pattern M1a and a second lower wiring pattern M1b connected to the first active region AR1 and the second active region AR2, respectively. Each of the first lower wiring pattern M1a and the second lower wiring pattern M1b can be an input wiring pattern connected to a gate electrode (not shown) of a logic transistor. Each of the first lower wiring pattern M1a and the second lower wiring pattern M1b can have a linear shape extending in the first direction D1, and the first lower wiring pattern M1a and the second lower wiring pattern M1b can be spaced apart from each other in the second direction D2. Each of the first lower wiring pattern M1a and the second lower wiring pattern M1b can include two patterns separated in the first direction D1.

[0055] In another example embodiment (see Figure 7 ), the layout of the lower wiring layer extends in the first direction D1 on the substrate and can further include an additional lower wiring pattern spaced apart from the first lower wiring pattern M1a and the second lower wiring pattern M1b in the second direction D2. The additional lower wiring pattern can be located between the first lower wiring pattern M1a and the second lower wiring pattern M1b and can be an output pattern connected to a source / drain region.

[0056] The first lower wiring pattern Mla and the second lower wiring pattern Mlb can include pin regions Pll, P12, P21, and P22 wired using the layout of the upper wiring layer described below. For example, each of the first lower wiring pattern Mla and the second lower wiring pattern Mlb can have a double pin region Pll, a double pin region P12, a double pin region P21, or a double pin region P22, each of which includes two pin regions. In an example embodiment, all of the double pin regions Pll, P12, P21, or P22 are available pin regions, but only a part of the pin regions is selected in the wiring process, and can be set as a region in which an upper via is to be formed.

[0057] In an example embodiment, all of the double pin regions Pll, P12, P21, or P22 are available pin regions, but one of the pin regions of the double pin regions Pll, P12, P21, and P22 that overlap in the second direction D2 can be designated in advance. For example, as shown in Figure 4A , each of the double pin regions Pll, P12, P21, and P22 can include a designated pin region AP designated as a via position and an unavailable pin region DP not used as a via position.

[0058] The layout of the standard cell described above can be stored in the cell library described above with reference to Figure 2 The layout of the standard cell stored in the cell library can be placed (S124).

[0059] In Figure 4A , a single standard cell layout is shown. However, the standard cell layout can be set to a plurality of standard cell layouts, and the plurality of standard cell layouts can be placed in parallel in the first direction Dl and / or the second direction D2.

[0060] Wiring to the layout of the upper wiring layer can be performed on the placed standard cell layout (S126).

[0061] In this process, the wiring can be a design process by programming as shown in Figure 2 , and can not be implemented as an entity element using a semiconductor process. However, for the purpose of illustration, Figure 4B and Figure 4C the wiring result of the design process is shown.

[0062] Referring to Figure 4B , the layout of the upper wiring layer can include placement of the first upper wiring pattern M2a and the second upper wiring pattern M2b and placement of the first upper via Vla and the second upper via Vlb.

[0063] Each of the first upper wiring pattern M2a and the second upper wiring pattern M2b can have a line shape extending in the second direction D2, and the first upper wiring pattern M2a and the second upper wiring pattern M2b can be spaced apart from each other in the first direction D1. Each of the first upper via V1a and the second upper via V1b can be placed in a pre-designated single region (i.e., a pre-designated pin region AP) among a plurality of pin regions overlapping in the second direction D2 along which the first upper wiring pattern M2a and the second upper wiring pattern M2b extend.

[0064] As shown in FIG. 2B, the first upper via V1a is located in the pre-designated pin region AP of the double pin regions P11 and P12 of the first lower wiring pattern M1a, and can be connected to the first upper wiring pattern M2a overlapping the pin region AP and extending in the second direction D2. In a similar manner, the second upper via V1b is located in the pre-designated pin region AP of the double pin regions P21 and P22 of the second lower wiring pattern M1b, and can be connected to the second upper wiring pattern M2b overlapping the pin region AP and extending in the second direction D2. As described above, in the standard cell layout according to the example embodiment, the upper wiring layer can be connected to the lower wiring layer through the first upper via V1a and the second upper via V1b. Figure 4B As shown in FIG. 2B, the first upper via V1a is located in the pre-designated pin region AP of the double pin regions P11 and P12 of the first lower wiring pattern M1a, and can be connected to the first upper wiring pattern M2a overlapping the pin region AP and extending in the second direction D2. In a similar manner, the second upper via V1b is located in the pre-designated pin region AP of the double pin regions P21 and P22 of the second lower wiring pattern M1b, and can be connected to the second upper wiring pattern M2b overlapping the pin region AP and extending in the second direction D2. As described above, in the standard cell layout according to the example embodiment, the upper wiring layer can be connected to the lower wiring layer through the first upper via V1a and the second upper via V1b.

[0065] Figure 4A As shown in FIG. 2B, the first upper via V1a is located in the pre-designated pin region AP of the double pin regions P11 and P12 of the first lower wiring pattern M1a, and can be connected to the first upper wiring pattern M2a overlapping the pin region AP and extending in the second direction D2. In a similar manner, the second upper via V1b is located in the pre-designated pin region AP of the double pin regions P21 and P22 of the second lower wiring pattern M1b, and can be connected to the second upper wiring pattern M2b overlapping the pin region AP and extending in the second direction D2. As described above, in the standard cell layout according to the example embodiment, the upper wiring layer can be connected to the lower wiring layer through the first upper via V1a and the second upper via V1b. Figure 4B As shown in FIG. 2B, the first upper via V1a is located in the pre-designated pin region AP of the double pin regions P11 and P12 of the first lower wiring pattern M1a, and can be connected to the first upper wiring pattern M2a overlapping the pin region AP and extending in the second direction D2. In a similar manner, the second upper via V1b is located in the pre-designated pin region AP of the double pin regions P21 and P22 of the second lower wiring pattern M1b, and can be connected to the second upper wiring pattern M2b overlapping the pin region AP and extending in the second direction D2. As described above, in the standard cell layout according to the example embodiment, the upper wiring layer can be connected to the lower wiring layer through the first upper via V1a and the second upper via V1b.

[0066] As shown in FIG. 2B, the first upper via V1a is located in the pre-designated pin region AP of the double pin regions P11 and P12 of the first lower wiring pattern M1a, and can be connected to the first upper wiring pattern M2a overlapping the pin region AP and extending in the second direction D2. In a similar manner, the second upper via V1b is located in the pre-designated pin region AP of the double pin regions P21 and P22 of the second lower wiring pattern M1b, and can be connected to the second upper wiring pattern M2b overlapping the pin region AP and extending in the second direction D2. As described above, in the standard cell layout according to the example embodiment, the upper wiring layer can be connected to the lower wiring layer through the first upper via V1a and the second upper via V1b.

[0067] Figure 4C As shown in FIG. 2B, the first upper via V1a is located in the pre-designated pin region AP of the double pin regions P11 and P12 of the first lower wiring pattern M1a, and can be connected to the first upper wiring pattern M2a overlapping the pin region AP and extending in the second direction D2. In a similar manner, the second upper via V1b is located in the pre-designated pin region AP of the double pin regions P21 and P22 of the second lower wiring pattern M1b, and can be connected to the second upper wiring pattern M2b overlapping the pin region AP and extending in the second direction D2. As described above, in the standard cell layout according to the example embodiment, the upper wiring layer can be connected to the lower wiring layer through the first upper via V1a and the second upper via V1b.

[0068] ​​For the additional design, the placement can be performed simultaneously with, in coordination with, or after the placement of the first and second upper via V1a and V1b and the first and second upper wiring pattern M2a and M2b.

[0069] The above series of processes of Figure 3 may be implemented using a layout design tool and / or a placement and routing tool. In an example embodiment, although the layout of the upper wiring layer is shown as a single layer, the layout can be set to multiple layers, and the layers can be sequentially stacked.

[0070] As described above, a layout design can be performed to implement a semiconductor integrated circuit on a silicon substrate. For example, the layout design can include a wiring process of placing and connecting various cells provided in a cell library according to defined design rules.

[0071] In an example embodiment, the pin region to be connected to the upper wiring patterns M2a and M2b is defined as using one of the pin regions of the cells library that overlap in one direction (e.g., the second direction D2), and thus the wiring design can be simplified in a complex cell of integration. This can be advantageous when the distance between the first and second lower wiring patterns M1a and M1b is relatively small. In some embodiments, the distance between the first and second lower wiring patterns can be equal to or less than 100 nm. When the lower wiring layer further includes an additional lower wiring pattern, the first and second lower wiring patterns M1a and M1b and the additional lower wiring pattern can be arranged in the second direction at a pitch of 30 nm or less.

[0072] The example embodiments are described above by schematic illustrations of transistors. However, in the following, a semiconductor device according to some example embodiments of the inventive concept will be described with reference to drawings showing layouts of device layers including transistors in various forms.

[0073] Figure 5 is a layout of a standard cell according to some example embodiments of the inventive concept, Figures 6A-6C is a cross-sectional view taken along a line A-A', a line B-B', and a line C-C' of the standard cell of Figure 5

[0074] Figure 5 The standard cell shown in Figure 2 ​The process of manufacturing a semiconductor device (S150) described in the above example of a standard cell layout consisting of three-dimensional transistors (such as FINFETs) in a semiconductor device implemented on the semiconductor substrate 100.

[0075] Referring to Figure 5 and Figures 6A-6C The standard cell can include a first active pattern and a second active pattern each extending in a first direction D1 on the substrate 100. For example, the substrate 100 can be a silicon substrate or a germanium substrate or a silicon-on-insulator (SOI) substrate. Each of the first active pattern FN1 and the second active pattern FN2 can include three active fins, but in other embodiments, can be provided as one active fin or a plurality of active fins.

[0076] A first device isolation pattern ST1 can be formed on the substrate 100 to separate the respective first active pattern FN1 and the second active pattern FN2 while filling a gap therebetween. The first device isolation pattern ST1 can be recessed to expose an upper portion of the first active pattern FN1 and the second active pattern FN2 (i.e., at least a portion of the upper portion of the first active pattern FN1 and the second active pattern FN2 can be free of the first device isolation pattern ST1). A second device isolation pattern ST2 can be formed on the substrate 100 to define a P-MOSFET region PR and an N-MOSFET region NR. For example, the P-MOSFET region PR can be defined by the first active pattern FN1, and the N-MOSFET region NR can be defined by the second active pattern FN2.

[0077] The first device isolation pattern ST1 and the second device isolation pattern ST2 can be formed using an insulating material such as silicon oxide. As an example, the first device isolation pattern ST1 can be formed to have a shallower depth than the second device isolation pattern ST2. In these embodiments, the first device isolation pattern ST1 can be formed by a process different from that of the second device isolation pattern ST2. The first device isolation pattern ST1 can be formed using a shallow trench isolation (STI) process, while the second device isolation pattern ST2 can be formed using a deep trench isolation (DTI) process.

[0078] A gate line GL can be formed to intersect the first active pattern FN1 and the second active pattern FN2 and extend in a second direction D2. The gate lines GL can be spaced apart from each other in the first direction D1. As Figure 6AAs shown in FIG. 1, each of the gate lines GL can include a gate electrode GE extending in the second direction D2, a gate insulating pattern GI located below the gate electrode GE, and a gate spacer GS provided in both sides of the gate electrode GE. In addition, in each of the gate lines GL, a cover pattern CP located on an upper surface of the gate electrode GE and at least partially covering the upper surface of the gate electrode GE can be formed.

[0079] For example, the gate electrode GE can include one or more materials including, but not limited to, a doped semiconductor, a metal, and / or a conductive metal nitride. The gate insulating pattern GI can include a silicon oxide film or a silicon oxynitride film, or a high dielectric film having a dielectric constant higher than that of a silicon oxide film. Each of the cover pattern CP and the gate spacer GS can include one or more materials including, but not limited to, a silicon oxide film, a silicon nitride film, and / or a silicon oxynitride film.

[0080] The source / drain regions SD can be formed in the first and second active patterns FN1 and FN2 located on both sides of each of the gate electrodes GE. The source / drain regions SD on the P-MOSFET region PR can be doped with a p-type impurity, and the source / drain regions SD on the N-MOSFET region NR can be doped with an n-type impurity.

[0081] The source / drain regions SD can include selectively epitaxially regrown layers. A portion of the first and second active patterns FN1 and FN2 in both sides of the gate electrode GE can be recessed, and then an epitaxial growth process can be performed on the recessed regions of the first and second active patterns FN1 and FN2. The epitaxial growth process can be performed using a semiconductor element different from the substrate 100. As an example, the source / drain regions SD can be formed of a semiconductor element having a lattice constant greater than or less than that of the semiconductor element of the substrate 100. The source / drain regions SD are formed of a semiconductor element different from the substrate 100, and thus a compressive stress or a tensile stress can be provided to the channel regions AF between the source / drain regions SD.

[0082] An interlayer insulating film 110 located on and at least partially covering the source / drain regions SD and the gate lines GL can be formed. The interlayer insulating film 110 can be formed of a silicon oxide film or a silicon oxynitride film. First and second contact structures CA1 and CA2 can be formed on the source / drain regions SD of the P-MOSFET region PR and the N-MOSFET region NR, respectively.

[0083] The first contact structure CA1 and the second contact structure CA2 can have a linear or strip shape extending in the second direction D2. In a subsequent design process, the lower wiring layer M1 can include a first power wiring pattern VDD and a second power wiring pattern VSS, which can extend in the first direction D1 along the boundaries of the standard cells, and a first lower wiring pattern and a second lower wiring pattern. In addition, a portion of the first contact structure CA1 and the second contact structure CA2 can extend to be connected to the first power wiring pattern VDD and the second power wiring pattern VSS. This will be described with reference to Figure 5 Embodiments are described.

[0084] A portion of each of the first contact structure CA1 and the second contact structure CA2 can be located on the second device isolation pattern ST2 adjacent to the P-MOSFET region PR or the N-MOSFET region NR. The upper surfaces of the first contact structure CA1 and the second contact structure CA2 can be coplanar with the upper surface of the interlayer insulating film 110.

[0085] The interlayer insulating film 110 is patterned to form holes that expose at least a portion of the source / drain region SD, and then the holes are at least partially filled with a conductive material CN to form the first contact structure CA1 and the second contact structure CA2. In the process of forming the holes that expose the source / drain region SD (the portions of the source / drain region SD that do not have the interlayer insulating film 110), an upper portion of the source / drain region SD can be removed. The first contact structure CA1 and the second contact structure CA2 can include one or more materials, including but not limited to doped semiconductors, conductive metal nitrides, metals, and / or metal silicides. In a similar manner, the interlayer insulating film 110 is patterned to form holes that expose the gate electrode GE (i.e., at least a portion of the gate electrode GE does not have the interlayer insulating film 110), and then the holes are at least partially filled with a conductive material CN to form the gate contact structure CB.

[0086] Figure 7 is a layout of a semiconductor device according to some example embodiments of the inventive concepts, Figures 8A-8C is a cross-sectional view taken along Figure 7 the line A-A', the line B-B', and the line C-C' of the semiconductor device of Figure 7 shows a layout of a lower wiring layer M1 according to some example embodiments, while Figures 8A-8C shows a structure of the lower wiring layer M1 formed in processing performed according to the layout.

[0087] Reference will be made to Figure 7The first power wiring pattern VDD and the second power wiring pattern VSS are placed at the boundaries of the adjacent standard cells (i.e., outside the P-MOSFET region PR and outside the N-MOSFET region NR), and extend in the first direction D1. A portion of the first contact structure CA1 and the second contact structure CA2 extend to be connected to the first power wiring pattern VDD and the second power wiring pattern VSS. A single active contact structure CA1' in the first contact structure CA1 has an extension CA_E located under the first power wiring pattern VDD, and can be connected to the first power wiring pattern VDD by a via V0 located in the extension CA_E. Two active contact structures CA2' located at both ends of the second contact structure CA2 have extensions CA_E located under the second power wiring pattern VSS, and can be connected to the second power wiring pattern VSS by a via V0 located in the extension CA_E. In this regard, a drain voltage Vdd (i.e., a power supply voltage) can be applied from the first power wiring pattern VDD to the P-MOSFET region PR, and a source voltage Vss (i.e., a ground voltage) can be applied from the second power wiring pattern VSS to the N-MOSFET region NR.

[0088] Referring to Figures 8A-8C and Figure 7 A first dielectric film 120 can be formed on the interlayer insulating film 110. For example, the first dielectric film 120 can include a silicon oxide film and / or a silicon oxynitride film.

[0089] A lower wiring layer M1 can be formed in the first dielectric film 120. The lower wiring layer M1 can include first, second, third, and fourth lower wiring patterns 161, 162, 163a, 163b, and 164 extending in the first direction D1, and vias V0 connected to the first, second, third, and fourth lower wiring patterns 161, 162, 163a, 163b, and 164, respectively.

[0090] Each of the first and second lower wiring patterns 161 and 162 can be connected to gate electrodes GE of the first and second gate lines GL1 and GL2 by the via V0 and a gate contact structure CB (see Figure 8A ). Each of the first and second lower wiring patterns 161 and 162 can be an input wiring pattern connected to each of the gate electrodes GE. In an example embodiment, the first and second lower wiring patterns 161 and 162 can include dielectric separation patterns CT1 and CT2 separating the two lower wiring patterns in the first direction D1.

[0091] The third lower wiring patterns 163a and 163b can be connected to the source / drain regions SD of the first active pattern FN1 through the lower via V0 and the first contact structure CA1, while the fourth lower wiring pattern 164 can be connected to the source / drain regions SD of the second active pattern FN2 through the lower via V0 and the second contact structure CA2 (see Figure 8B and Figure 8C ). Each of the third lower wiring patterns 163a, 163b and the fourth lower wiring pattern 164 can be an output wiring pattern connected to each of the source / drain regions SD. In an example embodiment, the third lower wiring pattern can include two lower wiring patterns 163a and 163b placed between the first lower wiring pattern 161 and the second lower wiring pattern 162. If necessary, other lower wiring patterns 161, 162 and 164 can also be provided as a plurality of lower wiring patterns.

[0092] As shown in Figure 7 , in the first lower wiring pattern 161 and the second lower wiring pattern 162 connected to the gate electrode GE, the pin regions AP and DP can be provided as a plurality of pin regions, and the plurality of pin regions can be connected to the upper wiring layer. The pin regions AP and DP can preliminarily define pins to be used through a cell library. A single pin region of the two pin regions overlapping in the second direction D2 can be preliminarily defined, and a position for connection with the upper wiring layer can be provided in the preliminarily designated pin region AP. As a result, the remaining pin regions can be unusable pin regions DP not used as via positions. In Figure 7 , some pin regions are designated, and the designated pin regions are indicated by the preliminarily designated pin region AP. However, if the upper wiring patterns (171 and 172 of Figure 9 ) to be connected to the first lower wiring pattern 161 and the second lower wiring pattern 162 satisfy the condition that the upper wiring pattern is connected to only a single pin region among a plurality of pin regions overlapping in the second direction D2, other pin regions can be selected as the preliminarily designated pin region AP.

[0093] The wiring design of the upper wiring layer (M2 of Figure 9 ) using the above-described preliminary designation method can be advantageously applied to a complex standard cell. For example, to an embodiment in which the first lower wiring pattern 161, the second lower wiring pattern 162, the third lower wiring pattern 163a, 163b and the fourth lower wiring pattern 164 are densely arranged. For example, the pitch P of the first lower wiring pattern 161, the second lower wiring pattern 162, the third lower wiring pattern 163a, 163b and the fourth lower wiring pattern 164 can be equal to or less than 30 nm. In some embodiments, the distance between the first lower wiring pattern 161 and the second lower wiring pattern 162 can be equal to or less than 100 nm.

[0094] Referring toFigures 8A-8C The first dielectric film 120 can include a first insulating film 121 and a second insulating film 122. For example, the lower wiring layer M1 can be formed in the first dielectric film 120 by a dual damascene process.

[0095] The lower wiring layer M1 can include a conductive material CN and a barrier film BL disposed between the conductive material CN and the first dielectric film 120. The barrier film BL can be directly on sidewalls and a bottom surface of the conductive material CN other than an upper surface of the conductive material CN and at least partially cover the sidewalls and the bottom surface of the conductive material CN other than the upper surface of the conductive material CN. For example, the conductive material CN can include one or more materials including, but not limited to, conductive metal nitride and / or metal. The barrier film BL can include a metal nitride, for example, TiN. The upper surface of the conductive material CN can be coplanar with an upper surface of the first dielectric film 120.

[0096] Figure 9 is a layout of a semiconductor device according to some example embodiments of the present inventive concepts, while Figures 10A-10C is a cross-sectional view taken along Figure 9 lines A-A', B-B', and C-C' of the semiconductor device of Figure 9 is a layout of an upper wiring layer M2 according to some example embodiments, while Figures 10A-10C is a structure of the upper wiring layer M2 formed in a process performed according to the layout.

[0097] Referring to Figures 10A-10C and Figure 9 A second dielectric film 130 can be formed on the first dielectric film 120. For example, the second dielectric film 130 can include a silicon oxide film and / or a silicon oxynitride film in a similar manner as the first dielectric film 120.

[0098] An upper wiring layer M2 connected to the lower wiring layer M1 can be formed in the second dielectric film 130. The upper wiring layer M2 can include first, second, third, and fourth upper wiring patterns 171, 172, 173, and 174 extending in the second direction D2 and upper vias V1 connected to the first, second, third, and fourth upper wiring patterns 171, 172, 173, and 174.

[0099] The first and second upper wiring patterns 171 and 172 can be designed to pass through a single pre-specified pin region AP of a plurality of pin regions overlapping in the second direction D2 and can be connected to the first and second lower wiring patterns 161 and 162, respectively, through the upper vias V1.

[0100] The first upper wiring pattern 171 can pass through a first upper via V1a (see Figure 10A andFigure 10B ) respectively to the pre-designated pin regions (APa of FIG. 8) of the first lower wiring patterns 161. In a similar manner, the second upper wiring patterns 172 can be connected to the pre-designated pin regions (APb of FIG. 8) of the second lower wiring patterns 162 respectively through the second upper vias V1b.

[0101] As described above, the first upper wiring patterns 171 and the second upper wiring patterns 172 can form an input wiring structure connected to the gate electrode GE and the first lower wiring patterns 161 and the second lower wiring patterns 162. The design of the upper wiring layer M2 for forming the input wiring structure can be performed using the pre-designated pin regions APa and APb.

[0102] The third upper wiring patterns 173 can be connected to the third lower wiring patterns 163b and the fourth lower wiring patterns 164 through the third upper vias V1c. The third upper wiring patterns 173 can form an output wiring structure connected to the source / drain regions SD and the third lower wiring patterns 163b and the fourth lower wiring patterns 164.

[0103] The fourth upper wiring patterns 174 can not be connected to the first lower wiring patterns 161 and the second lower wiring patterns 162. The fourth upper wiring patterns 174 can extend through the standard cells of Figure 9 In some embodiments, all of the fourth upper wiring patterns 174 can not be connected to the third lower wiring patterns 163a, 163b and the fourth lower wiring patterns 164.

[0104] In the example embodiments, in the first lower wiring patterns 161 and the second lower wiring patterns 162 connected to the gate electrode GE, the pin regions can be connected to the upper wiring layer M2 and can be provided as a plurality of pin regions. However, the pin regions to be used can be pre-defined using the cell library, and thus the wiring design of the upper wiring layer can be simplified. Referring to Figure 9 and Figure 7 , one pin region APa and one pin region APb are pre-defined respectively among two pin regions APa and DPb and two pin regions APb and DPa overlapped in one direction (e.g., the second direction D2), and the positions of the first upper via V1a and the second upper via V1b for connection with the upper wiring layer M2 can be selected in the pre-designated pin regions APa and APb.

[0105] The second dielectric film 130 can include a first insulating film 131 and a second insulating film 132 in a similar manner to the first dielectric film 120. For example, the upper wiring layer M2 can be formed in the second dielectric film 130 through a dual damascene process in a similar manner to the lower wiring layer M1. The upper wiring layer M2 can include a conductive material CN and a barrier film BL placed between the conductive material CN and the first dielectric film 120.

[0106] In the example embodiment, the layout of the upper wiring layer M2 is described as a single layer, but its layout can be set as a plurality of wiring layers. The plurality of wiring layers can be sequentially stacked on the upper wiring layer M2 in the same or similar process as the forming process of the lower wiring layer M1 and the upper wiring layer M2.

[0107] The wiring design method of the semiconductor device according to some example embodiments can be advantageously applied to various types of semiconductor devices. For example, it can also be advantageously applied to semiconductor devices including transistors equipped with nanosheets (for example, ) and / or different types of three-dimensional semiconductor devices. Figure 11 is a cross-sectional view showing a semiconductor device provided with a transistor equipped with nanosheets according to some embodiments of the inventive concept.

[0108] Referring to Figure 11 , the semiconductor device according to some example embodiments can include a transistor provided with nanosheets (for example, ). The active pattern FN of the semiconductor device can be understood to be similar to that of the semiconductor device shown in Figures 10A-10C , except that it is implemented as a multi-channel structure using nanosheets. In addition, unless specifically stated otherwise, the description of the components of the example embodiment semiconductor device including nanosheets can be understood with reference to the description of components identical or similar to those of the semiconductor device shown in Figure 10A and Figure 10C .

[0109] As shown in Figure 11 , the semiconductor device can include a plurality of channel layers CH having a nanosheet structure and spaced apart from each other in a direction D3 perpendicular to the upper surface of the substrate 100, and a gate electrode GE extending in a second direction (D2) intersecting the first direction D1 while being adjacent to the plurality of channel layers CH. As described above, the gate electrode GE used in the example embodiment can be formed not only to be interposed between the gate insulating films GI but also to be interposed between the plurality of channel layers CH.

[0110] The semiconductor device can include a source / drain region SD provided in the active pattern FN on each of the two sides of the gate electrode GE and connected to the plurality of channel layers CH. In the example embodiment, the source / drain region SD is provided in the active pattern FN on each of the two sides of the gate electrode GE and can be connected to each of the two sides of the plurality of channel layers CH in the first direction D1.

[0111] In the example embodiment, three channel layers CH are described by way of example, but the number of channel layers is not particularly limited. The channel layers CH can be formed of a semiconductor pattern. For example, the semiconductor pattern can include one or more materials including, but not limited to, silicon (Si), silicon germanium (SiGe), and / or germanium (Ge). The source / drain regions SD can include epitaxial layers formed using the plurality of channel layers CH and the active region as a seed. For example, the source / drain regions SD can include one or more materials including, but not limited to, silicon germanium (SiGe), silicon (Si), and / or silicon carbide (SiC).

[0112] An internal spacer IS can be provided between each of the source / drain regions SD and the gate electrode GE. The internal spacer IS can be provided on one side of the gate electrode GE. The internal spacer IS and the channel layer CH can be alternately disposed in a direction perpendicular to the upper surface of the substrate 100. Each of the source / drain regions SD can be in physical contact with the channel layer CH, and can be spaced apart from the gate electrode GE with the internal spacer IS interposed between the source / drain region SD and the gate electrode GE. The gate insulating film GI is interposed between the gate electrode GE and each of the channel layers CH, and can extend between the gate electrode GE and each of the internal spacers IS.

[0113] In the semiconductor device according to the example embodiment, in a similar manner to the above-described example embodiment (see Figure 7 and Figure 9 ), the first lower wiring pattern 161 and the second lower wiring pattern 162 are connected to the gate electrode GE, and a pin to be used is previously defined among a plurality of available pin regions in the first lower wiring pattern 161 and the second lower wiring pattern 162 using a unit library. In detail, referring to Figure 7 and Figure 9 , one pin region APa and one pin region APb are respectively previously defined among two pin regions APa and DPb and two pin regions APb and DPa overlapping in one direction (for example, the second direction D2), and positions of the first upper via V1a and the second upper via V1b for connection with the upper wiring layer M2 can be selected in the previously designated pin regions APa and APb. Thus, in a complex standard cell, the wiring design of the upper wiring layer M2 can be more efficiently performed.

[0114] As set forth above, according to the example embodiment of the inventive concept, in order to perform the design of the wiring layer complicated due to the integration of the semiconductor device with improved efficiency, the position of the signal input via can be previously set in the wiring unit library, that is, the position of the upper via connected to the gate electrode can be previously set in the lower wiring pattern. Thus, not only the running time of the wiring process can be reduced, but also the area of the block level can be reduced.

[0115] While the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the present disclosure as defined in the appended claims.

Claims

1. A semiconductor device, comprising: The device layer includes a first active pattern and a second active pattern, and a plurality of gate electrodes. The first active pattern and the second active pattern extend on the substrate in a first direction and are adjacent to each other. The plurality of gate electrodes extend on the substrate in a second direction intersecting the first direction and intersecting the first active pattern and the second active pattern. A lower wiring layer, located on the device layer, includes a first lower wiring pattern and a second lower wiring pattern, the first lower wiring pattern and the second lower wiring pattern extending in the first direction, located on the first active pattern and the second active pattern respectively, and connected to the plurality of gate electrodes; An additional underwire pattern extends on the substrate in the first direction and is spaced apart from the first underwire pattern and the second underwire pattern in the second direction; as well as An upper wiring layer, located on the lower wiring layer, has a first upper via and a second upper via located on the first lower wiring pattern and the second lower wiring pattern, respectively, and a first upper wiring pattern and a second upper wiring pattern extending in the second direction. The first upper wiring pattern is connected to the first upper via, but not to the second upper via. The second upper wiring pattern is connected to the second upper via, but not to the first upper via. The device layer further includes source / drain regions located on either side of each of the plurality of gate electrodes in the first active pattern and the second active pattern. The additional lower wiring patterns include a third lower wiring pattern connected to the source / drain regions of the first active pattern and a fourth lower wiring pattern connected to the source / drain regions of the second active pattern. The first, second, third, and fourth lower wiring patterns are arranged in the second direction with a pitch of 30 nm or less.

2. The semiconductor device according to claim 1, wherein, The lower wiring layer further includes a first lower via and a second lower via, wherein the first lower via connects a first portion of the plurality of gate electrodes to the first lower wiring pattern, and the second lower via connects a second portion of the plurality of gate electrodes to the second lower wiring pattern.

3. The semiconductor device according to claim 1, further comprising: The third upper wiring pattern is connected to the third lower wiring pattern and the fourth lower wiring pattern. The upper wiring layer further includes a third upper via and a fourth upper via that connect the third upper wiring pattern to the third lower wiring pattern and the fourth lower wiring pattern, respectively.

4. The semiconductor device according to claim 1, further comprising: The fourth upper wiring pattern is not connected to the first lower wiring pattern and the second lower wiring pattern.

5. The semiconductor device according to claim 1, wherein, At least one of the first upper wiring pattern and the second upper wiring pattern extends to intersect with all of the first lower wiring patterns and the second lower wiring patterns.

6. The semiconductor device according to claim 1, wherein, At least one of the first lower wiring pattern and the second lower wiring pattern includes a dielectric separation pattern, the dielectric separation pattern being configured to divide the at least one of the first lower wiring pattern and the second lower wiring pattern into two lower wiring patterns in the first direction.

7. A semiconductor device, comprising: Multiple units located on the substrate, At least one of the plurality of units includes: A first active pattern and a second active pattern having different conductivity types and extending in a first direction; Multiple gate electrodes intersect with the first active pattern and the second active pattern, and extend in a second direction intersecting the first direction; A first lower wiring pattern and a second lower wiring pattern are located on the plurality of gate electrodes and are configured to apply an electrical signal to the plurality of gate electrodes. A first upper via and a second upper via, the first upper via and the second upper via being located on the first lower wiring pattern and the second lower wiring pattern and respectively connected to the first lower wiring pattern and the second lower wiring pattern; and Multiple upper wiring patterns are located on the first lower wiring pattern and the second lower wiring pattern. The plurality of upper wiring patterns include an input wiring pattern, which is connected to the first upper via and the second upper via, but not to the second upper via. The plurality of gate electrodes includes at least two first gate electrodes and at least two second gate electrodes, and Wherein, the first lower wiring pattern is connected to the first gate electrode and the second gate electrode of the first pair, and the second lower wiring pattern is connected to the first gate electrode and the second gate electrode of the second pair. The first lower wiring pattern and the second lower wiring pattern are arranged in the second direction with a pitch of 30 nm or less.

8. The semiconductor device according to claim 7, further comprising: The first source / drain region and the second source / drain region are located on either side of each of the plurality of gate electrodes in the first active pattern and the second active pattern.

9. The semiconductor device according to claim 8, further comprising: The third and fourth lower wiring patterns are configured to output electrical signals from the first source / drain region and the second source / drain region.

10. The semiconductor device according to claim 9, wherein, The plurality of upper wiring patterns include: an output wiring pattern that is connected to each of the third lower wiring pattern and the fourth lower wiring pattern.

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