Semiconductor device and method of manufacturing the same

Abstract

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor device can include an active pattern, a silicon liner, an insulating layer, an isolation pattern, and a transistor. The active pattern can protrude from a substrate. The silicon liner having a crystal structure can be conformally formed on a surface of the active pattern and the substrate. The insulating layer can be formed on the silicon liner. The isolation pattern can be formed on the insulating layer to fill a trench adjacent to the active pattern. The transistor can include a gate structure and an impurity region. The gate structure can be disposed on the silicon liner, and the impurity region can be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

Description

Technical Field

[0001] The example embodiments relate to semiconductor devices and methods of manufacturing them. More specifically, the example embodiments relate to semiconductor devices including active patterns and methods of manufacturing them. Background Technology

[0002] Recently, as semiconductor devices have become highly integrated, reducing the area of ​​the upper surface of each active pattern can be beneficial. Furthermore, the distance between active patterns can be reduced. Each active pattern should be virtually defect-free or defect-free and have sufficient area for forming transistors and contact plugs. Summary of the Invention

[0003] The example implementation provides a method for manufacturing a semiconductor device with excellent properties.

[0004] An example implementation provides a semiconductor device.

[0005] According to an example embodiment, a semiconductor device is provided, which may include an active pattern, a silicon pad, an insulating layer, an isolation pattern, and a transistor. The active pattern may protrude from a substrate. The silicon pad, having a crystal structure, may conformally lie on the surface of the active pattern and the surface of the substrate. The insulating layer may be formed on the silicon pad. The isolation pattern may be formed on the insulating layer to fill trenches adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be on the silicon pad, and the impurity regions may be located on the silicon pads adjacent to both sides of the gate structure and on the active pattern adjacent to both sides of the gate structure.

[0006] According to an example embodiment, a semiconductor device is provided, which may include an active pattern, a silicon pad, an isolation pattern, a transistor, a first insulating interlayer, a first contact plug and a second contact plug, a bit line, and a capacitor. The active pattern may protrude from a substrate. A silicon pad having a crystal structure may be formed on the active pattern and the substrate. The silicon pad may cover the surface of the active pattern and the surface of the substrate. The isolation pattern may fill trenches adjacent to the active pattern on the silicon pad. The transistor may include a gate structure and a first impurity region and a second impurity region. The gate structure may be on the silicon pad, with the first impurity region located on the silicon pad adjacent to a first side of the gate structure and on the active pattern adjacent to the first side of the gate structure, and the second impurity region located on the silicon pad adjacent to a second side of the gate structure and on the active pattern adjacent to the second side of the gate structure. The first insulating interlayer may cover the silicon pad, the isolation pattern, and the gate structure. The first contact plug and the second contact plug may pass through the first insulating interlayer to contact the first impurity region and the second impurity region, respectively. The bit line may be electrically connected to the first contact plug. The capacitor may be electrically connected to the second contact plug.

[0007] According to an example embodiment, a semiconductor device is provided that may include an active pattern, a silicon pad, an insulating layer, a stop layer pattern, an isolation pattern, and a transistor. The active pattern may protrude from a substrate. The silicon pad, having a crystal structure, may conformally lie on the surface of the active pattern and the surface of the substrate. The insulating layer may be on the silicon pad. The stop layer pattern may be on the insulating layer. The stop layer pattern may be in a trench adjacent to the active pattern. An isolation pattern may be formed on the stop layer pattern to fill the trench. The transistor may include a gate structure and a sludge region. The gate structure may be on the silicon pad, and the sludge region may be located on the silicon pad adjacent to both sides of the gate structure and on the active pattern adjacent to both sides of the gate structure.

[0008] According to an example embodiment, a method for manufacturing a semiconductor device is provided. In this method, a portion of a substrate may be etched to form an active pattern protruding from the substrate. A first silicon pad having a crystal structure may be conformally formed on the surface of the active pattern and the surface of the substrate. The surface of the first silicon pad may be oxidized to form a second silicon pad and an insulating layer on the second silicon pad. The second silicon pad may have a thickness less than that of the first silicon pad. An isolation layer may be formed on the insulating layer to fill trenches adjacent to the active pattern. A transistor including a gate structure and impurity regions may be formed. The gate structure may be disposed on the second silicon pad, and impurity regions may be formed at the second silicon pads adjacent to both sides of the gate structure and at the active patterns adjacent to both sides of the gate structure.

[0009] As described above, according to the exemplary embodiment, the active structure may include a first active pattern formed by etching a substrate and a pad layer having a crystal structure. Furthermore, an insulating layer may be formed on the pad layer having a crystal structure. The pad layer having a crystal structure can have excellent surface roughness and may be free of defects. Therefore, the semiconductor device formed on the active structure can have high performance. Moreover, since the area of ​​the upper surface of the first active pattern is not reduced, transistors and contact plugs can be easily formed on the active structure. Attached Figure Description

[0010] The exemplary embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 37 This refers to a non-limiting example implementation as described herein.

[0011] Figures 1 to 10 and Figures 12 to 24 These are cross-sectional views, top views, and perspective views of a vertical semiconductor device according to an example embodiment;

[0012] Figure 11 It is a device used to manufacture semiconductor devices;

[0013] Figures 25 to 27These are top and perspective views illustrating stages of a method for manufacturing a semiconductor device according to an exemplary embodiment;

[0014] Figures 28 to 30 These are top and perspective views illustrating stages of a method for manufacturing a semiconductor device according to an exemplary embodiment;

[0015] Figures 31 to 35 This is a cross-sectional view illustrating stages of a method for manufacturing a semiconductor device according to an exemplary embodiment; and

[0016] Figure 36 and Figure 37 This is a cross-sectional view showing the stages of a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0017] The exemplary embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0018] In the following text, two directions that are substantially parallel to the upper surface of the substrate and intersect each other are defined as the first direction and the second direction, respectively. The first direction and the second direction are substantially perpendicular to each other. The direction of inclination relative to the first direction is defined as the third direction, and the direction perpendicular to the third direction is defined as the fourth direction. The third direction and the fourth direction are substantially parallel to the upper surface of the substrate.

[0019] Figures 1 to 10 and Figures 12 to 24 These are cross-sectional views, top views, and perspective views of a vertical semiconductor device according to an example embodiment. Figure 11 It is a device used to manufacture semiconductor devices.

[0020] Specifically, Figure 1 , Figure 7 , Figure 12 and Figure 23 It is a top view. Figures 2 to 5 , Figures 8 to 9 , Figure 13 , Figure 14 , Figures 16 to 19 , Figure 21 , Figure 22 and Figure 24 It is a sectional view, and Figure 6 , Figure 10 , Figure 15 and Figure 20 It is a perspective view. Figure 2 , Figure 4 , Figure 8 , Figure 13 , Figure 16 and Figure 18 It is along Figure 1 A sectional view taken from line I-I'. Figure 3 , Figure 5, Figure 9 , Figure 14 , Figure 17 , Figure 19 , Figure 21 and Figure 24 It is along Figure 1 The sectional view taken from line II-II'. Figure 22 It is along Figure 1 A sectional view taken from line III-III'. Each perspective view shows only the layer formed on the sidewall of one of the active patterns.

[0021] Semiconductor devices may include dynamic random access memory (DRAM) devices.

[0022] Reference Figures 1 to 3 The substrate 100 may include a single-crystal semiconductor material. The substrate 100 may include semiconductor materials such as silicon, germanium, or silicon-germanium. In an example embodiment, the substrate 100 may be single-crystal silicon.

[0023] A hard mask pattern (not shown) may be formed on substrate 100. The hard mask pattern can be used as an etching mask to etch substrate 100 to form a first active pattern 102 and trenches 104. The first active pattern 102 may protrude from substrate 100, and trenches 104 may be formed between the first active patterns 102. In an example embodiment, the first active pattern 102 may be used as an active region for forming a DRAM device. The hard mask pattern may then be removed.

[0024] In the following text, substrate 100 and first active pattern 102 are described as different elements. However, the first active pattern 102 can be formed by etching substrate 100 such that the first active pattern 102 and substrate 100 can include the same semiconductor material. Moreover, the first active pattern 102 and substrate 100 can be the same single entity.

[0025] The first active patterns 102 can be isolated from each other, and the first active patterns 102 can be arranged regularly. The sidewalls of the trench 104 can correspond to the sidewalls of the first active patterns 102, and the bottom of the trench 104 can correspond to the surface of the substrate 100.

[0026] In the example implementation, the first active pattern 102 may extend in a third direction. That is, the length of the first active pattern 102 in the third direction may be greater than the length of the first active pattern 102 in the fourth direction. Therefore, in the first active pattern 102, the third direction may be the major axis direction, and the fourth direction may be the minor axis direction.

[0027] When this process is performed, the surfaces of the substrate 100 and the first active pattern 102 can be exposed. In this case, at least a portion of the surfaces of the substrate 100 and the first active pattern 102 can be irregularly oxidized. That is, a native oxide layer 106 can be formed on the surfaces of the substrate 100 and the first active pattern 102. The native oxide layer 106 can be discontinuous and irregular, or it can appear as islands of oxide material.

[0028] Reference Figures 4 to 6 The natural oxide layer 106 formed on the substrate 100 and the first active pattern 102 can be removed. The removal process of the natural oxide layer 106 can include a dry etching process or a wet etching process.

[0029] In an exemplary embodiment, to remove the native oxide layer 106, a first process can be performed to introduce an etching source gas onto the surface of the substrate 100 and the surface of the first active pattern 102. Therefore, at least one of the etching source gases can contact the surface of the substrate 100 and the surface of the first active pattern 102. In an exemplary embodiment, the etching source gas may include Ar, NH3, and / or NF3.

[0030] Subsequently, a second process can be performed to apply heat and pressure to the substrate 100 and the first active pattern 102. The native oxide layer 106 can be removed by the first and second processes.

[0031] In the example implementation, the first process of introducing the etching source gas and the second process of applying heat and pressure can be performed in different etching chambers. That is, the first process can be performed in the first etching chamber, and the second process can be performed in the second etching chamber. The first and second processes can be performed in situ without vacuum braking.

[0032] The first process can be performed at room temperature. For example, the first process can be performed at a temperature ranging from about 5°C to about 30°C. Moreover, the first process can be performed at a pressure ranging from about 0.5 Torr to about 10 Torr.

[0033] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical values ​​include manufacturing or operational tolerances (e.g., ±10%) around said values. Similarly, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended that the geometry is not required to be precise, but rather that the latitude of the shape is within the scope of this disclosure. Furthermore, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said values ​​or shapes.

[0034] The second process can be performed at a temperature ranging from about 100°C to about 200°C, and at a pressure ranging from about 1 Torr to about 20 Torr.

[0035] Reference Figures 7 to 10 A semiconductor pad with a crystal structure can be formed on a substrate 100 without a natural oxide layer and a first active pattern 102.

[0036] In an example implementation, the semiconductor pad may be a crystalline silicon pad. Hereinafter, the semiconductor pad will be referred to as the first silicon pad 110.

[0037] The first silicon pad 110 can be formed by crystal growth (e.g., deposition process) from the surface of the substrate 100 and the surface of the first active pattern 102. Therefore, the first silicon pad 110 can have a crystal structure that is substantially the same as the crystal structure of the substrate 100 and the crystal structure of the first active pattern 102.

[0038] The first silicon pad 110 can cover the entire surface of the first active pattern 102 and the entire surface of the substrate 100. That is, a barrier layer does not need to be formed on the substrate 100 and the first active pattern 102, so that the first silicon pad 110 can be formed by crystal growth from the entire surface of the substrate 100 and the entire surface of the first active pattern 102. In other words, the first silicon pad can directly contact the substrate 100 and the first active pattern 102.

[0039] The first silicon pad 110 may not be formed as amorphous, but can be formed as a crystalline structure during the deposition process. Therefore, a crystallization process can be omitted in subsequent processes. Thus, an amorphous silicon layer with partially and / or unevenly crystalline surfaces can be avoided during the crystallization process, thereby reducing undesirable surface roughness of the silicon pad.

[0040] In addition, the surface of the first silicon pad 110 can be uniformly oxidized in subsequent processes.

[0041] If the native oxide layer 106 is on the surface of the substrate 100 and the surface of the first active pattern 102 during the formation of the first silicon pad 110, the first silicon pad 110 may include crystal defects formed by the deposition process of the first silicon pad 110. Therefore, when the first silicon pad 110 is formed, the native oxide layer 106 may not be on the surface of the substrate 100 and the surface of the first active pattern 102. That is, the deposition process of the first silicon pad 110 and the removal of the native oxide layer 106 can be performed in situ, and the process can be performed without vacuum braking.

[0042] In order to form the first silicon pad 110 with a crystalline structure, a deposition process can be performed at high temperature and high pressure, and the conditions of the deposition process can be adjusted to increase the partial pressure of the silicon source gas.

[0043] Specifically, the process for forming the first silicon pad 110 can be performed at a pressure ranging from about 50 Torr to about 500 Torr. The process temperature can be ranging from about 400°C to about 800°C. The silicon source gas can be, for example, silane, dichlorosilane, dichlorosilane (DCS), etc. The silicon source gas can be introduced at a flow rate of about 30 standard cubic centimeters per minute (sccm) to about 150 sccm.

[0044] The silicon source gas may not contain carbon. Furthermore, the process for forming a carbon-containing silicon seed layer can be omitted in the deposition process. Therefore, the first silicon pad 110 may not contain carbon. As a result, defects caused by carbon contained in the first silicon pad can be reduced.

[0045] To meet the temperature and pressure conditions, the volume used to form the first silicon pad 110 in the deposition chamber can be about 20 L or less. For example, the volume can be from about 5 L to about 20 L. In the deposition process, nitrogen gas can be introduced into the deposition chamber at a flow rate of about 100 sccm or greater. For example, nitrogen gas can be introduced at a flow rate of from about 100 sccm to about 10,000 sccm.

[0046] As described above, a first silicon pad 110 without crystal defects can be formed, and the first silicon pad 110 can have a crystal structure that is substantially the same as the crystal structure of the substrate 100 and the crystal structure of the first active pattern 102.

[0047] In an example embodiment, a first silicon pad 110 can be uniformly grown on the surface of the first active pattern 102 and the surface of the substrate 100. Therefore, the first silicon pad 110 can be conformally formed on the sidewalls and top surface of the first active pattern 102 and the surface of the substrate 100 to have a uniform thickness.

[0048] The first silicon pad 110 may have a thickness such that the surface of the first active pattern 102 is not oxidized during the formation of the first insulating layer. The first silicon pad 110 may be formed to not completely fill the trench 104. Therefore, the first silicon pad 110 may be formed to have a thickness less than half the minimum width of the trench 104. In an example embodiment, the first silicon pad 110 may be formed to have a thickness of approximately... to approximately The thickness is within the range.

[0049] Figure 11 This is an example of an apparatus for etching a natural oxide layer and depositing a first silicon pad.

[0050] Reference Figure 11 The apparatus may include a first etching chamber 20a and a second etching chamber 20b for an etching process, and a deposition chamber 22 for a deposition process. Each of the first etching chamber 20a, the second etching chamber 20b, and the deposition chamber 22 may be connected to a transfer chamber 16. The transfer chamber 16 may include a transfer member 18 for transferring the substrate 100.

[0051] While maintaining a vacuum through the transfer chamber 16, the substrate 100 can be sequentially or selectively transferred to the first etching chamber 20a, the second etching chamber 20b, and the deposition chamber 22. The transfer chamber 16 can be connected to a loadlock chamber 14. The loadlock chamber 14 can be connected to a transfer port 12 and a loading port 10, which includes a cassette or front-opening wafer transfer cassette for receiving the substrate 100.

[0052] The etching process of the natural oxide layer and the deposition process of the first silicon pad using this device can be briefly described below.

[0053] First, in order to perform the reference Figures 4 to 6 The etching process shown involves loading a substrate into a first etching chamber 20a and introducing an etching source gas into the first etching chamber 20a. The substrate is then transferred to a second etching chamber 20b via a transfer chamber 16. The native oxide layer formed on the substrate and the first active pattern can be removed by controlling the temperature and pressure in the second etching chamber 20b.

[0054] Subsequently, in order to implement the reference Figures 7 to 10 The deposition process shown allows a substrate to be loaded onto a chuck in a deposition chamber 22 via a transfer chamber 16. A first silicon pad can then be formed in the deposition chamber 22.

[0055] As described above, a vacuum can be maintained during the etching and deposition processes, preventing the surface of the first active pattern 102 from being oxidized during the movement of the substrate between chambers. Therefore, defects such as crystal defects or particle adsorption caused by the natural oxide layer on the surface of the first active pattern 102 can be reduced.

[0056] Reference Figures 12 to 15 A first insulating layer 112 can be formed on the first silicon pad 110 by a deposition process. The first insulating layer 112 may include silicon oxide. The deposition process may include chemical vapor deposition or atomic layer deposition.

[0057] When the first insulating layer 112 is formed, the surface of the first silicon pad 110 can be oxidized by heat and an oxygen source. Through oxidation, the first silicon pad 110 can be transformed into a second silicon pad 110a having a thickness smaller than that of the first silicon pad 110.

[0058] That is, when the deposition process is performed, the first insulating layer 112 can be conformally formed on the second silicon pad 110a. In this case, the first insulating layer 112 may include an oxide layer formed by oxidizing the surface of the first silicon pad 110 and an oxide layer formed by the deposition process.

[0059] The first silicon pad 110 may have a crystalline structure, and the natural oxide layer may not be present on the surface of the first silicon pad 110. Therefore, the surface of the first silicon pad 110 can be uniformly oxidized, resulting in the second silicon pad 110a having excellent roughness after oxidation. Furthermore, crystal defects caused by irregular oxidation of the second silicon pad 110a are almost non-existent.

[0060] The first silicon pad 110 can be used as a layer to prevent oxidation of the first active pattern 102 in subsequent processes. When the first insulating layer 112 is formed, the first active pattern 102 may not be oxidized. The first active pattern 102 may not be consumed by oxidation, thus the area of ​​the upper surface of the first active pattern 102 may not be reduced.

[0061] In an example implementation, the thickness of the first insulating layer 112 may be greater than the thickness of the second silicon pad 110a.

[0062] The second silicon pad 110a may cover the entire surface of the first active pattern 102 and the entire surface of the substrate 100. In an example embodiment, the second silicon pad 110a may have a uniform thickness from the surface of the first active pattern 102 and the surface of the substrate 100.

[0063] In some example embodiments, the first silicon pad 110 can be completely oxidized when the first insulating layer 112 is formed. In this case, all the first silicon pads 110 can be consumed, so that the first insulating layer 112 can be formed on the first active pattern 102.

[0064] Reference Figure 16 and Figure 17 A stop layer 114 can be conformally formed on the first insulating layer 112. Subsequently, an isolation layer 116 can be formed on the stop layer 114 to completely fill the trench 104.

[0065] In an example implementation, stop layer 114 may comprise silicon nitride and / or silicon oxide nitride. Isolation layer 116 may comprise silicon oxide.

[0066] The process for forming the stop layer 114 and the isolation layer 116 may include a chemical vapor deposition process or an atomic layer deposition process.

[0067] In some example implementations, the stop layer 114 may not be formed. In this case, only the insulating layer 116 may be formed on the first insulating layer 112. Alternatively, the first insulating layer 112 and the insulating layer 116 may be formed using the same deposition process.

[0068] Reference Figure 18 and Figure 19 The upper surface of the isolation layer 116 can be planarized until the upper surface of the stop layer 114 can be exposed to form the isolation pattern 116a. The isolation pattern 116a can fill the trench 104. The planarization process can be performed by a chemical mechanical polishing (CMP) process and / or an etch-back process. Thereafter, the exposed portion of the stop layer 114 can be etched to form the stop layer pattern 114a.

[0069] Therefore, the second silicon pad 110a, the first insulating layer 112, the stop layer pattern 114a, and the isolation pattern 116a can be formed in the trench 104. Moreover, the second silicon pad 110a and the first insulating layer 112 can be formed on the upper surface of the first active pattern 102.

[0070] The first active pattern 102 and the second silicon pad 110a can be used as active regions. The first insulating layer 112, the stop layer pattern 114a, and the isolation pattern 116a formed in the trench 104 can be used as field regions. In the process for forming the field regions, the area of ​​the upper surface of the first active pattern 102 and the volume of the first active pattern 102 can be maintained, so that the active regions can have sufficient area.

[0071] Reference Figure 20 The first active pattern 102, the second silicon pad 110a, the first insulating layer 112, the stop layer pattern 114a, and the isolation pattern 116a can be partially etched to form a gate trench 120 extending in the second direction.

[0072] The bottom of the gate trench 120 may be higher than the bottom of the isolation pattern 116a.

[0073] In an example embodiment, the bottom of the gate trench 120 located in the field region may be lower than the bottom of the gate trench 120 located in the active region. Therefore, portions of the first active pattern 102 and the isolation pattern 116a may be exposed on the bottom of the gate trench 120. The first active pattern 102 formed in the gate trench 120 may protrude from the isolation pattern 116a formed in the gate trench 120. Portions of the first active pattern 102 and the second silicon pad 110a may be exposed on the sidewalls of the gate trench 120 in the first direction.

[0074] Reference Figure 21 and Figure 22 A gate structure 130 is formed in the gate trench 120.

[0075] The gate structure 130 may include a gate insulating layer pattern 130a, a gate electrode 130b, and a capping layer pattern 130c.

[0076] A gate insulating layer pattern 130a may be conformally formed on the surface of a first active pattern 102 and a second silicon pad 110a in a gate trench 120. A gate electrode 130b may contact the gate insulating layer pattern 130a and may be formed in the gate trench 120. In an example embodiment, the gate electrode 130b may include metal. The gate electrode 130b may have a stacked structure including a barrier metal layer and metal layers. For example, the gate electrode 130b may include tungsten nitride or tungsten. In some example embodiments, the gate electrode 130b may include polysilicon.

[0077] A capping pattern 130c may be formed on the gate electrode 130b to fill the gate trench 120. The capping pattern 130c may include a nitride, such as a silicon nitride.

[0078] A first impurity region 132a and a second impurity region 132b serving as source / drain regions can be formed at the first active pattern 102 and the second silicon pad 110a adjacent to both sides of the gate structure 130. For example, the first impurity region 132a may have one side adjacent to the active pattern 102, one side adjacent to one side of the gate structure 130, and at least one side adjacent to the second silicon pad 110a. Furthermore, the second impurity region 132b may have one side adjacent to the active pattern 102, one side adjacent to the other side of the gate structure 130, and at least one side adjacent to the second silicon pad 110a.

[0079] Reference Figure 23 and Figure 24A first insulating interlayer 140 may be formed on the gate structure 130, the first active pattern 102, the second silicon pad 110a, the first insulating layer 112, the stop layer pattern 114a, and the isolation pattern 116a. The first insulating interlayer 140 may include oxides such as silicon oxide.

[0080] A first contact plug 142 may be formed through the first insulating interlayer 140, the first insulating layer 112, and the second silicon pad 110a. The first contact plug 142 may contact the first impurity region 132a. A bit line 144 may be formed on the first contact plug 142 and the first insulating interlayer 140. The bit line 144 may extend in a first direction.

[0081] Bit line 144 may be formed to contact the upper surface of the first contact plug 142. A hard mask pattern (not shown) may be formed on bit line 144. Spacers (not shown) may be formed on the sidewalls of bit line 144 and the sidewalls of the hard mask pattern.

[0082] A second insulating interlayer 146 covering bit line 144 may be formed on the first insulating interlayer 140.

[0083] The second contact plug 148 can be formed through the second insulating interlayer 146, the first insulating interlayer 140, the first insulating layer 112, and the second silicon pad 110a. The second contact plug 148 can contact the second impurity region 132b. The second contact plug 148 can be formed such that a short circuit fault between the second contact plug 148 and the bit line 144 can not occur.

[0084] As described above, oxidation of the surface of the first active pattern 102 can be almost completely avoided during the process. Therefore, the area of ​​the upper surface of the first active pattern 102 can be maintained. The first contact plug 142 and the second contact plug 148 can be formed on the first active pattern 102 with sufficient area margin. Furthermore, since the area of ​​the upper surface of the first active pattern 102 is sufficient, the resistance of the first contact plug 142 and the second contact plug 148 can be reduced.

[0085] The capacitor 150 may be configured to contact the second contact plug 148. The capacitor 150 may include a lower electrode 150a, a dielectric layer 150b, and an upper electrode 150c.

[0086] Semiconductor devices can have the following structural features. The structural features of a semiconductor device can be primarily described during the manufacturing process. Therefore, repeated descriptions can be omitted below, and only the important parts can be described with reference to the accompanying drawings.

[0087] Reference Figures 20 to 24A first active pattern 102 can be formed on the substrate 100. A trench 104 can be formed between the first active patterns 102.

[0088] A second silicon pad 110a covering the surface of the first active pattern 102 may be formed on the first active pattern 102. The second silicon pad 110a may be conformally formed on the surface of the first active pattern 102. The second silicon pad 110a may cover the entire surface of the first active pattern 102 and the entire surface of the substrate 100.

[0089] The second silicon pad 110a may include crystalline silicon.

[0090] A first insulating layer 112 may be formed on a second silicon pad 110a. The first insulating layer 112 may comprise silicon oxide. At least a portion of the first insulating layer 112 may be formed by oxidizing the surface of the first silicon pad 110.

[0091] In an example implementation, the thickness of the first insulating layer 112 may be greater than the thickness of the second silicon pad 110a.

[0092] Stop layer pattern 114a and isolation pattern 116a can be formed on the first insulating layer 112 to fill the trench 104.

[0093] The gate trench 120 may be formed at a portion of the first active pattern 102, the second silicon pad 110a, the first insulating layer 112, the stop layer pattern 114a, and the isolation pattern 116a, and the gate trench may extend in a first direction.

[0094] The gate structure 130 may be formed in the gate trench 120. The gate structure 130 may include a gate insulating layer pattern 130a, a gate electrode 130b, and a capping layer pattern 130c.

[0095] In an example implementation, the bottom of the gate trench 120 in the field region may be lower than the bottom of the gate trench 120 in the active region.

[0096] Therefore, the first active pattern 102 and the second silicon pad 110a can be exposed on both sides of the gate trench 120 in the first direction.

[0097] That is, the gate insulating layer pattern 130a can contact the first active pattern 102 and the second silicon pad 110a exposed by the gate trench 120. Since the surface roughness of the second silicon pad 110a is very good and the second silicon pad 110a has no crystal defects, crystal defects can be excluded from the gate insulating layer pattern 130a. Therefore, the leakage current of the transistor caused by the gate insulating layer pattern 130a can be reduced.

[0098] A first impurity region 132a and a second impurity region 132b, which serve as source / drain, can be formed on the first active pattern 102 and the second silicon pad 110a adjacent to both sides of the gate structure 130.

[0099] The first insulating interlayer 140 can be formed on the gate structure 130, the first active pattern 102, the second silicon pad 110a, the first insulating layer 112, the stop layer pattern 114a, and the isolation pattern 116a.

[0100] A first contact plug 142 may be formed through the first insulating interlayer 140, the first insulating layer 112, and the second silicon pad 110a. The first contact plug 142 may contact the first impurity region 132a. A bit line 144 may be formed on the first contact plug 142 and the first insulating interlayer 140.

[0101] A second insulating interlayer 146 covering bit line 144 may be formed on the first insulating interlayer 140.

[0102] The second contact plug 148 can be formed through the second insulating interlayer 146, the first insulating interlayer 140, the first insulating layer 112, and the second silicon pad 110a. The second contact plug 148 can contact the second impurity region 132b.

[0103] Capacitor 150 can contact the second contact plug 148.

[0104] Therefore, the first contact plug 142 and the second contact plug 148 can be formed on the first active pattern 102. The first active pattern 102 can have a sufficient area to form the first contact plug 142 and the second contact plug 148.

[0105] Furthermore, crystal defects included in the gate insulating layer pattern 130a can be reduced, thereby reducing the leakage current of the transistor caused by the gate insulating layer pattern 130a. Therefore, transistor reliability failures can be reduced.

[0106] Figures 25 to 27 These are top and perspective views illustrating stages of a method for manufacturing a semiconductor device according to an exemplary embodiment. Figure 25 It is a top view. Figure 26 and Figure 27 Only the layer formed on the sidewall of one of the active patterns is shown.

[0107] This method can be compared with the reference Figures 1 to 24 The methods for manufacturing semiconductor devices shown are essentially the same, except for the formation of the first silicon pad.

[0108] First, you can execute the reference. Figures 1 to 6The same process is shown. Therefore, the native oxide layer 106 formed on the surface of the substrate 100 and the surface of the first active pattern 102 (see reference) can be removed. Figure 3 ).

[0109] Reference Figure 25 and Figure 26 A first silicon pad 210 with a crystal structure can be formed on a substrate 100 without a natural oxide layer and a first active pattern 102.

[0110] The first silicon pad 210 can be formed by crystal growth from the surface of the substrate 100 and the surface of the first active pattern 102. In this case, the crystal growth rate can vary depending on the surface of the first active pattern 102.

[0111] In an example embodiment, during crystal growth of the first silicon pad 210, the growth rate at the sidewall surface of the first active pattern in the long axis direction (i.e., the third direction) can be different from the growth rate at the sidewall surface of the first active pattern in the short axis direction (i.e., the fourth direction). For example, the growth rate of the first silicon pad 210 at the sidewall of the first active pattern 102 in the third direction can be higher than the growth rate of the first silicon pad 210 at the sidewall of the first active pattern 102 in the fourth direction. Therefore, the first thickness d1 of the first silicon pad 210 on the sidewall of the first active pattern 102 in the third direction can be greater than the second thickness d2 of the first silicon pad 210 on the sidewall of the first active pattern 102 in the fourth direction.

[0112] The growth rate of the first silicon pad 210 can be varied by controlling the temperature and pressure during the deposition process of the first silicon pad 210. Additionally, the growth rate of the first silicon pad 210 can be varied by the process conditions used to remove the native oxide layer.

[0113] In the example implementation, the process for removing the native oxide layer can be compared with the reference process. Figures 4 to 6 The processes shown are essentially the same. That is, the first process can be performed at room temperature. For example, the first process can be performed at a temperature ranging from about 5°C to about 30°C. Furthermore, the first process can be performed at a pressure ranging from about 0.5 Torr to about 10 Torr. The second process can be performed at a temperature ranging from about 100°C to about 200°C. Furthermore, the second process can be performed at a pressure ranging from about 1 Torr to about 20 Torr. When the native oxide layer is removed by the process conditions, the deposition process can be performed at a temperature ranging from about 400°C to about 490°C and a pressure ranging from about 50 Torr to 150 Torr.

[0114] Reference Figure 27A first insulating layer 112 can be formed on the first silicon pad 210 by a deposition process. During the deposition process, the first silicon pad 210 can be oxidized to reduce its thickness. Therefore, the first silicon pad 210 can be transformed into a second silicon pad 210a. The first insulating layer 112 can be formed on the second silicon pad 210a.

[0115] In this configuration, the first silicon pad 210 is oxidized to a uniform thickness. Therefore, the thickness of the second silicon pad 210a formed on the sidewall of the first active pattern 102 in the long axis direction and the thickness of the second silicon pad 210a formed on the sidewall of the first active pattern 102 in the short axis direction can be different from each other. That is, the third thickness d3 of the second silicon pad 210a on the sidewall of the first active pattern 102 in the third direction can be greater than the fourth thickness d4 of the second silicon pad 210b on the sidewall of the first active pattern 102 in the fourth direction.

[0116] The thickness of the first insulating layer 112 can be greater than the thickness of the second silicon pad 210a.

[0117] After that, the reference can be executed. Figures 16 to 24 The same process is shown. Therefore, an active region with a sufficient area in the third direction can be formed.

[0118] Semiconductor devices can have the same characteristics as a reference. Figures 23 to 24 The structures of the semiconductor devices shown are substantially the same. However, in the second silicon pad 210a, the third thickness d3 of the second silicon pad 210a on the third-direction sidewall of the first active pattern 102 can be greater than the fourth thickness d4 of the second silicon pad 210a on the fourth-direction sidewall of the first active pattern 102. Therefore, the area of ​​the first active pattern 102 for forming the first contact plug 142 and the second contact plug 148 can be sufficiently ensured.

[0119] Figures 28 to 30 These are top and perspective views illustrating stages of a method for manufacturing a semiconductor device according to an exemplary embodiment. Figure 28 It is a top view. Figure 29 and Figure 30 Only the layer formed on the sidewall of one of the active patterns is shown.

[0120] This method can be compared with the reference Figures 1 to 24 The methods for manufacturing semiconductor devices shown are essentially the same, except for the formation of the first silicon pad.

[0121] First, you can execute the reference. Figures 1 to 6 The same process is shown. Therefore, the native oxide layer 106 formed on the surface of the substrate 100 and the surface of the first active pattern 102 (see reference) can be removed. Figure 3 ).

[0122] Reference Figure 28 and Figure 29 A first silicon pad 310 having a crystal structure can be formed on a substrate 100 without a native oxide layer and a first active pattern 102.

[0123] In an example embodiment, the growth rate of the first silicon pad 310 on the third-direction sidewall of the first active pattern 102 can be lower than the growth rate of the first silicon pad 310 on the fourth-direction sidewall of the first active pattern 102. Therefore, the first thickness d1 of the first silicon pad 310 on the third-direction sidewall of the first active pattern 102 can be less than the second thickness d2 of the first silicon pad 310 on the fourth-direction sidewall of the first active pattern 102.

[0124] The growth rate of the first silicon pad 310 can be varied by controlling the temperature and pressure during the deposition process of the first silicon pad 310. Furthermore, the growth rate of the first silicon pad 310 can be varied by controlling the process conditions used to remove the native oxide layer.

[0125] In the example implementation, the process for removing the native oxide layer can be compared with the reference process. Figures 4 to 6 The processes shown are essentially the same. When the native oxide layer is removed by process conditions, the deposition process can be performed at temperatures ranging from about 490°C to about 700°C and pressures ranging from about 50 Torr to about 150 Torr.

[0126] Reference Figure 30 A first insulating layer 112 can be formed on the first silicon pad 310 by a deposition process. During the deposition process, the first silicon pad 310 can be oxidized to reduce its thickness. Therefore, the first silicon pad 310 can be transformed into a second silicon pad 310a. Furthermore, the first insulating layer 112 can be formed on the second silicon pad 310a.

[0127] In this configuration, the first silicon pad 310 is oxidized to a uniform thickness. Therefore, the thickness of the second silicon pad 310a formed on the sidewall of the first active pattern 102 in the long axis direction and the thickness of the second silicon pad 310a formed on the sidewall of the first active pattern 102 in the short axis direction can be different from each other. That is, the third thickness d3 of the second silicon pad 310a on the sidewall of the first active pattern 102 in the third direction can be less than the fourth thickness d4 of the second silicon pad 310a on the sidewall of the first active pattern 102 in the fourth direction.

[0128] In addition, the thickness of the first insulating layer 112 can be greater than the thickness of the second silicon pad 310a.

[0129] After that, the reference can be executed. Figures 16 to 24 The same process is shown. Therefore, an active region with a sufficient area in the fourth direction can be formed.

[0130] Semiconductor devices can have the same characteristics as a reference. Figure 23 and Figure 24 The structure of the semiconductor device shown is the same. However, in the second silicon pad 310a, the third thickness d3 of the second silicon pad 310a on the third-direction sidewall of the first active pattern 102 can be smaller than the fourth thickness d4 of the second silicon pad on the fourth-direction sidewall of the first active pattern 102. Therefore, the first active pattern 102 can have sufficient area for forming transistors and the first contact plug 142 and the second contact plug 148.

[0131] Figures 31 to 35 This is a cross-sectional view showing the stages of a method for manufacturing a semiconductor device according to an example embodiment.

[0132] Semiconductor devices can be fin field-effect transistors.

[0133] Reference Figure 31 A hard mask pattern (not shown) can be formed on the substrate 100, and the hard mask pattern can be used as an etching mask to etch the substrate 100 to form a first active pattern. The first active pattern 402 can be formed to protrude from the substrate 100.

[0134] In an example implementation, the first active pattern 402 may extend in a second direction. The first active patterns 402 may be spaced apart from each other in a first direction. A trench 404 may be formed between the first active patterns 402.

[0135] Reference Figure 32 Reference can be performed on the first active pattern 402 and the substrate 100. Figures 4 to 10 The same process is shown. Therefore, the first silicon pad 406 can be formed on the surface of the first active pattern 402 and on the surface of the substrate 100.

[0136] Reference Figure 33 The isolation layer 410 can be formed on the first silicon pad 406 by a deposition process to fully fill the trench 404.

[0137] When performing the deposition process for forming the isolation layer 410, the surface of the first silicon pad 406 can be oxidized to reduce the thickness of the first silicon pad 406. Therefore, the first silicon pad 406 can be transformed into a second silicon pad 406a. That is, the isolation layer 410 can be formed on the second silicon pad 406a.

[0138] The isolation layer 410 may include an oxide layer formed by oxidizing the surface of the first silicon pad 406 and an oxide layer formed by a deposition process. The oxide layer included in the isolation layer 410 may include substantially the same material, such as silicon oxide.

[0139] Reference Figure 34 The isolation layer 410 can be planarized until the upper surface of the second silicon pad 406a can be exposed. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0140] Then, a portion of the isolation layer 410 can be etched to expose a second silicon pad 406a formed on the upper sidewall of the first active pattern 402, thereby forming the isolation pattern 410a. The isolation pattern 410a can fill the lower portion of the trench 404. That is, the second silicon pad 406a can be exposed on the isolation pattern 410a.

[0141] Reference Figure 35 A gate structure 420 is formed on the exposed surface of the second silicon pad 406a and the exposed surface of the isolation pattern 410a. The gate structure 420 may include a gate insulating layer pattern 420a, a gate electrode 420b, and a capping layer pattern 420c.

[0142] A first impurity region and a second impurity region, which serve as source / drain, can be formed at the first active pattern 402 and the second silicon pad 406a adjacent to both sides of the gate structure 420.

[0143] Although not shown, contact plugs can be formed to contact the first impurity region, the second impurity region, and the gate electrode 420b, respectively.

[0144] A second silicon pad 406a can be formed without reducing the area of ​​the first active pattern 402. Therefore, sufficient area can be ensured for forming the transistor and contact plugs. In the semiconductor device, a gate insulating layer pattern 420a can be formed on the second silicon pad 406a. Therefore, crystal defects included in the gate insulating layer pattern 420a can be reduced, thereby reducing the leakage current of the transistor caused by the gate insulating layer pattern 420a. Furthermore, transistor reliability failures can be reduced.

[0145] Figure 36 and Figure 37 This is a cross-sectional view showing the stages of a method for manufacturing a semiconductor device according to an example embodiment.

[0146] Reference Figure 36A hard mask pattern (not shown) can be formed on the substrate 100, and the hard mask pattern can be used as an etching mask to etch the substrate 100 to form a first active pattern 102. The first active pattern 102 can protrude from the substrate 100. In an example embodiment, the first active patterns 102 can be isolated from each other. The longitudinal direction of each first active pattern 102 can be a first direction.

[0147] After that, the reference can be executed. Figures 4 to 10 The same process is shown. Therefore, the first silicon pad can be formed on the surface of the first active pattern 102 and on the surface of the substrate 100.

[0148] Subsequently, an isolation layer 450 can be formed on the first silicon pad 110 by a deposition process to fully fill the trench 104. When forming the isolation layer 450, the thickness of the first silicon pad can be reduced by oxidizing the surface of the first silicon pad. Therefore, the first silicon pad can be transformed into a second silicon pad 110a. The first isolation layer 450 can be formed on the second silicon pad 110a.

[0149] Reference Figure 37 The isolation layer 450 can be planarized until the upper surface of the second silicon pad 110a can be exposed. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0150] The gate structure 460 may be formed on the second silicon pad 110a. The gate structure 460 may include a gate insulating layer pattern 460a, a gate electrode 460b, and a capping layer pattern 460c.

[0151] In an example implementation, the gate structure 460 may be formed on the second silicon pad 110a and the isolation layer 450a to intersect with the first active pattern 102.

[0152] A first impurity region 462a and a second impurity region 462b, serving as source / drain electrodes, can be formed on the second silicon pad 110a and the substrate 100 adjacent to both sides of the gate structure 460. Although not shown, contact plugs can be formed to contact the first impurity region 462a, the second impurity region 462b, and the gate electrode 460b, respectively.

[0153] In this way, planar transistors can be formed on the second silicon pad 110a.

[0154] As described above, in the example implementation, the area of ​​the active region can be sufficiently ensured. Therefore, a semiconductor device with excellent characteristics can be formed on the active region.

[0155] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the clauses for "device plus function" are intended to cover structures described herein as performing the listed functions, covering not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed and other exemplary embodiments are intended to be included within the scope of the appended claims.

[0156] This application claims priority to Korean Patent Application No. 10-2019-0117246, filed on September 24, 2019, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device comprising: an active pattern protruding from a substrate; a silicon liner having a crystal structure, the silicon liner conformally on a surface of the active pattern and a surface of the substrate; an insulating layer on the silicon liner; an isolation pattern on the insulating layer to fill a trench adjacent to the active pattern; and a transistor including a gate structure on the silicon liner, and an impurity region adjacent to a respective side of the gate structure, wherein the active pattern is isolated from other active patterns and extends in a long axis direction, a length of the active pattern in the long axis direction is greater than a length of the active pattern in a short axis direction perpendicular to the long axis direction, and a first thickness of the silicon liner on a sidewall of the active pattern in the long axis direction is different from a second thickness of the silicon liner on a sidewall of the active pattern in the short axis direction.

2. The semiconductor device of claim 1, wherein the silicon liner has a same crystal structure as a crystal structure of the active pattern and a crystal structure of the substrate.

3. The semiconductor device of claim 1, wherein a thickness of the insulating layer is greater than a thickness of the silicon liner.

4. The semiconductor device of claim 1, wherein the silicon liner covers an entire surface of the active pattern and an entire surface of the substrate.

5. The semiconductor device of claim 1, wherein the gate structure includes a gate insulating layer pattern, a gate electrode, and a cap layer pattern, and the gate insulating layer pattern contacts a portion of the silicon liner.

6. The semiconductor device of claim 1, wherein a portion of the active pattern, a portion of the silicon liner, and a portion of the isolation pattern include a gate trench extending in a first direction, and the gate structure is formed in the gate trench.

7. The semiconductor device of claim 6, wherein the active pattern and the silicon liner are exposed by the gate trench, and a portion of the gate structure contacts the silicon liner in the gate trench.

8. The semiconductor device of claim 1, wherein the silicon liner on the active pattern and the substrate has a uniform thickness.

9. The semiconductor device of claim 1, wherein the first thickness of the silicon liner on a sidewall of the active pattern in the long axis direction is greater than the second thickness of the silicon liner on a sidewall of the active pattern in the short axis direction.

10. The semiconductor device of claim 1, wherein the first thickness of the silicon liner on a sidewall of the active pattern in the long axis direction is less than the second thickness of the silicon liner on a sidewall of the active pattern in the short axis direction.

11. The semiconductor device of claim 10, further comprising: a stop layer pattern between the insulating layer and the isolation pattern.

12. The semiconductor device of claim 1, further comprising: a first insulating interlayer covering the silicon liner, the isolation pattern, and the gate structure; a contact plug through the first insulating interlayer to contact the impurity region. ​ 13. A semiconductor device, comprising: an active pattern protruding from a substrate; a silicon liner having a crystalline structure on the active pattern and the substrate, the silicon liner covering a surface of the active pattern and a surface of the substrate; an isolation pattern filling trenches between the active pattern on the silicon liner; a transistor including a gate structure on the silicon liner and first and second impurity regions adjacent respective sides of the gate structure; a first insulating interlayer covering the silicon liner, the isolation pattern, and the gate structure; first and second contact plugs through the first insulating interlayer to contact the first and second impurity regions, respectively; a bit line electrically connected to the first contact plug; and a capacitor electrically connected to the second contact plug, wherein the active pattern is isolated from other active patterns and extends in one direction, a length of the active pattern in a long axis direction is greater than a length of the active pattern in a short axis direction perpendicular to the long axis direction, and a first thickness of the silicon liner on a sidewall of the active pattern in the long axis direction is different from a second thickness of the silicon liner on a sidewall of the active pattern in the short axis direction.

14. The semiconductor device of claim 13, wherein the silicon liner on the active pattern and the substrate has a uniform thickness.

15. A semiconductor device, comprising: an active pattern protruding from a substrate; a silicon liner having a crystalline structure conformally on a surface of the active pattern and a surface of the substrate; an insulating layer on the silicon liner; a stop layer pattern on the insulating layer, the stop layer pattern in trenches between the active pattern; an isolation pattern on the stop layer pattern to fill the trenches; and a transistor including a gate structure on the silicon liner, and impurity regions adjacent respective sides of the gate structure, wherein the active pattern is isolated from other active patterns and extends in one direction, a length of the active pattern in a long axis direction is greater than a length of the active pattern in a short axis direction perpendicular to the long axis direction, and a first thickness of the silicon liner on a sidewall of the active pattern in the long axis direction is different from a second thickness of the silicon liner on a sidewall of the active pattern in the short axis direction.

16. The semiconductor device of claim 15, wherein a thickness of the insulating layer is greater than a thickness of the silicon liner.

17. The semiconductor device of claim 15, wherein the gate structure includes a gate insulating layer pattern, a gate electrode, and a cap layer pattern, and the gate insulating layer pattern contacts a portion of the silicon liner.

18. A method of manufacturing a semiconductor device, the method comprising: etching a portion of a substrate to form an active pattern protruding from the substrate; forming a first silicon liner having a crystalline structure conformally on a surface of the active pattern and a surface of the substrate; ​ ​ oxidizing a surface of the first silicon liner to form a second silicon liner and an insulating layer on the second silicon liner, the second silicon liner having a thickness less than a thickness of the first silicon liner; forming an isolation layer on the insulating layer to fill a trench adjacent to the active pattern; and forming a transistor, the transistor including a gate structure disposed on the second silicon liner, and an impurity region adjacent to a respective side of the gate structure, wherein the active pattern is isolated from other active patterns and extends in a long axis direction, a length of the active pattern in the long axis direction is greater than a length of the active pattern in a short axis direction perpendicular to the long axis direction, and a first thickness of the second silicon liner on a sidewall of the active pattern in the long axis direction is different from a second thickness of the second silicon liner on a sidewall of the active pattern in the short axis direction.

19. The method of claim 18, further comprising, prior to forming the first silicon liner, removing a native oxide layer formed on a surface of the active pattern and a surface of the substrate.

20. The method of claim 19, wherein removing the native oxide layer and forming the first silicon liner are performed in-situ.

21. The method of claim 19, wherein removing the native oxide layer includes: performing a first process of introducing an etching source gas onto the surface of the active pattern and the surface of the substrate; and performing a second process of applying heat and pressure on the surface of the active pattern and the surface of the substrate.

22. The method of claim 18, wherein forming the first silicon liner is performed in a deposition chamber having a volume of 20L or less, and nitrogen gas is introduced into the deposition chamber to have a flow rate of 100sccm or more. ​

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