Fully differential high-speed logic conversion circuit, chip and laser radar

Abstract

The present invention discloses a fully differential high-speed logic conversion circuit, a chip and a laser radar. The fully differential high-speed logic conversion circuit comprises: a logic gate circuit; a voltage series positive feedback circuit for expanding the range of the input signal of the logic gate circuit. The technical solution of the present invention enables the logic conversion circuit to adapt to input signals with different swing amplitudes, thereby improving the input signal compatibility of the logic conversion circuit. At the same time, the operating frequency of the logic conversion circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular to a fully differential high-speed logic conversion circuit, chip and laser radar. Background Art

[0002] With the continuous development of integrated circuits and the expansion of demand, logic conversion circuits need to adapt to input signals with a wider range of swings, that is, to adapt to both high-swing input signals and low-swing input signals.

[0003] In the prior art, the logic conversion circuit generally includes a digital logic circuit, such as a differential cascade logic, and the digital logic circuit has a strong processing capability for high-swing input signals.

[0004] However, for low-swing input signals such as LVDS, CML, VML, and LVPECL, the digital logic circuit at this time will encounter the problem that the differential output high and low level voltage difference is too low or even the output level cannot be flipped normally, and it cannot be compatible with multiple level standards.

[0005] The root cause of this problem is that the circuit design process needs to take into account both the rapid flipping of the level when the signal jumps and the static bias after the flip ends and stabilizes. It is difficult for a simple digital logic circuit to take into account both a large signal input range and a large output voltage difference. Summary of the invention

[0006] The technical problem solved by the present invention is to make the logic conversion circuit adapt to input signals with different swing amplitudes, thereby improving the input signal compatibility of the logic conversion circuit.

[0007] Furthermore, the operating frequency of the logic conversion circuit is increased.

[0008] The present invention discloses a fully differential high-speed logic conversion circuit, comprising:

[0009] Logic gate circuits;

[0010] The voltage series positive feedback circuit is used to expand the range of the input signal of the logic gate circuit.

[0011] The fully differential high-speed logic conversion circuit is provided with constant current sources at the power supply end and the ground end of the logic gate circuit respectively.

[0012] The logic gate circuit has multiple differential input signals and one differential output signal;

[0013] Each differential input signal realizes positive feedback through the voltage series positive feedback circuit.

[0014] The logic gate circuit includes at least one of a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XNOR gate, and an XOR gate.

[0015] The voltage series positive feedback circuit comprises an input resistor and a feedback resistor, and the DC bias after the output of the logic gate circuit depends on the resistance ratio of the input resistor to the feedback resistor.

[0016] The voltage series positive feedback circuit comprises a first input resistor, a first feedback resistor, a second input resistor, and a second feedback resistor;

[0017] The first end of the first input resistor receives the positive signal in the differential input signal, the second end of the first input resistor is connected to the positive input end of the logic gate circuit, the second end of the first input resistor is also connected to the first end of the first feedback resistor, and the second end of the first feedback resistor is connected to the positive output end of the logic gate circuit;

[0018] The first end of the second input resistor receives the negative signal in the differential input signal, the second end of the second input resistor is connected to the negative input end of the logic gate circuit, the second end of the second input resistor is also connected to the first end of the second feedback resistor, and the second end of the second feedback resistor is connected to the negative output end of the logic gate circuit.

[0019] The input signal of the logic gate circuit includes an LVDS, CML, CMOS, VML or LVPECL signal.

[0020] The logic gate circuit outputs a CMOS signal.

[0021] The fully differential high-speed logic conversion circuit is implemented by CMOS technology.

[0022] The invention discloses a logic conversion chip, which has at least one fully differential high-speed logic conversion circuit.

[0023] A plurality of the fully differential high-speed logic conversion circuits are cascade-connected to each other.

[0024] The present invention discloses a laser radar provided with the fully differential high-speed logic conversion circuit, or provided with the logic conversion chip.

[0025] The technical solution of the present invention enables the fully differential logic conversion circuit to adapt to input signals with different swing amplitudes, improves the input signal compatibility of the fully differential logic conversion circuit, and at the same time, improves the operating frequency of the logic conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a schematic diagram of the structure of the logic conversion chip of the present invention.

[0027] Figure 2 Shown is a structural schematic diagram of a fully differential high-speed logic conversion circuit disclosed in the present invention.

[0028] Figure 3 FIG. 1 is a circuit diagram of the fully differential high-speed logic conversion circuit 100 .

[0029] Figure 4 , 5 Shown is a schematic diagram of the structure of a logic conversion chip. DETAILED DESCRIPTION

[0030] The implementation process of the technical solution of the present invention is described below in conjunction with specific embodiments, which is not intended to limit the present invention.

[0031] The present invention relates to chip design, such as Figure 1 Shown is a schematic diagram of the structure of the logic conversion chip of the present invention.

[0032] The logic conversion chip includes a fully differential high-speed logic conversion circuit 100 and an output driver circuit BF. N As a high-speed input signal, the fully differential high-speed logic conversion circuit 100 is input to realize logic operation and output a CMOS level signal, which drives the lower load through the output buffer circuit BF. The current reference Current Ref is used to provide bias current for each module.

[0033] In order to make the fully differential high-speed logic conversion circuit adapt to high-speed input signals with different swing amplitudes and improve the compatibility of the fully differential high-speed logic conversion circuit with different input signals, the fully differential high-speed logic conversion circuit 100 of the present invention adopts a positive feedback design, so that the output signal amplitude of the fully differential high-speed logic conversion circuit 100 can be recognized by the lower-level circuit.

[0034] like Figure 2 Shown is a structural schematic diagram of a fully differential high-speed logic conversion circuit disclosed in the present invention.

[0035] A fully differential high-speed logic conversion circuit 100 includes:

[0036] Logic gate circuit 10;

[0037] The voltage series positive feedback circuit 20 is used to expand the range of the input signal of the logic gate circuit to be compatible with multiple interface electrical standards.

[0038] The fully differential high-speed logic conversion circuit 100 can receive input signals, that is, receive multiple high-speed interface levels in sequence and perform logic operations, and finally output CMOS signals.

[0039] The logic gate circuit 10 has multiple differential input signals and one differential output signal. Each differential input signal is positively fed back through the voltage series positive feedback circuit 20, and the voltage series positive feedback circuit 20 amplifies the differential input signal.

[0040] like Figure 3 FIG. 1 is a circuit diagram of the fully differential high-speed logic conversion circuit 100 .

[0041] The fully differential high-speed logic conversion circuit 100 receives n differential input signals of the same type and outputs one differential output signal, wherein VIP[n] is the differential input signal VIN. n The positive signal of VIN[n] is the differential input signal VIN n VOP is the negative signal of the differential output signal, VON is the positive signal of the differential output signal, and n=1...N, where N is a positive integer greater than or equal to 2.

[0042] All differential input signals are fed back through a voltage series positive feedback circuit 20. The voltage series positive feedback circuit 20 includes an input resistor R in P[n], feedback resistor R f P[n], input resistance R in N[n], feedback resistor R f Positive feedback network implemented by N[n].

[0043] R in The first end of P[n] receives VIP[n], R in The second end of P[n] is connected to the nth positive input terminal D[n] of the logic gate circuit 10, R in The second end of P[n] is also connected to R f The first end of P[n] is connected to R f The second end of P[n] is connected to the first output end Q of the logic gate circuit 10 .

[0044] R in The first end of N[n] receives VIN[n], R in The second end of N[n] is connected to the nth negative input terminal DN[n] of the logic gate circuit 10, R in The second end of N[n] is also connected to R f The first end of N[n] is connected to R f The second end of N[n] is connected to the second output end QN of the logic gate circuit 10 .

[0045] In the preferred embodiment, all input resistors R in P[n] and all input resistance R in The resistance of N[n] is the same, all feedback resistors Rf P[n] and all feedback resistors R f The resistance value of N[n] is the same.

[0046] The DC bias after the output of the logic gate circuit 10 depends on the feedback resistor R f P[n] and the input resistance R in The ratio X of the resistance values ​​of P[n].

[0047] The logic gate circuit 10 includes at least one of a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XNOR gate, and an XOR gate. Since the structure of the logic conversion circuit 100 is simple, the logic conversion circuit 100 can be implemented by a CMOS process. The use of a CMOS process facilitates further integration of the logic conversion circuit 100 of the present invention with other functional circuits, has strong compatibility, and reduces costs.

[0048] In an optimized embodiment, a constant current source I1 is provided at the power supply terminal Vcc of the logic gate circuit 10, and a constant current source I2 is provided at the ground terminal GND. By providing the above constant current source, the logic gate circuit 10 is always in a conducting state, thereby avoiding the time loss of repeated startup of the logic gate circuit 10, providing an adaptive high-speed operating frequency for the input signal with a high-speed interface level, and improving the operation efficiency of the chip.

[0049] The constant current sources I1 and I2 control the driving capability of the fully differential high-speed logic conversion circuit 100 , which helps to reduce the difficulty of logic inversion when a small-amplitude differential input signal is input, and together with the voltage series positive feedback circuit 20 , widens the input range of the differential input signal.

[0050] The input signal of the logic gate circuit may include LVDS, CML, CMOS, VML or LVPECL signal. Through the technical solution of the present invention, the output range of the low-swing input signal can be expanded to meet the signal requirements of subsequent circuits.

[0051] At the same time, the output buffer stage circuit BF has a driving capability, which can isolate the back-end load from the fully differential high-speed logic conversion circuit, and can adopt different implementation forms to generate the required output level type.

[0052] The scheme of the present invention is described below by way of example. This example is applicable to LVDS, CML, CMOS, VML or LVPECL signals as input signals. The following description is made by taking the logic gate circuit 10 as a two-input differential AND gate as an example.

[0053] In case 1, VIP[1] and VIN[1] are both at a high level, and VIP[2] and VIN[2] remain unchanged.

[0054] For example, VIP[1]=2 / 3*VCC, VIN[1]=1 / 2*VCC, at this time the input center value is higher than 0.5*VCC. If the voltage series positive feedback circuit 20 is not set, the outputs are all low level, that is, VOP=0.2*VCC, VON=0.1*VCC, the voltage difference is too small, and the output signal at this time cannot be recognized by the lower level BF, and the valid logic operation value cannot be output.

[0055] After the voltage series positive feedback circuit 20 is set, a current path is formed between the input and the output, causing the output to rise. Since the VIP[1] level is higher than VIN[1], the positive feedback effect of the path where VIP[1] is located is stronger, so VOP is pulled up to higher than 0.5*VCC, and VON is much lower than 0.5*VCC. The voltage difference is amplified, and can then be recognized by the lower-level BF and the output is amplified.

[0056] In case 2, VIP[1] is at a high level, VIN[1] is at a low level, and VIP[2] and VIN[2] remain unchanged.

[0057] At this time, since there is a voltage difference in the input signal, there is also a voltage difference in the output, and it can be recognized by the lower-stage BF even if the voltage series positive feedback circuit 20 is not set. After the voltage series positive feedback circuit 20 is set, the voltage series positive feedback circuit 20 does not make a large adjustment to VOP and VON, so the output signal can be normally recognized by the lower-stage BF and amplified for output.

[0058] In case three, VIP[1] is at a low level, VIN[1] is at a high level, and VIP[2] and VIN[2] remain unchanged.

[0059] At this time, since there is a voltage difference in the input signal, there is also a voltage difference in the output, and it can be recognized by the lower-stage BF even if the voltage series positive feedback circuit 20 is not set. After the voltage series positive feedback circuit 20 is set, the voltage series positive feedback circuit 20 does not make a large adjustment to VOP and VON, so the output signal can be normally recognized by the lower-stage BF and amplified for output.

[0060] In case 4, VIP[1] and VIN[1] are both at a lower level, and VIP[2] and VIN[2] remain unchanged.

[0061] For example, VIP[1]=1 / 3*VCC, VIN[1]=1 / 4*VCC, at this time the input center value is lower than 0.5*VCC. If the voltage series positive feedback circuit 20 is not set, the outputs are all high level, that is, VOP=0.8*VCC, VON=0.7*VCC, the voltage difference is too small, and the output signal cannot be recognized by the lower level BF, and the valid logic operation value cannot be output.

[0062] After the voltage series positive feedback circuit 20 is set, a current path is formed between the input and the output, causing the output to decrease. Since the VIN[1] level is lower than VIP[1], the positive feedback effect of the path where VIN[1] is located is stronger, so VOP is pulled down to above 0.5*VCC, and VON is pulled down to far below 0.5*VCC, and the voltage difference is amplified, which can then be recognized by the lower-level BF and amplified for output.

[0063] The above four cases can be applicable to LVDS, CML, CMOS, VML or LVPECL signals.

[0064] The DC bias after the output of the logic gate circuit 10, that is, the value of VOP, VON depends on the feedback resistor R f P[n] and the input resistance R in The ratio X of the resistance values ​​of P[n].

[0065] The present invention also discloses a logic conversion chip, such as Figure 4 Shown is a schematic diagram of the structure of the logic conversion chip.

[0066] The logic conversion chip includes a plurality of cascaded fully differential high-speed logic conversion circuits 100. The second-stage fully differential high-speed logic conversion circuit 100 receives the output signal of the first-stage fully differential high-speed logic conversion circuit 100 as an input signal. The second-stage fully differential high-speed logic conversion circuit 100 can also receive differential input signals from the outside or other circuits.

[0067] Figure 5 The differential output signals of two fully differential high-speed logic conversion circuits 100 are used as input signals of the next stage fully differential high-speed logic conversion circuit 100, but the number is not limited thereto. The next stage fully differential high-speed logic conversion circuit 100 can also receive differential input signals from the outside or other circuits.

[0068] like Figure 4 , 5 The cascade arrangement shown enables multiple fully differential high-speed logic conversion circuits 100 to be densely arranged, saving wiring area, saving space, and reducing costs.

[0069] The fully differential high-speed logic conversion circuit compatible with multiple high-speed interface levels and the corresponding logic conversion chip disclosed in the present invention are both arranged in the laser radar equipment.

[0070] The technical solution of the present invention enables the fully differential high-speed logic conversion circuit to adapt to input signals with different swing amplitudes, improves the input signal compatibility of the fully differential high-speed logic conversion circuit, and especially extends the compatibility range to low voltage, so that the fully differential high-speed logic conversion circuit can be compatible with high and low voltage levels. At the same time, the operating frequency of the fully differential high-speed logic conversion circuit is improved.

[0071] The above embodiments are merely exemplary descriptions for implementing the present invention and are not intended to limit the protection scope of the present invention. Those skilled in the art may make various obvious modifications and equivalent replacement technical solutions based on the above embodiments, which are all included in the disclosure scope of the present invention. The protection scope of the present invention shall be subject to the following claims.

Claims

1. A fully differential high-speed logic conversion circuit, characterized in that: include: Logic gate circuits; A voltage series positive feedback circuit is used to expand the range of the input signal of the logic gate circuit to be compatible with multiple interface electrical standards; The logic gate circuit has multiple differential input signals and one differential output signal, and each differential input signal realizes positive feedback through the voltage series positive feedback circuit; Wherein, the voltage series positive feedback circuit comprises a first input resistor, a first feedback resistor, a second input resistor, and a second feedback resistor; The first end of the first input resistor receives the positive signal in the differential input signal, the second end of the first input resistor is connected to the positive input end of the logic gate circuit, the second end of the first input resistor is also connected to the first end of the first feedback resistor, and the second end of the first feedback resistor is connected to the positive output end of the logic gate circuit; The first end of the second input resistor receives the negative signal in the differential input signal, the second end of the second input resistor is connected to the negative input end of the logic gate circuit, the second end of the second input resistor is also connected to the first end of the second feedback resistor, and the second end of the second feedback resistor is connected to the negative output end of the logic gate circuit.

2. The fully differential high-speed logic conversion circuit according to claim 1, characterized in that: A constant current source is respectively arranged at the power supply end and the ground end of the logic gate circuit.

3. The fully differential high-speed logic conversion circuit according to claim 1, characterized in that: The logic gate circuit includes at least one of a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XNOR gate, and an XOR gate.

4. The fully differential high-speed logic conversion circuit according to claim 1, characterized in that: The voltage series positive feedback circuit comprises an input resistor and a feedback resistor, and the DC bias after the output of the logic gate circuit depends on the resistance ratio of the input resistor to the feedback resistor.

5. The fully differential high-speed logic conversion circuit according to claim 1, characterized in that: The input signal of the logic gate circuit includes an LVDS, CML, CMOS, VML or LVPECL signal.

6. The fully differential high-speed logic conversion circuit according to claim 1, characterized in that: The fully differential high-speed logic conversion circuit is implemented by CMOS technology.

7. A logic conversion chip, characterized in that: A fully differential high-speed logic conversion circuit having at least one as claimed in any one of claims 1 to 6.

8. The logic conversion chip according to claim 7, characterized in that: A plurality of the fully differential high-speed logic conversion circuits are cascade-connected to each other.

9. A laser radar, characterized in that: A fully differential high-speed logic conversion circuit as described in any one of claims 1-6 is provided, or a logic conversion chip as described in any one of claims 7-8 is provided.

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