Digitally Assisted Dynamic Multi-Mode Power Supply Circuit

Abstract

Certain aspects of the present disclosure generally relate to methods and apparatus for switching between modes of a multi-mode power supply circuit. An example power supply circuit generally includes a switch mode power supply (SMPS) circuit; a voltage regulator circuit having an input coupled to an output of the SMPS circuit, the voltage regulator circuit being configured to be selectively enabled; a first voltage divider selectively coupled to the output of the SMPS circuit and selectively coupled to the output of the voltage regulator circuit; and a second voltage divider coupled to the output of the voltage regulator circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 16 / 554,082, filed on August 28, 2019, entitled “Digitally Assisted Dynamic Multi-Mode Power Supply Circuit,” which claims priority to U.S. Provisional Patent Application No. 62 / 725,033, filed on August 30, 2018, entitled “Digitally Assisted Dynamic Multi-Mode Power Supply Circuit,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits and, more particularly, to a multi-mode power supply circuit and operation thereof. Background Art

[0004] A power management integrated circuit (power management IC or PMIC) is used to manage the power requirements of a host system. A PMIC can be used in battery-operated devices such as mobile phones, tablets, laptops, wearable devices, etc. to control the flow and direction of electrical power in the device. A PMIC can perform multiple functions of a device, such as DC to DC conversion (e.g., using a voltage regulator), battery charging, power source selection, voltage scaling, power sequencing, etc.

[0005] Ideally, a voltage regulator provides a constant direct current (DC) output voltage regardless of changes in the load current or input voltage. Voltage regulators can be classified as linear regulators or switching regulators. Although linear regulators tend to be smaller and more compact, many applications may still benefit from the increased efficiency of switching regulators. For example, a linear regulator can be implemented by a low dropout (LDO) regulator. A switching regulator can be implemented, for example, by a switched mode power supply (SMPS) such as a buck converter or a boost converter. A buck converter (also called a step-down converter) converts a higher input voltage to a lower output voltage, while a boost converter (also called a step-up converter) converts a lower input voltage to a higher output voltage. Summary of the invention

[0006] Certain aspects of the present disclosure generally relate to techniques and apparatus for switching between different operating modes of a multi-mode power supply circuit.

[0007] Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes a switch mode power supply (SMPS) circuit; a voltage regulator circuit having an input coupled to an output of the SMPS circuit, the voltage regulator circuit being configured to be selectively enabled; a first voltage divider selectively coupled to at least one of the output of the SMPS circuit or the input of the voltage regulator circuit and selectively coupled to the output of the voltage regulator circuit; and a second voltage divider coupled to the output of the voltage regulator circuit.

[0008] Certain aspects of the present disclosure provide a method of operating a multi-mode power supply circuit. The method generally includes: detecting a high input voltage event in a multi-mode power supply circuit, the multi-mode power supply circuit including an SMPS circuit having an output coupled to an input of a voltage regulator circuit; enabling the voltage regulator circuit based on the detection; temporarily increasing a regulation point of the voltage regulator circuit to above an input voltage at the input of the voltage regulator circuit; and after a delay, reducing the regulation point of the voltage regulator circuit.

[0009] Certain aspects of the present disclosure provide an apparatus for supplying power via multiple modes. The apparatus generally includes components for supplying power via switch regulation; components for regulating a voltage from a component for supplying power; components for detecting a high input voltage event in the apparatus; components for enabling the component for regulating the voltage based on the detection; components for temporarily increasing a regulation point of the component for regulating the voltage above the voltage from the component for supplying power; and components for reducing the regulation point of the component for regulating the voltage after a delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order that the manner in which the features set forth above of the present disclosure are understood in detail, a more particular description briefly outlined above may be made by reference to various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered limiting of its scope, as the description may admit to other equally effective aspects.

[0011] Figure 1 A block diagram of an example device that may include a multi-mode power supply circuit according to certain aspects of the present disclosure is illustrated.

[0012] Figure 2 is a block diagram of an example multi-mode power supply circuit architecture in accordance with certain aspects of the present disclosure.

[0013] Figure 3A is an example timing diagram of digital signals associated with an example multi-mode power supply circuit during a large noise / ripple event on the power supply input voltage in accordance with certain aspects of the present disclosure.

[0014] Figure 3Bis an example timing diagram of digital signals associated with an example multi-mode power supply circuit during a high voltage level event of a power supply input voltage in accordance with certain aspects of the present disclosure.

[0015] Figure 4 is a timing diagram of various signals associated with an example multi-mode power supply circuit during an overshoot of a power supply input voltage in accordance with certain aspects of the present disclosure.

[0016] Figure 5 is a timing diagram of digital signals associated with an example multi-mode power supply circuit during a large input voltage noise / ripple event, illustrating blanking and cooldown timer behavior, in accordance with certain aspects of the present disclosure.

[0017] Figure 6 According to certain aspects of the present disclosure, Figure 2 Circuit diagram of an example programmable regulation point offset circuit system for a multi-mode power supply circuit architecture.

[0018] Fig. 7A is a block diagram of circuitry for large input voltage noise / ripple event detection in accordance with certain aspects of the present disclosure.

[0019] Figure 7B is a block diagram of circuitry for high input voltage level event detection in accordance with certain aspects of the present disclosure.

[0020] Figure 8 is a flow chart of example operations for power regulation in a multi-mode power circuit in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, various aspects of the present disclosure are described more fully with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, it should be appreciated by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether independent of any other aspect of the present disclosure or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice a method. In addition, the scope of the present disclosure is intended to cover such a device or method, which is practiced using other structures, functionality, or structure and functionality other than or in addition to the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the present disclosure disclosed herein may be embodied by one or more elements of a claim.

[0022] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] As used herein, in various tenses of the verb "connect", the term "connected with" may mean that element A is directly connected to element B or other elements may be connected between elements A and B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect elements A and B (and any components electrically connected therebetween).

[0024] Example Device

[0025] Figure 1 An example device 100 is illustrated in which aspects of the present disclosure may be implemented. The device 100 may be a battery operated device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless device, a laptop computer, a tablet computer, a smart phone, or the like.

[0026] The device 100 may include a processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). A memory 106, which may include both a read-only memory (ROM) and a random access memory (RAM), provides instructions and data to the processor 104. A portion of the memory 106 may also include a non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

[0027] In some aspects, the device 100 may also include a housing 108, which may include a transmitter 110 and a receiver 112 to allow data to be transmitted and received between the device 100 and a remote location. For some aspects, the transmitter 110 and the receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached or otherwise coupled to the housing 108 and electrically connected to the transceiver 114. The device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0028] The device 100 may also include a signal detector 118, which may be used to implement detection and quantization of the signal level received by the transceiver 114. The signal detector 118 may detect such signal parameters as total energy, energy per subcarrier per symbol, and power spectral density, etc. The device 100 may also include a digital signal processor (DSP) 120 for processing digital signals.

[0029] The device 100 may also include a battery 122 for powering the various components of the device 100. The device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing power from the battery to the various components of the device 100. The PMIC 124 may perform a variety of functions for the device, such as DC-DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In some aspects, the PMIC 124 may include a battery charging circuit (e.g., a master-slave battery charging circuit) or other switch mode power supply (SMPS). For some aspects, as described below, the battery charging circuit or other switch mode power supply may include a multi-mode power supply circuit. The various components of the device 100 may be coupled together via a bus system 126, which may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus.

[0030] Example Multi-Mode Power Supply Circuit

[0031] Power supply circuits for certain electronic devices, such as smartphones, tablets, and other portable devices, may be designed to meet stringent line transient performance specifications. For example, displays (e.g., active-matrix organic light-emitting diode (AMOLED) panels) may be very sensitive to the stability of the voltage supply rail, where voltages above 20 mV may be very sensitive to line transient performance specifications. pp And any voltage disturbance lasting 30μs to 100μs may cause screen striping behavior. However, the input voltage rail (e.g., VPH_PWR output by the battery charging circuit (such as in PMIC 124)) may be subjected to a large load attack or release, causing significant undershoot or overshoot (e.g., up to 750mV). Further still, in the case where a battery charger (also called a power adapter) is plugged into an electrical outlet, the DC value of VPH_PWR may increase to as high as 4.8V, which may be higher than the desired converter output voltage of 4.6V.

[0032] One solution includes utilizing a post-regulator stage after the converter stage, which can relax the converter design specifications. However, constantly enabling the post-regulator may result in a drop in efficiency (e.g., a drop of about 2% to 3%). Another solution requires enabling the post-regulator when desired (referred to as normal power mode) and keeping the post-regulator in bypass mode at other times. In bypass mode (BYP), the post-regulator is effectively bypassed, such as by shorting the post-regulator using a closed switch. However, the transition from bypass mode to normal power mode (NPM) and vice versa may introduce undesirable large voltage disturbances.

[0033] Certain aspects of the present disclosure provide a digitally assisted dynamic multi-mode power supply circuit. The multi-mode power supply circuit can provide high power supply rejection ratio (PSRR) regulation and can adapt to high input voltage level (e.g., high VPH_PWR) events. Based on the detected input power supply voltage conditions (e.g., large noise / ripple and / or high voltage levels), the digital controller can automatically enable or disable the post regulator and adjust its margin. In addition, the digital controller can control the timing and / or conversion rate of the margin adjustment to achieve smooth mode transitions (e.g., between BYP and NPM).

[0034] Figure 2 is a block diagram of an example multi-mode power supply circuit 200 according to certain aspects of the present disclosure. The multi-mode power supply circuit 200 includes a switch mode power supply (SMPS) circuit 202 (e.g., a boost converter) followed by a post regulator circuit 204 (a voltage regulator circuit such as a low dropout (LDO) regulator or other linear regulator).

[0035] The SMPS circuit 202 may be implemented as follows Figure 2 The boost converter shown in FIG. 1 may include, for example, an input filter 205, an inductor 208, a switch 210, a diode device 212, and an output filter 214. Figure 2As depicted, input filter 205 may be implemented by input shunt capacitor 206. Input shunt capacitor 206 may act as a bypass capacitor, thereby shunting high frequency signal components to a reference potential node (e.g., electrical ground 207) for multi-mode power supply circuit 200. Inductor 208 may be coupled between a VDD_ELVDD node (also referred to as a "VPH_PWR" node) and a VSW_ELVDD node, switch 210 may be coupled between the VSW_ELVDD node and a reference potential node (labeled "PGND_ELVDD"), and diode device 212 may be coupled between the VSW_ELVDD node and a MID_ELVDD node (also referred to as a "VMID" node). Switch 210 may be implemented by transistor 211, such as an n-channel metal oxide semiconductor field effect transistor (n-MOSFET or NMOS), a bipolar junction transistor (BJT), or an insulated gate bipolar transistor (IGBT) as illustrated. The diode device 212 may be implemented by a diode, a diode-connected transistor, or a transistor 213 with a body diode, such as a p-channel MOSFET (PMOS) as shown. The output filter 214 may be a low-pass filter designed to reduce ripple in the output voltage from the SMPS circuit 202. Such a low-pass filter may be implemented, for example, by one or more shunt capacitors, such as a shunt capacitor 218 (labeled “Cmid_VDISP”). The output of the output filter 214 at node 219 may be considered the output of the SMPS circuit 202 and / or the input of the post-regulator circuit 204.

[0036] The gates of transistors 211 and 213 may be coupled to and controlled by SMPS control circuit 250. SMPS control circuit 250 may control the duty cycle and switching frequency of the drive signal for SMPS circuit 202. Circuit 250 may also include logic and / or circuitry for adjusting a reference voltage (Vref), for detecting the duty cycle of a sensed signal, and / or for detecting an envelope of a sensed signal.

[0037] Post-regulator circuit 204 may include transistor 224 and output filter 226. Transistor 224 may be, for example, Figure 2The PMOS transistor shown. The PMOS transistor may have a drain and a source, the drain being coupled to an input node (labeled “LDO_IN_ELVDD”) of the post-regulator circuit 204; the source being coupled to the output filter 226. The output filter 226 may be a low-pass filter designed to reduce ripple in the output voltage (labeled “Vreg_ELVDD”) from the post-regulator circuit 204. Such a low-pass filter may be implemented, for example, by one or more shunt capacitors, such as the shunt capacitor 232 (labeled “Cout_ELVDD”).

[0038] The post-regulator circuit 204 may be controlled by a post-regulator control circuit 252, which may have an output coupled to the gate of the transistor 224. The post-regulator control circuit 252 may include, for example, an error amplifier.

[0039] The multi-mode power supply circuit 200 may also include one or more feedback elements for regulating the output voltage. These feedback elements may include a first feedback node 239 (labeled as "LDO_IN_ELVDD"), a second feedback node 240 (labeled as "FB_ELVDD"), a first voltage divider 242, a second voltage divider 246, a first feedback switch 241, and a second feedback switch 245. The LDO_IN_ELVDD node may be coupled (e.g., shorted) to the MID_ELVDD node, such as Figure 2 as shown (making the first feedback node 239 the same as node 219).

[0040] The first terminal of the first voltage divider 242 can be selectively coupled to the first feedback node 239 via the first feedback switch 241, or selectively coupled to the second feedback node 240 via the second feedback switch 245. The second terminal of the first voltage divider 242 can be coupled to a reference potential node (e.g., electrical ground 207). The first voltage divider 242 can be implemented by two or more resistive elements 243, 244. A tap node 251 between the resistive elements 243, 244 can be coupled to the SMPS control circuit 250. The first voltage divider 242 is configured to generate a representative voltage that is a portion of the sensed output voltage of the SMPS circuit 202 or the post-regulator circuit 204.

[0041] The second voltage divider 246 may be coupled between the second feedback node 240 and a reference potential node (e.g., electrical ground 207). The second voltage divider 246 may be implemented by two or more resistor elements 247, 248. A tap node 249 between the resistor elements 247, 248 may be coupled to the post-regulator control circuit 252 to generate a representative voltage that is a portion of the sensed output voltage of the post-regulator circuit 204.

[0042] The SMPS control circuit 250 and the post-regulator control circuit 252 may be communicatively coupled to the digital control circuit 260. The digital control circuit 260 may output a step control signal (labeled “Step_CTL”) to control the SMPS control circuit 250. The digital control circuit 260 may also output a post-regulator bypass mode control signal (labeled “LDO_Bypass”) and a post-regulator normal power mode control signal (labeled “LDO_NPM”) to control the operation mode of the post-regulator circuit 204. The digital control circuit 260 may receive various input signals, including a large input voltage noise / ripple detection signal (labeled “BST_high_psrr”), a high power supply input voltage level detection signal (labeled “BST_vph_high”), and a higher power supply input voltage level detection signal (labeled “BST_vph_higher”) from the SMPS control circuit 250. In addition, as Figure 2 As illustrated, the SMPS control circuit 250 may receive a large input voltage noise / ripple acknowledgement signal (labeled “high_psrr_ack”) from the post regulator control circuit 252 .

[0043] The post-regulator circuit 204 can operate in a bypass mode (BYP), a normal power mode (NPM), or an active bypass mode (a transition mode between BYP and NPM). Figure 2 If the VDD_ELVDD (also shown in FIG. 1 ) is regular and in a normal operating range (e.g., 2.5 V to 4.5 V), the post-regulator circuit 204 is in a bypass mode, where the conduction resistance is relatively low (e.g., the on-resistance (R) of a p-channel metal oxide semiconductor (PMOS) transistor less than 100 mΩ). DS_on )). To enter the bypass mode, the post-regulator control circuit 252 may output a signal to the gate of the transistor 224 to drive the transistor 224 to the linear mode (eg, pull the gate of the transistor 224 down to the ground potential).

[0044] If VPH_PWR is subject to large noise / ripple (referred to herein as a "High_PSRR regulation event", or simply "High_PSRR event") or is higher than the output voltage (Vreg_ELVDD) of the multi-mode power supply circuit 200 (defined as a High_VPH event), the post-regulator circuit 204 can be automatically enabled to enter the active bypass mode, and then enter the normal power mode (NPM) shortly thereafter. The main control logic (e.g., in the digital control circuit 260) can have a digital finite state machine (FSM) and can be used to control the post-regulator mode transition, especially the post-regulator circuit 204 is placed in the normal power mode. Compared with the normal power mode, the post-regulator circuit 204 can remain in the bypass mode for most of the time to achieve higher efficiency. The post-regulator circuit 204 can move to the normal power mode to better handle the two system events (High_PSRR and High_VPH) described above. These two events are asynchronous in nature and can occur at any point in time. These events can occur separately or simultaneously, and the duration of the events may not be predictable.

[0045] In detail, the digital FSM will perform step control, delay control, clamping voltage and switching frequency adjustment, and blanking and cooling timing control. Step control can include adjusting the margin of the post-regulator circuit 204 (e.g., LDO) from 0 millivolts (mV) to any value based on different input power supply voltage (e.g., VPH_PWR) conditions. The conversion rate of the margin can be fully controlled by the digital stepper in the digital control circuit 260. Delay control may require adjusting the timing and delay of entering and / or exiting the normal power mode based on the input power supply voltage (e.g., VPH_PWR) condition to have (multiple) smooth transitions. (Multiple) delays can be determined by the warm-up time of the analog circuit system (e.g., in the post-regulator circuit 204). As described below with respect to Figure 4 As described, clamping voltage and switching frequency adjustment may include optimizing or at least adjusting the behavior of the SMPS circuit 202 (e.g., a boost converter) so that the SMPS has a smooth transition. For blanking and cooling timing control, a sequencer in the digital control circuit 260 may automatically decide whether to remain in normal power mode or exit to bypass mode, as described below with respect to Figure 5 as described.

[0046] Figure 3A is an example timing diagram 300 of digital signals associated with an example multi-mode power supply circuit (eg, circuit 200 ) during a large noise / ripple event (eg, a High_PSRR event) for a power supply input voltage in accordance with certain aspects of the present disclosure. Figure 3B350 is an example timing diagram of digital signals associated with an example multi-mode power supply circuit (e.g., circuit 200) during a high voltage level event (e.g., High_VPH event) for a power supply input voltage according to certain aspects of the present disclosure. The High_PSRR event and the High_VPH event are unrelated. For example, High_PSRR and High_VPH may have different headroom voltages and different entry / exit delay timing settings. When the two events are mixed together (i.e., the two events occur at the same time), the digital control circuit 260 can automatically optimize or at least adjust the settings.

[0047] exist Figure 3A In the timing diagram 300, the post-regulator circuit (e.g., LDO) initially operates in a bypass mode (BPM) as indicated by the state of the FSM (the signal labeled “ldo_state_FSM”). The timing diagram 300 also shows a digital signal for indicating regulation triggered for a large input voltage noise / ripple event (a digital analog-to-digital boost converter high PSRR compensation signal labeled “d_a2d_bst_hpsrr_comp”), a digital signal for indicating regulation triggered for a high input voltage level event (a digital analog-to-digital boost converter high input voltage level compensation signal labeled “d_a2d_bst_vph_high_comp”) (e.g., at 4.4V), and a digital signal for indicating regulation triggered for a higher input voltage level event (a digital analog-to-digital boost converter higher input voltage level compensation signal labeled “d_a2d_bst_higher_comp”) (e.g., at 4.5V). Figure 3A In the scenario of FIG. 3 , a high input voltage level is not detected, and thus the digital signals d_a2d_bst_high_comp and d_a2d_bst_higher_comp remain logic low throughout the period illustrated in the timing diagram 300 .

[0048] At time t 1 At 100 ms, the multi-mode power supply circuit detects a large input voltage noise / ripple event, so the digital signal d_a2d_bst_hpsrr_comp changes from logic low to logic high to enable PSRR regulation. This causes the FSM to temporarily enter active bypass mode, as indicated by the ldo_state_FSM signal, and then enter normal power mode (NPM) to turn on the post regulator circuit. Triggering PSRR regulation also activates the digital step control, as indicated by the ldo_state_FSM signal. Figure 3Ad_d2a_bst_step_ctl' in the digital digital-to-analog boost converter step control signal. As described above, step control can include: adjusting the margin of the regulator circuit (e.g., LDO). Margin adjustment using step control can be based on the type, amplitude and / or duration of the detected input voltage noise / ripple. The digital controller can also use step control to control the conversion rate of the margin adjustment.

[0049] There may be a delay (referred to as a "step delay") between entering active bypass mode (as indicated by ldo_state_FSM) and the first step adjustment indicated by d_d2a_bst_step_ctl. The digital controller may control this delay based on input supply voltage (e.g., VPH_PWR) conditions to ensure smooth transitions between modes. The delay may be based on a warm-up time for the analog circuitry.

[0050] Eventually, the large input voltage noise / ripple event may end and no longer be detected by the multi-mode power supply circuit and thus at time t 2 At d_a2d_bst_hpsrr_comp goes from logic high to logic low to disable PSRR regulation. This may cause exiting margining by step control, as indicated by d_d2a_bst_step_ctl. For some aspects, the FSM may then enter bypass mode by disabling the post regulator circuit. To avoid premature return to bypass mode for other aspects, the FSM may delay exiting normal power mode for a period of time, referred to herein as a “blanking time” (which is in Figure 3A In this case, the FSM may exit the blanking time at time t unless another input voltage event is detected during the blanking time. 3 Enter bypass mode.

[0051] exist Figure 3B In the timing diagram 350 of FIG. 1 , the post regulator circuit (e.g., LDO) is initially operating in a bypass mode (BPM) as indicated by the ldo_state_FSM with a particular switching frequency of the SMPS circuit (e.g., a switching frequency state labeled “CLK_DIV”), as indicated by the digital switching frequency signal (labeled “FSW”). Figure 3B In the scenario of , no large input voltage noise / ripple event is detected, so d_a2d_bst_hpsrr_comp remains logic low throughout the period illustrated in timing diagram 350 .

[0052] At time t aAt time t, the multi-mode power supply circuit detects a high input voltage level event, so the d_a2d_bst_high_comp signal changes from logic low to logic high to enable high input voltage regulation. This rising edge may cause the FSM to temporarily enter active bypass mode and then enter normal power mode (NPM) to activate the post regulator circuit, as indicated by the ldo_state_FSM signal. At time t b At this point, the multi-mode power supply circuit detects a higher input voltage level event, so the d_a2d_bst_higher_comp signal changes from logic low to logic high. The rising edge of the d_a2d_bst_higher_comp signal triggers the digital step control, such as Figure 3B The digital controller can also use step control to control the slew rate of margin adjustment.

[0053] There may be a delay (referred to as a "step delay") between entering active bypass mode (as indicated by ldo_state_FSM) and the first step adjustment indicated by d_d2a_bst_step_ctl. The digital controller may control this delay based on input supply voltage (e.g., VPH_PWR) conditions to ensure smooth transitions between modes. The delay may be based on a warm-up time for the analog circuitry.

[0054] In timing diagram 350, the rising edge of the d_a2d_bst_higher_comp signal may also trigger the enabling or adjustment of the clamp circuit, as indicated by the falling edge of the digital digital-to-analog boost converter clamp source select signal (labeled "d_d2a_bst_clamp_src_sel"). After adjusting the clamp circuit, the switching frequency of the SMPS circuit may be adjusted (e.g., reduced) to a different switching frequency (e.g., to a switching frequency state labeled "CLK_DIV_VPH_HIGH") as indicated by the FSW signal. There may be a delay (labeled "SEL_CLK_DIV_VPH_HIGH_DLY") between triggering the clamp circuit (as indicated by d_d2a_bst_clamp_src_sel) and the switching frequency adjustment indicated by the FSW signal. This delay may also be controlled by the digital controller.

[0055] Eventually, the high input voltage level may begin to decrease (e.g., after unplugging the wall adapter). When the multi-mode power supply circuit no longer detects the higher input voltage level, the d_a2d_bst_vph_higher_comp signal is asserted at time t cAs the high input voltage level continues to decrease, the multi-mode power supply circuit may no longer detect the high input voltage level and at time t d At d_a2d_bst_vph_high_comp, the d_a2d_bst_vph_high_comp signal goes from logic high to logic low to disable high input voltage regulation. This may cause exiting margining by step control, as indicated by d_d2a_bst_step_ctl. For some aspects, the FSM may then enter bypass mode by disabling the post regulator circuit. To avoid premature return to bypass mode for other aspects, as described above, the FSM may delay exiting normal power mode by the blanking time (which is in Figure 3B The blanking time associated with high input voltage regulation can be the same as or different from the blanking time associated with high PSRR regulation. Unless another input voltage event is detected during the blanking time, the FSM may exit at time t e Enter bypass mode, such as Figure 3B In addition, at time t e At this point, the clamp circuit can be disabled or returned to its previous state, as indicated by the rising edge of the d_d2a_bst_clamp_src_sel signal, and the switching frequency can return to the CLK_DIV state, as indicated by the rising edge of the d_d2a_bst_clamp_src_sel signal. Figure 3B As indicated by the FSW signal in.

[0056] Figure 4 4 is a timing diagram 400 of various signals associated with an example multi-mode power supply circuit (e.g., circuit 200) during an overshoot of a power supply input voltage (e.g., VPH_PWR) according to certain aspects of the present disclosure. For example, the overshoot may be caused by plugging in a wall adapter. Timing diagram 400 illustrates adaptive switch (SW) frequency adjustment and clamping enablement. If VPH_PWR overshoots to a certain voltage level (e.g., 4.8V) or higher, for a shunt transistor (e.g., transistor 211) in the SMPS topology, the SMPS (e.g., boost converter) may be disabled due to, for example, a minimum on-time (e.g., 12ns, as shown in FIG. 4 ). Figure 4 In this case, the VMID voltage (which is Figure 2 By means of a digital controller (e.g., digital control circuit 260), when such a condition is detected, the switching frequency (as illustrated by the switching frequency clock signal labeled “SW_CLK”) can be immediately reduced to have a similarly smaller duty cycle (as illustrated by the switching frequency clock signal labeled “SW_CLK”). Figure 4) and maintain regulation. At the same time, the digital controller can enable the internal clamp circuit (as indicated by the clamp source select signal labeled "Clamp_SRC_SEL", the clamp voltage signal, and the Vc signal) to enable the analog circuit system to recover faster. Similarly, when VPH_PWR returns to a normal voltage level (e.g., increasing the switching frequency), a similar but opposite behavior can be used on the exit edge.

[0057] Figure 5 5 is a timing diagram 500 of digital signals associated with an example multi-mode power supply circuit (e.g., circuit 200) during a large input voltage noise / ripple event (also referred to herein as a High_PSRR event) in accordance with certain aspects of the present disclosure, illustrating blanking and cooldown timer behavior. A High_PSRR event is detected when the d_a2d_bst_high_psrr_comp signal is asserted. A digital controller (e.g., digital control circuit 260) may change a post regulator circuit (e.g., LDO) from a bypass mode (BYP) to a normal power mode (NPM), may assert a digital controller signal (labeled “d_pbs_hpsrr_req”) indicating that the post voltage regulator circuit is in NPM, and may start a blanking timer. The post regulator circuit remains in NPM as long as the blanking timer is running. When the blanking time is complete, the cooldown timer is started while still keeping the post voltage regulator circuit in NPM. During the cooldown time, if any new event request is received (e.g., during Figure 5 If a new request is received during the cooling cycle (as indicated in the first cooling period in ), the request is latched and at the end of the cooling time, a new cycle of blanking and subsequent cooling time is restarted. Figure 5 ), the d_pbs_hpsrr_req signal is de-asserted and the post-regulator circuit moves from NPM to BYP, as illustrated.

[0058] Figure 6 According to certain aspects of the present disclosure, Figure 2600 of a programmable regulation point offset circuit for a multi-mode power supply circuit 200. As shown in the multi-mode power supply circuit 200, only one feedback point can be used for the SMPS loop and the post-regulator loop in BYP and NPM, respectively. When the post-regulator circuit has a mode transition (e.g., from BYP to NPM), the initial condition of the post-regulator error amplifier 601 (e.g., in the post-regulator control circuit 252) is uncertain due to the mismatch of the two loops. As a result, the transient behavior of the post-regulator may overshoot or undershoot. Using the circuit diagram 600, a digital controller (e.g., the digital control circuit 260) can force the regulation point of the post-regulator to be slightly higher than the input, thereby forcing the starting point to exhibit an overshoot. For the post-regulator feedback, this can be achieved by adjusting the programmable reference voltage 603 of the error amplifier 601 in the post-regulator and / or closing a switch 606 across a resistor element 248 in the second voltage divider 246. The digital controller can then change the regulation point back to the desired point after a short delay time (e.g., by opening the previously closed switch 606). To minimize overshoot, the current sink 610 can also be turned on or otherwise enabled during this initial period to absorb additional power. This temporary activation of the current sink 610 can be achieved by closing the switch 608 in series with the current sink, where the series combination of the current sink 610 and the switch 608 is coupled in parallel with the second voltage divider 246 to achieve post-regulator feedback. Figure 6 As shown.

[0059] The circuit diagram 600 also includes a resistive element 602 (labeled "Rfb_h") connected in series with the switch 241 and the first voltage divider 242. The resistance of the resistive element 602 is comparable (e.g., within a tolerance of 5%) to the on-resistance of the transistor 224 in the post-regulator circuit and can be used to compensate for or at least adjust the current*resistance (IR) drop across the transistor 224 when the output voltage of the SMPS circuit is sensed using the first voltage divider 242 during the bypass mode.

[0060] Although Vreg_ELVDD and FB_ELVDD are Figure 2 and Figure 6 , but the two nodes may be shorted or otherwise coupled together in a load circuit (not shown) for the multi-mode power supply circuit. For example, the load circuit may be located on a printed circuit board (PCB) on which the multi-mode power supply circuit is disposed.

[0061] Fig. 7Ais a block diagram of an example circuit 700 for large input voltage noise / ripple event detection (e.g., high PSRR regulation event detection) according to certain aspects of the present disclosure. As illustrated, the ripple of VPH_PWR is sensed by two differential sample-and-hold (S / H) circuits 702. The peak signal and the valley signal are the maximum voltage value and the minimum voltage value of VPH_PWR in a certain period of time, respectively. The sampled difference between the peak signal and the valley signal represents the maximum ripple of VPH_PWR. If the ripple is above a threshold voltage (which is labeled “V comp ”), a digital signal (for example, High_PSRR_Comp) is triggered.

[0062] Figure 7B 7 is a block diagram of an example circuit system 750 for high input voltage level event detection (e.g., high VPH_PWR event detection) according to certain aspects of the present disclosure. For example, a load release of a charger may cause VPH_PWR to overshoot to 5.25V within 10μs to 100μs. Moreover, during battery charging, the DC value of VPH_PWR may slowly increase to 4.8V. Two signals are used to detect a high VPH_PWR event: (1) Vph_high is used to warm up the analog circuit system or tell the digital controller to keep the post regulator (e.g., LDO) in NPM if the post regulator is already in NPM; and (2) Vph_higher is used to determine whether an actual high VPH_PWR event is occurring. Vph_higher can be triggered if VPH_PWR is greater than a first threshold voltage (labeled as "Vref"), and Vph_high can be triggered if VPH_PWR is greater than a second threshold voltage (labeled as "Voffset"), which is a specific amount lower than the first threshold voltage.

[0063] The multi-mode power supply circuit described in this article adapts to the strict performance constraints of high PSRR regulation and VPH_PWR overshoot. Under normal conditions, the efficiency may be as high as a switch mode power supply circuit (e.g., a boost converter, whose peak efficiency may be as high as about 96% to 97%). In the LDO normal power mode, the PSRR of the multi-mode power supply circuit can be enhanced from 20dB to 50dB at a frequency of 10kHz, for example. When the VPH_PWR overshoot is higher than 4.6V, the boost converter can still maintain regulation, and the overall efficiency may remain above 85%. This figure is significantly higher than off-the-shelf products that typically operate in asynchronous mode (about 10% higher).

[0064] Certain aspects of the present disclosure provide a power supply circuit (e.g., multi-mode power supply circuit 200). The power supply circuit generally includes a switch mode power supply (SMPS) circuit (e.g., SMPS circuit 202); a voltage regulator circuit (e.g., post-regulator circuit 204) having an input coupled to an output of the SMPS circuit, the voltage regulator circuit being selectively enabled; a first voltage divider (e.g., first voltage divider 242) selectively coupled to the output of the SMPS circuit and selectively coupled to the output of the voltage regulator circuit; and a second voltage divider (e.g., second voltage divider 246) coupled to the output of the voltage regulator circuit.

[0065] According to certain aspects, the power supply circuit further includes a switch (e.g., switch 606) coupled in parallel with at least one resistive element (e.g., resistive element 248) of the second voltage divider. For certain aspects, the power supply circuit further includes a current source (e.g., current sink 610) selectively coupled in parallel with the second voltage divider.

[0066] According to certain aspects, a SMPS circuit includes a boost converter circuit.

[0067] According to certain aspects, the voltage regulator circuit includes a low dropout (LDO) regulator circuit. For certain aspects, the LDO regulator circuit includes a transistor (e.g., transistor 224) having a drain and a source, the drain coupled to an input of the voltage regulator circuit, the source coupled to an output of the voltage regulator circuit; a voltage reference (e.g., reference voltage 603); and an error amplifier (e.g., error amplifier 601) having an output, a first input, and a second input, the output coupled to a gate of the transistor, the first input coupled to the voltage reference, and the second input coupled to a tap of a second voltage divider (e.g., tap node 249). For certain aspects, the power supply circuit also includes logic (e.g., post-regulator control circuit 252) configured to disable the LDO regulator circuit by operating the transistor in a saturation mode. For certain aspects, the power supply circuit also includes a third switch (e.g., switch 241) coupled between the output of the SMPS circuit and the first voltage divider; and a fourth switch (e.g., switch 245) coupled between the output of the voltage regulator circuit and the first voltage divider. In this case, the power supply circuit may further include logic (e.g., digital control circuit 260 and / or post-regulator control circuit 252) configured to: (1) close the third switch and open the fourth switch if the voltage regulator circuit is disabled; and (2) open the third switch and close the fourth switch if the voltage regulator circuit is enabled. For certain aspects, the power supply circuit further includes a resistive element coupled between the output of the SMPS circuit and the third switch. In this case, the resistance of the resistive element may be equal to the on-resistance of the transistor (e.g., R DS_on) corresponds to (e.g., matches within 5% or 10%).

[0068] Certain aspects of the present disclosure provide a power management integrated circuit (PMIC) (eg, PMIC 124 ) that includes at least a portion of the power supply circuit described above.

[0069] Certain aspects of the present disclosure provide a battery charging circuit, which includes the power supply circuit described above.

[0070] Figure 8 8 is a flow chart of example operations 800 for power regulation in a multi-mode power circuit according to certain aspects of the present disclosure. Operations 800 may be performed, for example, by Figure 2 or Figure 6 The multi-mode power supply circuit 200 may include a switch mode power supply (SMPS) circuit (eg, SMPS circuit 202) having an output coupled to an input of a voltage regulator circuit (eg, post-regulator circuit 204).

[0071] Operations 800 may begin at block 802, where the multi-mode power supply circuit detects a high input voltage event. At block 804, the multi-mode power supply circuit may enable a voltage regulator circuit based on the detection at block 802. At block 806, the multi-mode power supply circuit may temporarily increase the regulation point of the voltage regulator circuit to above the input voltage at the input of the voltage regulator circuit. At block 808, the multi-mode power supply circuit may reduce the regulation point of the voltage regulator circuit after a delay.

[0072] According to certain aspects, increasing the regulation point of the voltage regulator circuit at block 806 may include closing a first switch (e.g., switch 606) coupled in parallel with at least one resistive element (e.g., resistive element 248) of a voltage divider (e.g., second voltage divider 246) coupled to an output (e.g., Vreg_ELVDD) of the voltage regulator circuit. In this case, decreasing the regulation point may require opening the first switch coupled in parallel with the voltage divider. For certain aspects, increasing the regulation point of the voltage regulator circuit at block 806 also includes: (1) enabling a current sink (e.g., current sink 610) coupled to the output of the voltage regulator circuit; or (2) closing a second switch (e.g., switch 608) in series with the current sink to couple the current sink to the output of the voltage regulator circuit.

[0073] According to certain aspects, increasing a regulation point of a voltage regulator circuit includes adjusting a reference voltage (eg, reference voltage 603 ) for the voltage regulator circuit.

[0074] According to certain aspects, the high input voltage event includes a large input voltage noise / ripple event for a multi-mode power supply circuit.

[0075] According to certain aspects, the high input voltage event comprises a high input voltage level event for a multi-mode power supply circuit.

[0076] According to certain aspects, operation 800 further includes the multi-mode power supply circuit detecting that the high input voltage event has ended, and disabling the voltage regulator circuit based on detecting that the high input voltage event has ended.

[0077] Certain aspects of the present disclosure provide an apparatus for supplying power via multi-mode. The apparatus generally includes components for supplying power via switching regulation (e.g., an SMPS, such as SMPS circuit 202); components for regulating the voltage from the components for supplying power (e.g., a voltage regulator, such as an LDO or post-regulator circuit 204); components for detecting high input voltage events in the apparatus (e.g., voltage divider 242 and / or voltage divider 246); components for enabling components for regulating voltage based on detection (e.g., a control circuit, such as post-regulator control circuit 252 and / or error amplifier 601 ... Components for temporarily increasing the regulation point of a component for regulating voltage to be higher than the voltage from the component for powering (e.g., a programmable voltage source such as programmable reference voltage 603, a current sink such as current sink 610, and / or a switch such as switch 606); and components for reducing the regulation point of a component for regulating voltage after a delay (e.g., a programmable voltage source such as programmable reference voltage 603, a current sink such as current sink 610, and / or one or more switches such as switch 606 and / or switch 608).

[0078] According to certain aspects, the apparatus further comprises means for dividing a voltage output from the means for regulating a voltage from the means for supplying power (e.g., voltage divider 246). For certain aspects, the means for temporarily increasing the regulation point may comprise means for selectively short-circuiting at least one element of the means for dividing (e.g., resistor element 248) (e.g., switch 606). In this case, the means for reducing the regulation point may comprise means for selectively short-circuiting at least one element of the means for dividing. For certain aspects, the means for temporarily increasing the regulation point of the means for regulating voltage further comprises means for sinking current from the output of the means for regulating voltage (e.g., ELVDD_Vreg) (e.g., current sink 610 and / or switch 608).

[0079] According to certain aspects, the means for temporarily increasing the regulation point includes means for adjusting a reference voltage (eg, programmable reference voltage 603) of means for regulating a voltage from means for supplying power.

[0080] According to certain aspects, a high input voltage event includes a large input voltage noise / ripple event.

[0081] According to certain aspects, the high input voltage event comprises a high input voltage level event.

[0082] According to certain aspects, the apparatus also includes components for detecting that a high input voltage event has ended (e.g., voltage divider 242 and / or voltage divider 246); and components for regulating voltage based on detection that a high input voltage event has ended (e.g., control circuitry, such as post-regulator control circuitry 252 and / or error amplifier 601).

[0083] The various operations of the methods described above may be performed by any suitable device capable of performing the corresponding functions. The device may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. Typically, where operations are illustrated in the accompanying drawings, those operations may have corresponding counterparts with similarly numbered device-plus-function components.

[0084] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), confirming, etc. In addition, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. In addition, "determine" may include resolving, selecting, choosing, establishing, etc.

[0085] As used herein, a phrase indicating "at least one" of a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0086] The method disclosed herein includes one or more steps or actions for implementing the described method. Without departing from the scope of the claims, the method steps and / or actions can be interchangeable with each other. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions can be modified without departing from the scope of the claims.

[0087] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A power supply circuit, comprising: Switching mode power supply SMPS circuit, including SMPS control circuit; a voltage regulator circuit having an input coupled to an output of the SMPS circuit, the voltage regulator circuit being selectively enabled, the voltage regulator circuit including a voltage regulator control circuit; a first voltage divider selectively coupled to the output of the SMPS circuit and selectively coupled to the output of the voltage regulator circuit, the first voltage divider including a top terminal connected to the output of the SMPS circuit, a bottom terminal connected to ground, and a tap node connected to the SMPS control circuit; as well as a second voltage divider coupled to the output of the voltage regulator circuit, the second voltage divider including a top terminal connected to the output of the voltage regulator circuit, a bottom terminal connected to ground, and a tap node connected to the voltage regulator control circuit; a first switch coupled in parallel with at least one resistive element of the second voltage divider; a current source selectively coupled in parallel with the second voltage divider; as well as A second switch is coupled in series with the current source. 2 . The power supply circuit of claim 1 , wherein the SMPS circuit comprises a boost converter circuit. 3 . The power supply circuit of claim 1 , wherein the voltage regulator circuit comprises a low dropout (LDO) regulator circuit.

4. The power supply circuit according to claim 3, wherein the LDO regulator circuit comprises: a transistor having a drain and a source, the drain coupled to the input of the voltage regulator circuit and the source coupled to the output of the voltage regulator circuit; Voltage reference; as well as An error amplifier has an output, a first input coupled to the gate of the transistor, and a second input coupled to the tap of the second voltage divider. 5 . The power supply circuit of claim 4 , further comprising logic configured to disable the LDO regulator circuit by operating the transistor in a saturation mode.

6. The power supply circuit according to claim 4, further comprising: a third switch coupled between the output of the SMPS circuit and the first voltage divider; as well as A fourth switch is coupled between the output of the voltage regulator circuit and the first voltage divider.

7. The power supply circuit of claim 6, further comprising logic configured to: If the voltage regulator circuit is disabled, closing the third switch and opening the fourth switch; and If the voltage regulator circuit is enabled, the third switch is opened and the fourth switch is closed.

8. The power supply circuit of claim 6, further comprising a resistive element coupled between the output of the SMPS circuit and the third switch. 9 . The power supply circuit according to claim 8 , wherein a resistance of the resistance element corresponds to an on-resistance of the transistor. 10 . A power management integrated circuit (PMIC), comprising the power supply circuit according to claim 1 .

11. A method of operating a multi-mode power supply circuit, comprising: detecting a high input voltage event in the multi-mode power supply circuit, the multi-mode power supply circuit comprising a switch mode power supply (SMPS) circuit having an output coupled to an input of a voltage regulator circuit; enabling the voltage regulator circuit based on the detecting; temporarily increasing a regulation point of the voltage regulator circuit to above an input voltage at the input of the voltage regulator circuit, wherein increasing the regulation point of the voltage regulator circuit comprises: closing a first switch coupled in parallel with at least one resistive element of a voltage divider coupled to an output of the voltage regulator circuit, wherein increasing the regulation point of the voltage regulator circuit further comprises: enabling a current sink coupled to the output of the voltage regulator circuit; or closing a second switch in series with the current sink to couple the current sink to the output of the voltage regulator circuit; and After a delay, the regulation point of the voltage regulator circuit is decreased.

12. The method of claim 11, wherein reducing the settling point comprises: The first switch is opened, the first switch being coupled in parallel with the voltage divider.

13. The method of claim 11 , wherein increasing the regulation point of the voltage regulator circuit comprises: A reference voltage of the voltage regulator circuit is adjusted.

14. The method of claim 11, wherein the high input voltage event comprises a large input voltage noise / ripple event.

15. The method of claim 11, wherein the high input voltage event comprises a high input voltage level event.

16. The method according to claim 11, further comprising: detecting that the high input voltage event has ended; as well as The voltage regulator circuit is disabled based on the detecting that the high input voltage event has ended.

17. An apparatus for supplying power via multiple modes, comprising: Means for supplying power via switching regulation; means for regulating the voltage from said means for supplying power; means for detecting a high input voltage event in said device; means for enabling said means for regulating said voltage based on said detecting; means for temporarily increasing a regulation point of said means for regulating said voltage above said voltage from said means for supplying power; means for reducing the regulation point of the means for regulating the voltage after a delay; as well as means for dividing a voltage output from the means for regulating the voltage from the means for supplying power, wherein the means for temporarily increasing the regulation point comprises means for selectively short-circuiting at least one element of the means for dividing, and wherein the means for temporarily increasing the regulation point of the means for regulating the voltage further comprises means for sinking current from the output of the means for regulating the voltage.

18. The apparatus of claim 17, wherein the means for reducing the regulation point comprises means for selectively short-circuiting the at least one element of the means for partitioning.

19. The apparatus of claim 17, wherein the means for temporarily increasing the regulation point comprises means for adjusting a reference voltage of the means for regulating the voltage from the means for supplying power.

20. The apparatus of claim 17, wherein the high input voltage event comprises a large input voltage noise / ripple event.

21. The apparatus of claim 17, wherein the high input voltage event comprises a high input voltage level event.

22. The apparatus of claim 17, further comprising: means for detecting that the high input voltage event has ended; as well as Means for disabling the means for regulating the voltage based on detecting that the high input voltage event has ended.

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