Method for manufacturing a MOSFET having an undoped channel

Abstract

The present invention discloses a method for manufacturing a MOSFET with an undoped channel. The method includes: manufacturing a semiconductor structure with a pseudo polysilicon gate, a pseudo interlayer (IL) oxide and a doped channel on a substrate. The method also includes removing the pseudo polysilicon gate and the pseudo IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the above-mentioned area on the substrate, and forming a metal gate for the semiconductor structure. Removing the pseudo polysilicon gate may include dry and wet etching operations. Removing the pseudo IL oxide may include dry etching operations. Removing the doped channel may include performing an anisotropic etching operation on the substrate. Forming the undoped channel may include using an epitaxial process to grow the undoped channel. The method may also include growing IL oxide above the undoped channel.

Description

[0001] The present application is a divisional application of the invention patent application entitled “Method for manufacturing a MOSFET having an undoped channel” with application number 201410386121.4 filed on August 7, 2014. Technical Field

[0002] The present invention relates to the field of semiconductors, and more particularly, to a method for manufacturing a MOSFET having an undoped channel. Background Art

[0003] The technology described in this patent document relates to metal oxide semiconductor field effect transistors (MOSFETs), and more particularly to channel designs for HKMG CMOS (High-K Metal Gate Complementary Metal Oxide Semiconductor) devices.

[0004] Scaling of semiconductor devices (eg, MOSFETs) has resulted in continuous improvements in speed, performance, density, and cost of unit functions per integrated circuit over the past several decades. Improvements in the process of building transistor channels have facilitated the scaling of integrated circuits.

[0005] MOSFETs can be manufactured on bulk semiconductor substrates (planar devices) or silicon-on-insulator (SOI) structures. In the gate replacement process, the dummy gate structure can be composed of, for example, polysilicon (poly). After the source-drain (S / D) processing begins or continues, the dummy gate structure is removed and replaced with a conductive metal-containing gate stack that covers the channel region between the S / D in the bulk semiconductor substrate or the channel region between the S / D in the silicon layer of the SOI structure. Summary of the invention

[0006] The present invention provides a method for manufacturing a MOSFET with an undoped channel, the method comprising: manufacturing a semiconductor structure with a pseudo polysilicon gate, a pseudo interlayer (IL) oxide and a doped channel on a substrate; removing the pseudo polysilicon gate and the pseudo IL oxide to expose the doped channel; removing the doped channel from an area on the substrate; forming an undoped channel for the semiconductor structure at the area on the substrate; and forming a metal gate for the semiconductor structure.

[0007] Preferably, the removing of the dummy polysilicon gate comprises dry and wet etching operations to remove the dummy polysilicon gate.

[0008] Preferably, the removing the dummy IL oxide comprises a dry etching operation to remove the dummy IL oxide.

[0009] Preferably, the removing of the doped channel comprises performing an anisotropic etching operation on the substrate.

[0010] Preferably, forming the undoped channel comprises growing the undoped channel by an epitaxial process.

[0011] Preferably, the method of manufacturing a MOSFET having an undoped channel further comprises growing an IL oxide on the undoped channel by using a wet chemical method on the undoped channel.

[0012] Preferably, the removing the dummy IL oxide comprises performing an etching operation both before and after removing the doped channel.

[0013] According to another aspect of the present invention, the present invention also provides a method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel, the method comprising: removing a pseudo polysilicon gate and a pseudo interlayer (IL) oxide to expose the doped channel; removing the doped channel from an area on the substrate; and growing an undoped channel for the semiconductor structure at the area on the substrate.

[0014] Preferably, the removing of the dummy polysilicon gate comprises dry and wet etching operations to remove the dummy polysilicon gate.

[0015] Preferably, the removing of the dummy IL oxide comprises a dry etching operation to remove the dummy IL oxide.

[0016] Preferably, the removing of the doped channel comprises performing an anisotropic etching operation on the substrate.

[0017] Preferably, growing the undoped channel includes using an epitaxial process to grow the undoped channel.

[0018] Preferably, the method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel further comprises growing an IL oxide on the undoped channel by a wet chemical method.

[0019] Preferably, the removing of the dummy IL oxide comprises performing an etching operation both before and after removing the doped channel.

[0020] According to another aspect of the present invention, the present invention provides a semiconductor structure formed above a doped well in a substrate and having an undoped channel region, the semiconductor structure comprising: a source and a drain region located in the substrate; an undoped channel region located in the doped well in the substrate, the undoped channel region being connected between the source and the drain regions; and a gate stack fabricated above the undoped channel region; wherein the undoped channel region is formed by removing a pseudo polysilicon gate and a pseudo interlayer (IL) oxide to expose the doped channel region in the doped well, removing the doped channel region from the substrate, and growing an undoped channel region in the doped well to replace the doped channel region.

[0021] Preferably, the dummy polysilicon gate is removed using dry and wet etching operations.

[0022] Preferably, the dummy IL oxide is removed using a dry etching operation.

[0023] Preferably, the doped channels are removed using an anisotropic etching operation.

[0024] Preferably, the undoped channel is grown using an epitaxial process.

[0025] Preferably, the dummy IL oxide is removed by performing etching operations both before and after removing the doped channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The scheme of the present disclosure can be best understood based on the following detailed description and reading the accompanying drawings at the same time. It is worth noting that, according to standard practice in the industry, the various components are not drawn to scale. In fact, the size of each component can be arbitrarily increased or reduced for clarity of description.

[0027] Figure 1A is a schematic diagram of an exemplary transistor showing that practical doping techniques may leave a non-uniform concentration of impurities in the channel region of the transistor;

[0028] Figure 1B is a schematic diagram of an exemplary transistor in which impurities from a practical doping technique have been removed from at least a portion of a channel region of the transistor, according to some embodiments;

[0029] Figure 2 is a process flow diagram describing an exemplary method for producing a semiconductor device having an undoped channel according to some embodiments;

[0030] Figure 3 depicts a cross-sectional view of an exemplary semiconductor structure after partial fabrication according to some embodiments;

[0031] Figure 4depicts a cross-sectional view of an exemplary semiconductor structure after removal of a dummy polysilicon gate according to some embodiments;

[0032] Figure 5 depicts a cross-sectional view of an exemplary semiconductor structure after removal of dummy IL oxide according to some embodiments;

[0033] Figure 6 depicts a cross-sectional view of an exemplary semiconductor structure after removal of a channel from a particular region on a substrate in accordance with some embodiments;

[0034] Figure 7 depicts a cross-sectional view of an exemplary semiconductor structure after removing additional dummy IL oxide from the dummy IL oxide according to some embodiments;

[0035] Figure 8 depicts a cross-sectional view of an exemplary semiconductor structure after forming a new undoped channel according to some embodiments;

[0036] Fig. 9 Depicted is a cross-sectional view of an exemplary semiconductor structure after IL oxide regrowth in accordance with some embodiments. DETAILED DESCRIPTION

[0037] The following disclosure provides a plurality of different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and devices are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the first component described later formed above the second component or on the second feature may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or terms in multiple instances. This repetition is intended to simplify and clarify, which itself determines the association between the multiple instances and / or structures discussed.

[0038] Additionally, spatially relative terms, such as "below," "beneath," "below," "above," "over," etc., may be used herein for simplicity of description to describe the relationship of one element or component to another element or components shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0039] Well doping, light drain doping (LDD) and pocket doping are practical doping techniques that may be used in semiconductor production processes. In some cases, such as with short channel devices, these practical doping techniques can complicate carrier transport and reduce global / local threshold voltage (Vt) uniformity due to random doping fluctuations (RDF). Figure 1A is a schematic diagram of an exemplary transistor illustrating that practical doping techniques may leave a non-uniform concentration of impurities 10 in the channel region of the transistor, which can complicate carrier transport and degrade global / local Vt uniformity.

[0040] Figure 1B , a schematic diagram of a transistor is depicted in which impurities from a practical doping technique are removed from at least a portion of the channel region 12 of the transistor. The transistor after the impurities are removed from the channel region 12 (i.e., a transistor with a clean channel) will achieve better Vt uniformity and better performance. The following example describes an exemplary technique for fabricating a semiconductor device with a clean channel even when practical doping is used.

[0041] Figure 2 1 is a process flow chart describing an exemplary method for producing a semiconductor device with an undoped channel. The method begins with manufacturing a semiconductor structure having a pseudo polysilicon gate, a pseudo interlayer (IL) oxide, and a doped channel on a substrate (operation 102). After this initial manufacturing, the pseudo polysilicon gate is removed (operation 104) to expose the doped channel to be removed. In the present example, removing the pseudo polysilicon gate includes dry etching and wet etching operations (operation 204). After removing the pseudo polysilicon gate, a pseudo IL oxide removal operation (operation 106) may be started. In the present example, removing the pseudo IL oxide includes a dry etching operation (operation 206). Then, removing the channel from the region on the substrate (operation 108) is performed. In the present example, the channel removal operation may include anisotropic etching the silicon substrate using a low etching rate to prevent damage to the source-drain region (operation 208). Additional pseudo IL oxide may be removed (operation 110). Removing additional pseudo oxide may be completed by a second pseudo IL etching operation (operation 210). A new undoped channel is formed in an area on the wafer that previously existed due to the doped channel that has been removed (operation 112). In the present example, the new channel formation is completed by an epitaxial growth process (operation 212). After the new channel is grown, the IL oxide can be regrown on the new channel area (operation 114). In the present example, the IL oxide re-growth is completed by using a wet chemical method on the new undoped Si channel (operation 214). After the IL is regrown, a metal gate can be formed (operation 116). In the present example, forming the metal gate includes a high dielectric constant (Hi-k) deposition operation and a metal gate deposition operation (operation 216).

[0042] Figures 3 to 9 Cross-sectional views of exemplary semiconductor structures at various stages of fabrication are depicted. Figure 3 A cross-sectional view of an exemplary semiconductor structure after partial fabrication is depicted. The exemplary semiconductor structure includes an n-channel MOSFET (NFET) 302 and a p-channel MOSFET (PFET) 304 separated by shallow trench isolation (STI) 306. The NFET 302 and the PFET 304 are both formed over a doped well in a substrate. The NFET 302 includes source and drain regions 310 formed over a doped well 312 in the substrate, a channel region 314 in the doped well 312, a pseudo-polysilicon gate 316, and a pseudo-IL oxide 318. The PFET 304 includes source and drain regions 320 formed over a doped well 322 in the substrate, a channel region 324 in the doped well 322, a pseudo-polysilicon gate 326, and a pseudo-IL oxide 328. The exemplary semiconductor structure also includes an interlayer dielectric layer (ILD0) 330 and a contact etch stop layer (CESL) 332 shared by both the NFET 302 and the PFET 304. The channel regions 314, 324 and doped wells 312, 322 in this example are formed of silicon (Si). The source and drain regions 310 of the NFET 302 in this example are composed of silicon phosphorus (SiP). The source and drain regions 320 of the PFET 304 in this example are formed of silicon germanium (SiGe).

[0043] Figure 4 A cross-sectional view of the exemplary semiconductor structure after removal of the dummy polysilicon gate is depicted. Holes 334, 336 are shown, where the dummy polysilicon gates previously existed in NEFT 302 and PFET 304, respectively. In the present example, removal of the dummy polysilicon gates includes dry and wet etching operations.

[0044] Figure 5 A cross-sectional view of the present exemplary semiconductor structure after removal of the dummy IL oxide is depicted. A reduced amount of dummy IL oxide 318, 328 is shown. In the present example, the dummy IL oxide 318, 328 has been removed using a dry etching operation.

[0045] Figure 6 A cross-sectional view of the exemplary semiconductor structure is depicted after the removal of the channel from specific regions 338, 340 on the substrate. In this example, the channel removal is performed by anisotropically etching the Si substrate using a low etch rate to prevent damage to the source-drain regions.

[0046] Figure 7 A cross-sectional view of the exemplary semiconductor structure after the remaining dummy IL oxide is removed is depicted. In the present example, the dummy IL oxide has been removed using a dry etching operation.

[0047] Figure 8 The cross-sectional view of the exemplary semiconductor structure after forming new undoped channels 342 and 344 in specific regions 338 and 340, respectively, is described. In the present example, the new channels 342 and 344 are formed by an epitaxial growth process. This results in two undoped channel regions 342 and 344 being located in the doped well regions 312 and 322 in the substrate, respectively. The undoped channel regions 342 and 344 are connected between the source and drain regions 310 and 320 of the corresponding transistors, respectively.

[0048] Fig. 9 A cross-sectional view of the exemplary semiconductor structure is depicted after regrowth of the IL oxide 346, 348 over the new channel regions 342, 344. In the present example, the IL oxide 346, 348 is grown by wet chemical methods on the new undoped Si channel regions 342, 344. After regrowth of the IL oxide 346, 348, fabrication of the semiconductor structure may continue, including forming a gate stack over the undoped Si channel regions 342, 344 and other semiconductor fabrication operations.

[0049] The above examples provide a variety of techniques whereby a very lightly doped channel and better Vt uniformity can be obtained by regrowth of silicon (or other channel materials). The above examples illustrate techniques that can achieve high Vt uniformity required for sub-28nm integrated circuit (IC) devices. The new buried channel fabrication techniques disclosed herein can be fully combined with replacement metal gate techniques.

[0050] In one embodiment, a method for manufacturing a MOSFET with an undoped channel is disclosed. The method includes manufacturing a semiconductor structure having a pseudo polysilicon gate, a pseudo interlayer (IL) oxide, and a doped channel on a substrate. The method also includes removing the pseudo polysilicon gate and the pseudo IL oxide to expose the doped channel, removing the doped channel from an area on the substrate, forming an undoped channel for the semiconductor structure at the above-mentioned area on the substrate, and forming a metal gate for the semiconductor structure.

[0051] These aspects and other embodiments may include one or more of the following features. Removing the pseudo polysilicon gate may include dry and wet etching operations to remove the pseudo polysilicon gate. Removing the pseudo IL oxide may include a dry etching operation to remove the pseudo IL oxide. Removing the doped channel may include performing an anisotropic etching operation on the substrate. Forming the undoped channel may include using an epitaxial process to grow the undoped channel. The method may also include growing an IL oxide above the undoped channel by using a wet chemical method on the undoped channel. Removing the pseudo IL oxide may include performing an etching operation both before and after removing the doped channel.

[0052] In another embodiment, a method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel is disclosed. The method includes removing a dummy polysilicon gate and a dummy interlayer (IL) oxide to expose the doped channel, removing the doped channel from an area on the substrate, and growing an undoped channel for the semiconductor structure at the area on the substrate.

[0053] These aspects and other embodiments may include one or more of the following features. Removing the pseudo polysilicon gate may include dry and wet etching operations to remove the pseudo polysilicon gate. Removing the pseudo IL oxide may include a dry etching operation to remove the pseudo IL oxide. Removing the doped channel may include performing an anisotropic etching operation on the substrate. Growing the undoped channel may include using an epitaxial process to grow the undoped channel. The method may also include growing IL oxide above the undoped channel by using a wet chemical method on the undoped channel. Removing the pseudo IL oxide may include performing an etching operation both before and after removing the doped channel.

[0054] In another embodiment, a semiconductor device formed above a doped well in a substrate and having an undoped channel region is disclosed. The semiconductor device includes a source and drain region located in the substrate and an undoped channel region in the doped well in the substrate. The undoped channel region is connected between the source and drain regions. The semiconductor device also includes a gate stack fabricated above the undoped channel region. The undoped channel region is formed by removing a pseudo polysilicon gate and a pseudo interlayer (IL) oxide to expose the doped channel region in the doped well, removing the doped channel region from the substrate, and growing an undoped channel region in the doped well to replace the doped channel region.

[0055] These aspects and other embodiments may also include one or more of the following features. The pseudo polysilicon gate is removed using dry and wet etching operations. The pseudo IL oxide is removed using a dry etching operation. The doped channel is removed using an anisotropic etching operation. The undoped channel is grown using an epitaxial process. The pseudo IL oxide is removed by performing an etching operation both before and after removing the doped channel.

[0056] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or obtaining the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures should not deviate from the spirit and scope of the present disclosure, and they can make a variety of changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a MOSFET having an undoped channel, the method comprising: Fabricating a semiconductor structure having a dummy polysilicon gate, a dummy interlayer oxide, and a doped channel on a substrate; removing the pseudo polysilicon gate and a portion of the pseudo interlayer oxide to form a hole, wherein the hole exposes the doped channel; The portion of the pseudo interlayer oxide located on the sidewall and the bottom of the hole is retained, and the doped channel is removed from the area on the substrate using the retained pseudo interlayer oxide as a mask, wherein the lateral range of the removed doped channel extends beyond the lateral range enclosed by the retained pseudo interlayer oxide; removing the retained dummy interlayer oxide; After removing the remaining dummy interlayer oxide in which the hole is formed, forming an undoped channel for the semiconductor structure at the region on the substrate, wherein the undoped channel is directly above a doped well in the substrate; and forming a metal gate for the semiconductor structure, wherein removing the pseudo interlayer oxide comprises performing an etching operation both before and after removing the doped channel, The undoped channel has an inclined sidewall, and the width of the undoped channel gradually increases in a direction away from the substrate.

2. The method for manufacturing a MOSFET having an undoped channel according to claim 1, wherein: The removing of the dummy polysilicon gate includes dry and wet etching operations to remove the dummy polysilicon gate.

3. The method for manufacturing a MOSFET having an undoped channel according to claim 1, wherein: The removing of the dummy interlayer oxide comprises a dry etching operation to remove the dummy interlayer oxide.

4. The method for manufacturing a MOSFET having an undoped channel according to claim 1, wherein: The removing of the doped channel comprises performing an anisotropic etching operation on the substrate.

5. The method for manufacturing a MOSFET having an undoped channel according to claim 1, wherein: Forming the undoped channel includes growing the undoped channel using an epitaxial process. 6 . The method of manufacturing a MOSFET having an undoped channel according to claim 1 , further comprising growing an interlayer oxide over the undoped channel by applying a wet chemical method to the undoped channel.

7. A method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel, the method comprising: removing the dummy polysilicon gate and a portion of the dummy interlayer oxide to form a hole, wherein the hole exposes the doped channel; The portion of the pseudo interlayer oxide located on the sidewall and the bottom of the hole is retained, and the doped channel is removed from the area on the substrate using the retained pseudo interlayer oxide as a mask, wherein the lateral range of the removed doped channel extends beyond the lateral range enclosed by the retained pseudo interlayer oxide; removing the remaining dummy interlayer oxide; and After removing the remaining dummy interlayer oxide in which the hole is formed, growing an undoped channel for the semiconductor structure at the region on the substrate, wherein the undoped channel is directly above a doped well in the substrate, Wherein, removing the portion of the pseudo interlayer oxide comprises performing an etching operation both before and after removing the doped channel, The undoped channel has an inclined sidewall, and the width of the undoped channel gradually increases in a direction away from the substrate.

8. The method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel according to claim 7, wherein: The removing of the dummy polysilicon gate includes dry and wet etching operations to remove the dummy polysilicon gate.

9. The method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel according to claim 7, wherein: Removing the portion of the dummy interlayer oxide includes performing a dry etching operation to remove the dummy interlayer oxide.

10. The method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel according to claim 7, wherein: The removing of the doped channel comprises performing an anisotropic etching operation on the substrate.

11. The method for replacing a doped channel on a substrate in a semiconductor structure with an undoped channel according to claim 7, wherein: Growing the undoped channel includes using an epitaxial process to grow the undoped channel. 12 . The method of replacing a doped channel on a substrate in a semiconductor structure with an undoped channel according to claim 7 , further comprising growing an interlayer oxide on the undoped channel by a wet chemical method.

13. A semiconductor structure formed above a doped well in a substrate and having an undoped channel region, the semiconductor structure comprising: source and drain regions located in the substrate; an undoped channel region directly above the doped well in the substrate, the undoped channel region connected between the source and drain regions; as well as a second dummy interlayer oxide fabricated over the undoped channel region; a gate stack located above the second dummy interlayer oxide; wherein the undoped channel region is formed by removing the pseudo polysilicon gate and the first pseudo interlayer oxide to expose the doped channel region in the doped well, removing the doped channel region from the substrate, and growing an undoped channel region in the doped well to replace the doped channel region, and the undoped channel region laterally extends beyond the pseudo polysilicon gate, wherein the first pseudo interlayer oxide is removed by performing an etching operation both before and after removing the doped channel region, The undoped channel region has an inclined sidewall, and the width of the undoped channel region gradually increases in a direction away from the substrate. Wherein, the lateral extent of the undoped channel region extends beyond the lateral extent of the second dummy interlayer oxide.

14. The semiconductor structure formed above a doped well in a substrate and having an undoped channel region according to claim 13, wherein: The dummy polysilicon gate is removed using dry and wet etching operations.

15. The semiconductor structure formed in a substrate over a doped well and having an undoped channel region according to claim 13, wherein: The first dummy interlayer oxide is removed using a dry etching operation.

16. The semiconductor structure formed above a doped well in a substrate and having an undoped channel region according to claim 13, wherein: The doped channel region is removed using an anisotropic etching operation.

17. The semiconductor structure formed in a substrate over a doped well and having an undoped channel region according to claim 13, wherein: The undoped channel region is grown using an epitaxial process.

18. The semiconductor structure formed in a substrate over a doped well and having an undoped channel region according to claim 13, wherein: Fabricating the gate stack includes growing an interlayer oxide over the undoped channel region by applying a wet chemical process to the undoped channel region.

19. The semiconductor structure formed above a doped well in a substrate and having an undoped channel region according to claim 18, wherein: After growing the interlayer oxide, a metal gate is formed over the interlayer oxide.

20. The semiconductor structure formed in a substrate over a doped well and having an undoped channel region according to claim 13, wherein: The undoped channel region is formed of silicon.

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