Semiconductor structure and method for forming the same

Abstract

Embodiments of the present invention relate to semiconductor structures and methods for forming the same. According to some embodiments of the present invention, a semiconductor structure includes: a substrate; a first electrode located above the substrate; a second electrode located above the first electrode; and a first insulating layer interposed between the first and second electrodes. The first insulating layer includes a first portion and a second portion coupled to the first portion, the second portion of the first insulating layer contacts the second electrode, and the first portion is separated from the second electrode by the second portion. The second portion is thicker than the first portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure and a method for forming the same. Background Art

[0002] Integrated chips are formed on semiconductor dies that include millions or billions of transistor devices. The transistor devices are configured to act as switches and / or generate power gain to implement the logic functions of the integrated chip (e.g., the function of performing a logic function). Integrated chips also typically include passive devices such as capacitors, resistors, inductors, varactors, and the like. Passive devices are widely used to control integrated chip characteristics (e.g., gain, time constant, etc.) and to provide various different functions to the integrated chip (e.g., combining analog and digital circuits on the same die).

[0003] Among passive devices, capacitors including at least a top metal plate and a bottom metal plate separated by a capacitor dielectric, such as metal-insulator-metal (MIM) capacitors, are commonly implemented in integrated circuits. Summary of the Invention

[0004] According to an embodiment of the present invention, a semiconductor structure includes: a substrate; a first electrode located above the substrate; a second electrode located above the first electrode; and a first insulating layer located between the first electrode and the second electrode, wherein the first insulating layer has a first portion and a second portion coupled to the first portion, the second portion of the first insulating layer contacts the second electrode, the first portion is separated from the second electrode by the second portion, and the thickness of the second portion is greater than the thickness of the first portion.

[0005] According to an embodiment of the present invention, a semiconductor structure includes: a first electrode; a second electrode located above the first electrode; a third electrode located above the second electrode; a first insulating layer located between the first electrode and the second electrode; and a second insulating layer located between the second electrode and the third electrode; wherein the third electrode includes a first bottom surface and a second bottom surface, the first bottom surface and the second bottom surface are at different levels, and the width of the first bottom surface is greater than the width of the second bottom surface.

[0006] According to an embodiment of the present invention, a method for forming a semiconductor structure includes: receiving a substrate including a first electrode and a first insulating layer on the first electrode; forming a first conductive layer on the first insulating layer; removing a portion of the first conductive layer to form a patterned first conductive layer on the first insulating layer and exposing a first portion of the first insulating layer; and removing a portion of the patterned first conductive layer to form a second electrode and expose a second portion of the first insulating layer, wherein the thickness of the second portion of the first insulating layer is greater than the thickness of the first portion of the first insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a flow chart representing a method for fabricating a semiconductor structure according to aspects of an embodiment of the present invention.

[0009] Figures 2A to 2M is a schematic diagram illustrating a semiconductor structure at various stages of fabrication constructed according to aspects of one or more embodiments of the present invention. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples of the different features for implementing the provided target. Specific examples of elements and arrangements will be described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be directly contacted. In addition, embodiments of the present invention may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," and the like) may be used herein to describe the relationship of one element or component to another element or component, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0012] As used herein, although terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and "third" as used herein do not imply a sequence or order.

[0013] Although the numerical ranges and parameters describing the broad scope of the embodiments of the present invention are approximate, the numerical values described in the specific examples should be reported as accurately as possible. However, any numerical value inherently contains certain errors that are necessarily caused by the standard deviation present in the corresponding test measurements. In addition, as used herein, the terms "substantially," "approximately," or "about" generally mean within a value or range that one skilled in the art would consider. Alternatively, the terms "substantially," "approximately," or "approximately" mean within an acceptable standard deviation of the mean value considered by one skilled in the art. One skilled in the art will appreciate that acceptable standard deviations can vary depending on the technology. Except in the operating / working examples or unless otherwise expressly stated, all numerical ranges, quantities, values, and percentages disclosed herein (e.g., numerical ranges, quantities, values, and percentages of material quantities, durations, temperatures, operating conditions, quantitative ratios, and the like) should be understood as being modified in all instances by the terms "substantially," "approximately," or "approximately." Therefore, unless otherwise indicated, the numerical parameters described in the embodiments of the present invention and the appended claims are approximate values that can vary as desired. Finally, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other or between two endpoints. Unless otherwise indicated, all ranges disclosed herein include endpoints.

[0014] MIM capacitors can be used as decoupling capacitors, configured to reduce the variance of the power supply to mitigate switching noise caused by current variations. In some embodiments, MIM capacitors are integrated into the back-end-of-line (BEOL) metallization stack at a location between an underlying metal layer and an overlying metal layer. However, positioning MIM capacitors within the BEOL metallization stack presents a number of manufacturing challenges. For example, MIM capacitors typically have a large number of layers, which results in a more irregular topology than the largest BEOL metallization layer (e.g., having a step size greater than 400 nanometers (nm)). Therefore, in some embodiments, MIM capacitors are placed above the BEOL metallization stack rather than within the BEOL metallization stack to avoid topological issues. In some embodiments, MIM capacitors are placed within or above a redistribution layer (RDL). However, other challenges remain.

[0015] During the formation of the MIM capacitor, metal layers are deposited and patterned to form electrodes. In some comparative embodiments, the dielectric layer between the metal layers may be damaged and the thickness of the dielectric layer may be undesirably reduced. As a result, a higher potential may be induced due to edge effects; therefore, the breakdown voltage (Vbd) of the MIM capacitor may be reduced (which is undesirable), and Vbd failure problems may occur. In addition, various etching techniques are used during the patterning of the electrodes. However, it has been found that no matter which etching technique is used, metal byproducts are left after the patterning of the electrodes. The metal byproducts remain in the corners of the patterned layer and are not easily removed. The remaining metal byproducts present undesirable leakage paths and thus reduce the breakdown voltage and induce Vbd failure problems.

[0016] Therefore, embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same that alleviate the Vbd failure problem.

[0017] Figure 1 1 is a flow chart representing a method for fabricating a semiconductor structure according to aspects of an embodiment of the present invention. Method 10 includes operation 102, wherein a substrate is received. In some embodiments, the substrate includes a first electrode and a first insulating layer formed on the first electrode. Method 10 further includes operation 104, wherein a first conductive layer is formed on the first insulating layer. Method 10 further includes operation 106, wherein a portion of the first conductive layer is removed to form a patterned first conductive layer on the first insulating layer and expose a first portion of the first insulating layer. Method 10 further includes operation 108, wherein a portion of the patterned first conductive layer is removed to form a second electrode and expose a second portion of the first insulating layer. Method 10 will be further described according to one or more embodiments. It should be noted that the operations of method 10 may be rearranged or otherwise modified within the scope of various aspects. It should further be noted that additional processes may be provided before, during, and after method 10, and that some other processes may be only briefly described herein. Therefore, other implementations may be made within the scope of the various aspects described herein.

[0018] Please refer to Figures 2A to 2M , which is a schematic diagram illustrating a semiconductor structure 20 at various stages of fabrication constructed according to aspects of one or more embodiments of the present invention. Figure 2A, a substrate 200 is received or provided according to operation 102. In some embodiments, substrate 200 (also referred to as a die substrate) may include a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In other embodiments, substrate 200 may include a semiconductor material including Group III, Group IV, and / or Group V elements. For example, substrate 200 may include germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), or the like. Substrate 200 may be a p-type semiconducting substrate (acceptor type) or an n-type semiconducting substrate (donor type).

[0019] Still refer to Figure 2A In some embodiments, a peripheral region 202 and a cell region 204 may be defined above the substrate 200. Various electrical components may be formed above the substrate 200. Examples of electrical components include active devices (such as transistors and diodes) and passive devices (such as capacitors, inductors, and resistors). Figure 2A As shown in FIG, in some embodiments, active devices (i.e., transistors) may be formed over substrate 200 in peripheral region 202, while capacitors may be formed over substrate 200 in cell region 204. Substrate 200 may include an interconnect structure 210 disposed therein. Interconnect structure 210 may include a plurality of conductive members 212 (e.g., conductive lines or conductive paths) and an insulating layer 214 that electrically insulates conductive members 212. Conductive members 212 at the same level are collectively referred to as metal layers or connection layers. Figure 2A , showing the uppermost conductive line 216 of the interconnect structure 210. However, one skilled in the art will readily appreciate that the interconnect structure 210 may include multiple connection layers (although not shown) interconnected by conductive pathways.

[0020] In some embodiments, the conductive member 212 may include a metal such as copper (Cu), tungsten (W), or aluminum (Al), but the present invention is not limited thereto. In addition, a barrier layer 218 (e.g., a tungsten layer) is disposed between the conductive member 212 and the insulating layer 214. Figure 2B ) to prevent metal diffusion, but the embodiments of the present invention are not limited thereto.

[0021] Please refer to Figure 2B , which is Figure 2A FIG. 2 is a partial enlarged view of the interconnect structure 210 in FIG. 2 . It should be readily appreciated that for clarity, Figure 2BOnly the insulating layer 214 and the uppermost connecting layer 216 are shown. In some embodiments, the insulating layer 220 and the insulating layer 222 may be disposed over the substrate 200 and the interconnect structure 210. In some embodiments, the insulating layers 220 and 222 may be formed of various dielectric materials and may be, for example, oxides (e.g., Ge oxides), nitrides, oxynitrides (e.g., GaP oxynitrides), silicon dioxide (SiO2), nitrogen-containing oxides (e.g., nitrogen-containing SiO2), nitrogen-doped oxides (e.g., SiO2 implanted with N2), silicon oxynitride (SiO2), or the like. x O y N z ), polymer materials, or the like. In some embodiments, the insulating layers 220 and 222 may comprise different materials. For example, the insulating layer 220 may comprise a SiN layer and the insulating layer 222 may be a plasma enhanced oxide (PEOX) undoped silicate glass (USG) (PEOX-USG) layer, but the present invention is not limited thereto. The insulating layers 220 and 222 may be formed using CVD, PVD, spin coating, or other suitable operations. In one embodiment, the insulating layer 220 has a thickness of approximately Arrive at the appointment In one embodiment, the insulating layer 222 has a thickness of about Arrive at the appointment The thickness is between , but the embodiment of the present invention is not limited thereto.

[0022] Please refer to Figure 2C to Figure 2E , which is Figure 2B A partial enlarged view of the reference Figure 2C , a first electrode 230e is formed over the substrate 200 and an insulating layer 240 is formed over the first electrode 230e. In some embodiments, the first electrode 230e can be obtained by forming a conductive layer (not shown) on the insulating layer 222 and patterning the conductive layer. For the sake of brevity, methods suitable for forming and patterning the conductive layer are not described in detail. The first electrode 230e may include various conductive materials, such as indium tin oxide (ITO), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), molybdenum nitride (MoN), copper (Cu), platinum (Pt), palladium (Pd), osmium (Os), ruthenium (Ru), iridium dioxide (IrO2), rhenium dioxide (ReO2), rhenium trioxide (ReO3) or a combination thereof. In some embodiments, the thickness of the first electrode 230e may be between about Arrive at the appointment However, the embodiments of the present invention are not limited thereto.

[0023] Still refer to Figure 2C, conformally forming an insulating layer 240 to cover the first electrode 230e. In some embodiments, the insulating layer 240 may include a high-k dielectric material (i.e., a dielectric material having a dielectric constant greater than that of silicon dioxide (SiO2)). In various embodiments, the insulating layer 240 may include a single layer. In other embodiments, the insulating layer 240 may include multiple layers of: SiO2, silicon nitride (Si4N4), aluminum oxide (Al2O4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanate (SrTiO4), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium silicate (HfSiO4), lanthanum oxide (La2O4), yttrium oxide (Y2O3) or other suitable materials. In some embodiments, the insulating layer 240 may include a stacked layer of ZrO2 / Al2O3 / ZrO2 (ZAZ), but embodiments of the present invention are not limited thereto. In some embodiments, the thickness of the insulating layer 240 may be between about Arrive at the appointment For example, the thickness of the insulating layer 240 may be about However, the embodiments of the present invention are not limited thereto.

[0024] refer to Figure 2D According to operation 104, a conductive layer 232 is formed on the insulating layer 240. The conductive layer 232 may include the same material and thickness as the first electrode 230e, and therefore, these details are omitted for brevity. Figure 2D As shown in FIG, a conductive layer 232 may be conformally formed over the substrate 200. Subsequently, a patterned shielding layer 231 is formed on the conductive layer 232.

[0025] refer to Figure 2E According to operation 106, a portion of the conductive layer 232 is removed to form a patterned conductive layer 232p on the insulating layer 240 and expose a first portion 240a of the insulating layer 240. In some embodiments, removing the portion of the conductive layer 232 may include an etching technique, such as dry etching. In addition, the patterned shielding layer 231 may be removed after forming the patterned conductive layer 232p. In addition, the first portion 240a refers to any portion of the insulating layer 240 exposed by the patterned conductive layer 232p, such as Figure 2E In some embodiments, the insulating layer 240 is disposed between the patterned conductive layer 232p and the insulating layer 222. In other embodiments, the insulating layer 240 is between the first electrode 230e and the patterned conductive layer 232p.

[0026] Please refer to Figure 2F , which is Figure 2E2. As mentioned above, the portion of the conductive layer 232 exposed by the patterned shielding layer 231 can be removed by etching, and the etching not only removes the portion of the conductive layer 232 but also consumes the portion of the insulating layer 240 after exposing the insulating layer 240. Therefore, the thickness of the first portion 240a exposed by the patterned conductive layer 232p can be reduced, and a corner Ca can be formed between the first portion 240a and another portion of the insulating layer 240 below the patterned conductive layer 232p, as shown in FIG. Figure 2F In other words, the thickness of the first portion 240a is less than the thickness of the portion of the insulating layer 240 below the patterned conductive layer 232p, and a thickness difference T1 can be obtained at the corner Ca, as shown in FIG. Figure 2F As shown in FIG. It should be noted that in some embodiments, even if the thickness difference T1 is only a few angstroms, it can amplify edge effects, while the thinner first portion 240a of the insulating layer 240 itself induces a larger potential. Consequently, Vbd failure may occur at the corner Ca. Furthermore, metal byproducts 233 may be generated during etching and remain at the corner Ca. It should be noted that because the metal byproducts 233 remain at the corner Ca, they are not easily removed even after a cleaning operation.

[0027] refer to Figure 2G , the portion of the patterned conductive layer 232p is removed according to operation 108. It should be noted that the portion of the patterned conductive layer 232p is removed by a solution having a higher etching rate for the conductive material than for the insulating layer. For example, in some embodiments, the portion of the patterned conductive layer 232p can be removed by dipping in hydrogen peroxide (H2O2). By dipping in H2O2 for about 30 seconds, the portion of the patterned conductive layer 232p can be removed without consuming almost any insulating layer 240. Figure 2G As shown in FIG, a portion of the patterned conductive layer 232p is removed to form the second electrode 232e and expose the second portion 240b of the insulating layer. It should be noted that because the insulating layer 240 is almost unaffected by the removal of the portion of the patterned conductive layer 232p, the thickness of the second portion 240b of the insulating layer 240 is greater than the thickness of the first portion 240a of the insulating layer 240. In some embodiments, the width of the first portion 240a is greater than the width of the second portion 240b. It should be noted that the width of the second portion 240b is related to the duration of the H2O2 immersion process. In some embodiments, the width of the second portion 240b is between about Arrive at the appointment , but the present invention is not limited thereto. Alternatively, another corner Cb may be formed where the second electrode 232e contacts the second portion 240b of the insulating layer 240. Furthermore, in some embodiments, the metal byproducts 233 may be removed by immersion in H2O2. In other embodiments, even if the metal byproducts 233 remain at the corner Ca, they are still separated from the second electrode 232e by the second portion 240b of the insulating layer 240.

[0028] refer to Figure 2H In some embodiments, another insulating layer 242 is formed on the second electrode 232e and the insulating layer 240. The insulating layer 242 may include the same material as the insulating layer 240, so these details are omitted for brevity. In some embodiments, when the insulating layers 240 and 242 include the same material, the step interface between the insulating layers 240 and 242 may not be easily observed, so for clarity, Figure 2H This step interface is shown by the dashed line in FIG. In other embodiments, when the insulating layer 242 comprises a material different from the insulating layer 240, the step interface between the insulating layer 242 and the insulating layer 240 can be easily observed. The thickness of the insulating layer 242 can be the same as the thickness of the insulating layer 240, so these details are omitted for simplicity. In some embodiments, the insulating layer 242 is conformally formed on the second electrode 232e and the insulating layer 240 and thus covers both the corner Ca and the corner Cb.

[0029] refer to Figure 2I , another conductive layer 234 may be formed on the insulating layer 242. The conductive layer 234 may comprise the same material and thickness as the conductive layer 232. Therefore, for the sake of brevity, these details are omitted. Subsequently, a patterned shielding layer (not shown) is formed on the conductive layer 234.

[0030] In some embodiments, operation 106 may be performed on conductive layer 234. Figure 2J , a portion of the conductive layer 234 is removed to form a third electrode 234e on the insulating layer 242 and expose a third portion 242a of the insulating layer 242. In some embodiments, the removal of the portion of the conductive layer 234 may include an etching technique, such as dry etching. In addition, the patterned shielding layer may be removed after the third electrode 234e is formed. In some embodiments, a MIM capacitor 250 is obtained, which includes a first electrode 230e, a second electrode 232e, a third electrode 234e, an insulating layer 240 between the first electrode 230e and the second electrode 232e, and an insulating layer 242 between the second electrode 232e and the third electrode 234e. In some embodiments, the portion of the insulating layer 242 exposed by the third electrode 234e is referred to as the third portion 242a, and the portion of the insulating layer 242 below the third electrode 234e and protected by the third electrode 234e is referred to as the fourth portion 242b. As Figure 2J As shown in FIG, the third portion 242a and the fourth portion 242b are coupled to each other.

[0031] Still refer to Figure 2J As mentioned above, the portion of the conductive layer 234 exposed by the patterned shielding layer can be removed by etching, and the etching not only removes the portion of the conductive layer 234, but also consumes the portion of the insulating layer 242 after exposing the insulating layer 242. Therefore, the third portion 242a of the insulating layer 242 can be consumed by etching, and the thickness of the third portion 242a of the insulating layer 242 can be reduced accordingly. In other words, the thickness of the third portion 242a of the insulating layer 242 is less than the thickness of the fourth portion 242b of the insulating layer 242. In addition, because the thickness of the third portion 242a exposed by the third electrode 234e is reduced, a corner Cc can be formed between the third portion 242a and the fourth portion 242b. It should be noted that because the insulating layer 242 (such as Figure 2J ), so the thickness reduction at corner Cc has a much smaller effect on the capacitor than the thickness reduction at corner Ca. However, in some embodiments, operation 108 may be performed on the third electrode 234e.

[0032] refer to Figure 2K , a dielectric layer 260 is formed to completely cover the MIM capacitor 250. In some embodiments, the dielectric layer 260 may be formed and then planarized to obtain a flat surface, such as Figure 2K The insulating layer 260 may include a low-k dielectric material (e.g., PEOX-USG), but the present invention is not limited thereto. In some embodiments, the thickness of the insulating layer 260 may be between about Arrive at the appointment The insulating layer 260 not only provides electrical isolation, but also provides sufficient mechanical strength to withstand stress. In some embodiments, the thickness of the insulating layer 260 may be even greater than To withstand stress.

[0033] refer to Figure 2L In some embodiments, a via 262 is formed through dielectric layer 260. In some embodiments, via 262 may include a diffusion barrier layer (not shown) and a conductive material. In some embodiments, the diffusion barrier layer may include a single layer. In some alternative embodiments, the diffusion barrier layer may include multiple layers. For example, but not limited to, the diffusion barrier layer may include Ta, TaN, Ti, or TiN. The conductive material of via 262 may include Cu, Al, W, Co, or alloys thereof (e.g., AlCu), but embodiments of the present invention are not limited thereto.

[0034] Still refer to Figure 2L, via 262 also penetrates insulating layers 240 and 242 and insulating layers 222 and 220. Therefore, dielectric and insulating layers 260, 240, 242, 222, and 220 contact the sidewalls of via 262, while uppermost conductive layer 216 contacts the bottom of via 262. In some embodiments, via 262 not only penetrates dielectric and insulating layers 260, 240, 242, 222, and 220, but also penetrates first electrode 230e and third electrode 234e. In these embodiments, uppermost conductive layer 216 is electrically connected to first electrode 230e and third electrode 234e via via 262. In other embodiments, via 262 further penetrates second electrode 232e and third electrode 234e, thus electrically connecting uppermost conductive layer 216 to second electrode 232e and third electrode 234e via via 262. Terminal 264 may be formed on via 262. In some embodiments, the terminal 264 may include W, Al, Cu, or AlCu, but the present invention is not limited thereto.

[0035] refer to Figure 2M , further forming a dielectric layer 266 and a dielectric layer 268 on the dielectric layer 260. Then, as Figure 2M As shown in FIG, openings 270 are formed in the insulating layers 266 and 268 to expose the connection pads 264. Thus, a semiconductor structure 20 including at least one MIM capacitor 250 is obtained.

[0036] It should be noted that two of the three electrodes 230e, 232e, and 234e are electrically connected to the via 262 and the terminal 264. The terminal 264 exposed by the opening 270 is used to receive an external signal. When a voltage is applied to the MIM capacitor 250, current can flow into the MIM capacitor 250 through two of the three electrodes 230e, 232e, and 234e. Therefore, the MIM capacitor 250 allows high-frequency noise on the direct current (DC) power line to be directly shunted between the lines to prevent the noise from reaching the internal devices disposed in the substrate 200 through the topmost conductive layer 216. Therefore, in some embodiments, the MIM capacitor 250 can help provide more stable power to the internal devices. In addition, if the power supply needs to switch between various operating modes, then sufficient decoupling capacitance can be used as an energy reserve to reduce the magnitude of undesirable voltage drops during mode switching events. Therefore, in some embodiments of the present invention, the MIM capacitor 250 can be used as a filter.

[0037] Return to reference again Figure 2K In some embodiments, a semiconductor structure such as a MIM capacitor 250 is provided. The semiconductor structure includes a substrate 200 (e.g. Figure 2L), a first electrode 230e over the substrate 200, a second electrode 232e over the first electrode 230e, a third electrode 234e over the second electrode 232e, an insulating layer 240 between the first and second electrodes 230e, 232e, and an insulating layer 242 between the second and third electrodes 232e, 234e. In some embodiments, the insulating layer 240 and the insulating layer 242 are disposed together between the first and third electrodes 230e, 234e. In some embodiments, the first electrode 230e is referred to as the bottom electrode, the second electrode 232e is referred to as the middle electrode, and the third electrode 234e is referred to as the top electrode.

[0038] The insulating layer 240 has a first portion 240a and a second portion 240b coupled to the first portion 240a. Figure 2K As shown in FIG, the second portion 240b of the insulating layer 240 is in contact with the second electrode 232e (e.g., the sidewall of the second electrode 232e), while the first portion 240a of the insulating layer 240 is separated from the second electrode 232e by the second portion 240b. Therefore, a corner Ca can be formed where the first portion 240a is coupled to the second portion 240b, and a corner Cb can be formed where the second portion 240b is in contact with the sidewall of the second electrode 232e. In addition, the thickness of the second portion 240b is greater than the thickness of the first portion 240a. In some embodiments, depending on different product requirements, the thickness of the second portion 240b of the insulating layer 240 is between about 1000Å and 1000Å. Arrive at the appointment and the thickness of the first portion 240a of the insulating layer 240 is less than about In some embodiments, because the insulating layer 240 has the first portion 240 a and the second portion 240 b , a step interface may be formed between the insulating layer 240 and the insulating layer 242 .

[0039] Still refer to Figure 2K , the width of the second portion 240b is less than the width of the first portion 240a. In some embodiments, the width of the second portion 240b is between about Arrive at the appointment It should be noted that if the width of the second portion 240b is less than about Then the first portion 240a with a smaller thickness may be close to the corner Cb and cannot alleviate the Vbd failure problem. However, if the width of the second portion 240b is greater than about Then, because the width of the second electrode 232 e is reduced, the function of the MIM capacitor 250 may be adversely affected.

[0040] The insulating layer 242 includes a third portion 242a and a fourth portion 242b coupled to the third portion 242a. As mentioned above, the fourth portion 242b is located below and in contact with the third electrode 234e, while the third portion 242a is exposed by the third electrode 234e and separated from the third electrode 234e. The thickness of the fourth portion 242b is greater than that of the third portion 242a. Furthermore, the thickness of the fourth portion 242b of the insulating layer 242 is consistent between the second electrode 232e and the third electrode 234e, and between the first electrode 230e and the third electrode 234e.

[0041] Still refer to Figure 2K On the other hand, the third electrode 234e may include a first bottom surface B1 and a second bottom surface B2. The first bottom surface B1 is adjacent to the corner Cc, and the second bottom surface B2 is separated from the corner Cc by the first bottom surface B1. The first bottom surface B1 and the second bottom surface B2 are at different levels. In some embodiments, the second bottom surface B2 is higher than the first bottom surface B1. In addition, the width of the first bottom surface B1 is greater than the width of the second bottom surface B2. In some embodiments, the width of the second bottom surface B2 is substantially equal to the width of the second portion 240b of the insulating layer 240, but embodiments of the present invention are not limited thereto. The distance between the first bottom surface B1 of the first electrode 230e and the third electrode 234e is less than the distance between the first electrode 230e and the second bottom surface B2 of the third electrode 234e.

[0042] According to the MIM capacitor 250 provided by the embodiment of the present invention, the second electrode 232e is retreated by, for example, (but not limited to) H2O2 immersion. As a result, the thinned first portion 240a of the insulating layer 240 is separated from the corner Cb by the second portion 240b. Consequently, Vbd failure issues are mitigated because the insulating layer 240 between the two electrodes (i.e., the first electrode 230e and the second electrode 232e) is sufficiently thick. Furthermore, by retreating the second electrode 232e, metal byproducts formed by etching techniques can be removed or separated from the sidewalls of the second electrode 232e by the second portion 240b of the insulating layer 240. Consequently, leakage paths are isolated or eliminated, further mitigating Vbd failure issues.

[0043] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first electrode over the substrate, a second electrode over the first electrode, and a first insulating layer between the first and second electrodes. The first insulating layer includes a first portion and a second portion coupled to the first portion. The second portion of the first insulating layer contacts the second electrode, and the first portion is separated from the second electrode by the second portion. The second portion is thicker than the first portion.

[0044] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first electrode, a second electrode above the first electrode, a third electrode above the second electrode, a first insulating layer between the first and second electrodes, and a second insulating layer between the second and third electrodes. The third electrode includes a first bottom surface and a second bottom surface. The first bottom surface and the second bottom surface are at different levels. The width of the first bottom surface is greater than the width of the second bottom surface.

[0045] In some embodiments, a method for fabricating a semiconductor structure is provided. The method includes the following operations: receiving a substrate comprising a first electrode and a first insulating layer overlying the first electrode; forming a first conductive layer overlying the first insulating layer; removing a portion of the first conductive layer to form a patterned first conductive layer overlying the first insulating layer and exposing a first portion of the first insulating layer; and removing a portion of the patterned first conductive layer to form a second electrode and expose a second portion of the first insulating layer. The second portion of the first insulating layer has a thickness greater than that of the first portion of the first insulating layer.

[0046] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the embodiments of the present invention. Those skilled in the art will appreciate that they can readily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that these equivalent constructions should not depart from the spirit and scope of the embodiments of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present invention.

[0047] Explanation of symbols

[0048] 10 Methods

[0049] 20 Semiconductor Structure

[0050] 102 Operation

[0051] 104 Operation

[0052] 106 Operations

[0053] 108 Operations

[0054] 200 substrate

[0055] 202 Outer Area

[0056] Unit 204 area

[0057] 210 Interconnection Structure

[0058] 212 conductive components

[0059] 214 insulation layer

[0060] 216 Top conductive line / top connection layer / top conductive layer

[0061] 218 Barrier layer

[0062] 220 insulation layer

[0063] 222 insulation layer

[0064] 230e first electrode

[0065] 231 patterned shielding layer

[0066] 232 conductive layer

[0067] 232e Second electrode

[0068] 232p patterned conductive layer

[0069] 233 Metal Byproducts

[0070] 234 conductive layer

[0071] 234e Third electrode

[0072] 240 insulation layer

[0073] 240a Part 1

[0074] 240b Part 2

[0075] 242 insulation layer

[0076] 242a Part III

[0077] 242b Part 4

[0078] 250 Metal-Insulator-Metal (MIM) Capacitors

[0079] 260 Dielectric layer / insulating layer

[0080] 262 access

[0081] 264 terminals / connection pads

[0082] 266 Dielectric layer / insulating layer

[0083] 268 dielectric layer / insulating layer

[0084] 270 Opening

[0085] B1 First bottom surface

[0086] B2 Second bottom surface

[0087] Ca Corner

[0088] Cb Corner

[0089] Cc Corner

[0090] T1 thickness difference

Claims

1. A semiconductor structure comprising: substrate; a first electrode located above the substrate; a second electrode located above the first electrode; a first insulating layer disposed between the first electrode and the second electrode; The first insulating layer includes a first portion and a second portion coupled to the first portion, the second portion of the first insulating layer contacts the second electrode, the first portion is separated from the second electrode by the second portion, and the thickness of the second portion is greater than the thickness of the first portion, the second portion includes a top surface exposed by the second electrode and a sidewall coupled to the top surface and the first portion, the top surface of the first portion and the sidewall of the second portion form a first corner, and the top surface of the second portion and the sidewall of the second electrode form a second corner; and A third electrode is located above the second electrode and has an upper portion and a first lower portion and a second lower portion respectively contacting two side walls of the upper portion, wherein the bottom surface of the upper portion is higher than the top surface of the second electrode, the bottom surface of the first lower portion and the bottom surface of the second lower portion are lower than the top surface of the second electrode, the side wall of the first lower portion is aligned with the first side wall of the first insulating layer, and the side wall of the second lower portion is aligned with the second side wall of the first insulating layer.

2. The semiconductor structure according to claim 1 , wherein the thickness of the second portion of the first insulating layer is between 60 angstroms and 100 angstroms. arrive between.

3. The semiconductor structure according to claim 2 , wherein the thickness of the first portion of the first insulating layer is less than 4. The semiconductor structure according to claim 1 , wherein the width of the second portion is between arrive between. The semiconductor structure according to claim 1 , further comprising a second insulating layer between the third electrode and the second electrode. 6 . The semiconductor structure according to claim 5 , wherein the second insulating layer has a third portion and a fourth portion coupled to the third portion, and a thickness of the fourth portion is greater than a thickness of the third portion. 7 . The semiconductor structure according to claim 5 , further comprising a stepped interface between the first insulating layer and the second insulating layer.

8. A semiconductor structure comprising: a first electrode; a second electrode located above the first electrode; a third electrode located above the second electrode and having an upper portion and a first lower portion and a second lower portion contacting two side walls of the upper portion, wherein a bottom surface of the upper portion is higher than a topmost surface of the second electrode, and a bottom surface of the first lower portion and a first bottom surface and a second bottom surface of the second lower portion are lower than the topmost surface of the second electrode; a first insulating layer interposed between the first electrode and the second electrode, wherein a first sidewall of the first insulating layer is aligned with a sidewall of the first lower portion, and a second sidewall of the first insulating layer is aligned with a sidewall of the second lower portion; and a second insulating layer, which is between the second electrode and the third electrode, wherein the first bottom surface and the second bottom surface of the second lower portion of the third electrode are at different levels, and the width of the first bottom surface is greater than the width of the second bottom surface, the first insulating layer includes a first portion and a second portion with different thicknesses, the second portion of the first insulating layer contacts the second electrode, the first portion is separated from the second electrode by the second portion, the second portion includes a top surface exposed by the second electrode and a side wall coupling the top surface and the first portion, the top surface of the first portion and the side wall of the second portion form a first corner, and the top surface of the second portion and the side wall of the second electrode form a second corner. 9 . The semiconductor structure of claim 8 , wherein the second insulating layer has a uniform thickness between the second electrode and the third electrode and between the first electrode and the third electrode. 10 . The semiconductor structure according to claim 8 , wherein a distance between the first electrode and the first bottom surface of the second lower portion of the third electrode is smaller than a distance between the first electrode and the second bottom surface of the second lower portion of the third electrode.

11. The semiconductor structure according to claim 8, wherein the width of the second bottom surface is between arrive between. 12 . The semiconductor structure according to claim 8 , wherein the second insulating layer comprises a third portion and a fourth portion coupled to the third portion, the fourth portion contacts the third electrode, and the third portion is separated from the third electrode. The semiconductor structure of claim 12 , wherein a thickness of the fourth portion is greater than a thickness of the third portion.

14. A method of forming a semiconductor structure, comprising: receiving a substrate including a first electrode and a first insulating layer on the first electrode; forming a first conductive layer on the first insulating layer; removing a portion of the first conductive layer to form a patterned first conductive layer on the first insulating layer and exposing a first portion of the first insulating layer; removing a portion of the patterned first conductive layer to form a second electrode and exposing a second portion of the first insulating layer, wherein the thickness of the second portion of the first insulating layer is greater than the thickness of the first portion of the first insulating layer, the second portion of the first insulating layer contacts the second electrode, the first portion is separated from the second electrode by the second portion, the second portion has a top surface exposed by the second electrode and a sidewall coupling the top surface and the first portion, the top surface of the first portion and the sidewall of the second portion form a first corner, and the top surface of the second portion and the sidewall of the second electrode form a second corner; and A third electrode is formed on the second electrode, wherein the third electrode has an upper portion and a first lower portion and a second lower portion respectively contacting two side walls of the upper portion, the bottom surface of the upper portion is higher than the top surface of the second electrode, the bottom surface of the first lower portion and the bottom surface of the second lower portion are lower than the top surface of the second electrode, the side wall of the first lower portion is aligned with the first side wall of the first insulating layer, and the side wall of the second lower portion is aligned with the second side wall of the first insulating layer.

15. The method according to claim 14, wherein the thickness of the second portion of the first insulating layer is between arrive between. The method of claim 14 , wherein removing the portion of the first conductive layer comprises dry etching.

17. The method of claim 14, wherein removing the portion of the patterned first conductive layer comprises a hydrogen peroxide (H2O2) dip.

18. The method of claim 14, further comprising: forming a second insulating layer on the second electrode and the first insulating layer; forming a second conductive layer on the second insulating layer; and A portion of the second conductive layer is removed to form the third electrode on the second insulating layer and expose a third portion of the second insulating layer. 19 . The method of claim 18 , wherein the second insulating layer further comprises a fourth portion coupled to the third portion, and a thickness of the fourth portion of the second insulating layer is greater than a thickness of the third portion of the second insulating layer.

20. The method of claim 18, further comprising forming a dielectric layer over the first electrode, the second electrode, and the third electrode.

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