Method of manufacturing a semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device. The manufacturing method includes: (a) forming a gate structure for controlling a gate electrode on a semiconductor substrate; (b) forming a charge storage film to cover a first side surface, a second side surface, and an upper surface of the gate structure; (c) forming a first conductive film for a memory gate electrode on the charge storage film; (d) removing a part of the charge storage film and a part of the conductive film such that the charge storage film and the conductive film are retained on the first side surface and the second side surface of the gate structure in this order; and (e) removing a part of the gate structure separated from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2019-190492, filed on October 17, 2019, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a memory element. Background Art

[0004] Semiconductor devices having electrically writable and electrically erasable flash memories are known. For example, a flash memory includes a semiconductor substrate, a control gate electrode, a memory gate electrode, and a charge storage film (see, for example, Japanese Patent Application Laid-Open No. 2015-053474 (Patent Document 1)). The control gate electrode and the memory gate electrode are formed on the semiconductor substrate. The charge storage film is formed between the control gate electrode and the memory gate electrode, and between the semiconductor substrate and the memory gate electrode. Writing and erasing of the flash memory are performed by injecting charge into the charge storage film or by extracting charge from the charge storage film.

[0005] The method for manufacturing the semiconductor device described in Patent Document 1 includes: step (a) forming a control gate electrode on a semiconductor substrate; step (b) forming a charge storage film on the semiconductor substrate so as to cover a first side surface, a second side surface, and an upper surface of the control gate electrode; step (c) forming a conductive film for a memory gate electrode on the charge storage film; and step (d) removing the charge storage film and the conductive film formed on the second side surface and the upper surface of the control gate electrode so that the charge storage film and the conductive film remain on the first side surface of the control gate electrode in this order. Summary of the Invention

[0006] In the method for manufacturing the semiconductor device described in Patent Document 1, in step (b), the charge storage film is formed on the second side surface of the control gate electrode at once, and then, in step (d), the charge storage film is removed from the second side surface. Depending on the manufacturing conditions, the charge storage film cannot be sufficiently removed from the second side surface, and in some cases, residues of the charge storage film may remain on the second side surface. This residue becomes a cause of foreign matter in the steps after step (d). Therefore, it may not be possible to obtain the desired characteristics of the semiconductor device. As described above, from the viewpoint of enhancing the characteristics of the semiconductor device, there is room for improvement in the conventional method for manufacturing a semiconductor device.

[0007] The purpose of the embodiment is to enhance the characteristics of a semiconductor device. Other purposes and novel features will become apparent from the description of this specification and the accompanying drawings.

[0008] The method of manufacturing a semiconductor device according to an embodiment includes (a) to (e) described below. In (a), a gate structure for controlling a gate electrode is formed on a semiconductor substrate via a gate insulating film. In (b), a charge storage film is formed on the semiconductor substrate so as to cover a first side surface, a second side surface, and an upper surface of the gate structure. In (c), a first conductive film for a memory gate electrode is formed on the charge storage film. In (d), a part of the charge storage film and a part of the first conductive film are removed such that the charge storage film and the first conductive film remain on the first side surface and the second side surface of the gate structure on the semiconductor substrate in this order, thereby forming a memory gate electrode. In (e), a part of the gate structure separated from the first side surface and the second side surface is removed such that a part of the semiconductor substrate is exposed from the gate structure.

[0009] According to the embodiment, the characteristics of the semiconductor device can be enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a first embodiment;

[0011] Figure 2 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a first embodiment;

[0012] Figure 3 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a first embodiment;

[0013] Figure 4 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a first embodiment;

[0014] Figure 5 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a first embodiment;

[0015] Figure 6 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a first embodiment;

[0016] Figure 7 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a first embodiment;

[0017] Figure 8is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0018] Figure 9 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0019] Figure 10 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0020] Figure 11 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0021] Figure 12 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0022] Figure 13 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0023] Figure 14 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0024] Figure 15 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to the first embodiment;

[0025] Figure 16 is a cross-sectional view showing the step of forming a charge storage film in the method of manufacturing a semiconductor device according to the comparative example;

[0026] Figure 17 is a cross-sectional view showing the state after removing the charge storage film in the method of manufacturing a semiconductor device according to the comparative example;

[0027] Figure 18 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a modified example of the first embodiment;

[0028] Figure 19 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a modified example of the first embodiment;

[0029] Figure 20 is a cross-sectional view showing an example of each step included in the method of manufacturing a semiconductor device according to a modified example of the first embodiment;

[0030] Figure 21 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to a modified example of the first embodiment;

[0031] Figure 22 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to a modified example of the first embodiment;

[0032] Figure 23 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0033] Figure 24 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0034] Figure 25 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0035] Figure 26 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0036] Figure 27 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0037] Figure 28 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0038] Figure 29 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0039] Figure 30 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0040] Figure 31 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment;

[0041] Figure 32 is a cross-sectional view showing an example of each step included in a method of manufacturing a semiconductor device according to the second embodiment; and

[0042] Figure 33It is a cross-sectional view showing an example of each step included in the manufacturing method of a semiconductor device according to the second embodiment. Detailed Description of the Invention

[0043] Hereinafter, semiconductor devices according to each embodiment will be described in detail with reference to the drawings. Note that in the specification and drawings, the same components or corresponding components are denoted by the same reference numerals, and redundant descriptions will be omitted. In addition, in the drawings, for ease of explanation, in some cases, the configuration will be omitted and simplified. At least parts of each embodiment and modification example can be appropriately combined with each other. Further, in some cases, the cross-sectional view is shown as an end view.

[0044] [First Embodiment]

[0045] (Manufacturing Method of Semiconductor Device)

[0046] An example of the manufacturing method of a semiconductor device SD1 according to the first embodiment will be described. Figures 1 to 15 It is a cross-sectional view showing an example of each step included in the manufacturing method of a semiconductor device SD1.

[0047] The manufacturing method of the semiconductor device SD1 according to the first embodiment includes: Step 1. Forming a gate structure GS1; Step 2. Forming a charge storage film CSF; Step 3. Forming a conductive film CFmg for a memory gate electrode MG; Step 4. Forming a memory gate electrode MG; Step 5. Removing a part of the gate structure GS1; Step 6. Forming a first impurity region IPR1; Step 7. Forming sidewalls SW; Step 8. Forming a second impurity region IPR2; and Step 9. Forming a multilayer wiring layer.

[0048] 1. Formation of Gate Structure GS1

[0049] The step of forming the gate structure GS1 includes: (1) a step of preparing a semiconductor substrate SS; (2) a step of forming a stacked film SF; (3) a step of forming a first gate structure portion GSP1 and a second gate structure portion GSP2; and (4) a step of forming a sacrificial layer SCL.

[0050] (1) Preparation of Semiconductor Substrate SS

[0051] First, as Figure 1As shown, a semiconductor substrate SS is prepared, and a gate insulating film GIF is formed on the semiconductor substrate SS. The semiconductor substrate SS is a single-crystalline silicon substrate having a specific resistance of 1 Ωcm or greater than 1 Ωcm and less than 10 Ωcm or 10 Ωcm. The semiconductor substrate SS has, for example, an impurity region containing a p-type impurity. Examples of the p-type impurity include boron (B) and aluminum (Al). Although not particularly shown, an insulating film for element isolation may be pre-formed in the semiconductor substrate SS.

[0052] The method of forming the gate insulating film GIF is, for example, a thermal oxidation method. The gate insulating film GIF is formed, for example, by thermally oxidizing the main surface of the semiconductor substrate SS. The material of the gate insulating film GIF is, for example, silicon oxide. Note that the gate insulating film GIF is a gate insulating film for controlling the gate electrode CG.

[0053] (2) Formation of the stacked film SF

[0054] Next, a stacked film SF in which a conductive film CFcg for controlling the gate electrode CG and a cap insulating film CIF are stacked in this order is formed on the gate insulating film GIF.

[0055] The method of forming the conductive film CFcg is, for example, a CVD (chemical vapor deposition) method. The material of the conductive film CFcg is, for example, polysilicon. The thickness of the conductive film CFcg is appropriately adjusted according to the desired thickness of the control gate electrode CG. For example, the thickness of the conductive film CFcg is 40 nm or greater than 40 nm and less than 100 nm or 100 nm.

[0056] The method of forming the cap insulating film CIF is, for example, a CVD method. Examples of the material of the cap insulating film CIF include silicon oxide and silicon nitride. The cap insulating film CIF may be a single-layer film or a stacked film composed of two or more layers. The thickness of the cap insulating film CIF can be adjusted according to the desired thickness of the memory gate electrode MG. For example, the thickness of the cap insulating film CIF is preferably 20 nm or greater than 20 nm and less than 100 nm or 100 nm.

[0057] (3) Formation of the first gate structure portion GSP1 and the second gate structure portion GSP2

[0058] Next, as Figure 3 shown, a part of the stacked film SF is removed to form the first gate structure portion GSP1 and the second gate structure portion GSP2. More specifically, at least a part of the cap insulating film CIF and a part of the conductive film CFcg are removed. Thus, the control gate electrode CG is formed. The stacked film SF is removed by, for example, a photolithography method and an etching method.

[0059] At this time, a plurality of first gate structure portions GSP1 and a plurality of second gate structure portions GSP2 are formed so as to be alternately and repeatedly arranged. In Figure 3 it, a pair of first gate structure portions GSP1 and second gate structure portions GSP2 are mainly shown.

[0060] The first gate structure portion GSP1 has a first side surface SF1 and a third side surface SF3 located on opposite sides of each other, and a first upper surface TS1. The second gate structure portion GSP2 has a second side surface SF2 and a fourth side surface SF4 located on opposite sides of each other, and a second upper surface TS2. The third side surface SF3 of the first gate structure portion GSP1 and the fourth side surface SF4 of the second gate structure portion GSP2 face each other.

[0061] In a cross-section orthogonal to the extending direction of the first gate structure portion GSP1 and the second gate structure portion GSP2, an opening is formed between the adjacent first gate structure portion GSP1 and the second gate structure portion GSP2. In the first embodiment, as Figure 3 shown in it, a first opening OP1 and a second opening OP2 are formed so as to sandwich the first gate structure portion GSP1 therebetween. A second opening OP2 and a third opening OP3 are formed so as to sandwich the second gate structure portion GSP2 therebetween. The first side surface SF1 of the first gate structure portion GSP1 is exposed in the first opening OP1. The third side surface SF3 of the first gate structure portion GSP1 and the fourth side surface SF4 of the second gate structure portion GSP2 are exposed in the second opening OP2. That is, the first gate structure portion GSP1 and the second gate structure portion GSP2 are separated from each other via the opening OP2. In addition, the second side surface SF2 of the second gate structure portion GSP2 is exposed in the third opening OP3.

[0062] In this step, the gate insulating film GIF may or may not be removed. That is, the gate insulating film GIF or the semiconductor substrate SS may be exposed in each of the first opening OP1, the second opening OP2, and the third opening OP3. In the first embodiment, the gate insulating film GIF exposed from the control gate electrode CG is removed. That is, a part of the semiconductor substrate SS is exposed in each of the first opening OP1, the second opening OP2, and the third opening OP3.

[0063] (4) Formation of the sacrificial layer SCL

[0064] Next, as Figure 4 and Figure 5As shown, a sacrificial layer SCL is formed on a semiconductor substrate SS to fill at least the second opening OP2. Although details will be described later, in the first embodiment, the steps of forming the sacrificial layer SCL include: (4-1) a step of forming a first layer FL; (4-2) a step of forming a second layer SL; and (4-3) a polishing step.

[0065] In the first embodiment, a sacrificial layer SCL is formed on the semiconductor substrate SS to fill each of the first opening OP1, the second opening OP2, and the third opening OP3. That is, the sacrificial layer SCL is formed to cover the first side surface SF1, the third side surface SF3, and the first upper surface TS1 of the first gate structure portion GSP1, and the second side surface SF2, the fourth side surface SF4, and the second upper surface TS2 of the second gate structure portion GSP2. The sacrificial layer SCL is preferably formed to at least fill the second opening OP2.

[0066] The sacrificial layer SCL may be a single-layer film or a stacked film composed of two or more layers. In the first embodiment, the sacrificial layer SCL is a stacked film including a first layer FL and a second layer SL. As described above, in the first embodiment, the steps of forming the sacrificial layer SCL include: (4-1) a step of forming a first layer FL; (4-2) a step of forming a second layer SL; and (4-3) a patterning step.

[0067] (4-1) Formation of the first layer FL

[0068] First, as Figure 4 shown, the first layer FL is formed at least on the inner surface of the second opening OP2. In the first embodiment, the first layer FL is formed on the semiconductor substrate SS to cover the first gate structure portion GSP1 and the second gate structure portion GSP2. A method of forming the first layer FL is, for example, a CVD method. Any material and thickness the same as those of the first layer FL may be applied as long as the first layer FL can suitably cover at least the inner surface of the second opening OP2. Examples of the material of the first layer FL include silicon oxide. The thickness of the first layer FL is, for example, 3 nm or greater than 3 nm and less than 10 nm or 10 nm.

[0069] (4-2) Formation of the second layer SL

[0070] Next, as Figure 5As shown, the second layer SL is formed on the first layer FL so as to at least fill the second opening OP2. In the first embodiment, the second layer SL is formed on the first layer FL so as to fill the interiors of each of the first opening OP1, the second opening OP2, and the third opening OP3, and to cover the first gate structure portion GSP1 and the second gate structure portion GSP2. A method for forming the second layer SL is, for example, a CVD method. There is no particular limitation on the material and thickness of the second layer SL as long as the second layer SL can suitably fill at least the second opening OP2. Examples of the material of the second layer SL include polysilicon. The thickness of the second layer SL is, for example, 100 nm or greater than 100 nm and less than 300 nm or 300 nm.

[0071] As described above, the sacrificial layer SCL can be a single-layer film. When the sacrificial layer SCL is a single-layer film, the sacrificial layer SCL is the second layer SL. From the perspective of reducing manufacturing costs, the sacrificial layer SCL is preferably a single-layer film. When removing the sacrificial layer in the patterning step described later, from the perspective of reducing damage to the semiconductor substrate SS, the sacrificial layer SCL is preferably a stacked film.

[0072] (4-3) Patterning step

[0073] Next, as Figure 6 and Figure 7 shown, the sacrificial layer SCL is patterned. In the first embodiment, the sacrificial layer SCL is patterned such that a portion of the sacrificial layer SCL that is formed in the second opening OP2 remains. That is, the sacrificial layer SCL is partially removed such that at least a portion of the sacrificial layer SCL that is located on the third side surface SF3 of the first gate structure portion GSP1 and on the fourth side surface SF4 of the second gate structure portion GSP2 remains.

[0074] In the first embodiment, the patterning step includes a polishing step and an etching step.

[0075] In the polishing step, as Figure 6As shown in the figure, a part of the sacrificial layer SCL located above the first upper surface TS1 of the first gate structure portion GSP1 and the second upper surface TS2 of the second gate structure portion GSP2 is polished. The method of polishing the sacrificial layer SCL is, for example, the CMP (chemical mechanical polishing) method. After the polishing step, the height difference formed by the upper surface TS1 of the first gate structure portion GSP1, the second upper surface TS2 of the second gate structure portion GSP2, and the upper surface of the sacrificial layer SCL is preferably 30 nm or less than 30 nm. By doing so, it is possible to prevent the high-k dielectric film HKF to be formed from becoming thick due to the height difference, and thus, as described later, the high-k dielectric film HKF is likely to be appropriately removed when removed. Note that the upper surface of the sacrificial layer SCL may be located inside or outside the second opening OP2.

[0076] In the etching step, as Figure 7 shown in the figure, a part of the sacrificial layer SCL located outside the second opening OP2 is removed. That is, a part of the sacrificial layer SCL located in each of the first opening OP1 and the third opening OP3 is removed. Accordingly, the first side surface SF1 of the first gate structure portion GSP1 is exposed in the first opening OP1, and the second side surface SF2 of the second gate structure portion GSP2 is exposed in the third opening OP3.

[0077] Through the steps described above, the gate structure GS1 for controlling the gate electrode CG is formed on the semiconductor substrate SS via the gate insulating film GIF. In the first embodiment, the gate structure GS1 includes the first gate structure portion GSP1, the sacrificial layer SCL, and the second gate structure portion GSP2. The first gate structure portion GSP1, the sacrificial layer SCL, and the second gate structure portion GSP2 are arranged in this order. In the gate structure GS1, the first gate structure portion GSP1 and the sacrificial layer SCL are adjacent to each other, and the sacrificial layer SCL and the second gate structure portion GSP2 are adjacent to each other.

[0078] 2. Formation of the charge storage film CSF

[0079] Next, as Figure 8 shown in the figure, the charge storage film CSF is formed on the semiconductor substrate SS. In the first embodiment, the charge storage film CSF is formed by stacking the first insulating film IF1, the high-k dielectric film HKF, and the second insulating film IF2 in this order. The charge storage film CSF is formed on the semiconductor substrate SS so as to cover the gate structure GS1. In the first embodiment, the charge storage film CSF covers the first side surface SF1 and the first upper surface TS1 of the first gate structure portion GSP1, the upper surface of the sacrificial layer SCL, and the second side surface SF2 and the second upper surface TS2 of the second gate structure portion GSP2.

[0080] Examples of the method for forming the first insulating film IF1 include ISSG (in-situ steam generation) oxidation method, thermal oxidation method, or CVD method. Examples of the material of the first insulating film IF1 include silicon oxide.

[0081] Examples of the method for forming the high-k dielectric film HKF include LPCVD (low-pressure CVD) method or ALD (atomic layer deposition) method. The high-k dielectric film HKF is an insulating film containing a material having a dielectric constant higher than that of silicon nitride. Examples of the material in the high-k dielectric film HKF mentioned above are, for example, hafnium (Hf). The high-k dielectric film HKF contains, for example, hafnium and oxygen. The high-k dielectric film HKF is, for example, a hafnium oxide film or a hafnium silicate film.

[0082] Examples of the method for forming the second insulating film IF2 include LPCVD method or ALD method. The second insulating film IF2 is also an insulating film having a dielectric constant higher than that of silicon nitride. Examples of the material of the second insulating film IF2 include aluminum (Al), titanium (Ti), zirconium (Zr), yttrium (Y), lanthanum (La), praseodymium (Pr), and lutetium (Lu).

[0083] 3. Formation of the conductive film CFmg for the memory gate electrode MG

[0084] Next, as shown in Figure 9 , a conductive film CFmg for the memory gate electrode MG is formed on the charge storage film CSF. Examples of the method for forming the conductive film CFmg are the same as the examples of the method for forming the conductive film CFcg. In addition, examples of the material of the conductive film CFmg are the same as the examples of the material of the conductive film CFcg. The material of the conductive film CFmg may be the same as or different from the material of the conductive film CFcg.

[0085] 4. Formation of the memory gate electrode MG

[0086] Next, as shown in Figure 10 , a part of the charge storage film CSF and a part of the conductive film CFmg are removed to form the memory gate electrode MG. More specifically, an etching process is performed on the semiconductor substrate SS such that the charge storage film CSF and the conductive film CFmg are retained on the first side surface SF1 and the second side surface SF2 of the gate structure GS1 in this order. Thus, a memory gate electrode MG having a so-called sidewall shape is formed. The sidewall shape mentioned here means a shape in which the thickness in the main surface direction of the semiconductor substrate SS is larger as the position gets closer to the main surface of the semiconductor substrate SS compared to the position away from the main surface of the semiconductor substrate SS.

[0087] Examples of methods of an etching process include an anisotropic etching method and an isotropic etching method. From the viewpoint of increasing the etching rate of a high dielectric constant film, the anisotropic etching method is preferred as a method of the etching process. In isotropic etching, high temperature conditions (e.g., several hundreds of degrees) are preferred from the viewpoint of increasing the etching rate.

[0088] In addition, it is preferable that a part of the charge storage film CSF formed on the upper surface of the gate structure GS1 is also removed. Accordingly, the upper surface of the sacrificial layer SCL in the gate structure GS1 is exposed. When this part is not removed in this step, the manufacturing method of the semiconductor device SD1 may separately include the following step: exposing the upper surface of the sacrificial layer SCL by removing a part of the charge storage film CSF formed on the upper surface of the gate structure GS1.

[0089] Furthermore, it is preferable that a part of the charge storage film CSF located on the main surface of the semiconductor substrate SS and exposed from the memory gate electrode MG is also removed. Accordingly, a part of the semiconductor substrate SS is exposed from the memory gate electrode MG. When this part is not removed in this step, the manufacturing method of the semiconductor device SD1 may separately include the following step: removing a part of the charge storage film CSF located on the main surface of the semiconductor substrate SS and exposed from the memory gate electrode MG.

[0090] 5. Removal of a part of the gate structure GS1

[0091] Next, as Figure 11 shown, a part of the gate structure GS1 is removed. More specifically, a part of the gate structure GS1 separated from the first side surface SF1 and the second side surface SF2 is removed such that a part of the semiconductor substrate SS is exposed from the gate structure GS1. In the first embodiment, the sacrificial layer SCL is removed. A method of removing the sacrificial layer SCL is, for example, a CDE (chemical dry etching) method.

[0092] 6. Formation of the first impurity region IPR1

[0093] Next, as Figure 12 shown, the first impurity region IPR1 is formed in the semiconductor substrate SS by an ion implantation method. At this time, the control gate electrode CG, the capping insulating film CIF, and the memory gate electrode MG are used as implantation masks. That is, in a plan view, the first impurity region IPR1 is formed in a region of the semiconductor substrate SS different from the regions of the control gate electrode CG, the capping insulating film CIF, and the memory gate electrode MG. Impurities for forming the first impurity region IPR1 are, for example, n-type impurities such as phosphorus (P) or arsenic (As).

[0094] 7. Formation of the sidewall SW

[0095] Next, as shown in Figure 13 as shown, sidewalls SW are formed on each of a side surface of the control gate electrode CG, a side surface of the capping insulating film CIF, and a side surface of the memory gate electrode MG. For example, the sidewalls SW can be formed by forming an insulating film made of the material of the sidewalls SW on the semiconductor substrate SS via a CVD method so as to cover the first gate structure portion GSP1 and the second gate structure portion GSP2, and then forming the sidewalls SW by etching back the insulating film. The sidewalls SW are, for example, a silicon oxide film, a silicon nitride film, or a stacked film of these films.

[0096] 8. Formation of the second impurity region IPR2

[0097] Next, as shown in Figure 14 as shown, the second impurity region IPR2 is formed in the semiconductor substrate SS by an ion implantation method. At this time, the control gate electrode CG, the capping insulating film CIF, the memory gate electrode MG, and the sidewalls SW are used as implantation masks. That is, in a plan view, the second impurity region IPR2 is formed in a region of the semiconductor substrate SS different from the regions of the control gate electrode CG, the capping insulating film CIF, the memory gate electrode MG, and the sidewalls SW. The impurity for forming the second impurity region IPR2 is, for example, an n-type impurity such as phosphorus (P) or arsenic (As). The impurity concentration of the second impurity region IPR2 is preferably higher than the impurity concentration of the first impurity region IPR1. Note that the first impurity region IPR1 is a semiconductor region corresponding to the LDD (lightly doped drain) region. The second impurity region IPR2 is a semiconductor region corresponding to the source region and / or the drain region.

[0098] 9. Formation of the multilayer wiring layer

[0099] Next, as shown in Figure 15 as shown, the multilayer wiring layer is formed. The multilayer wiring layer is a layer configured by two or more wiring layers. The multilayer wiring layer is a layer including an interlayer insulating layer and one or both of wirings and plugs formed in the interlayer insulating layer. A plug is a conductor that electrically connects two wirings formed in different layers.

[0100] In the first embodiment, the step of forming the multilayer wiring layer includes: step (1) forming the first interlayer insulating layer IIL1; step (2) forming the second interlayer insulating layer IIL2; step (3) forming the plug PG; and step (4) forming the wiring WR.

[0101] (1) Formation of the first interlayer insulating layer IIL1

[0102] First, a first interlayer insulating layer IIL1 is formed on a semiconductor substrate SS to fill a first opening OP1, a second opening OP2, and a third opening OP3. A method for forming the first interlayer insulating layer IIL1 is, for example, a CVD method. The upper surface of the first interlayer insulating layer IIL1 may be polished so that the upper surface of the capping insulating film CIF is exposed from the first interlayer insulating layer IIL1. The polishing method is, for example, a CMP method. The material of the first interlayer insulating layer IIL1 is, for example, silicon oxide.

[0103] Note that the polishing process of the first interlayer insulating layer IIL1 may be performed so that the upper surface of the control gate electrode CG is exposed. In this case, a part (upper part) of the capping insulating film CIF, a part (upper part) of the charge storage film CSF, and a part (upper part) of the memory gate electrode MG are removed. Thus, for example, a silicide layer may be formed on the exposed upper surface of the control gate electrode CG.

[0104] (2) Formation of the second interlayer insulating layer IIL2

[0105] Next, a second interlayer insulating layer IIL2 is formed on the first interlayer insulating layer IIL1. A method for forming the second interlayer insulating layer IIL2 is, for example, a CVD method. The upper surface of the second interlayer insulating layer IIL2 may also be polished. The material of the second interlayer insulating layer IIL2 is, for example, silicon oxide.

[0106] (3) Formation of the plug PG

[0107] Next, a plug PG reaching the second impurity region IPR2 is formed in the first interlayer insulating layer IIL1 and the second interlayer insulating layer IIL2. A well-known method as a method for forming a plug in semiconductor technology may be used as a method for forming the plug PG. The plug PG is, for example, a stacked film composed of a barrier metal film and a conductive film formed on the barrier metal film. Examples of the material of the barrier metal film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of the material of the conductive film include tungsten (W), aluminum (Al), and copper (Cu).

[0108] (4) Formation of the wiring WR

[0109] Next, a wiring WR is formed on the second interlayer insulating layer IIL2. The wiring WR is electrically connected to the second impurity region IPR2 through the plug PG. A well-known method as a method for forming a wiring in semiconductor technology may be used as a method for forming the wiring WR. The wiring WR may be, for example, an aluminum wiring or a copper wiring.

[0110] Although not particularly shown, a wiring layer is formed over the second interlayer insulating layer IIL2 located in the multilayer wiring layer in the same manner as the steps of forming the second interlayer insulating layer IIL2, the step of forming the plug PG, and the step of forming the wiring WR.

[0111] In the manner described above, a semiconductor device SD1 according to the first embodiment is formed. Note that the manufacturing method of the semiconductor device SD1 may further include a silicide step, a dicing step, etc., as needed.

[0112] (Function of the sacrificial layer SCL)

[0113] Herein, the function of the sacrificial layer SCL will be described. First, for comparison, a comparative example of a manufacturing method of a semiconductor device that does not include the step of forming the sacrificial layer SCL will be described. Figure 16 FIG. is a cross-sectional view showing the step of forming the charge storage film CSF in a comparative example of a manufacturing method of a semiconductor device. Figure 17 FIG. is a cross-sectional view showing the state after the charge storage film CSF is removed in a comparative example of a manufacturing method of a semiconductor device.

[0114] As Figure 16 shown, in a comparative example of a manufacturing method of a semiconductor device, in the step of forming the charge storage film CSF, the charge storage film CSF is also formed on the third side surface SF3 of the first gate structure portion GSP1 and the fourth side surface SF4 of the second gate structure portion GSP2. Next, as Figure 17 shown, the charge storage film CSF is removed after forming the memory gate electrode MG.

[0115] As Figure 17As shown, when the charge storage film CSF in the second opening OP2 is removed, the charge storage film CSF is not completely removed, and in some cases, the residue rCSF of the charge storage film CSF remains on the inner surface of the second opening OP2. Specifically, in the case of anisotropic etching using the resist mask RM, the etchant moves in a direction perpendicular to the main surface of the semiconductor substrate SS, and thus the residue rCSF of the charge storage film CSF is likely to remain on the third side surface SF3 of the first gate structure portion GSP1 and the fourth side surface SF4 of the second gate structure portion GSP2. In addition, for example, when the charge storage film CSF is made of a material that is difficult to etch (such as a hafnium-containing material), the above-mentioned phenomenon becomes obvious. Therefore, in each step, the residue rCSF may adhere to an unexpected position on the semiconductor substrate SS. As a result, the characteristics of the semiconductor device deteriorate. In addition, the residue rCSF may cause contamination of the manufacturing apparatus. Furthermore, in the step of forming the impurity region IPR using the control gate electrode CG as a mask, ion implantation is hindered by the residue rCSF on the sidewall of the control gate electrode CG. As described above, in the conventional manufacturing method of semiconductor devices, the desired characteristics of semiconductor devices cannot be obtained in some cases.

[0116] On the other hand, in the first embodiment, since the sacrificial layer SCL is present in the second opening OP2, the charge storage film CSF is not formed on the inner surface of the second opening OP2. In addition, since the charge storage film CSF is formed on the upper surface of the sacrificial layer SCL, the charge storage film CSF can be appropriately removed by anisotropic etching. Therefore, when compared with a conventional semiconductor device, no residue of the charge storage film CSF is formed in the second opening OP2 in the semiconductor device SD1 according to the first embodiment. Therefore, the characteristics of the semiconductor device can be enhanced compared with a conventional semiconductor device.

[0117] (Configuration of the semiconductor device SD1)

[0118] As Figure 15 shown, the semiconductor device SD1 according to the first embodiment includes a semiconductor substrate SS, a gate insulating film GIF, a control gate electrode CG, a capping insulating film CIF, a charge storage film CSF, a memory gate electrode MG, and the multilayer wiring layer described above. The multilayer wiring layer described above includes a first interlayer insulating layer IIL1, a second interlayer insulating layer IIL2, a plug PG, and a wiring WR.

[0119] The semiconductor substrate SS is a single-crystalline silicon substrate having a specific resistance of, for example, 1 Ωcm to 10 Ωcm. The semiconductor substrate SS has an impurity region containing, for example, p-type impurities. Examples of the p-type impurities include boron (B) and aluminum (Al). The semiconductor substrate SS has an impurity region formed to configure semiconductor elements. In the first embodiment, the first impurity region IPR1 is formed as an LDD region, and the second impurity region IPR2 is formed as a source region and / or a drain region in the semiconductor substrate SS. Although not particularly shown, an insulating film for element isolation may be formed in the semiconductor substrate SS.

[0120] The gate insulating film GIF is formed on a part of the main surface of the semiconductor substrate SS. The gate insulating film GIF is formed between the semiconductor substrate SS and the control gate electrode CG. The material of the gate insulating film GIF is, for example, silicon oxide.

[0121] The control gate electrode CG is formed on the gate insulating film GIF. Examples of the material of the control gate electrode CG include polysilicon. The thickness of the control gate electrode CG is appropriately adjusted according to the desired thickness of the control gate electrode CG.

[0122] The capping insulating film CIF is formed on the control gate electrode CG. Examples of the material of the capping insulating film CIF include silicon oxide and silicon nitride. The capping insulating film CIF may be a single-layer film or a stacked film composed of two or more layers. Preferably, the thickness of the capping insulating film CIF is, for example, 20 nm or greater than 20 nm and less than 100 nm or 100 nm.

[0123] In a plan view, a charge storage film CSF is formed on a region adjacent to the control gate electrode CG on the main surface of the semiconductor substrate SS, on the side surface of the control gate electrode CG, and on the side surface of the capping insulating film CIF. The charge storage film CSF is a stacked film in which a first insulating film IF1, a high dielectric constant film HKF, and a second insulating film IF2 are stacked in this order. Examples of the material of each of the first insulating film IF1, the high dielectric constant film HKF, and the second insulating film IF2 are as described above.

[0124] The memory gate electrode MG is formed on the charge storage film CSF. Examples of the material of the memory gate electrode MG are the same as the examples of the material of the control gate electrode CG. The thickness of the memory gate electrode MG is determined according to the total thickness of the control gate electrode CG and the capping insulating film CIF.

[0125] A multilayer wiring layer is formed on a semiconductor substrate SS so as to cover a capping insulating film CIF, a charge storage film CSF, and a memory gate electrode MG. A first interlayer insulating layer IIL1 is formed on the semiconductor substrate SS so as to fill a gap between two adjacent control gate electrodes CG and two adjacent memory gate electrodes MG. A second interlayer insulating layer IIL2 is formed on the first interlayer insulating layer IIL1. Plugs PG are formed in the first interlayer insulating layer IIL1 and the second interlayer insulating layer IIL2 so as to reach the semiconductor substrate SS. The plugs PG are electrically connected to second impurity regions IPR2, which are each formed between two adjacent control gate electrodes CG and two adjacent memory gate electrodes MG in a plan view. A wiring WR is formed on the second interlayer insulating layer IIL2. The wiring WR is electrically connected to the plugs PG.

[0126] (Operation of the semiconductor device SD1)

[0127] Next, an example of the operation of the semiconductor device SD1 will be described. Hereinafter, each of a write operation, an erase operation, and a read operation will be described. In the following description, the injection of electrons into the charge storage film CSF is defined as "write", and the injection of holes is defined as "erase".

[0128] (Write operation)

[0129] In the write operation, a write voltage for writing is applied to each of the memory gate electrode MG, the source region (second impurity region IPR2), the control gate electrode CG, the drain region (second impurity region IPR2), and the semiconductor substrate SS. Accordingly, electrons are injected into the charge storage film CSF. Accordingly, the threshold voltage of the memory element constituting the semiconductor device SD1 is increased. In this way, the write operation is completed. The memory element is in a written state.

[0130] The write voltage applied to the memory gate electrode MG is, for example, 6V. The write voltage applied to the source region (second impurity region IPR2) is, for example, 4V. The write voltage applied to the control gate electrode CG is, for example, 1V. The write voltage applied to the drain region (second impurity region IPR2) is, for example, 0.3V. The write voltage applied to the semiconductor substrate SS is, for example, 0V.

[0131] (Erase operation)

[0132] In an erase operation, an erase voltage for erasing is applied to each of a memory gate electrode MG, a source region (second impurity region IPR2), a control gate electrode CG, a drain region (second impurity region IPR2), and a semiconductor substrate SS. Accordingly, holes are injected into a charge storage film CSF. As a result, the threshold voltage of the memory element constituting the semiconductor device SD1 is decreased. In this manner, the erase operation is completed. The memory element is in an erased state.

[0133] The erase voltage applied to the memory gate electrode MG is, for example, -4V. The erase voltage applied to the source region (second impurity region IPR2) is, for example, 4V. The erase voltage applied to the control gate electrode CG is, for example, 0V. The erase voltage applied to the drain region (second impurity region IPR2) is, for example, 0V. The erase voltage applied to the semiconductor substrate SS is, for example, 0V.

[0134] (Read operation)

[0135] In a read operation, a read voltage for reading is applied to each of a memory gate electrode MG, a source region (second impurity region IPR2), a control gate electrode CG, a drain region (second impurity region IPR2), and a semiconductor substrate SS. In the read operation, the read voltage applied to the memory gate electrode MG is set between the threshold of the memory element in the written state and the threshold of the memory element in the erased state. Accordingly, no current flows in the memory element in the written state, while current flows in the memory element in the erased state. In this manner, the state of the memory element is read depending on whether current flows in the memory element.

[0136] (Effect)

[0137] As described above, in the first embodiment, after the charge storage film CSF is formed and patterned, the sacrificial layer SCL that is part of the gate structure GS1 is removed to form the control gate electrode CG. Accordingly, as described above, the charge storage film CSF is not formed on the side surface of the control gate electrode CG. Accordingly, it is possible to prevent the residue rCSF of the charge storage film CSF from remaining on the side surface of the control gate electrode CG. As a result, the characteristics of the semiconductor device can be enhanced.

[0138] [Modification example of the embodiment]

[0139] Figures 18 to 22 is a cross-sectional view showing an example of each step included in a method for manufacturing a semiconductor device mSD1 according to a modification example.

[0140] As Figure 18As described in [ ], the method of manufacturing the semiconductor device mSD1 according to the modified example includes a step of removing the second layer SL, instead of the step of removing the sacrificial layer SCL described above. That is, in the step of removing the second layer SL according to the modified example, the second layer SL is removed such that the first layer FL remains. Specifically, the first layer FL remains on the third side surface SF3 of the first gate structure portion GSP1, the fourth side surface SF4 of the second gate structure portion GSP2, and a part of the semiconductor substrate SS exposed in the second opening OP2.

[0141] As Figure 19 shown in [ ], in the step of forming the first impurity region IPR1 according to the modified example, ion implantation is performed on a part of the semiconductor substrate SS exposed in the second opening OP2 in a state where the first layer FL exists. Therefore, the first layer FL can be used as a so-called through film (protective film). As a result, the drain region becomes shallower than the source region. Therefore, the short-channel effect is improved.

[0142] As Figure 20 shown in [ ], in the step of forming the sidewall SW according to the modified example, the sidewall SW on the side surface of the control gate electrode CG is formed via the first layer FL on the third side surface SF3 of the first gate structure portion GSP1. On the other hand, in the absence of an insulating film, the sidewall SW on the side surface of the memory gate electrode MG is formed on the fourth side surface SF4 of the second gate structure portion GSP2.

[0143] As Figure 21 shown in [ ], in the step of forming the second impurity region IPR2 according to the modified example, ion implantation is performed on a part of the semiconductor substrate SS exposed in the second opening OP2 in a state where the first layer FL exists.

[0144] As Figure 22 shown in [ ], in the step of forming the multilayer wiring layer according to the modified example, a plug PG is formed to penetrate the first layer FL, the first interlayer insulating layer IIL1, and the second interlayer insulating layer IIL2.

[0145] As described above, in the semiconductor device mSD1 according to the modified example, the first layer FL is formed on the inner surface of the second opening OP2. In other words, the first layer FL is formed between the sidewall SW and the side surface of the control gate electrode CG, and the sidewall SW is formed on the side surface of the control gate electrode CG. Therefore, the length L1 of the LDD region (first impurity region IPR1) located below the sidewall SW formed on the side surface of the control gate electrode CG is greater than the thickness of the first layer FL compared to the length L2 of the LDD region (first impurity region IPR1) located below the sidewall SW formed on the side surface of the memory gate electrode MG. If sufficient breakdown voltage can be ensured, the length L1 can be greater than the length L2. The length of the LDD region (first impurity region IPR1) mentioned here is the length of the first impurity region IPR1 in the arrangement direction of the control gate electrode CG and the memory gate electrode MG (see Figure 22 ).

[0146] In the modified example described above, the case where the manufacturing method of the semiconductor device mSD1 does not include the step of removing the first layer FL has been described, but the present embodiment is not limited thereto. For example, the manufacturing method of the semiconductor device may include a step of removing the first layer FL after the step of forming the first impurity region IRP1 and before the step of forming the sidewall SW.

[0147] [Second Embodiment]

[0148] (Manufacturing Method of Semiconductor Device)

[0149] The manufacturing method of the semiconductor device SD2 according to the second embodiment is different from the manufacturing method of the semiconductor device SD1 according to the first embodiment, and the difference mainly lies in the configuration of the gate structure GS2. Therefore, components that are the same as those in the first embodiment or components corresponding to those in the first embodiment are denoted by the same reference numerals, and their descriptions will be omitted.

[0150] An example of the manufacturing method of the semiconductor device SD2 according to the second embodiment will be described. Figures 23 to 33 is a cross-sectional view showing an example of each step included in the manufacturing method of the semiconductor device SD2.

[0151] The manufacturing method of the semiconductor device SD2 according to the second embodiment includes: Step 1. Forming the gate structure GS2; Step 2. Forming the charge storage film CSF; Step 3. Forming the conductive film CFmg for the memory gate electrode MG; Step 4. Forming the memory gate electrode MG; Step 5. Removing a part of the gate structure GS2; Step 6. Forming the first impurity region IPR1; Step 7. Forming the sidewall SW; Step 8. Forming the second impurity region IPR2; and Step 9. Forming the multilayer wiring layer.

[0152] 1. Formation of Gate Structure GS2

[0153] The steps for forming the gate structure GS2 include: step (1) preparing a semiconductor substrate SS; step (2) forming a stacked film SF; and step (3) removing a part of the stacked film SF.

[0154] (1) Preparation of Semiconductor Substrate SS

[0155] First, as Figure 23 shown, the semiconductor substrate SS is prepared, and a gate insulating film GIF is formed on the semiconductor substrate SS. Since this situation is the same as that in the first embodiment, its description is omitted.

[0156] (2) Formation of Stacked Film SF

[0157] Next, as Figure 24 shown, a stacked film SF in which a conductive film CFcg for controlling the gate electrode CG and a capping insulating film CIF are stacked in this order is formed on the gate insulating film GIF. Since the method of forming the stacked film SF in the second embodiment is the same as that in the first embodiment, its description is omitted.

[0158] (3) Removal of a Part of Stacked Film SF

[0159] Next, as Figure 25 shown, a part of the stacked film SF is removed. Thus, a gate structure GS2 made of the other part of the stacked film SF for controlling the gate electrode CG is formed. The gate structure GS2 has a first side surface SF1 and a second side surface SF2 on opposite sides of each other, and an upper surface TS. A part of the stacked film SF is removed by, for example, a photolithography method and an etching method. In the second embodiment, the first opening OP1 and the third opening OP3 in the first embodiment are formed. On the other hand, in this step, the second opening OP2 formed between two adjacent control gate electrodes CG is not formed in the manufactured semiconductor device SD2.

[0160] 2. Formation of Charge Storage Film CSF

[0161] Next, as Figure 26 shown, a charge storage film CSF is formed on the semiconductor substrate SS so as to cover the gate structure GS2. In the second embodiment, the charge storage film covers the first side surface SF1, the second side surface SF2, and the upper surface TS of the gate structure GS2.

[0162] 3. Formation of Conductive Film CFmg for Memory Gate Electrode MG

[0163] Next, as Figure 27As shown in [reference], a conductive film CFmg for a memory gate electrode MG is formed on a charge storage film CSF. An example of a method for forming the conductive film CFmg is the same as that of the first embodiment.

[0164] 4. Formation of Memory Gate Electrode MG

[0165] Next, as Figure 28 shown in [reference], a part of the charge storage film CSF and a part of the conductive film CFmg are removed to form the memory gate electrode MG. The method for forming the memory gate electrode MG is the same as that of the first embodiment.

[0166] 5. Removal of a Portion of Gate Structure GS2

[0167] Next, as Figure 29 shown in [reference], a part of the gate structure GS2 is removed. More specifically, a part of the gate structure GS2 separated from the first side surface SF1 and the second side surface SF2 is removed so that a part of the semiconductor substrate SS is exposed from the gate structure GS2. Thus, a control gate electrode CG and a second opening OP2 are formed. In the second embodiment, a part of the stacked film SF and a part of the gate insulating film GIF are removed. A part of the stacked film SF removed in this step is appropriately adjusted according to the desired position of the control gate electrode CG. A part of the gate structure GS2 (stacked film SF) is removed by, for example, a photolithography method and an etching method.

[0168] 6. Formation of First Impurity Region IPR1

[0169] Next, as Figure 30 shown in [reference], a first impurity region IPR1 is formed in the semiconductor substrate SS by an ion implantation method. The method for forming the first impurity region IPR1 is the same as that of the first embodiment.

[0170] 7. Formation of Sidewall SW

[0171] Next, as Figure 31 shown in [reference], a sidewall SW is formed on each of the side surfaces of the control gate electrode CG, the capping insulating film CIF, and the memory gate electrode MG. The method for forming the sidewall SW is the same as that of the first embodiment.

[0172] 8. Formation of Second Impurity Region IPR2

[0173] Next, as Figure 32 shown in [reference], a second impurity region IPR2 is formed in the semiconductor substrate SS by an ion implantation method. The method for forming the second impurity region IPR2 is the same as that of the first embodiment.

[0174] 9. Formation of Multilayer Wiring Layer

[0175] Next, as shown in Figure 33 , a multilayer wiring layer is formed on the semiconductor substrate SS. The method of forming the multilayer wiring layer is the same as that of the first embodiment.

[0176] In the manner described above, a semiconductor device SD2 according to the second embodiment is formed. The configuration of the semiconductor device SD2 is the same as that of the semiconductor device SD1 according to the first embodiment.

[0177] (Effect)

[0178] As described above, in the second embodiment, after the charge storage film CSF is formed and patterned, a part of the stacked film SF that is part of the gate structure GS2 is removed to form the control gate electrode CG. Therefore, the same effect as that of the first embodiment can be achieved. In addition, in the manufacturing method of the gate structure GS2 according to the second embodiment, the sacrificial layer SCL is not formed. Therefore, the manufacturing method of the semiconductor device SD2 according to the second embodiment is simpler. Further, the gate structure GS2 is formed by patterning performed in two steps (so-called double patterning technique). Therefore, from the perspective of miniaturization of semiconductor elements, the manufacturing method of the semiconductor device SD2 according to the second embodiment is more preferable. That is, from the perspective of reducing the size and cost of the semiconductor device, the second embodiment is more preferable.

[0179] Note that the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present invention. For example, the following case has been described: the high-k dielectric film HKF and the second insulating film IF2 in the charge storage film CSF contain materials having a dielectric constant higher than that of silicon nitride. However, another embodiment of the present invention is not limited to this configuration. For example, one or both of the high-k dielectric film HKF and the second insulating film IF2 may not contain materials having a dielectric constant higher than that of silicon nitride. In this case, the film material corresponding to the high-k dielectric film HKF is silicon oxynitride, silicon carbide, or silicon carbonitride, and the material of the second insulating film IF2 is silicon oxide.

[0180] In addition, in the embodiments described above, the memory gate electrode MG has a sidewall shape. However, the cross-sectional shape of the memory gate electrode MG may be rectangular.

Claims

1. A method of manufacturing a semiconductor device, comprising: (a) forming a gate structure for controlling a gate electrode on a semiconductor substrate via a gate insulating film; (b) forming a charge storage film on the semiconductor substrate so as to cover a first side surface, a second side surface, and an upper surface of the gate structure; (c) forming a first conductive film for a memory gate electrode on the charge storage film; (d) removing a part of the charge storage film and a part of the first conductive film such that the charge storage film and the first conductive film remain on the first side surface and the second side surface of the gate structure on the semiconductor substrate in this order, thereby forming the memory gate electrode; and (e) removing a part of the gate structure that is separated from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure, wherein the (a) includes: (a1) forming a stacked film on the gate insulating film, in which a second conductive film for controlling the gate electrode and a capping insulating film are stacked in this order; (a2) forming a first gate structure part and a second gate structure part that are separated from each other by removing a part of the stacked film; and (a3) forming a sacrificial layer on the semiconductor substrate so as to fill an opening formed between the first gate structure part and the second gate structure part, and wherein the sacrificial layer is removed in the (e).

2. The method of manufacturing a semiconductor device according to claim 1, wherein the (a3) includes: (a3-1) forming a first layer on an inner surface of the opening; and (a3- ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ Remove a part of the sacrificial layer located outside the opening.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the material of the sacrificial layer is polysilicon.

7. The method of manufacturing a semiconductor device according to claim 1, wherein the (a) includes: (a1) Form a stacked film on the gate insulating film, and stack a second conductive film for controlling the gate electrode and a capping insulating film in this order in the stacked film; and (a2) Remove a part of the stacked film to form a gate structure configured by another part of the stacked film.

8. The method of manufacturing a semiconductor device according to claim 1, wherein a part of the gate structure is removed by anisotropic etching in the (e).

9. The method of manufacturing a semiconductor device according to claim 1, Among them, In the (b), the stacked film is formed as the charge storage film, and a first insulating film, a high-k dielectric film, and a second insulating film are formed in this order in the stacked film, and wherein the high-k dielectric film contains a material having a dielectric constant higher than that of silicon nitride.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the material in the high-k dielectric film is hafnium.

11. The method of manufacturing a semiconductor device according to claim 9, wherein the second insulating film contains a material having a dielectric constant higher than that of silicon nitride.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the material in the second insulating film is aluminum.

13. The method of manufacturing a semiconductor device according to claim 1, after the (e), further includes (f) By an ion implantation method, using the control gate electrode as an implantation mask, form an impurity region in the semiconductor substrate.

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